Dynamic circuit calibration during voltage change transitions

Abstract

In some aspects, an electronic device may detect a start of a voltage ramp transition period associated with changing a voltage of an integrated circuit operation from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage causes a change in one or more parameters that affect performance associated with the integrated circuit during the voltage ramp transition period. The electronic device may trigger a dynamic calibration mode in response to detecting the start of the voltage ramp transition period that compensates for changes in one or more parameters that affect performance associated with the integrated circuit during the voltage ramp transition period. The electronic device may exit the dynamic calibration mode in response to detecting an end of the voltage ramp transition period. Numerous other aspects are described.

Description

Cross-reference to related applications

[0001] This patent application claims priority to U.S. Patent Application No. 18 / 481,657, filed October 5, 2023, entitled “DYNAMIC CIRCUIT CALIBRATIONDURING VOLTAGE CHANGE TRANSITIONS”, assigned to the assignee of this application. The disclosure of the earlier application is considered part of this patent application and is incorporated herein by reference. Technical Field

[0002] This disclosure relates in general to integrated circuits, and, for example, to dynamic circuit calibration during voltage change transitions. Background Technology

[0003] Dynamic voltage and frequency scaling (DVFS) (interchangeably referred to as dynamic voltage and frequency switching, dynamic clock and voltage scaling, or dynamic clock and voltage switching (DCVS)) includes techniques for adjusting the power and / or speed settings of one or more processors, controller chips, and / or peripherals of an electronic device to optimize resource allocation for one or more tasks and / or maximize power savings when resources are not needed. For example, synchronous digital circuits (e.g., memory devices, central processing units (CPUs), or digital signal processors (P)) require clock signals to coordinate the logic timing in the circuit. The frequency of the clock signal controls the switching speed or rate of the logic and thus the performance of the circuit, and the clock frequency of the circuit can be related to the voltage level supplying the circuit. For example, increasing the clock frequency will correspondingly increase the minimum voltage level required to power the circuit for proper operation. Therefore, increasing the clock frequency generally leads to increased power consumption. The power consumption of the circuit can be reduced by lowering the voltage level. However, lowering the voltage level will reduce the maximum clock frequency that the circuit can achieve. The voltage level can be reduced to the minimum level required for the circuit to operate properly at the desired clock frequency. Therefore, to optimize power consumption while still providing acceptable performance, DVFS or DCVS technologies can be employed in processor-based electronic devices, including user-based portable electronic devices. DVFS or DCVS circuitry controls clock frequency and voltage levels by configuring optimal clock frequency and voltage settings for the processor and / or other synchronous timing components based on the performance requirements of the electronic device. In this way, DVFS or DCVS circuitry can optimize the power consumption required for the desired performance level. Other information, such as temperature, battery level, and the operating system's scheduler state, can also be used to influence how DVFS or DCVS circuitry operates. Summary of the Invention

[0004] In some embodiments, an electronic device includes: one or more memories; and one or more processors coupled to the one or more memories, the one or more processors being configured to cause the electronic device to: detect the start of a voltage ramp transition period associated with changing the voltage for operating an integrated circuit from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage during the voltage ramp transition period results in a change in one or more parameters affecting the performance associated with the integrated circuit; trigger a dynamic calibration mode in response to detecting the start of the voltage ramp transition period, the dynamic calibration mode compensating for the change in the one or more parameters affecting the performance associated with the integrated circuit during the voltage ramp transition period; and exit the dynamic calibration mode in response to detecting the end of the voltage ramp transition period.

[0005] In some specific implementations, a method performed by an electronic device includes: detecting the start of a voltage ramp transition period associated with changing the voltage of an integrated circuit from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage during the voltage ramp transition period results in a change of one or more parameters affecting the performance associated with the integrated circuit; triggering a dynamic calibration mode in response to detecting the start of the voltage ramp transition period, the dynamic calibration mode compensating for the change of the one or more parameters affecting the performance associated with the integrated circuit during the voltage ramp transition period; and exiting the dynamic calibration mode in response to detecting the end of the voltage ramp transition period.

[0006] In some embodiments, a non-transitory computer-readable medium storing an instruction set includes one or more instructions that, when executed by one or more processors of an electronic device, cause the electronic device to: detect the start of a voltage ramp transition period associated with changing the voltage of an integrated circuit from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage during the voltage ramp transition period results in a change of one or more parameters affecting the performance associated with the integrated circuit; trigger a dynamic calibration mode in response to detecting the start of the voltage ramp transition period, the dynamic calibration mode compensating for the change of the one or more parameters affecting the performance associated with the integrated circuit during the voltage ramp transition period; and exit the dynamic calibration mode in response to detecting the end of the voltage ramp transition period.

[0007] In some embodiments, an apparatus includes: means for detecting the start of a voltage ramp transition period associated with changing the voltage for operating an integrated circuit from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage during the voltage ramp transition period results in a change in one or more parameters affecting the performance associated with the integrated circuit; means for triggering a dynamic calibration mode in response to detecting the start of the voltage ramp transition period, the dynamic calibration mode compensating for the change in the one or more parameters affecting the performance associated with the integrated circuit during the voltage ramp transition period; and means for exiting the dynamic calibration mode in response to detecting the end of the voltage ramp transition period.

[0008] Aspects generally include methods, apparatus, systems, computer program products, non-transitory computer-readable media, user equipment, user gear, electronic equipment, and / or processing systems that are substantially described with reference to the accompanying drawings and description and illustrated as illustrated by the drawings and description.

[0009] The features and technical advantages of the examples according to this disclosure have been summarized rather extensively above in order to better understand the detailed description below. Additional features and advantages will be described below. The disclosed concepts and specific examples can be readily used as the basis for modifying or designing other structures for achieving the same purpose as this disclosure. Such equivalent constructions do not depart from the scope of the appended claims. The characteristics of the concepts disclosed herein (both their organization and manner of operation) and the associated advantages will be better understood from the following description when considered in conjunction with the accompanying drawings. Each figure in the drawings is provided for illustrative and descriptive purposes and not as a definition of limitation of the claims. Attached Figure Description

[0010] To gain a full understanding of the foregoing features of this disclosure, a more specific description of the invention, briefly outlined above, can be obtained by referring to various aspects, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only certain typical aspects of this disclosure and are therefore not to be considered as limiting its scope, as other equally valid aspects are permissible in this description. The same reference numerals in different drawings may identify the same or similar elements.

[0011] Figure 1 This is a diagram illustrating an example electronic device that supports dynamic circuit calibration during voltage change transitions according to this disclosure.

[0012] Figure 2 This is a diagram illustrating example components included in a memory device that supports dynamic circuit calibration during voltage change transitions according to the present disclosure.

[0013] Figures 3A to 3BThis is a diagram illustrating an example of dynamic circuit calibration associated with voltage change transitions according to this disclosure.

[0014] Figure 4 This is a flowchart illustrating an example process associated with dynamic circuit calibration during voltage change transitions according to this disclosure.

[0015] Figure 5 This is a diagram illustrating an example system that supports dynamic circuit calibration during voltage change transitions according to this disclosure. Detailed Implementation

[0016] Various aspects of this disclosure are described more fully below with reference to the accompanying drawings. However, this disclosure may be embodied in many different forms and should not be construed as limited to any particular structure or function presented throughout this disclosure. Rather, these aspects are provided to make this disclosure thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art. Those skilled in the art will appreciate that the scope of this disclosure is intended to cover any aspect of this disclosure disclosed herein, whether implemented independently or in combination with any other aspect of this disclosure. For example, any number of aspects set forth herein may be used to implement an apparatus or practice. Furthermore, the scope of this disclosure is intended to cover such apparatus or methods practiced using structures, functionalities, or structures and functionalities other than or different from the aspects of the disclosure set forth herein. It should be understood that any aspect of this disclosure disclosed herein may be embodied by one or more elements of the present claims.

[0017] Dynamic voltage and frequency scaling, or dynamic voltage and frequency switching (DVFS), is a power management technique that can be used in processors or integrated circuits to optimize energy efficiency and performance. Specifically, DVFS (interchangeably referred to as dynamic clock and voltage scaling, or dynamic clock and voltage switching (DCVS)) is used to dynamically adjust the voltage and clock frequency associated with a processor, integrated circuit, or other suitable component based on workload, thermal conditions, or other factors, where voltage affects power consumption and clock frequency affects performance. For example, when electronic devices are idle, under light load, or when temperatures meet (e.g., equal to or exceed) a threshold, DVFS can be used to reduce the voltage and frequency of one or more circuit operations to save power or cool the device. Similarly, during periods of high computational demand or other suitable conditions, DVFS can be used to increase the voltage and frequency of one or more circuit operations to improve performance.

[0018] While DVFS technology enables electronic devices to balance performance and energy efficiency by dynamically adjusting the voltage and frequency of one or more circuit operations based on workload and / or thermal conditions, it is associated with various challenges. For example, when using DVFS to increase or decrease the voltage and frequency of integrated circuit operation, a voltage ramp transition period typically exists, during which the voltage gradually changes from a first voltage level to a second voltage level. During the voltage ramp transition period, one or more operating parameters and / or system parameters of the circuit associated with the changed voltage and frequency may change. For example, the voltage change during the voltage ramp transition period produces or causes a change in one or more operating parameters and / or system parameters, such as one or more delays (e.g., clock path delay and / or data path delay), impedance, reference voltage, data eye width, and / or data eye height, etc. Parameter changes occurring during the voltage ramp transition period are generally acceptable only if the circuit associated with the changed voltage and frequency is operating in a low-performance mode (e.g., when longer delays are acceptable). However, in some cases, it may be necessary to improve performance during the voltage ramp transition period, which presents a challenge because the frequency of circuit operation cannot be increased or decreased unless the voltage has ramped up or down to the target voltage level.

[0019] Various aspects broadly relate to dynamic circuit calibration during voltage ramp transitions. In some aspects, as described herein, voltage ramp transitions may occur when DVFS techniques are applied to gradually decrease a voltage level from a first (e.g., current) voltage level to a second (e.g., target) voltage level (e.g., to save power or mitigate thermal conditions during low-performance modes) and / or when DVFS techniques are applied to gradually increase a voltage level from a first (e.g., current) voltage level to a second (e.g., target) voltage level (e.g., to improve performance). Therefore, in some aspects, electronic devices employing DVFS techniques may include a calibration controller that can compensate for changes in one or more parameters affecting the performance of an integrated circuit during a voltage ramp transition period. For example, in some aspects, the calibration controller may detect the onset of a voltage ramp transition period and may apply one or more techniques during this period to adjust one or more parameters affecting the performance of the integrated circuit to restore those parameters to their optimal state. For example, when the voltage supplied to the integrated circuit changes, the calibration controller may dynamically adjust one or more input / output (I / O) drivers and / or I / O receiver codes to compensate for impedance changes that vary according to the changing voltage. Additionally or alternatively, the calibration controller may dynamically compensate for one or more delays, reference voltages, data eye widths, data eye heights, and / or other suitable parameters that vary with the changing voltage during voltage ramp transitions to improve performance. Additionally or alternatively, the calibration controller may store or access a lookup table (LUT) containing pre-calibration values ​​for one or more parameters, which can be retrieved and used to dynamically compensate for one or more parameters. For example, in some aspects, the calibration controller may monitor one or more parameters of an integrated circuit undergoing a voltage ramp transition, wherein the value of the monitored parameter indicates the current state of the voltage ramp transition based on a comparison with an item in the LUT table. In this way, the calibration controller can determine the current voltage and retrieve or otherwise obtain appropriate pre-calibration values ​​to compensate for one or more parameters that change with the changing voltage (e.g., dynamic calibration need not be run in task mode, which could lead to a degraded user experience or other adverse effects).

[0020] Specific aspects of the subject matter described in this disclosure can be implemented to achieve one or more of the following potential advantages. In some examples, by implementing a dynamic calibration mode during the voltage ramp transition period to compensate for changes in one or more parameters affecting the performance associated with the integrated circuit, the performance of the integrated circuit can be improved before the frequency of the integrated circuit can be increased or decreased to a target level corresponding to the target voltage level of the voltage ramp transition period. In this way, the calibration controller can avoid or reduce the performance and / or power effects that would otherwise occur when one or more parameters associated with the integrated circuit change from the current voltage level to the target voltage level during the voltage ramp transition period.

[0021] Figure 1 This is a diagram illustrating an example electronic device 100 that supports dynamic circuit calibration during voltage change transitions according to the present disclosure. Electronic device 100 may include one or more devices, means, and / or components for performing the operations described herein. For example, electronic device 100 may include a host device 110 and a memory device 120. Memory device 120 may include a controller 130 and a memory 140. Host device 110 may communicate with memory device 120 (e.g., the controller 130 of memory device 120) via host interface 150. Controller 130 may communicate with memory 140 via memory interface 160.

[0022] Electronic device 100 can be any suitable electronic device configured to store data in memory. For example, electronic device 100 can be a computer, mobile phone, wired or wireless communication device, network device, server, device in a data center, device in a cloud computing environment, vehicle (e.g., car or airplane), and / or Internet of Things (IoT) device. Host device 110 may include one or more processors configured to execute instructions and store data in memory 140. For example, host device 110 may include a central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), or application-specific integrated circuit (ASIC), etc.

[0023] Memory device 120 can be any electronic device configured to store data in memory. In some aspects, memory device 120 can be an electronic device configured to temporarily store data in volatile memory. For example, memory device 120 can be a random access memory (RAM) device, such as a dynamic RAM (DRAM) device or a static RAM (SRAM) device. In this case, memory 140 may include volatile memory that requires power to maintain the stored data and loses the stored data after power is turned off from memory device 120. For example, memory 140 may include one or more latches and / or RAM, such as DRAM and / or SRAM. In some aspects, memory 140 may include non-volatile memory, such as NAND memory or NOR memory, configured to retain the stored data after power is turned off from memory device 120. For example, non-volatile memory may store persistent firmware or other instructions for execution by controller 130.

[0024] Controller 130 can be any device configured to communicate with host device 110 (e.g., via host interface 150) and memory 140 (e.g., via memory interface 160). Additionally or alternatively, controller 130 can be configured to control the operation of memory device 120 and / or memory 140. For example, controller 130 may include control logic, a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and / or one or more processing components. In some embodiments, controller 130 may be a high-level controller that communicates directly with host device 110 and can instruct one or more low-level controllers to perform memory operations with respect to memory 140. In some embodiments, controller 130 may be a low-level controller that receives instructions regarding memory operations from a high-level controller that interacts directly with host device 110. For example, the high-level controller may be a solid-state drive (SSD) controller, and the low-level controller may be a non-volatile memory controller (e.g., a NAND controller) or a volatile memory controller (e.g., a DRAM controller). In some respects, it is described herein that a set of operations performed by controller 130 may be performed by a single controller (e.g., the entire set of operations may be performed by a single high-level controller or a low-level controller). Alternatively, it is described herein that a set of operations performed by controller 130 may be performed by more than one controller (e.g., a first subgroup of operations may be performed by a high-level controller, and a second subgroup of operations may be performed by a low-level controller).

[0025] Host interface 150 enables communication between host device 110 and storage device 120. Host interface 150 may include, for example, a Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Serial Advanced Technology Attached (SATA) interface, Fast Peripheral Component Interconnect (PCIe) interface, High-Speed ​​Non-Volatile Memory (NVMe) interface, Universal Serial Bus (USB) interface, Universal Flash Storage (UFS) interface, and / or an Embedded Multimedia Card (eMMC) interface.

[0026] Memory interface 160 enables communication between controller 130 and memory 140. Memory interface 160 may include a non-volatile memory interface (e.g., for communicating with non-volatile memory), such as a NAND interface or a NOR interface. Additionally or alternatively, memory interface 160 may include a volatile memory interface (e.g., for communicating with volatile memory), such as a double data rate (DDR) interface.

[0027] In some respects, as described in more detail elsewhere in this article, Figure 1One or more systems, devices, apparatuses, components, and / or controllers may be configured to: detect the start of a voltage ramp transition period associated with changing the voltage of an integrated circuit from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage during the voltage ramp transition period results in a change in one or more parameters affecting the performance associated with the integrated circuit; trigger a dynamic calibration mode in response to detecting the start of the voltage ramp transition period, the dynamic calibration mode compensating for the change in the one or more parameters affecting the performance associated with the integrated circuit during the voltage ramp transition period; and exit the dynamic calibration mode in response to detecting the end of the voltage ramp transition period. Additionally or alternatively, Figure 1 One or more systems, devices, apparatuses, components, and / or controllers may be configured to perform one or more other operations described herein.

[0028] As indicated above, Figure 1 This is provided as an example. Other examples are available with reference to [the relevant information]. Figure 1 The examples described are different. For example, some aspects described herein are broadly applicable to other circuits, including circuits that are entirely contained on the die (e.g., within a system-on-a-chip (SoC)) and / or associated with non-memory external interfaces (e.g., serializers / deserializers (SerDes)).

[0029] Figure 2 This is a diagram illustrating an example 200 of components included in a memory device 120 that supports dynamic circuit calibration during voltage change transitions according to this disclosure. (As described above in conjunction with...) Figure 1 As described, memory device 120 may include controller 130 and memory 140. For example... Figure 2 As shown, memory 140 may include one or more non-volatile memory arrays 205, such as one or more NAND memory arrays and / or one or more NOR memory arrays. Additionally or alternatively, memory 140 may include one or more volatile memory arrays 210, such as one or more SRAM arrays and / or one or more DRAM arrays. Controller 130 may use non-volatile memory interface 215 to send signals to and receive signals from the non-volatile memory arrays. Controller 130 may use volatile memory interface 220 to send signals to and receive signals from the volatile memory arrays.

[0030] Controller 130 may control the operation of memory 140, for example, by executing one or more instructions. For instance, memory device 120 may store one or more instructions in memory 140 as firmware, and controller 130 may execute such one or more instructions stored in memory 140. Additionally or alternatively, controller 130 may receive one or more instructions from host device 110 via host interface 150 and may execute such one or more instructions. In some embodiments, a non-transitory computer-readable medium (e.g., volatile memory and / or non-volatile memory) may store a set of instructions (e.g., one or more instructions or procedure codes) for controller 130 to execute. Controller 130 may execute the set of instructions to perform one or more operations or methods described herein. In some aspects, execution of the set of instructions by controller 130 causes controller 130 and / or memory device 120 to perform one or more operations or methods described herein. In some embodiments, hard-wired circuitry is used in place of or in combination with one or more instructions to perform one or more operations or methods described herein. Additionally or alternatively, the controller 130 and / or one or more components of the memory device 120 may be configured to perform one or more operations or methods described herein. Instructions are sometimes referred to as “commands”.

[0031] For example, controller 130 may send signals to and / or receive signals from memory 140 based on one or more instructions, such as transferring (e.g., writing or programming) data to memory 140, transferring (e.g., reading) data from memory, and / or erasing all or part of memory (e.g., one or more memory cells, pages, sub-blocks, blocks, or planes of memory 140). Additionally or alternatively, controller 130 may be configured to control access to memory 140 and / or provide a translation layer (e.g., mapping logical addresses to physical addresses in the memory array) between host device 110 and memory 140. In some implementations, controller 130 may translate host interface commands (e.g., commands received from host device 110) into memory interface commands (e.g., commands for performing operations on the memory array).

[0032] like Figure 2 As shown, controller 130 may include memory management components 225. In some implementations, one or more of these components are implemented as one or more instructions (e.g., firmware) executed by controller 130. Alternatively, one or more of these components may be implemented as application-specific integrated circuits (ASICs) different from controller 130.

[0033] Memory management component 225 may be configured to manage the performance of memory device 120. For example, memory management component 225 may perform wear leveling, bad block management, block erasure, read interference management, and / or other memory management operations. In some implementations, memory device 120 may (e.g., in memory 140) store one or more memory management tables. Memory management tables may store information that can be used or updated by memory management component 225, such as information about memory block aging, memory block erase counts, and / or error information associated with memory partitions (e.g., memory cells, rows of memory, and blocks of memory). Additionally or alternatively, memory management component 225 may employ DVFS or DCVS techniques to reduce the voltage level of circuit operation (e.g., to save power during low-performance modes) and / or increase the voltage level of circuit operation (e.g., during high-performance modes or after exiting low-performance modes).

[0034] Figure 2 One or more devices or components shown may be configured to perform the operations described herein, such as combining Figures 3A to 3B , Figure 4 and / or Figure 5 One or more operations and / or methods are described. For example, controller 130 and memory management component 225 may be configured to perform one or more operations and / or methods for memory device 120.

[0035] For example, in some aspects, the memory device 120 may include: means for detecting the start of a voltage ramp transition period associated with changing the voltage for operating an integrated circuit from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage during the voltage ramp transition period results in a change in one or more parameters affecting the performance associated with the integrated circuit; means for triggering a dynamic calibration mode in response to detecting the start of the voltage ramp transition period, the dynamic calibration mode compensating for the change in the one or more parameters affecting the performance associated with the integrated circuit during the voltage ramp transition period; and / or means for exiting the dynamic calibration mode in response to detecting the end of the voltage ramp transition period. In some aspects, the means of the memory device 120 for performing the processes and / or operations described herein may include Figure 2 One or more components are shown, such as controller 130 and / or memory management component 225.

[0036] Figure 2 The number and arrangement of components shown are provided as an example. In reality, with... Figure 2 Compared to the components shown, there may be additional components, fewer components, different components, or components arranged in a different manner. Furthermore, Figure 2The two or more components shown can be implemented within a single component, or Figure 2 The single component shown can be implemented as multiple distributed components. Additionally or alternatively, Figure 2 The component collection shown (e.g., one or more components) can be executed as described by Figure 2 The other set of components shown performs one or more functions.

[0037] Figures 3A to 3B This is a diagram illustrating example 300 associated with dynamic circuit calibration during voltage change transitions according to this disclosure. More specifically, as described herein, DVFS (or alternatively DCVS) is a power management technique that can be used in processors or integrated circuits to optimize energy efficiency and performance. Specifically, DVFS is used to dynamically adjust the voltage and clock frequency associated with a processor, integrated circuit, or other suitable component based on workload, thermal conditions, or other factors, where voltage affects power consumption and clock frequency affects performance. For example, DVFS can be used to reduce the voltage and / or frequency of one or more circuit operations to save power or cool electronic equipment, and / or increase the voltage and / or frequency of one or more circuit operations to improve performance.

[0038] While DVFS technology enables electronic devices to balance performance and energy efficiency by dynamically adjusting the voltage and frequency of one or more circuit operations based on workload and / or thermal conditions, it is associated with various challenges. For example, when using DVFS to increase or decrease the voltage and frequency of integrated circuit operations, there is typically a voltage ramp transition period during which the voltage gradually changes from a first voltage level to a second voltage level. For example, as... Figure 3A As shown by reference numeral 310 in the figure, DVFS technology can be applied to gradually increase the voltage level of an integrated circuit operation from a first voltage level (shown as V1) to a second voltage level (shown as V2). Before the voltage ramp transition period that gradually increases the voltage level, the circuit controlled using DVFS technology can operate at a first frequency (shown as F1), and during the voltage ramp transition period, the circuit can continue to operate at that first frequency. For example, as shown, the circuit can continue to operate at the first frequency during the voltage ramp transition period, and can later increase to a second (higher) frequency associated with improved performance after the voltage level has ramped up to the second voltage level. Furthermore, as... Figure 3A As shown by reference numeral 312 in the figure, the DVFS technique can be similarly applied to gradually reduce the voltage level of integrated circuit operation (e.g., from V1 to V2). In this case, the frequency of the circuit can be reduced to a lower frequency associated with the target voltage level (e.g., from F1 to F2) before the voltage ramp transition period that gradually lowers the voltage level, thus resulting in a performance impact.

[0039] During the voltage ramp transition, a voltage change affects one or more circuit parameters and / or system parameters, such as one or more delays (e.g., clock path delay and / or data path delay), impedance, reference voltage, data eye width, and / or data eye height. Parameter changes occurring during the voltage ramp transition are generally acceptable only if the circuitry associated with the changed voltage and frequency is operating in a low-performance mode (e.g., when lower frequencies are acceptable). For example, Figures 3A to 3B Examples of DDR circuits are illustrated that may undergo substantial changes in one or more parameters or characteristics, such as delay, impedance, reference voltage, data eye width, data eye height, and / or performance, during voltage ramp transitions (e.g., when DDR data traffic is in progress). However, the DDR circuits are provided merely as examples of circuits that may undergo parameter changes during voltage ramp transitions, and some aspects described herein are generally applicable to any suitable circuit that may undergo changes in one or more parameters affecting performance during voltage ramp transitions.

[0040] like Figures 3A to 3B As shown, the DDR circuitry may include a system-on-chip (SoC) component 320 corresponding to a DDR PHY component (e.g., physical layer interface circuitry), wherein the SoC component 320 may include a set of I / O drivers (or I / O transmitters (Tx)) 322. In some aspects, when the SoC component 320 interacts with a memory device (such as a DRAM device), the DDR PHY component may be included in the controller of the memory device (e.g., Figure 1 and / or Figure 2 In the controller 130). For example... Figures 3A to 3B As further shown, I / O driver 322 can deliver one or more signals (such as write clock signal 330, denoted as WCK, and data signal 332, denoted as DQ[x]) to DRAM device 340 (e.g., in a package or on a board housing SoC component 320 and DRAM device 340) that intersects with SoC component 320. Furthermore, it should be understood that the relationship between WCK-DQ (or clock-data) signals is merely an example (e.g., a similar example could be the CK-CA relationship of the clock on the command-address (CA) bus of a strobe / latch memory device). Figures 3A to 3BAs further shown, the DRAM device 340 may include a set of I / O receivers (Rx) 342 that receive signals provided by the I / O driver 322 of the SoC component 320. For example, as shown, the DRAM device 340 includes a first I / O receiver 342 that receives a write clock signal 330 and a second I / O receiver that receives a data strobe signal 332. In some aspects, the first I / O receiver 342 may provide the write clock signal 330 to a latch or register (D) via a clock tree 344 associated with a clock path delay Tclk (e.g., to temporarily latch the bit within a loop before passing it to the internal structure of the memory device). As indicated by reference numeral 346, the second I / O receiver 342 may provide the data strobe signal 332 to the latch / register D via a data path associated with a data path delay Td.

[0041] Typically, the DRAM clock path delay Tclk and DRAM data path delay Td are not balanced due to architectural considerations. The calibrated delay circuitry 350 of the SoC component 320 compensates for the {Tclk-Td} imbalance and adds a T / 4 (quarter-cycle) offset to position the gating clock in the middle of the data bit. For example, in a DRAM device, the clock path delay Tclk is unbalanced with the data path delay Td because the DRAM clock distribution for all bits requires buffering and routing (e.g., the clock path delay is long), while each DQ data bit has a latch receiver close to the data input, resulting in a very short data path delay (e.g., relative to the clock path delay). Therefore, the SoC component 320 can be configured to compensate for the offset {Tclk-Td} imbalance in the DRAM device and position the gating clock in the middle of the data eye diagram. For example, in some aspects, the SoC component 320 may include the calibrated delay circuitry 350, which can provide a fixed delay based on a closed-loop hardware-based and / or software-based calibration process. For example, as... Figure 3AAs indicated by reference numeral 352 in the figure, the calibrated delay circuit 350 can be calibrated to compensate for a fixed offset (or delay difference) {Tclk-Td} in the DRAM device. Specifically, as shown by reference numeral 352, the calibrated delay circuit 350 is calibrated to compensate for the offset {Tclk-Td} outside the voltage ramp transition period, such that the strobe clock is provided in the middle of the data bits. However, when the voltage supplied to the DRAM device 340 changes (e.g., increases or decreases) from a first voltage level to a second voltage level during the voltage ramp transition period, the changed voltage causes changes in the delay associated with the clock path and the delay associated with the data path. Therefore, the change in the clock-data relationship {Tclk-Td} caused by the voltage at the input of latch D can result in timing failures. For example, as shown by reference numeral 354, the associated change in voltage and delay difference that occurs during the voltage ramp transition period causes the gating clock to shift away from the center of the data bit (e.g., towards the right end in the illustrated example, potentially reaching a point that violates the set or hold time constraints of latch / register D). Furthermore, as further shown by reference numeral 352, the voltage change during the voltage ramp transition period causes data eye diagram distortion, which is compressed and therefore associated with poor performance relative to a calibrated data eye diagram (e.g., due to duty cycle distortion).

[0042] Therefore, one way to address potential performance degradation during voltage ramp transitions is to mitigate the timing or other performance impacts caused by parameter changes occurring during the voltage ramp transition period. For example, one potential approach is to reduce the timing impact associated with changes in {Tclk-Td} in the system budget associated with DRAM device 340, where {Tclk-Td} represents the difference between the delay associated with clock path delay Tclk and the delay associated with data path delay Td. For instance, during a voltage ramp transition period where the voltage level increases or decreases from a first voltage level to a second voltage level, SoC component 320 and / or DRAM device 340 may operate at a lower frequency to mitigate the timing impact associated with changes in {Tclk-Td} occurring during the voltage ramp transition period. However, this approach results in performance degradation during the voltage ramp transition period.

[0043] Therefore, some aspects described herein relate to dynamic circuit calibration techniques that can be applied during voltage ramp transition periods. For example, as described herein and as... Figure 3B As shown, an electronic device employing DVFS technology may include a calibration controller 360 that can compensate for changes in one or more parameters affecting the performance of an integrated circuit during the voltage ramp transition period. For example, as Figure 3BAs shown, calibration controller 360 may be coupled to SoC component 320 to allow control of calibrated delay circuitry 350, Tx element 322, and / or any other component or device of SoC component 320. Additionally or alternatively, calibration controller 360 may be coupled to DRAM device 340 to allow control of Rx element 342, clock tree 344, and / or any other component or device of DRAM device 340. In some aspects, calibration controller 360 may be implemented in hardware, software, firmware, or any suitable combination thereof. Furthermore, in some aspects, calibration controller 360 may be a single controller or multiple controllers for calibrating or otherwise controlling one or more passive circuits during a voltage ramp transition period. For example, calibration controller 360 may detect the start of a voltage ramp transition period and may apply one or more techniques during the voltage ramp transition period to adjust one or more parameters affecting the performance of the integrated circuit to restore those parameters to an optimal state (e.g., similar to or approximating a condition where the gating clock is set at the center of the calibrated data eye diagram). For example, when the voltage supplied to the integrated circuit changes, the calibration controller 360 can dynamically adjust one or more I / O driver codes to compensate for impedance changes that vary with the changing voltage. Additionally or alternatively, the calibration controller 360 can dynamically adjust one or more parameters of the I / O receiver 342, such as an input reference (or Vref) offset. Additionally or alternatively, the calibration circuitry can dynamically compensate for one or more parameters (such as delay, reference voltage, data eye width, data eye height, and / or other suitable parameters) that vary with the changing voltage during the voltage ramp transition period to improve performance during the voltage ramp transition period.

[0044] For example, such as Figure 3BAs shown, at block 362, calibration controller 360 can detect the start of a voltage ramp transition period in which DVFS technology is applied to change the operating voltage of an integrated circuit (e.g., DRAM device 340) from a first voltage to a second voltage, during which a change in one or more parameters affecting the performance associated with the integrated circuit occurs. For example, one or more delays, impedances, reference voltages, data eye widths, and / or other parameters may change during the voltage ramp transition period, so calibration controller 360 can detect the start of the voltage ramp transition period to determine whether and / or when to trigger a dynamic calibration mode. For example, before, after, or between voltage ramp transition periods, calibration controller 360 can periodically calibrate one or more delays, impedances, reference voltages, data eye widths, data eye heights, and / or other parameters affecting the performance of the integrated circuit based on a constant or relatively stable voltage at which the integrated circuit operates outside of voltage ramp transition periods. However, during the voltage ramp transition period, the calibration controller 360 may need to calibrate (e.g., compensate) for changes in one or more delays, impedances, reference voltages, data eye widths, and / or other parameters that affect the performance of the integrated circuit, based on the changing voltage.

[0045] Therefore, as shown in box 362, the calibration controller 360 can detect the start of a voltage ramp transition period to determine whether and / or when to initiate a dynamic calibration mode in which one or more delays, impedances, reference voltages, data eye widths, data eye heights, and / or other parameters affecting the performance of the integrated circuit are dynamically calibrated to compensate for voltage changes during the voltage ramp transition period. For example, in some aspects, the calibration controller 360 may include or be coupled to a voltage sensor that measures the voltage supplied to the dynamically calibrated DRAM device 340 (or other integrated circuit). Additionally or alternatively, the DRAM device 340 or SoC component 320 may obtain local circuit measurements indicating the voltage supplied to the dynamically calibrated DRAM device 340 (or other integrated circuit). In such cases, a voltage sensor or local circuit measurement can provide a signal or other suitable information (e.g., from circuitry or devices involved in the DVFS orchestration) indicating the voltage supplied to the DRAM device 340 to the calibration controller 360. The calibration controller 360 can then use this signal or other suitable information (e.g., based on an increase or decrease in the operating voltage) to detect the start of a voltage ramp transition period. Additionally or alternatively, a module or component controlling a power management integrated circuit (PMIC) used to set the operating voltage of the integrated circuit can generate a signal indicating when a voltage ramp transition period has begun or ended, which the calibration controller 360 can use to detect the start of a voltage ramp transition period. Additionally or alternatively, the SoC (DDR PHY) component 320 and the circuitry controlling the DVFS (e.g., including the PMIC) can be synchronized at the SoC level, so that the SoC component 320 and the circuitry controlling the DVFS can exchange synchronization messages that transmit the timing of the start and end of the voltage ramp transition period to the SoC component 320 and the associated calibration controller 360.

[0046] like Figure 3B Further shown, at block 364, the calibration controller 360 can dynamically compensate for changes in one or more parameters affecting the performance of the integrated circuit during the voltage ramp transition period. Specifically, during the voltage ramp transition period, the calibration controller 360 can dynamically compensate for changes in one or more delays, impedances, reference voltages, data eye widths, data eye heights, and / or other parameters associated with the integrated circuit that vary according to the voltage change during the voltage ramp transition period. For example, the reference... Figures 3A to 3BThe example circuit shown requires calibrating the I / O driver 322 associated with the SoC component 320 to the precise impedance of the interface between the SoC component 320 and the DRAM device 340 for high-speed operation with adequate signal integrity. However, when the I / O supply voltage changes during the voltage ramp transition period, the impedance of the I / O driver 322 changes, leading to signal integrity degradation and potential system failure. Furthermore, the I / O receiver 342 in the DRAM device 340 may face similar issues when the I / O supply voltage changes due to voltage variations during the voltage ramp transition period. Therefore, in one example of dynamically compensating for parameter changes occurring during the voltage ramp transition period, the calibration controller 360 may dynamically change or adjust the impedance associated with the I / O driver 322, which varies according to the voltage change during the voltage ramp transition period, and / or dynamically change or adjust the Vref offset or other parameters of the I / O receiver 342, which vary according to the voltage change during the voltage ramp transition period. For example, in some aspects, the calibration controller 360 may trigger a fast I / O calibration mode that operates only during voltage ramp transition periods, and may increment or decrement one or more I / O codes associated with I / O driver 322 and / or I / O receiver 342 multiple times during the voltage transition period (e.g., from V1 to V2). For example, the I / O codes may be incremented or decremented according to the changing voltage to constrain the impedance of I / O driver 322 and / or the Vref offset of I / O receiver 342 from optimal values ​​(e.g., associated with a calibrated data eye diagram) to a maximum extent. Additionally or alternatively, one or more impedance codes of I / O driver 322 may be precalibrated for the initiating voltage and target voltage (e.g., for V1 and V2) and for one or more intermediate voltages between the initiating voltage and the target voltage, and the I / O driver 322 may be programmed at regular intervals using the precalibrated impedance codes during voltage ramp transition periods. For example, in some aspects, the calibration controller 360 may store or access a lookup table (LUT) containing pre-calibrated values ​​of one or more parameters, which can be retrieved and used during a voltage ramp transition period to dynamically compensate for one or more parameters. For example, in some aspects, the calibration controller 360 may monitor one or more parameters of an integrated circuit undergoing a voltage ramp transition period, wherein the value of the monitored parameter indicates the current state of the voltage ramp transition period based on a comparison with an item in the LUT table. In this way, the calibration controller 360 can determine the current voltage and retrieve or otherwise obtain appropriate pre-calibrated values ​​to compensate for one or more parameters that change according to the changing voltage (e.g., dynamic calibration need not be run in task mode, which could lead to a degraded user experience or other adverse effects).

[0047] Therefore, as described herein, the calibration controller 360 may typically employ one or more techniques to calibrate one or more parameters affecting the performance of the integrated circuit during the voltage ramp transition period to maintain the parameters as close as possible to their optimal state (e.g., such that a gating clock signal is provided at the center of a data bit having a calibrated data eye diagram width). For example, some aspects described herein relate to example calibration techniques that can be used to dynamically calibrate one or more impedances during the voltage ramp transition period, and the calibration controller 360 may also apply one or more suitable techniques to dynamically calibrate other parameters that change according to the changing voltage during the voltage ramp transition period (e.g., one or more delays, reference voltages, data eye diagram widths, and / or data eye diagram heights, etc.). For example, when a dynamic calibration mode is triggered (e.g., in response to detecting the start of a voltage ramp transition period), the calibration controller 360 may receive, obtain, or otherwise determine the voltage at which the integrated circuit operates at various time instances (e.g., based on signals from voltage sensors, local circuit measurements, signals from PMIC controllers, or voltage scaling tables), and the calibration controller 360 may initiate one or more new or updated settings for one or more parameters calibrated according to the voltage at each time instance. For example, the calibration controller 360 can periodically check the current voltage at which the integrated circuit is operating and can initiate one or more new or updated settings at each time interval. Additionally or alternatively, the calibration controller 360 can initiate one or more new or updated settings when the difference between the current voltage and the most recent setting update meets a threshold.

[0048] like Figure 3B Further shown, at block 366, the calibration controller 360 may exit dynamic calibration mode in response to detecting the end of a voltage ramp transition period (e.g., indicating that the voltage has ramped up or down to a target level). For example, as described in more detail elsewhere herein, the calibration controller 360 may detect the end of a voltage ramp transition period based on signals provided by voltage sensors that measure and / or indicate the current voltage, local circuit measurements indicating the current voltage, signals from modules or components controlling the PMIC used to set the operating voltage, and / or based on synchronization between the calibration controller 360 and other SoC or PMIC components configured to manage or coordinate DVFS transitions. For example, as Figure 3B As indicated by reference numeral 370 in the accompanying drawings, the calibration circuit can perform regular calibration at periodic intervals outside of periods when the voltage is gradually increasing or decreasing (e.g., indicated by solid vertical arrows). Furthermore, when the calibration controller 360 detects a voltage ramp transition period (e.g., during...), Figure 3BAt the start of an increase in operating voltage (as depicted in the example), the calibration controller 360 can trigger a dynamic calibration mode in which one or more parameters of the integrated circuit that vary according to the voltage change during the voltage ramp transition period are calibrated (e.g., adjusted). Figure 3B In the diagram, the fast calibration mode during the voltage ramp transition period, illustrated by the dashed vertical arrow, occurs at more frequent time intervals during the voltage ramp transition period, or when the difference between the current voltage and the voltage associated with a previous calibration example meets a threshold. This fast calibration mode is in contrast to the regular calibration mode, illustrated by the solid arrow, which occurs at less frequent time intervals. In some aspects, calibrations associated with the dynamic calibration mode can occur at periodic intervals, and dynamic calibration can occur more frequently during the voltage ramp transition period relative to periods of constant or stable voltage. Additionally or alternatively, dynamic calibration can occur at non-periodic time intervals (e.g., when the transition voltage passes through equidistant voltage points and / or when a circuit and / or system parameter change meets (e.g., exceeds) a threshold). Furthermore, the frequency (e.g., periodicity) of dynamic calibration (e.g., updates) can be varied proportionally to the rate of voltage change, such that faster voltage changes can be compensated for by faster dynamic calibration updates (and vice versa). Furthermore, as... Figure 3B As shown, the calibration controller 360 can return to regular periodic calibration after the voltage ramp transition period has ended (indicated by the return indicated by the vertical arrow pointing towards the solid line). In this way, by implementing a dynamic calibration mode that dynamically compensates for changes in one or more parameters affecting the performance associated with the integrated circuit during the voltage ramp transition period, the performance of the integrated circuit can be improved before the frequency of the integrated circuit can be increased or decreased to a target level corresponding to the target voltage level of the voltage ramp transition period. Thus, the calibration circuit can avoid or reduce the performance and / or power effects that would otherwise occur when voltage changes during the voltage ramp transition period cause changes in one or more parameters associated with the integrated circuit.

[0049] As indicated above, this is provided as an example only. Figures 3A to 3B Other examples can be found in relation to... Figures 3A to 3B The descriptions are different.

[0050] Figure 4 This is a flowchart of an example process 400 associated with dynamic circuit calibration during voltage change transitions according to this disclosure. In some aspects, Figure 4 One or more process frames are executed by calibration circuitry (e.g., calibration controller 360). In some respects, Figure 4One or more process frames are executed by another device or group of devices, such as electronic devices (e.g., electronic device 100, memory device 120, or the like), which is separate from or includes the calibration circuit.

[0051] like Figure 4 As shown, process 400 may include: detecting the start of a voltage ramp transition period associated with changing the voltage for operating the integrated circuit from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage during the voltage ramp transition period results in a change in one or more parameters affecting the performance associated with the integrated circuit (block 410). For example, calibration circuitry may detect the start of a voltage ramp transition period associated with changing the voltage for operating the integrated circuit from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage during the voltage ramp transition period results in a change in one or more parameters affecting the performance associated with the integrated circuit, as described above.

[0052] like Figure 4 As further shown, process 400 may include: triggering a dynamic calibration mode in response to detecting the start of the voltage ramp transition period, the dynamic calibration mode compensating for the change in one or more parameters affecting the performance associated with the integrated circuit during the voltage ramp transition period (box 420). For example, calibration circuitry may trigger a dynamic calibration mode in response to detecting the start of the voltage ramp transition period, the dynamic calibration mode compensating for the change in one or more parameters affecting the performance associated with the integrated circuit during the voltage ramp transition period, as described above.

[0053] like Figure 4 As further shown, process 400 may include exiting the dynamic calibration mode in response to detecting the end of the voltage ramp transition period (block 430). For example, the calibration circuit may exit the dynamic calibration mode in response to detecting the end of the voltage ramp transition period, as described above.

[0054] Process 400 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in conjunction with one or more other processes described elsewhere herein.

[0055] In a first aspect, the dynamic calibration mode calibrates one or more impedance codes associated with one or more I / O devices based on the voltage during the voltage ramp transition period, in order to compensate for changes in the one or more parameters that affect the performance associated with the integrated circuit.

[0056] In the second aspect, alone or in combination with the first aspect, the dynamic calibration mode adjusts the value of the one or more impedance codes associated with the one or more I / O devices multiple times during the voltage ramp transition period.

[0057] In a third aspect, alone or in combination with one or more of the first and second aspects, the dynamic calibration mode adjusts the values ​​of one or more parameters at periodic intervals during the voltage ramp transition period based on pre-calibrated values ​​associated with one or more of the first voltage, the second voltage, or one or more intermediate voltages between the first voltage and the second voltage.

[0058] In the fourth aspect, either alone or in combination with one or more of the first to third aspects, the one or more precalibrated values ​​are stored in a lookup table.

[0059] In a fifth aspect, alone or in combination with one or more of the first to fourth aspects, the start and end of the voltage ramp transition period are detected based on an indicator provided by a voltage sensor associated with the integrated circuit or a local measurement associated with the integrated circuit.

[0060] In a sixth aspect, alone or in combination with one or more of the first to fifth aspects, the start and end of the voltage ramp transition period are detected based on signals received from components of the control power management integrated circuit.

[0061] In a seventh aspect, alone or in combination with one or more of the first to sixth aspects, the start and end of the voltage ramp transition period are detected based on a signal related to the switching of the frequency of operation of the integrated circuit from a first frequency to a second frequency.

[0062] In the eighth aspect, alone or in combination with one or more of the first to seventh aspects, the voltage ramp transition period is associated with increasing the voltage at which the integrated circuit is operated from the first voltage to the second voltage.

[0063] In a ninth aspect, alone or in combination with one or more of the first to eighth aspects, the voltage ramp transition period is associated with reducing the voltage at which the integrated circuit is operated from the first voltage to the second voltage.

[0064] In the tenth aspect, alone or in combination with one or more of the first to ninth aspects, the one or more parameters compensated according to the voltage during the voltage ramp transition period include one or more delays, one or more impedances, one or more reference voltages, data eye width, or data eye height.

[0065] although Figure 4 An example box for process 400 is shown, but in some respects, it differs from... Figure 4Compared to the boxes depicted, process 400 includes additional boxes, fewer boxes, different boxes, or boxes arranged in a different manner. Additionally or alternatively, two or more boxes in the frame of process 400 may be executed in parallel.

[0066] Figure 5 This is a diagram illustrating an example system 500 that supports dynamic circuit calibration during voltage change transitions according to this disclosure. More specifically, as described herein, the dynamic circuit calibration mechanism and corresponding methods or processes described herein can be used in any circuit, including but not limited to microprocessor-based circuits, systems, or other suitable electronic devices. For example, electronic devices that may include or otherwise employ the dynamic circuit calibration mechanism described herein may include, but are not limited to, mobile phones, cellular phones, computers, portable computers, desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, wireless equipment, satellite wireless equipment, digital music players, portable music players, digital video players, digital video disc (DVD) players, or portable digital video players, etc.

[0067] For example, in some aspects, Figure 5 An example system 500 is illustrated, which can employ the dynamic circuit calibration mechanism and corresponding methods and / or processes described in more detail herein. For example, such as Figure 5 As shown, system 500 may include CPU 510, which includes cache 516 and processor 512, which may include components configured to perform the functions described herein. Figures 3A to 3B The calibration controller 514 describes one or more operations. Furthermore, although... Figure 5 As illustrated, calibration controller 514 is included within processor 512, but calibration controller 514 may reside in any suitable location within electronic device 500, such as within an integrated circuit controlled using DVFS technology and / or on an external integrated circuit. Additionally or alternatively, calibration controller 514 may be configured to perform one or more processes described herein, such as Figure 4 The process is 400. Additional or alternative land, Figure 5 One or more components shown may be implemented, at least in part, as software stored in one or more memories. For example, a component (or a portion thereof) may be implemented as instructions or code stored in a non-transitory computer-readable medium and may be executed by one or more controllers or one or more processors to perform the function or operation of the component.

[0068] For example, in some aspects, the calibration controller 514 may be configured to: detect the start of a voltage ramp transition period associated with changing the voltage of an integrated circuit from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage during the voltage ramp transition period results in a change in one or more parameters affecting the performance associated with the integrated circuit; trigger a dynamic calibration mode in response to detecting the start of the voltage ramp transition period, the dynamic calibration mode compensating for the change in the one or more parameters affecting the performance associated with the integrated circuit during the voltage ramp transition period; and exit the dynamic calibration mode in response to detecting the end of the voltage ramp transition period.

[0069] In some respects, CPU 510 may be coupled to system bus 520, which may interconnect various other devices or components included in system 500. CPU 510 may exchange address, control, and data information via system bus 520 to communicate with other devices or components included in system 500. For example, as... Figure 5 As illustrated, the devices or components included in system 500 may include: a memory subsystem 530, which may include static memory 532 and / or dynamic memory 534; one or more input devices 522; one or more output devices 524; a network interface device 526; and a display controller 540. In various embodiments, input devices 522 may include any suitable input device type, such as input keys, switches, or voice processors. Output devices 524 may similarly include any suitable output device type, such as audio, video, or other visual indicators. Network interface device 526 may be any device configured to allow the exchange of data to and from network 580, which may include any suitable network type, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wide area networks (WLANs), and the Internet. Network interface device 526 may support any type of communication protocol desired. CPU 510 accesses memory subsystem 530 via system bus 520.

[0070] In some aspects, CPU 510 can also access display controller 540 via system bus 520 to control information sent to display 570. Display controller 540 may include memory controller 542 and memory 544, which stores data sent to display 570 in response to communication with CPU 510. Display controller 540 sends information to display 570 for display via video processor 560, which processes the information to display it in a format suitable for display 570. Display 470 may include any suitable display type, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), or plasma display.

[0071] Figure 5 The number and arrangement of components shown are provided as an example. In reality, with... Figure 5 Compared to the components shown, there may be additional components, fewer components, different components, or components arranged in a different manner. Furthermore, Figure 5 The two or more components shown can be implemented within a single component, or Figure 5 The single component shown can be implemented as multiple distributed components. Additionally or alternatively, Figure 5 The component collection (one or more components) shown can be executed as described by Figure 5 The other set of components shown performs one or more functions.

[0072] The following provides an overview of some aspects of this disclosure: Aspect 1: A method performed by an electronic device, the method comprising: detecting the start of a voltage ramp transition period associated with changing a voltage for operating an integrated circuit from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage during the voltage ramp transition period results in a change of one or more parameters affecting performance associated with the integrated circuit; triggering a dynamic calibration mode in response to detecting the start of the voltage ramp transition period, the dynamic calibration mode compensating for the change of the one or more parameters affecting the performance associated with the integrated circuit during the voltage ramp transition period; and exiting the dynamic calibration mode in response to detecting the end of the voltage ramp transition period.

[0073] Aspect 2: According to the method of aspect 1, wherein the dynamic calibration mode calibrates one or more impedance codes associated with one or more I / O devices based on the voltage of the integrated circuit operation during the voltage ramp transition period to compensate for changes in the one or more parameters affecting the performance associated with the integrated circuit.

[0074] Aspect 3: According to the method of aspect 2, wherein the dynamic calibration mode adjusts the value of the one or more impedance codes associated with the one or more I / O devices multiple times during the voltage ramp transition period.

[0075] Aspect 4: According to the method of aspect 1, wherein the dynamic calibration mode adjusts the values ​​of the one or more parameters at periodic intervals during the voltage ramp transition period based on a pre-calibration value associated with one or more of the first voltage, the second voltage, or one or more intermediate voltages between the first voltage and the second voltage.

[0076] Aspect 5: According to the method of aspect 4, wherein the one or more pre-calibration values ​​are stored in a lookup table.

[0077] Aspect 6: The method according to any one of Aspects 1 to 5, wherein the start and end of the voltage ramp transition period are detected based on an indicator provided by a voltage sensor associated with the integrated circuit or a local measurement associated with the integrated circuit.

[0078] Aspect 7: The method according to any one of Aspects 1 to 6, wherein the start and end of the voltage ramp transition period are detected based on a signal received from a component of the control power management integrated circuit.

[0079] Aspect 8: The method according to any one of Aspects 1 to 7, wherein the start and end of the voltage ramp transition period are detected based on a signal related to switching the frequency of operation of the integrated circuit from a first frequency to a second frequency.

[0080] Aspect 9: The method according to any one of Aspects 1 to 8, wherein the voltage ramp transition period is associated with increasing the voltage at which the integrated circuit operates from the first voltage to the second voltage.

[0081] Aspect 10: The method according to any one of Aspects 1 to 9, wherein the voltage ramp transition period is associated with reducing the voltage at which the integrated circuit operates from the first voltage to the second voltage.

[0082] Aspect 11: The method according to any one of Aspects 1 to 10, wherein the one or more parameters compensated according to the voltage during the voltage ramp transition period include one or more delays, one or more impedances, one or more reference voltages, data eye width, or data eye height.

[0083] Aspect 12: An electronic device for wireless communication, the electronic device comprising: one or more memories; and one or more processors coupled to the one or more memories, the one or more processors being configured to cause the electronic device to: detect the start of a voltage ramp transition period associated with changing a voltage for operating an integrated circuit from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage during the voltage ramp transition period results in a change of one or more parameters affecting the performance associated with the integrated circuit; trigger a dynamic calibration mode in response to detecting the start of the voltage ramp transition period, the dynamic calibration mode compensating for the change of the one or more parameters affecting the performance associated with the integrated circuit during the voltage ramp transition period; and exit the dynamic calibration mode in response to detecting the end of the voltage ramp transition period.

[0084] Aspect 13: The electronic device according to aspect 12, wherein the dynamic calibration mode calibrates one or more impedance codes associated with one or more I / O devices according to the voltage of operation of the integrated circuit during the voltage ramp transition period to compensate for changes in the one or more parameters affecting the performance associated with the integrated circuit.

[0085] Aspect 14: The electronic device according to aspect 13, wherein the dynamic calibration mode adjusts the value of the one or more impedance codes associated with the one or more I / O devices multiple times during the voltage ramp transition period.

[0086] Aspect 15: The electronic device according to aspect 12, wherein the dynamic calibration mode adjusts the values ​​of the one or more parameters at periodic intervals during the voltage ramp transition period based on a pre-calibration value associated with one or more of the first voltage, the second voltage, or one or more intermediate voltages between the first voltage and the second voltage.

[0087] Aspect 16: The electronic device according to aspect 15, wherein one or more pre-calibration values ​​are stored in a lookup table.

[0088] Aspect 17: An electronic device according to any one of Aspects 12 to 16, wherein the start and end of the voltage ramp transition period are detected based on an indicator provided by a voltage sensor associated with the integrated circuit or a local measurement associated with the integrated circuit.

[0089] Aspect 18: An electronic device according to any one of Aspects 12 to 17, wherein the start and end of the voltage ramp transition period are detected based on a signal received from a component of a control power management integrated circuit.

[0090] Aspect 19: An electronic device according to any one of Aspects 12 to 18, wherein the start and end of the voltage ramp transition period are detected based on a signal related to switching the frequency of operation of the integrated circuit from a first frequency to a second frequency.

[0091] Aspect 20: An electronic device according to any one of Aspects 12 to 19, wherein the voltage ramp transition period is associated with increasing the voltage at which the integrated circuit operates from the first voltage to the second voltage.

[0092] Aspect 21: An electronic device according to any one of Aspects 12 to 20, wherein the voltage ramp transition period is associated with reducing the voltage at which the integrated circuit operates from the first voltage to the second voltage.

[0093] Aspect 22: The method according to any one of Aspects 12 to 21, wherein the one or more parameters compensated according to the voltage during the voltage ramp transition period include one or more delays, one or more impedances, one or more reference voltages, data eye width, or data eye height.

[0094] Aspect 23: A non-transitory computer-readable medium storing an instruction set for wireless communication, the instruction set comprising: one or more instructions, which, when executed by one or more processors of an electronic device, cause the electronic device to: detect the start of a voltage ramp transition period associated with changing a voltage for operating an integrated circuit from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage during the voltage ramp transition period results in a change of one or more parameters affecting the performance associated with the integrated circuit; trigger a dynamic calibration mode in response to detecting the start of the voltage ramp transition period, the dynamic calibration mode compensating for the change of the one or more parameters affecting the performance associated with the integrated circuit during the voltage ramp transition period; and exit the dynamic calibration mode in response to detecting the end of the voltage ramp transition period.

[0095] Aspect 24: The non-transitory computer-readable medium according to aspect 23, wherein the dynamic calibration mode calibrates one or more impedance codes associated with one or more I / O devices according to the voltage of the integrated circuit operation during the voltage ramp transition period to compensate for changes in the one or more parameters affecting the performance associated with the integrated circuit.

[0096] Aspect 25: A non-transitory computer-readable medium according to any one of Aspects 23 to 24, wherein the start and end of the voltage ramp transition period are detected based on an indicator provided by a voltage sensor associated with the integrated circuit or a local measurement associated with the integrated circuit.

[0097] Aspect 26: A non-transitory computer-readable medium according to any one of aspects 23 to 25, wherein the start and end of the voltage ramp transition period are detected based on a signal received from a component of a control power management integrated circuit.

[0098] Aspect 27: A non-transitory computer-readable medium according to any one of aspects 22 to 26, wherein the start and end of the voltage ramp transition period are detected based on a signal related to switching the frequency of operation of the integrated circuit from a first frequency to a second frequency.

[0099] Aspect 28: A non-transitory computer-readable medium according to any one of aspects 23 to 27, wherein the voltage ramp transition period is associated with increasing or decreasing the voltage at which the integrated circuit operates from the first voltage to the second voltage.

[0100] Aspect 29: An apparatus for wireless communication, the apparatus comprising: means for detecting the start of a voltage ramp transition period associated with changing a voltage for operating an integrated circuit from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage during the voltage ramp transition period results in a change of one or more parameters affecting performance associated with the integrated circuit; means for triggering a dynamic calibration mode in response to detecting the start of the voltage ramp transition period, the dynamic calibration mode compensating for the change of the one or more parameters affecting the performance associated with the integrated circuit during the voltage ramp transition period; and means for exiting the dynamic calibration mode in response to detecting the end of the voltage ramp transition period.

[0101] Aspect 30: The apparatus according to aspect 29, wherein the dynamic calibration mode calibrates one or more impedance codes associated with one or more I / O devices based on the voltage during the voltage ramp transition period to compensate for changes in the one or more parameters affecting the performance associated with the integrated circuit.

[0102] Aspect 31: The apparatus according to any one of Aspects 29 to 30, wherein the start and end of the voltage ramp transition period are detected based on one or more of the following: an indicator provided by a voltage sensor associated with the integrated circuit, a local measurement associated with the integrated circuit, a signal received from a component of a control power management integrated circuit, or a signal associated with switching the frequency of operation of the integrated circuit from a first frequency to a second frequency.

[0103] Aspect 32: The apparatus according to any one of aspects 29 to 31, wherein the voltage ramp transition period is associated with increasing or decreasing the voltage at which the integrated circuit operates from the first voltage to the second voltage.

[0104] Aspect 33: A system configured to perform one or more of the operations described in aspects 1 to 32.

[0105] Aspect 34: An apparatus comprising: components for performing one or more of the operations described in aspects 1 to 32.

[0106] Aspect 35: A non-transitory computer-readable medium storing an instruction set comprising one or more instructions that, when executed by a device, cause the device to perform one or more of the operations described in aspects 1 to 32.

[0107] Aspect 36: A computer program product comprising: instructions or code for performing one or more of the operations described in aspects 1 to 32.

[0108] While the foregoing disclosure provides examples and descriptions, it is not intended to be exhaustive or to limit all aspects to the precise form disclosed. Modifications and variations may be made based on the foregoing disclosure, or from various practices.

[0109] As used herein, the term "component" is intended to be interpreted broadly as hardware and / or a combination of hardware and software. Whether referred to as software, firmware, middleware, microcode, hardware description language, or other names, "software" should be interpreted broadly as meaning instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, and / or functions, etc. As used herein, a "processor" is implemented in hardware and / or a combination of hardware and software. It will be apparent to those skilled in the art that the systems and / or methods described herein can be implemented in various forms of hardware and / or combinations of hardware and software. The actual dedicated control hardware or software code used to implement these systems and / or methods is not limiting in any way. Therefore, no specific software code is referenced in this document to describe the operation and behavior of the systems and / or methods, as those skilled in the art will understand that the software and hardware can be designed, at least in part, based on the descriptions herein, to implement the systems and / or methods.

[0110] As used in this article, depending on the context, "meeting the threshold" can mean a value greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, not equal to the threshold, etc.

[0111] Although specific combinations of features are set forth in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of various aspects. Many of these features may be combined in ways not specifically set forth in the claims and / or not disclosed in the specification. The disclosure of various aspects includes each dependent claim in combination with each other claim in the set of claims. As used herein, the phrase referring to “at least one of” the list of items means any combination of these items, including a single member. As an example, “at least one of a, b, or c” is intended to cover: a, b, c, a+b, a+c, b+c, and a+b+c, as well as any combination having multiple identical elements (e.g., a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c, and c+c+c, or any other ordering of a, b, and c).

[0112] No element, action, or instruction used herein should be construed as essential or necessary unless explicitly stated otherwise. Furthermore, as used herein, the articles “a” and “an” are intended to include one or more items and are used interchangeably with “one or more.” Furthermore, as used herein, the article “the” is intended to include one or more items mentioned in connection with the article “the” and is used interchangeably with “one or more.” Furthermore, as used herein, the terms “group” and “cluster” are intended to include one or more items and are used interchangeably with “one or more.” If only one item is desired, the phrase “only one” or similar terminology will be used. Furthermore, as used herein, the terms “have,” “possess,” “have,” etc., are intended to be open-ended terms that do not limit the elements they modify (e.g., an element “having” A may also have B). Furthermore, the phrase “based on” is intended to mean “at least partially based on” unless otherwise explicitly stated. Furthermore, as used herein, the term “or” is intended to be inclusive when used in a series and is interchangeable with “and / or” unless otherwise explicitly stated (e.g., in combination with “any” or “only one”).

Claims

1. A method performed by an electronic device, the method comprising: The detection is associated with the start of a voltage ramp transition period that changes the voltage of an integrated circuit from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage during the voltage ramp transition period results in a change of one or more parameters that affect the performance associated with the integrated circuit; A dynamic calibration mode is triggered in response to the detection of the start of the voltage ramp transition period, the dynamic calibration mode compensating for changes in one or more parameters that affect the performance associated with the integrated circuit during the voltage ramp transition period; as well as The dynamic calibration mode is exited in response to the detection of the end of the voltage ramp transition period.

2. The method of claim 1, wherein the dynamic calibration mode calibrates one or more impedance codes associated with one or more input / output (I / O) devices according to the voltage during the voltage ramp transition period, to compensate for changes in the one or more parameters affecting the performance associated with the integrated circuit.

3. The method of claim 2, wherein the dynamic calibration mode adjusts the value of the one or more impedance codes associated with the one or more I / O devices multiple times during the voltage ramp transition period.

4. The method of claim 1, wherein the dynamic calibration mode adjusts the values ​​of the one or more parameters at periodic intervals during the voltage ramp transition period based on a pre-calibration value associated with one or more of the first voltage, the second voltage, or one or more intermediate voltages between the first voltage and the second voltage.

5. The method of claim 4, wherein the one or more precalibration values ​​are stored in a lookup table.

6. The method of claim 1, wherein the start and end of the voltage ramp transition period are detected based on an indicator provided by a voltage sensor associated with the integrated circuit or a local measurement associated with the integrated circuit.

7. The method of claim 1, wherein the start and end of the voltage ramp transition period are detected based on a signal received from a component of the control power management integrated circuit.

8. The method of claim 1, wherein the start and end of the voltage ramp transition period are detected based on a signal related to switching the frequency of operation of the integrated circuit from a first frequency to a second frequency.

9. The method of claim 1, wherein the voltage ramp transition period is associated with increasing the voltage at which the integrated circuit operates from the first voltage to the second voltage.

10. The method of claim 1, wherein the voltage ramp transition period is associated with reducing the voltage at which the integrated circuit operates from the first voltage to the second voltage.

11. The method of claim 1, wherein the one or more parameters compensated according to the voltage during the voltage ramp transition period include one or more delays, one or more impedances, one or more reference voltages, data eye width, or data eye height.

12. An electronic device for wireless communication, the electronic device comprising: One or more memory units; and One or more processors, said one or more processors coupled to said one or more memories, said one or more processors being configured to cause the electronic device to: The detection is associated with the start of a voltage ramp transition period that changes the voltage of an integrated circuit from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage during the voltage ramp transition period results in a change of one or more parameters that affect the performance associated with the integrated circuit; A dynamic calibration mode is triggered in response to the detection of the start of the voltage ramp transition period, the dynamic calibration mode compensating for changes in one or more parameters that affect the performance associated with the integrated circuit during the voltage ramp transition period; as well as The dynamic calibration mode is exited in response to the detection of the end of the voltage ramp transition period.

13. The electronic device of claim 12, wherein the dynamic calibration mode calibrates one or more impedance codes associated with one or more input / output (I / O) devices according to the voltage during the voltage ramp transition period, to compensate for changes in the one or more parameters affecting the performance associated with the integrated circuit.

14. The electronic device of claim 13, wherein the dynamic calibration mode adjusts the value of the one or more impedance codes associated with the one or more I / O devices multiple times during the voltage ramp transition period.

15. The electronic device of claim 12, wherein the dynamic calibration mode adjusts the values ​​of the one or more parameters at periodic intervals during the voltage ramp transition period based on a pre-calibration value associated with one or more of the first voltage, the second voltage, or one or more intermediate voltages between the first voltage and the second voltage.

16. The electronic device of claim 15, wherein the one or more pre-calibration values ​​are stored in a lookup table.

17. The electronic device of claim 12, wherein the start and end of the voltage ramp transition period are detected based on an indicator provided by a voltage sensor associated with the integrated circuit or a local measurement associated with the integrated circuit.

18. The electronic device of claim 12, wherein the start and end of the voltage ramp transition period are detected based on a signal received from a component of the control power management integrated circuit.

19. The electronic device of claim 12, wherein the start and end of the voltage ramp transition period are detected based on a signal related to switching the frequency of operation of the integrated circuit from a first frequency to a second frequency.

20. The electronic device of claim 12, wherein the voltage ramp transition period is associated with increasing the voltage at which the integrated circuit operates from the first voltage to the second voltage.

21. The electronic device of claim 12, wherein the voltage ramp transition period is associated with reducing the voltage at which the integrated circuit operates from the first voltage to the second voltage.

22. The electronic device of claim 12, wherein the one or more parameters compensated according to the voltage during the voltage ramp transition period include one or more delays, one or more impedances, one or more reference voltages, data eye diagram width, or data eye diagram height.

23. A non-transitory computer-readable medium storing an instruction set for wireless communication, the instruction set comprising: One or more instructions, which, when executed by one or more processors of the electronic device, cause the electronic device to: The detection is associated with the start of a voltage ramp transition period that changes the voltage of an integrated circuit from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage during the voltage ramp transition period results in a change of one or more parameters that affect the performance associated with the integrated circuit; A dynamic calibration mode is triggered in response to the detection of the start of the voltage ramp transition period, the dynamic calibration mode compensating for changes in one or more parameters that affect the performance associated with the integrated circuit during the voltage ramp transition period; as well as The dynamic calibration mode is exited in response to the detection of the end of the voltage ramp transition period.

24. The non-transient computer-readable medium of claim 23, wherein the dynamic calibration mode calibrates one or more impedance codes associated with one or more input / output (I / O) devices according to the voltage of the integrated circuit operation during the voltage ramp transition period to compensate for changes in the one or more parameters affecting the performance associated with the integrated circuit.

25. The non-transient computer-readable medium of claim 23, wherein the start and end of the voltage ramp transition period are detected based on an indicator provided by a voltage sensor associated with the integrated circuit or a local measurement associated with the integrated circuit.

26. The non-transitory computer-readable medium of claim 23, wherein the start and end of the voltage ramp transition period are detected based on a signal received from a component of the control power management integrated circuit.

27. The non-transitory computer-readable medium of claim 23, wherein the start and end of the voltage ramp transition period are detected based on a signal related to switching the frequency of operation of the integrated circuit from a first frequency to a second frequency.

28. An apparatus for wireless communication, the apparatus comprising: A component for detecting the start of a voltage ramp transition period associated with changing the voltage for operating an integrated circuit from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage during the voltage ramp transition period results in a change in one or more parameters affecting the performance associated with the integrated circuit; Components for triggering a dynamic calibration mode in response to detecting the start of the voltage ramp transition period, the dynamic calibration mode compensating for changes in one or more parameters affecting the performance associated with the integrated circuit during the voltage ramp transition period; and A component for exiting the dynamic calibration mode in response to detecting the end of the voltage ramp transition period.

29. The apparatus of claim 28, wherein the dynamic calibration mode calibrates one or more impedance codes associated with one or more input / output (I / O) devices according to the voltage during the voltage ramp transition period, to compensate for changes in the one or more parameters affecting the performance associated with the integrated circuit.

30. The apparatus of claim 28, wherein the start and end of the voltage ramp transition period are detected based on one or more of the following: an indicator provided by a voltage sensor associated with the integrated circuit, a local measurement associated with the integrated circuit, a signal received from a component of the control power management integrated circuit, or a signal associated with switching the frequency of operation of the integrated circuit from a first frequency to a second frequency.

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