Data storage device and method for data processing optimization for compute storage

Abstract

A data storage device and method for data processing optimization for compute storage is disclosed. In one embodiment, a data storage device is provided that includes a memory and one or more processors. The one or more processors, individually or in combination, are configured to: receive data to be written to a data structure; analyzing the data for a predetermined pattern; writing the data into a plurality of storage positions in the memory; and writing, in the memory, information on which storage locations store the predetermined pattern. Other embodiments are disclosed.

Description

Cross-reference to related applications

[0001] This application claims the benefit and priority of U.S. Nonprovisional Patent Application Serial No. 18 / 640,166, filed April 19, 2024. Background Technology

[0002] Data storage devices can be used to store databases (or other data structures) that can be read by a host. When processing the database for data analysis, the host may need to perform value replacements (e.g., padding and / or replacing missing values ​​within the database when "Not a Number (NaN)" is written instead of a value). After the host reads the database from the data storage device, the host can replace NaN values ​​with some default value (such as 0 or the average column value). Attached Figure Description

[0003] Figure 1A This is a block diagram of the data storage device in the implementation plan.

[0004] Figure 1B This is a block diagram illustrating the storage module of an example implementation.

[0005] Figure 1C This is a block diagram illustrating a hierarchical storage system for an example implementation.

[0006] Figure 2A This is an example based on the implementation plan. Figure 1A The diagram illustrates the components of the controller for a data storage device.

[0007] Figure 2B This is an example based on the implementation plan. Figure 1A The diagram illustrates the components of a data storage device. Figure 3 This is a block diagram of the host and data storage devices in the implementation plan.

[0008] Figure 4 This is an example of the architecture of the implementation plan.

[0009] Figure 5 This is a flowchart of the write operation for the implementation plan.

[0010] Figure 6 This is a flowchart of the reading operation for the implementation plan. Detailed Implementation

[0011] The following embodiments generally relate to a data storage device and method for data processing optimization for computational storage. In one embodiment, a data storage device is provided, comprising a memory and one or more processors. The one or more processors are configured individually or in combination to: receive data to be written into a data structure; analyze the data against a predetermined pattern; write the data into a plurality of storage locations in the memory; and write information in the memory about which storage locations store the predetermined pattern.

[0012] In some implementations, one or more processors are further configured individually or in combination to: in response to receiving a request from the host to read a data structure, perform an immediate replacement of the predetermined pattern with a replacement pattern during the read operation using information about which storage locations store the predetermined pattern.

[0013] In some implementations, the request includes a computational read with a replacement; and one or more processors, individually or in combination, are further configured to: in response to receiving a request from the host to read a data structure without replacement, read data from memory and provide the data to the host without replacing the predetermined pattern with a replacement pattern.

[0014] In some implementations, the predetermined pattern includes a "non-numeric (NaN)" character, and the alternative pattern includes a number.

[0015] In some implementations, the predetermined pattern includes specific characters.

[0016] In some implementations, the predetermined pattern includes regular expressions.

[0017] In some implementations, the predetermined pattern includes a predefined bit sequence.

[0018] In some implementations, information about which storage locations store the predetermined pattern is stored in a page plus offset format.

[0019] In some implementations, information about which storage locations store the predetermined pattern is stored in a compressed format.

[0020] In some implementations, the predetermined pattern, alternative pattern, and / or alternative granularity are defined by the host providing the data to be stored in the data storage device.

[0021] In some implementations, the predetermined pattern is represented as the values ​​of key-value (KV) pairs.

[0022] In some implementations, the data structure includes a database.

[0023] In some implementations, the memory includes a three-dimensional memory.

[0024] In another embodiment, a method is provided to be performed in a data storage device including memory. The method includes: identifying a character set in data of a data structure to be stored in memory; storing information about the storage location of the character set in memory; and, in response to a request to read data from a host: using the information to replace the character set with a replacement character set; and providing the host with data including the replacement character set.

[0025] In some implementations, the method also includes notifying the host that the replacement character set has changed the length of the read payload.

[0026] In some implementations, the method also includes allocating an additional buffer to accommodate the changed length.

[0027] In some implementations, the method also includes reducing the whitespace defined in the comma-separated values ​​(CSV) file to accommodate the changed length.

[0028] In some implementations, the replacement character set uses a different buffer than the one used in standard read operations.

[0029] In some implementations, the data structure includes a database.

[0030] In another embodiment, a data storage device is provided, comprising: a memory; and means for performing instantaneous data replacement during a read operation of a data structure stored in the memory based on previously stored information identifying the location of the data to be replaced.

[0031] Other embodiments are possible, and each embodiment can be used alone or in combination. Therefore, various embodiments will now be described with reference to the accompanying drawings.

[0032] Implementation Plan

[0033] The implementation schemes described below relate to data storage devices (DSDs). As used herein, a "data storage device" refers to a non-volatile device that stores data. Examples of DSDs include, but are not limited to, hard disk drives (HDDs), solid-state drives (SSDs), tape drives, hybrid drives, etc. Detailed information about example DSDs is provided below.

[0034] Figures 1A to 1C Examples of data storage devices suitable for implementing these implementation schemes are shown below. It should be noted that these are merely examples and other specific implementations may be used. Figure 1A This is a block diagram illustrating a data storage device 100 according to an implementation scheme. (See reference) Figure 1AIn this example, the data storage device 100 includes a controller 102 coupled to non-volatile memory, which may consist of one or more non-volatile memory dies 104. As used herein, the term "die" refers to a non-volatile memory cell formed on a single semiconductor substrate and the associated circuitry for managing the physical operations of those non-volatile memory cells. The controller 102 interacts with a host system and sends sequences of commands for read, program, and erase operations to the non-volatile memory die 104. Furthermore, as used herein, the phrase "communicating with" or "coupled with" can mean directly communicating / coupling with or indirectly communicating / coupling with through one or more components, which may or may not be shown or described herein. The communication / coupling can be wired or wireless.

[0035] Controller 102 (which may be a non-volatile memory controller (e.g., flash memory, resistive random access memory (ReRAM), phase-change memory (PCM), or magnetoresistive random access memory (MRAM) controller)) may include one or more components configured individually or in combination to perform certain functions, including but not limited to those described herein and illustrated in the flowcharts. For example, such as Figure 2A As shown, controller 102 may include one or more processors 138, which are individually or in combination configured to perform functions, such as, but not limited to, those described herein and illustrated in the flowcharts, by executing computer-readable program code stored in one or more non-transitory memories 139 within controller 102 and / or external to controller 102 (e.g., in random access memory (RAM) 116 or read-only memory (ROM) 118). Furthermore, the one or more components may include circuitry, such as, but not limited to, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0036] In one example implementation, a nonvolatile memory controller 102 is a device that manages data stored on nonvolatile memory and communicates with a host (such as a computer or electronic device) having any suitable operating system. The nonvolatile memory controller 102 may have various functionalities beyond those specifically described herein. For example, the nonvolatile memory controller may format the nonvolatile memory to ensure proper operation, map out faulty nonvolatile memory cells, and allocate spare cells to replace future failed cells. A portion of the spare cells may be used to maintain firmware (and / or other metadata for housekeeping and tracking) to operate the nonvolatile memory controller and implement other features. In operation, the host may communicate with the nonvolatile memory controller when it needs to read data from or write data to the nonvolatile memory. If the host provides a logical address where data will be read / written, the nonvolatile memory controller may translate the logical address received from the host into a physical address in the nonvolatile memory. The non-volatile memory controller can also perform various memory management functions, such as, but not limited to, wear leveling (distributing writes to avoid wear on specific memory blocks that would otherwise be repeatedly written) and garbage collection (moving only valid data pages to a new block after a block is full, so that the full block can be erased and reused).

[0037] The non-volatile memory die 104 may comprise any suitable non-volatile storage medium, including resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), phase-change memory (PCM), NAND flash memory cells, and / or NOR flash memory cells. The memory cells may take the form of solid-state (e.g., flash memory) memory cells and may be programmable once, less-programmable, or more-programmable. The memory cells may also be single-level cells (SLC), multi-level cells (MLC) (e.g., two-level cells, three-level cells (TLC), four-level cells (QLC), etc.) or may use other memory cell-level technologies now known or developed hereafter. Furthermore, the memory cells may be fabricated in two or three dimensions.

[0038] The interface between controller 102 and non-volatile memory die 104 can be any suitable flash memory interface, such as switching modes 200, 400, or 800. In one embodiment, data storage device 100 can be a card-based system, such as a Secure Digital (SD) card or a micro-Secure Digital (micro-SD) card. In another embodiment, data storage device 100 can be part of an embedded data storage device.

[0039] Despite Figure 1AIn the illustrated example, data storage device 100 (sometimes referred to herein as a storage module) includes a single channel between controller 102 and non-volatile memory die 104; however, the subject matter described herein is not limited to having a single memory channel. For example, in some architectures (such as...) Figure 1B and Figure 1C In the architecture shown, depending on the controller's capabilities, there may be two, four, eight, or more memory channels between the controller and the memory device. In any of the embodiments described herein, even if a single channel is shown in the figures, there may be more than one single channel between the controller and the memory die.

[0040] Figure 1B An example is illustrated of a storage module 200 comprising multiple non-volatile data storage devices 100. Thus, the storage module 200 may include a storage controller 202 that interfaces with a host and with data storage devices 204, which include multiple data storage devices 100. The interface between the storage controller 202 and the data storage devices 100 may be a bus interface, such as a Serial Advanced Technology Attachment (SATA), a Peripheral Component Rapid Interconnect (PCIe) interface, a Double Data Rate (DDR) interface, or a Serial Connected Small Scale Compute Interface (SAS / SCSI). In one embodiment, the storage module 200 may be a solid-state drive (SSD) or a non-volatile dual in-line memory module (NVDIMM), as found in server PCs or portable computing devices such as laptops and tablets.

[0041] Figure 1C This is a block diagram illustrating a tiered storage system. The tiered storage system 250 includes a plurality of storage controllers 202, each of which controls a corresponding data storage device 204. A host system 252 can access the memory within the storage system 250 via a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Fast (NVMe) interface or an Ethernet Fibre Channel (FCoE) interface. In one embodiment, Figure 1C The illustrated system may be a rack-mounted mass storage system that can be accessed by multiple host computers, such as those found in data centers or other locations where mass storage is required.

[0042] Refer again Figure 2AThe controller 102 in this example also includes a front-end module 108 communicating with the host, a back-end module 110 communicating with one or more non-volatile memory dies 104, and various other components or modules, such as, but not limited to, a buffer manager / bus controller module that manages buffers in RAM 116 and controls the internal bus arbitration of controller 102. Modules may include one or more processors or components, as discussed above. ROM 118 may store system boot code. Although in Figure 2A The RAM 116 and ROM 118 are illustrated as being located separately from the controller 102, but in other embodiments, one or both of them may be located within the controller 102. In yet another embodiment, portions of the RAM 116 and ROM 118 may be located both within and outside the controller 102.

[0043] Front-end module 108 includes a host interface 120 and a physical layer interface (PHY) 122 that provide electrical communication with the host or next-level storage controller. The type of host interface 120 may be selected depending on the type of memory used. Examples of host interfaces 120 include, but are not limited to, SATA, SATA Express, Serial ATA Small Computer System Interface (SAS), Fibre Channel, Universal Serial Bus (USB), PCIe, and NVMe. Host interface 120 typically facilitates the transmission of data, control signals, and timing signals.

[0044] Backend module 110 includes an error correction code (ECC) engine 124 that encodes data bytes received from the host and decodes and corrects errors in data bytes read from the non-volatile memory. Command sequencer 126 generates command sequences (such as programming and erasing command sequences) to be sent to the non-volatile memory die 104. RAID (Redundant Array of Independent Disks) module 128 manages the generation of RAID parity and the recovery of faulty data. RAID parity can be used as an additional level of integrity protection for data being written to memory device 104. In some cases, RAID module 128 may be part of ECC engine 124. Memory interface 130 provides command sequences to the non-volatile memory die 104 and receives status information from the non-volatile memory die 104. In one embodiment, memory interface 130 may be a double data rate (DDR) interface, such as a switching mode 200, 400, or 800 interface. The controller 102 in this example also includes a media management layer 137 and a flash control layer 132, which controls the overall operation of the back-end module 110.

[0045] The data storage device 100 also includes other discrete components 140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that can interface with the controller 102. In an alternative embodiment, one or more of the physical layer interface 122, RAID module 128, media management layer 138, and buffer management / bus controller are optional components that are not necessary in the controller 102.

[0046] Figure 2B This is a block diagram illustrating the components of a non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes peripheral circuitry 141 and a non-volatile memory array 142. The non-volatile memory array 142 includes non-volatile memory cells for storing data. The non-volatile memory cells can be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells, and / or NOR flash memory cells in a two-dimensional and / or three-dimensional configuration. The non-volatile memory die 104 also includes address decoders 148 and 150 and a data cache 156 for caching data. In this example, the peripheral circuitry 141 includes a state machine 152 that provides state information to the controller 102. The peripheral circuitry 141 may also include one or more components that are individually or in combination configured to perform certain functions, including but not limited to those described herein and illustrated in the flowchart. For example, as... Figure 2B As shown, the memory die 104 may include one or more processors 168, which are individually or in combination configured to execute computer-readable program code stored in one or more non-transitory memories 169, in the memory array 142, or external to the memory die 104. Alternatively, the one or more components may include circuitry, such as, but not limited to, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0047] As a complement or alternative to one or more processors 138 (or more generally, components) in controller 102 and one or more processors 168 (or more generally, components) in memory die 104, data storage device 100 may include another set of one or more processors (or more generally, components). Generally, regardless of the location and number of the one or more processors (or more generally, components) in data storage device 100, these processors may be configured individually or in combination to perform various functions, including but not limited to those described herein and illustrated in the flowcharts. For example, the one or more processors (or components) may be located in controller 102, memory device 104, and / or other locations within data storage device 100. Furthermore, different processors (or components) or combinations of processors (or components) may be used to perform different functions. Additionally, means for performing functions may be implemented using a controller that includes one or more components (e.g., processors or other components described above).

[0048] Return again Figure 2A The flash control layer 132 (which will be referred to herein as the flash translation layer (FTL)) handles flash errors and communicates with the host. Specifically, the FTL (which may be an algorithm in the firmware) is responsible for the internal operations of memory management and translates writes from the host into writes destined for memory 104. An FTL may be necessary because memory 104 may have limited endurance, may only be written to in multi-page format, and / or may not be written to at all (unless it is erased as a block). The FTL understands these potential limitations of memory 104, which may be invisible to the host. Therefore, the FTL attempts to translate writes from the host into writes destined for memory 104.

[0049] The FTL may include a logical-to-physical address (L2P) mapping (sometimes referred to herein as a table structure or data structure) and allocated cache memory. In this way, the FTL translates logical block addresses (“LBAs”) from the host into physical addresses in memory 104. The FTL may include other features such as, but not limited to, power-down recovery (enabling the recovery of the FTL’s data structures in the event of a sudden power outage) and wear leveling (ensuring uniform wear across memory blocks to prevent certain blocks from becoming excessively worn, which would lead to a greater likelihood of failure).

[0050] Turn to the attached image again. Figure 3This is a block diagram of a host 300 and a data storage device 100 according to an embodiment. The host 300 may take any suitable form, including but not limited to a computer, mobile phone, tablet, wearable device, digital video recorder, surveillance system, etc. The host 300 (hereinafter referred to as a computing device) in this embodiment includes one or more processors 330 and one or more memories 340. In one embodiment, computer-readable program code stored in one or more memories 340 configures one or more processors 330 to perform actions described herein as being performed by the host 300. Therefore, actions performed by the host 300 are sometimes referred to herein as being performed by an application (computer-readable program code) running on the host 300. For example, the host 300 may be configured to transfer data (e.g., initially stored in the host's memory 340) to the data storage device 100 for storage in the memory 104 of the data storage device.

[0051] As described above, data storage devices can be used to store databases (or other data structures) that can be read by a host. When processing the database for data analysis, the host may need to perform value replacements (e.g., filling in and / or replacing missing values ​​within the database when "Not a Number (NaN)" is written instead of a value). After the host reads the database from the data storage device, it can replace NaN values ​​with some default value (such as 0 or the average column value). However, having the host perform replacements after loading the database from the data storage device can require some effort and cause latency. Moreover, the database is rarely stored after replacements are performed because it is valuable to preserve the original data without replacements to distinguish between real and replaced values.

[0052] In the following embodiments, the controller 102 of the data storage device 100 is configured to optimize the replacement process by performing missing value preprocessing on a data structure (such as a database) stored in the memory 104 of the data storage device 100. These embodiments can reduce the latency and computational overhead of the value replacement operation. In one example embodiment (other embodiments may be used), the controller 102 is configured to optimize the replacement of a specific pattern in the stored data structure. A database will be used to illustrate the following example of this embodiment; however, it should be understood that data structures other than databases may be used.

[0053] In one example, the controller 102 of the data storage device 100 is configured to mark the written replaceable pattern, such that the controller 102 can perform on-the-fly replacement of the pattern during a read operation. The pattern can take any suitable form, such as, but not limited to, specific characters, regular expressions, or predefined bit sequences that would not otherwise be used in a structure persistently stored in the memory 104 of the data storage device 100. For simplicity, this example will use special character replacements; however, it should be understood that the claims are not limited thereto unless expressly stated therein.

[0054] Figure 4 This is an example architecture for the implementation plan. For example... Figure 4 As shown, in this example, host 300 includes a database write control module 400, which may be provided individually or in combination by one or more processors 330 of the host to execute instruction code stored in one or more memories 340 of the host. Also as Figure 4 As shown, in this example, the controller 102 of the data storage device includes a database replacement optimization control module 410, which may be provided individually or in combination by one or more processors 168 of the controller to execute instruction code stored in the memory of the data storage device 100. It should be understood that the database write control module 400 and the database replacement optimization control module 410 may be located in other locations (e.g., in the connection layer between the controller 102 and the host 300).

[0055] In this example, when host 300 is writing special characters belonging to the database, the database replacement optimization control module 410 can insert the locations of these special characters as metadata. The locations can be stored in a page plus offset format or a compressed format (e.g., if a large range of special characters exists). Indicating the locations of special characters can speed up replacement operations during the reading of these characters. It should be noted that in this example, the original data is entirely stored in memory 104, and replacement is optional. If the database write / read control does not request replacement, the original data can be read. This can also be represented as a "calculated" read with replacement or a "regular" read without replacement.

[0056] The database write control module 400 can define special characters or patterns to be used. For example, a sequence for "NaN" can be used in an integer field to indicate a non-numeric value, and the replacement to be used can be 0 or 1.

[0057] Figure 5 This is flowchart 500 illustrating the write operation of the implementation scheme. For example... Figure 5As shown, when host 300 writes data to data storage device 100, controller 102 (e.g., using database replacement module 410) identifies special characters in the data (action 510) and writes metadata about the location of the special characters (action 520). Special characters can be defined by host 300 through database write control module 400. The replacement character for each special character and the granularity of data defined as "characters" can also be defined through this interface.

[0058] Figure 6 This is a flowchart 600 illustrating the reading operation of the implementation scheme. For example... Figure 6 As shown, when host 300 reads database data from data storage device 100, controller 102 (e.g., using database replacement module 410) identifies special characters using previously written metadata (action 610) and immediately replaces the special characters with replacement characters (action 620). Therefore, in this example, when database data is set to be read, database replacement module 410 can read the metadata and replace each special character in the read data with a replacement character. The metadata can be stored in non-volatile memory 104 and loaded when database write / read control module 400 indicates that the database will be read.

[0059] Several advantages exist associated with these implementation schemes. For example, when reading large databases, using these schemes can reduce power consumption, latency, and host overhead. Computational storage is highly sought after, and these improvements are beneficial.

[0060] There are many alternatives that can be used with these implementations. For example, the database replacement module 410 can be integrated with the values ​​of a key-value (KV) database. Special characters can be represented as the values ​​of KV pairs, and their replacement can occur during database reads.

[0061] Furthermore, if the replacement changes the payload length, the replacement algorithm can indicate this as part of a read operation. For example, if the replacement increases the payload size, a database read operation may be required to allocate additional buffer space. Since logical block addresses (LBAs) are of fixed length, padding replacement can be used in this case. For example, the blank space defined in a comma-separated values ​​(CSV) file can be reduced to allow for variable lengths in the replacement field. If the replacement cannot fit into the buffer provided by host 300, the computation protocol can indicate additional buffer space available for this purpose. Moreover, computation reads can be performed using a different memory buffer than standard reads. Implementations can utilize NVMe technology recommendations 4091, 4131, and 4184 (which define the semantics for computation storage) to resolve communication between host 300 and data storage device 100.

[0062] Finally, as mentioned above, any suitable type of memory can be used. Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) devices or static random access memory (“SRAM”) devices; non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which is considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), as well as other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in a NAND configuration or a NOR configuration.

[0063] Memory devices can be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements such as antifuses, phase-change materials, and optionally manipulation elements such as diodes. As yet another non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements comprising charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0064] Multiple memory elements can be configured such that they are connected in series or that each element is individually accessible. As a non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically comprises memory elements connected in series. A NAND memory array can be configured such that the array consists of multiple memory strings, where a string consists of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements can be configured such that each element is individually accessible, for example, a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0065] Semiconductor memory elements located within and / or above a substrate can be arranged in two or three dimensions, such as two-dimensional memory structures or three-dimensional memory structures.

[0066] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane that extends substantially parallel to the main surface of the substrate supporting the memory element (e.g., in the xz plane). The substrate may be a wafer on which the memory element layer is formed, or the substrate may be a carrier substrate attached to the memory element after the memory element has been formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.

[0067] Memory elements can be arranged in an ordered array (such as by multiple rows and / or columns) within a single memory device level. However, memory elements can be arranged in an irregular or non-orthogonal configuration. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0068] The three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., along the x, y and z directions, where the y direction is generally perpendicular to the main surface of the substrate, and the x and z directions are generally parallel to the main surface of the substrate).

[0069] As a non-limiting example, a three-dimensional memory structure can be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate (i.e., along the y-direction), each column containing multiple memory elements. The columns can be arranged in a two-dimensional configuration (e.g., in the xz plane) to produce a three-dimensional arrangement of memory elements with multiple vertically stacked memory planes. Other configurations of the three-dimensional memory elements can also constitute a three-dimensional memory array.

[0070] As a non-limiting example, in a three-dimensional NAND memory array, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xz) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. Three-dimensional memory arrays can also be designed in NOR and ReRAM configurations.

[0071] Typically, in a monolithic three-dimensional memory array, one or more memory device classes are formed over a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers located at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layer constituting each memory device class of the array is typically formed on the layer of the lower memory device class of the array. However, the layers of adjacent memory device classes in a monolithic three-dimensional memory array may be shared or intermediate layers may be present between memory device classes.

[0072] Furthermore, two-dimensional arrays can be formed individually and then packaged together to form a non-monolithic memory device with multi-layered memory. For example, a non-monolithic stacked memory can be constructed by forming memory stages on individual substrates and then stacking the memory stages on top of each other. The substrates can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on individual substrates, the resulting memory array is not a monolithic three-dimensional memory array. Alternatively, multiple (monolithic or non-monolithic) two-dimensional or three-dimensional memory arrays can be formed on individual chips and then packaged together to form a stacked chip memory device.

[0073] The operation of memory elements and communication with them typically require associated circuitry. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory elements to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read / write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0074] Those skilled in the art will recognize that the present invention is not limited to the described two-dimensional and three-dimensional structures, but covers all relevant memory structures as described herein and as understood by those skilled in the art within the spirit and scope of the invention.

[0075] The above detailed description is intended to be understood as an illustration of selected forms of the invention, and not a definition of the invention. Only the following claims (including all equivalents) are intended to define the scope of the claimed invention. Finally, it should be noted that any aspect of any embodiment described herein may be used alone or in combination with each other.

Claims

1. A data storage device, the data storage device comprising: Memory; and One or more processors, wherein the one or more processors are configured individually or in combination to: Receive the data to be written into the data structure; The data is analyzed in relation to the predetermined pattern; The data is written to multiple storage locations in the memory; as well as Information about which storage locations store the predetermined pattern is written into the memory.

2. The data storage device of claim 1, wherein the one or more processors are further configured individually or in combination to: In response to receiving a request from the host to read the data structure, the information about which storage locations store the predetermined pattern is used to perform an immediate replacement of the predetermined pattern with a replacement pattern during the read operation.

3. The data storage device according to claim 2, wherein: The request includes a computational read with replacement; and The one or more processors are further configured individually or in combination to: In response to receiving a request from the host to read the data structure without replacement, the data is read from the memory and provided to the host without replacing the predetermined pattern with the replacement pattern.

4. The data storage device of claim 1, wherein the predetermined pattern includes a "non-numeric (NaN)" character, and the replacement pattern includes a number.

5. The data storage device according to claim 1, wherein the predetermined pattern includes specific characters.

6. The data storage device according to claim 1, wherein the predetermined pattern comprises a regular expression.

7. The data storage device according to claim 1, wherein the predetermined pattern comprises a predefined bit sequence.

8. The data storage device of claim 1, wherein the information regarding which storage locations store the predetermined pattern is stored in a page plus offset format.

9. The data storage device of claim 1, wherein the information regarding which storage locations store the predetermined pattern is stored in a compressed format.

10. The data storage device of claim 1, wherein the predetermined pattern, the replacement pattern, and / or replacement granularity are defined by a host providing the data to be stored in the data storage device.

11. The data storage device of claim 1, wherein the predetermined pattern is represented as the values ​​of key-value (KV) pairs.

12. The data storage device according to claim 1, wherein the data structure includes a database.

13. The data storage device according to claim 1, wherein the memory includes a three-dimensional memory.

14. A method, the method comprising: Execute in a data storage device that includes memory: The character set in the data of the data structure to be stored in the memory; Store information about the storage location of the character set in the memory; as well as In response to a request from the host to read the data: Use the information to replace the character set with a replacement character set; and The data, including the replacement character set, is provided to the host.

15. The method according to claim 14, further comprising: The host is notified that the replacement character set has changed the length of the read payload.

16. The method according to claim 15, further comprising: Allocate additional buffers to accommodate the changed length.

17. The method according to claim 15, further comprising: Reduce the amount of whitespace defined in the comma-separated values ​​(CSV) file to accommodate the changed length.

18. The method of claim 15, wherein replacing the character set with the replacement character set uses a buffer different from the buffer used in the standard read operation.

19. The method of claim 14, wherein the data structure comprises a database.

20. A data storage device, the data storage device comprising: Memory; and A means for performing instantaneous data replacement during a read operation of a data structure stored in the memory, based on previously stored information identifying the location of the data to be replaced.

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