Method for detecting whether power tube in switching circuit breaks down or not and driving system

Abstract

A method and driving system for detecting whether a power tube in a switching circuit has a fault, the switching circuit comprises a first detection loop, the first detection loop comprises a first device group and a second device group, the first device group comprises a first power tube, the second device group comprises a second power tube, and the detection method comprises the following steps: controlling the first power tube to be conducted; controlling the conduction of the second power tube by the first voltage value, and detecting the voltage between the first end and the second end of the first device group to obtain a first measurement value; controlling the conduction of the second power tube by a second voltage value, and detecting the voltage between the first end and the second end of the first device group to obtain a second measurement value; generating a first calculation value according to the first measurement value and the second measurement value; and judging whether the first power tube breaks down or not according to the first calculated value. According to the method, whether the first power tube breaks down or not can be judged more accurately.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a method and a drive system for detecting whether a power transistor in a switching circuit has failed. Background Technology

[0002] In applications such as inverter drives for new energy vehicles and drives for various high-power motors, drive circuits typically employ multiple power devices. These devices work together to control the rotation and stopping of the motor and other components. During operation, these power devices may suddenly fail, leading to production stoppages, operational shutdowns, or safety accidents. Therefore, appropriate monitoring circuits need to be designed to prevent such failures. Summary of the Invention

[0003] This disclosure provides at least one embodiment of a method for detecting whether a power transistor in a switching circuit has failed, wherein the switching circuit includes a first detection loop, the first detection loop includes a first device group and a second device group, the first device group includes a first power transistor, and the second device group includes a second power transistor, the method includes: controlling the first power transistor to conduct; controlling the second power transistor to conduct with a first voltage value, detecting the voltage between a first terminal and a second terminal of the first device group to obtain a first measured value; controlling the second power transistor to conduct with a second voltage value, detecting the voltage between the first terminal and a second terminal of the first device group to obtain a second measured value; generating a first calculated value based on the first measured value and the second measured value; and determining whether the first power transistor has failed based on the first calculated value.

[0004] At least one embodiment of this disclosure also provides a drive system for detecting whether a power transistor in a switching circuit has failed. The drive system includes a drive circuit and a processor. The switching circuit includes a first detection loop, which includes a first device group and a second device group. The first device group includes a first power transistor, and the second device group includes a second power transistor. The drive circuit includes: a first control circuit having a first terminal and a second terminal, wherein the first terminal of the first control circuit is coupled to the first terminal of the first power transistor via a first diode, and the second terminal of the first control circuit outputs a first output signal to the control terminal of the first power transistor; and a second control circuit having a first terminal and a second terminal, wherein the first... The first terminal of the second control circuit is coupled to the first terminal of the second power transistor via a second diode. The second terminal of the second control circuit outputs a second output signal to the control terminal of the second power transistor. When the driving circuit operates in the power transistor state detection state, the first output signal controls the first power transistor to turn on, and the second output signal controls the second power transistor to turn on with a first voltage value and a second voltage value, respectively. The first control circuit detects the voltage between the first terminal and the second terminal of the first device group to obtain corresponding first and second measured values. The controller generates a first calculated value based on the first and second measured values ​​and determines whether the first power transistor has failed based on the first calculated value.

[0005] This disclosure provides at least one embodiment of a method for detecting whether a power transistor in a switching circuit has failed, wherein the switching circuit includes multiple device groups, each device group including a power transistor, the method comprising: controlling the power transistor of a first device group to conduct, wherein the first device group is the device group under test among the multiple device groups, and the remaining device groups among the multiple device groups are control device groups; controlling the current flowing through the power transistor of the first device group to a first current based on the conduction state of the control device group, and detecting the voltage between a first terminal and a second terminal of the first device group to obtain a first measured value; controlling the current flowing through the power transistor of the first device group to a second current based on the conduction state of the control device group, wherein the second current is different from the first current, and detecting the voltage between the first terminal and the second terminal of the first device group to obtain a second measured value; generating a first calculated value based on the first measured value and the second measured value; and determining whether the power transistor of the first device group has failed based on the first calculated value. Attached Figure Description

[0006] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.

[0007] Figure 1 A flowchart of a method for detecting whether a power transistor in a switching circuit has failed, provided in at least one embodiment of this disclosure;

[0008] Figure 2 A circuit diagram of a driving circuit provided for at least one embodiment of this disclosure;

[0009] Figure 3 A circuit diagram of a first detection loop provided for at least one embodiment of this disclosure;

[0010] Figure 4A , Figure 4B and Figure 4C A signal timing diagram of the configuration voltage provided in at least one embodiment of this disclosure shows the change of voltage V with time t;

[0011] Figure 5 This is another flowchart of a method for detecting whether a power transistor in a switching circuit has failed, provided in at least one embodiment of the present disclosure;

[0012] Figure 6 A circuit diagram of a first detection loop provided for at least one embodiment of this disclosure;

[0013] Figure 7A , Figure 7B and Figure 7C A signal timing diagram of the configuration voltage provided for at least one embodiment of this disclosure shows the change of voltage V over time t; and

[0014] Figure 8 A schematic diagram of a driving system provided for at least one embodiment of this disclosure; and

[0015] Figure 9 A schematic diagram of an electronic device provided for at least one embodiment of this disclosure. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0017] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0018] This disclosure provides at least one embodiment of a method and driving system for detecting whether a power transistor in a switching circuit has failed. The switching circuit includes a first detection loop, which includes a first device group and a second device group. The first device group includes a first power transistor, and the second device group includes a second power transistor. The detection method includes: controlling the first power transistor to conduct; controlling the second power transistor to conduct with a first voltage value, and detecting the voltage between a first terminal and a second terminal of the first device group to obtain a first measured value; controlling the second power transistor to conduct with a second voltage value, and detecting the voltage between the first terminal and a second terminal of the first device group to obtain a second measured value; generating a first calculated value based on the first and second measured values; and determining whether the first power transistor has failed based on the first calculated value. The driving system can implement the above detection method.

[0019] In the method for detecting whether a power transistor in a switching circuit has failed, provided in this embodiment, the on-resistance of the power device in the power component can be characterized by measuring the voltage values ​​of the same device group under different currents. The difference can be calculated to determine whether the corresponding power device has failed. This avoids measurement path deviations (such as deviations caused by the on-resistance voltage drop of other devices included in the power component, such as diodes), and also avoids the influence of circuit aging or temperature fluctuations in the drive circuit on the measurement results. Furthermore, the above detection method can be implemented using the existing circuit structure in the drive circuit, making the detection method simpler and more accurate.

[0020] For example, in drive technologies such as IGBTs (Insulated Gate Bipolar Transistors), SiC transistors, and MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), the above method can be used to monitor whether power transistors are malfunctioning. For instance, when an increase in the on-resistance of a power transistor is detected, an early warning can be issued to prevent a fault from occurring. This detection method can be applied to scenarios such as inverter drives in new energy vehicles and drives for various high-power motors.

[0021] The following describes the method and driving system for detecting whether a power transistor in a switching circuit has failed, as provided in this disclosure, through several specific embodiments.

[0022] At least one embodiment of this disclosure provides a method for detecting whether a power transistor in a switching circuit has failed, i.e., a method for monitoring whether a power transistor is in a healthy state. This detection method can be applied to a switching circuit that includes multiple power devices (e.g., power transistors), the switching circuit including multiple device groups, each device group including one power transistor. During detection, a detection loop can be formed by controlling the switching states of multiple device groups to detect whether the power transistor in each device group has failed.

[0023] For example, the switching circuit includes a first detection circuit, which includes a first device group and a second device group. The first device group includes a first power transistor, and the second device group includes a second power transistor. Figure 1 A flowchart illustrating the method for detecting whether a power transistor in a switching circuit has malfunctioned is shown, such as... Figure 1 As shown, the detection method includes steps S101 to S105.

[0024] Step S101: Control the first power transistor to turn on.

[0025] Step S102: Control the second power transistor to turn on with the first voltage value, and detect the voltage between the first terminal and the second terminal of the first device group to obtain the first measurement value.

[0026] Step S103: Control the second power transistor to turn on with the second voltage value, and detect the voltage between the first terminal and the second terminal of the first device group to obtain the second measurement value.

[0027] Step S104: Generate a first calculated value based on the first measured value and the second measured value.

[0028] Step S105: Determine whether the first power transistor has malfunctioned based on the first calculated value.

[0029] For example, in specific operation, in response to the detection command, for the first detection circuit, the first power transistor is controlled to turn on, and the first power transistor is used as the power transistor to be detected.

[0030] For example, the first detection circuit is a detection circuit selected from a switching circuit including a multi-phase half-bridge, and the first device group and the second device group can be device groups in a co-phase half-bridge; in this case, the first device group is coupled to the high-side bus and the first switching node, and the second device group is coupled to the first switching node and the low-side bus (details to follow later); or, the first device group and the second device group are device groups in a phase-shifted half-bridge, in which case the first device group is coupled to the high-side bus and the first switching node, and the second device group is coupled to the second node and the low-side bus (details to follow later).

[0031] In embodiments of this disclosure, the high-side bus and the low-side bus are relative terms, meaning that the voltage of the high-side bus is higher than the voltage of the low-side bus.

[0032] For example, Figure 2 A circuit diagram of a switching circuit provided in at least one embodiment of the present disclosure is shown, such as... Figure 2 As shown, the switching circuit includes a three-phase half-bridge circuit, with each phase half-bridge circuit including two power transistors, for a total of six power transistors working together to control the rotation and stopping of the PMSM motor. For example, the PMSM motor can be used in fields such as new energy vehicles.

[0033] For example, such as Figure 2 As shown, in this switching circuit, the first device group M1 (including the first power transistor Q1) and the second device group M2 (including the second power transistor Q2) form a phase half-bridge, the third device group M3 (including the third power transistor Q3) and the fourth device group M4 (including the fourth power transistor Q4) form a phase half-bridge, the fifth device group M5 (including the fifth power transistor Q5) and the sixth device group M6 (including the sixth power transistor Q6) form a phase half-bridge, the first switching node SW1 is located between the first device group M1 and the second device group M2, the second switching node SW2 is located between the third device group M3 and the fourth device group M4, and the third switching node SW3 is located between the fifth device group M5 and the sixth device group M6.

[0034] For example, when detecting whether the power transistors in the aforementioned switching circuit have malfunctioned, the switching circuit can be divided into multiple detection loops to monitor the power devices in each loop separately. For instance, each detection loop includes at least two power transistors, and the detection of malfunctions is achieved through the cooperation of these at least two power transistors.

[0035] For example, when dividing the detection loop, two power devices in the in-phase half-bridge can be assigned to one detection loop; or, in other embodiments, two or more power components in the out-of-phase half-bridge can be assigned to one detection loop. The following describes the power device detection method provided in this disclosure embodiment, taking the assignment of two power devices in the in-phase half-bridge to one detection loop as an example.

[0036] For example, Figure 3 The circuit diagram shown above illustrates a single-phase half-bridge circuit comprising the first device group M1 and the second device group M2, as follows: Figure 3 As shown, a single-phase half-bridge comprising a first device group M1 and a second device group M2 forms a first detection circuit. The first device group M1 is coupled to the high-side bus VB and the first switching node SW1, and the second device group M2 is coupled to the first switching node SW1 and the low-side bus GND. At this time, the two-phase half-bridge including other power devices Q3~Q6 is in the off state. For example, the voltage of the high-side bus VB is several hundred volts, such as 600V~800V, or 600V, 700V, or 800V; the low-side bus GND can be, for example, a ground wire.

[0037] For example, each device group also includes other electronic components, such as diodes, etc. For example, such as Figure 3 As shown, the first device group M1 further includes a first diode D1, the anode of which is coupled to a first terminal of the first device group M1. The second device group M2 further includes a second diode D2, the anode of which is coupled to a first terminal of the second device group M1. For example, in some other embodiments, each device group may include only a power transistor, or include a power transistor and other electronic components besides diodes. The embodiments of this disclosure do not limit the specific configuration of the device groups.

[0038] For example, such as Figure 3 As shown, during testing, the first control circuit DT1 can be used to detect the first terminal of the first device group M1 (e.g., Figure 3 The upper end) and the second end (e.g.) Figure 3 The voltage between the lower end of the second device group M2 and the lower end of the second device group M2 is detected by the second control circuit DT2. Figure 3 The upper end) and the second end (e.g.) Figure 3 The voltage between the lower end of the middle.

[0039] For example, the first control circuit DT1 includes a first output terminal OUT1 and a first power supply DC1 connected to the first output terminal OUT1. The first power supply DC1 is configured to provide a configuration voltage. The first control circuit DT1 also includes a first detection terminal DESAT1 and a first voltage detection device ADC1 connected to the first detection terminal DESAT1, such as an analog-to-digital converter. The first voltage detection device ADC1 is configured to acquire the voltage measurement value of the first device group M1. The second control circuit DT2 includes a second output terminal OUT2 and a second power supply DC2 connected to the second output terminal OUT2. The second power supply DC2 is configured to provide a configuration voltage. The second control circuit DT2 also includes a second detection terminal DESAT2 and a second voltage detection device ADC2 connected to the second detection terminal DESAT2, such as an analog-to-digital converter. The second voltage detection device ADC2 is configured to acquire the voltage measurement value of the second device group M2.

[0040] For example, such as Figure 3 As shown, the first control circuit DT1 can be implemented using the desaturation detection (Desat detection) circuit already configured in the drive circuit. The pins of this circuit are implemented as the first detection terminal DESAT1. Thus, the detection method provided in this embodiment can be implemented by reusing the desaturation detection (Desat detection) circuit already configured in the drive circuit. For example, this circuit also includes a first input terminal IN1, a power supply terminal VCC2, a first capacitor C1, and a switch idesat_en. Similarly, the second control circuit DT2 can also be implemented using the desaturation detection (Desat detection) circuit already configured in the drive circuit. The pins of this circuit are implemented as the second detection terminal DESAT2. For example, this circuit also includes a second input terminal IN2, a power supply terminal VCC2, a ground terminal GND2, a second capacitor C2, and a switch idesat_en.

[0041] For example, refer to Figure 3 and Figure 4A In response to the detection command, for the aforementioned first detection loop, the first control circuit DT1 controls the first power transistor Q1 to conduct. For example, the first output terminal OUT1 of the first control circuit DT1 outputs a voltage VH. The second control circuit DT2 controls the second power transistor Q2 to conduct with a first voltage value V1. For example, the second output terminal OUT2 of the second control circuit DT2 inputs a first configuration voltage to the control terminal G of the second power transistor Q2. The voltage value of the first configuration voltage is the first voltage value V1, which is higher than the threshold voltage of the second power transistor Q2. At this time, the current flowing through the second power transistor Q2 is the first current I1. For example, the first voltage detection device ADC1 detects the voltage across the first device group M1 through the first detection terminal DESAT1 to obtain the first measured value V. ADC1 V ADC1 = I1 R Q1 +V D1 In this formula, I1 R Q1 R is the voltage between the first electrode (E) and the second electrode (C) of the first power transistor Q1. Q1 V is the impedance of the first power transistor Q1. D1 This is the voltage across the first diode D1.

[0042] For example, the first voltage value V1 can be slightly larger than the threshold voltage of the second power transistor Q2, such as a few volts higher, for example, 2V higher. This configured voltage can effectively control the saturation current of the second power transistor Q2 within a reasonable range. For example, in some examples, such as... Figure 4A As shown, the voltage VH output by the first output terminal OUT1 can be tens of volts to control the first power transistor Q1 to be fully turned on.

[0043] For example, after obtaining the first measurement value V mentioned above ADC1 Then, a second configuration voltage is input to the control terminal G of the second power transistor Q2. The voltage value of the second configuration voltage is a second voltage value V2, which is higher than the threshold voltage of the second power transistor Q2 and different from the first voltage value V1. At this time, the current flowing through the second power transistor Q2 is a second current I2, which is different from the first current I1. The voltage across the first device group Q1 is detected to obtain the second measured value V. ADC2 V ADC2 = I2 R Q1 +V D1 In this formula, R Q1 I2 is the impedance of the first power transistor Q1. R Q1 V is the voltage between the first electrode (E) and the second electrode (C) of the first power transistor Q1. D1 This is the voltage across the first diode D1.

[0044] For example, such as Figure 4A As shown, the second voltage value V2 can be slightly larger than the first voltage value V1. For example, the second voltage value V2 is a few volts higher than the first voltage value V1, such as 2V higher.

[0045] Alternatively, in some other embodiments, the second voltage value V2 may be slightly lower than the first voltage value V1. For example, the first voltage value V1 is 4V higher than the threshold voltage of the second power transistor Q2, and the second voltage value V2 is 2V lower than the first voltage value V1, and so on. The embodiments of this disclosure do not limit the specific values ​​of the first voltage value V1 and the second voltage value V2, and can be selected according to the specific circumstances of the circuit.

[0046] For example, in Figure 4A and Figure 4C In the first embodiment, the voltage VH output from the first output terminal OUT1 to the control terminal G of the first power transistor Q1 is discontinuous between two detections. In other embodiments, such as... Figure 4B As shown, the voltage VH output from the first output terminal OUT1 to the control terminal G of the first power transistor Q1 can also be continuous between the two detections. Figure 4A and Figure 4B In the second output terminal OUT2, the first voltage value V1 and the second voltage value V2 are discontinuous between the two detections, or, as... Figure 4C As shown, the first voltage value V1 and the second voltage value V2 output by the second output terminal OUT2 change continuously between the two detections, and the embodiments of this disclosure do not specifically limit this.

[0047] For example, in step S104, generating the first calculated value based on the first measured value and the second measured value can be achieved by using the difference between the first measured value and the second measured value as the first calculated value.

[0048] For example, the first measured value V ADC1 The difference V between the second measurement value ADC2 The difference is the first difference Delta1, Delta1 = V ADC2 - V ADC1 = (I2 - I1) R Q1 It can be seen that the first difference Delta1 is positively correlated with the impedance of the first power transistor Q1. This difference can eliminate interference from other components in the first device group, such as the voltage drop of the first diode D1. Using the first difference Delta1 as the first calculated value can more accurately determine whether the first power transistor Q1 has failed.

[0049] For example, in some embodiments, a first threshold and a second threshold can be set for the first difference Delta1 according to safety requirements and the specific circumstances of the drive circuit. In this case, if the first voltage measurement V ADC1 Value and second measured value V ADC2 If the absolute value of the difference (i.e., the first difference Delta1) is greater than the first threshold and less than the second threshold (the second threshold is greater than the first threshold), then the first power transistor Q1 is determined to be not faulty. If the absolute value is less than the first threshold or greater than the second threshold, then the first power transistor Q1 is determined to be faulty.

[0050] For example, when the first power transistor Q1 fails, a first alarm signal is generated. The first alarm signal can be displayed in the form of text or sound to alert the user.

[0051] For example, the same detection method as that used for the first power transistor Q1 can be used to determine whether the second power transistor Q2 has malfunctioned.

[0052] For example, in some embodiments, reference Figure 5 The detection method may also include steps S201 to S205.

[0053] Step S201: Control the second power transistor to turn on.

[0054] Step S202: Control the first power transistor to turn on with the first voltage value, and detect the voltage between the first and second terminals of the second device group to obtain the third measurement value.

[0055] Step S203: Control the first power transistor to turn on with the second voltage value, and detect the voltage between the first and second terminals of the second device group to obtain the fourth measurement value.

[0056] Step S204: Generate a second calculated value based on the third and fourth measured values.

[0057] Step S205: Determine whether the second power transistor has malfunctioned based on the second calculated value.

[0058] For example, refer to Figure 6 and Figure 7A The second power transistor Q2 is turned on. For example, the second control circuit DT2 outputs voltage VH to the control terminal G of the second power transistor Q2 through the second output terminal OUT2 to control the second power transistor Q2 to turn on.

[0059] For example, the first control circuit DT1 inputs a first configuration voltage to the control terminal G of the first power transistor Q1 through the first output terminal OUT1. The voltage value of the first configuration voltage is a first voltage value V1, which is higher than the threshold voltage of the first power transistor Q1. At this time, the current flowing through the second power transistor Q2 is a third current I3. For example, the second voltage detection device ADC2 detects the voltage across the two ends of the second device group M2 through the second detection terminal DESAT2 to obtain the third measured value V. ADC3 V ADC3 = I3 R Q2 +V D2 In this formula, I3 R Q2 R is the voltage between the first electrode (E) and the second electrode (C) of the second power transistor Q2. Q2 The impedance of the second power transistor Q2 is V. D2 This is the voltage across the second diode D2.

[0060] For example, the first voltage value V1 can be slightly larger than the threshold voltage of the first power transistor Q1, such as a few volts higher than the threshold voltage of the first power transistor Q1, for example, 2V higher. This configured voltage can effectively control the saturation current of the first power transistor Q1 within a reasonable range. For example, in some examples, such as... Figure 7A As shown, the voltage VH output by the second output terminal OUT2 can be tens of volts to control the second power transistor Q2 to be fully turned on.

[0061] For example, refer to Figure 6 and Figure 7A After obtaining the aforementioned third measurement value V ADC3 Then, a fourth configuration voltage is input to the control terminal G of the first power transistor Q1. The voltage value of the fourth configuration voltage is the second voltage value V2. The fourth configuration voltage is higher than the threshold voltage of the first power transistor Q1 and is different from the third configuration voltage. At this time, the current flowing through the first power transistor Q1 is the fourth current I4. The fourth current I4 is different from the third current I3. The voltage across the second device group M2 is detected to obtain the fourth measurement value V. ADC4 V ADC4 =I4 R Q2 +V D2 In this formula, I4 R Q2 V is the voltage between the first electrode (E) and the second electrode (C) of the second power transistor Q2. D2 This is the voltage across the first diode D2.

[0062] For example, such as Figure 7A As shown, the second voltage value V2 can be slightly larger than the first voltage value V1. For example, the second voltage value V2 is a few volts higher than the first voltage value V1, such as 2V higher.

[0063] Similarly, in other embodiments, the second voltage value V2 may be slightly lower than the first voltage value V1. For example, the first voltage value V1 is 4V higher than the threshold voltage of the first power transistor Q1, and the second voltage value V2 is 2V lower than the first voltage value V1.

[0064] For example, in Figure 7A and Figure 7C In the first embodiment, the voltage VH output from the second output terminal OUT2 to the control terminal G of the second power transistor Q2 is discontinuous between the two detections. In other embodiments, such as... Figure 7B As shown, the voltage VH output from the second output terminal OUT2 to the control terminal G of the second power transistor Q2 can also be continuous between the two detections; Figure 7A and Figure 7B In the above, the first voltage value V1 and the second voltage value V2 output by the first output terminal OUT1 are discontinuous between the two detections, or, as... Figure 7CAs shown, the first voltage value V1 and the second voltage value V2 output by the second output terminal OUT2 change continuously between the two detections.

[0065] For example, in step S204, generating the second calculated value based on the third and fourth measured values ​​can be achieved by taking the third measured value V... ADC3 The difference V between the fourth measurement and the fourth measurement ADC4 The difference is used as the second calculated value.

[0066] For example, the third measurement value V ADC3 and the fourth measurement value V ADC4 The difference is the second difference Delta2, Delta2 = V ADC4 - V ADC3 = (I4 - I3) R Q2 It is evident that the second difference, Delta2, is positively correlated with the impedance of the second power transistor Q2, thus eliminating interference from other components in the second device group, such as the voltage drop of the first diode D2. Using Delta2 as the first calculated value allows for a more accurate determination of whether the second power transistor Q2 has malfunctioned.

[0067] For example, in some embodiments, if the third measurement value V ADC3 The difference V between the fourth measurement and the fourth measurement ADC4 If the absolute value of the difference (i.e., the second difference Delta2) is greater than the first threshold and less than the second threshold (the second threshold is greater than the first threshold), it is determined that the second power transistor Q2 is not faulty. If the absolute value is less than the first threshold or greater than the second threshold, it is determined that the second power transistor Q2 is faulty.

[0068] For example, the first threshold and the second threshold can be set according to the specific conditions of the circuit and the user's needs, and the embodiments of this disclosure do not specifically limit this.

[0069] For example, steps S201 to S205 can be executed after steps S101 to S105, that is, they can be executed before steps S101 to S105. In other words, the embodiments of this disclosure do not specifically limit the detection order of each power transistor, as long as each power transistor can be detected.

[0070] For example, in some embodiments, the switching circuit further includes a second detection circuit and a third detection circuit. The second detection circuit includes a third device group M3 and a fourth device group M4. The third device group M3 includes a third power transistor Q3, the fourth device group M4 includes a fourth power transistor Q4, and the third detection circuit includes a fifth device group M5 and a sixth device group M6. The fifth device group M5 includes a fifth power transistor Q5, and the sixth device group M6 includes a sixth power transistor Q6.

[0071] At this point, the detection method further includes: performing the same operations on the third power transistor Q3 and the fourth power transistor Q4 in the second detection circuit as on the first power transistor Q1 and the second power transistor Q2 in the first detection circuit to obtain the third and fourth calculated values; for example, as Figure 2 As shown, the third control circuit DT3 and the fourth control circuit DT4 are used to perform the same operations on the third power transistor Q3 and the fourth power transistor Q4 in the second detection loop as on the first power transistor Q1 and the second power transistor Q2 in the first detection loop to obtain the third and fourth calculated values; the same operations are performed on the fifth power transistor Q5 and the sixth power transistor Q6 in the third detection loop as on the first power transistor Q1 and the second power transistor Q2 in the first detection loop to obtain the fifth and sixth calculated values; for example, the fifth control circuit DT5 and the sixth control circuit DT6 are used to perform the same operations on the fifth power transistor Q5 and the sixth power transistor Q6 in the third detection loop as on the first power transistor Q1 and the second power transistor Q2 in the first detection loop to obtain the fifth and sixth calculated values; based on the first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, and the sixth calculated value, it is determined whether the first power transistor Q1, the second power transistor Q2, the third power transistor Q3, the fourth power transistor Q4, the fifth power transistor Q5, and the sixth power transistor Q6 have failed.

[0072] For example, the structures of the third control circuit DT3 and the fourth control circuit DT4 are basically the same as those of the first control circuit DT1 and the second control circuit DT2. Similarly, the structures of the fifth power transistor Q5 and the sixth power transistor Q6 are basically the same as those of the first control circuit DT1 and the second control circuit DT2.

[0073] For example, such as Figure 2 As shown, the third control circuit DT2 includes a third output terminal OUT3 and a third power supply DC3 connected to the third output terminal OUT3. The third power supply DC3 is configured to provide a configuration voltage. The third control circuit DT3 also includes a third detection terminal DESAT3 and a third voltage detection device ADC3 connected to the third detection terminal DESAT3, such as an analog-to-digital converter. The third voltage detection device ADC3 is configured to acquire the voltage measurement value of the third device group M3. Similarly, the third control circuit DT3 can also be implemented using the desaturation detection (Desat detection) circuit originally configured in the drive circuit. The pins of this circuit are implemented as the third detection terminal DESAT3. For example, this circuit also includes a third input terminal IN3, a power supply terminal VCC3, and other structures.

[0074] For example, such as Figure 2As shown, the fourth control circuit DT4 includes a fourth output terminal OUT4 and a fourth power supply DC4 connected to the fourth output terminal OUT4. The fourth power supply DC4 is configured to provide a configuration voltage. The fourth control circuit DT4 also includes a fourth detection terminal DESAT4 and a fourth voltage detection device ADC4 connected to the fourth detection terminal DESAT4, such as an analog-to-digital converter. The fourth voltage detection device ADC4 is configured to acquire the voltage measurement value of the fourth device group M4. Similarly, the fourth control circuit DT4 can also be implemented using the desaturation detection (Desat detection) circuit originally configured in the drive circuit. The pins of this circuit are implemented as the fourth detection terminal DESAT4. For example, this circuit also includes a fourth input terminal IN4, a power supply terminal VCC4, and other structures.

[0075] For example, such as Figure 2 As shown, the fifth control circuit DT5 includes a fifth output terminal OUT5 and a fifth power supply DC5 connected to the fifth output terminal OUT5. The fifth power supply DC5 is configured to provide a configuration voltage. The fifth control circuit DT5 also includes a fifth detection terminal DESAT5 and a fifth voltage detection device ADC5 connected to the fifth detection terminal DESAT5, such as an analog-to-digital converter. The fifth voltage detection device ADC5 is configured to acquire the voltage measurement value of the fifth device group M5. Similarly, the fifth control circuit DT5 can also be implemented using the desaturation detection (Desat detection) circuit originally configured in the drive circuit. The pins of this circuit are implemented as the fifth detection terminal DESAT5. For example, this circuit also includes a fifth input terminal IN5, a power supply terminal VCC5, and other structures.

[0076] For example, such as Figure 2 As shown, the sixth control circuit DT6 includes a sixth output terminal OUT6 and a sixth power supply DC6 connected to the sixth output terminal OUT6. The sixth power supply DC6 is configured to provide a configuration voltage. The sixth control circuit DT6 also includes a sixth detection terminal DESAT6 and a sixth voltage detection device ADC6 connected to the sixth detection terminal DESAT6, such as an analog-to-digital converter. The sixth voltage detection device ADC6 is configured to acquire the voltage measurement value of the sixth device group M6. Similarly, the sixth control circuit DT6 can also be implemented using the desaturation detection (Desat detection) circuit originally configured in the drive circuit. The pins of this circuit are implemented as the sixth detection terminal DESAT6. For example, this circuit also includes a sixth input terminal IN6, a power supply terminal VCC6, and other structures.

[0077] For example, obtaining the third calculated value using the third control circuit DT3 and the fourth control circuit DT4 includes the following steps S301~S304.

[0078] Step S301: Control the third power transistor Q3 to turn on.

[0079] Step S302: Control the fourth power transistor Q4 to conduct with the first voltage value, and detect the voltage between the first and second terminals of the third device group M3 to obtain the fifth measurement value.

[0080] Step S303: Control the fourth power transistor Q4 to conduct with the second voltage value, and detect the voltage between the first and second terminals of the third device group M3 to obtain the sixth measurement value.

[0081] Step S304: Generate the third calculated value based on the fifth and sixth measured values.

[0082] For example, the third calculated value can be the difference between the fifth and sixth measured values. This difference can be called the third difference Delta3, which is used to determine whether the third power transistor Q3 has failed.

[0083] The specific operation of obtaining the third calculated value using the third control circuit DT3 and the fourth control circuit DT4 can be referred to the above embodiment for obtaining the first calculated value, and will not be repeated here.

[0084] For example, obtaining the fourth calculated value using the third control circuit DT3 and the fourth control circuit DT4 includes the following steps S401~S404.

[0085] Step S401: Control the fourth power transistor Q4 to turn on.

[0086] Step S402: Control the third power transistor Q3 to conduct with the first voltage value, and detect the voltage between the first and second terminals of the fourth device group M4 to obtain the seventh measurement value.

[0087] Step S403: Control the third power transistor Q3 to conduct with the second voltage value, and detect the voltage between the first and second terminals of the fourth device group M4 to obtain the eighth measurement value.

[0088] Step S404: Generate the fourth calculated value based on the seventh and eighth measured values.

[0089] For example, the fourth calculated value can be the difference between the seventh and eighth measured values. This difference can be called the fourth difference Delta4, which is used to determine whether the fourth power transistor Q4 has failed.

[0090] The specific operation of obtaining the fourth calculated value using the third control circuit DT3 and the fourth control circuit DT4 can be referred to the above embodiment for obtaining the second calculated value, and will not be repeated here.

[0091] For example, obtaining the fifth calculated value using the fifth control circuit DT5 and the sixth control circuit DT6 includes the following steps S501~S504.

[0092] Step S501: Control the fifth power transistor Q5 to turn on.

[0093] Step S502: Control the sixth power transistor Q6 to conduct with the first voltage value, and detect the voltage between the first and second terminals of the fifth device group M5 to obtain the ninth measurement value.

[0094] Step S503: Control the sixth power transistor Q6 to conduct with the second voltage value, and detect the voltage between the first and second terminals of the fifth device group M5 to obtain the tenth measurement value.

[0095] Step S504: Generate the fifth calculated value based on the ninth and tenth measured values.

[0096] For example, the fifth calculated value can be the difference between the ninth and tenth measured values. This difference can be called the fifth difference Delta5, which is used to determine whether the fifth power transistor Q5 has failed.

[0097] The specific operation of obtaining the fifth calculated value using the fifth control circuit DT5 and the sixth control circuit DT6 can be referred to the above embodiment for obtaining the first calculated value, and will not be repeated here.

[0098] For example, obtaining the sixth calculated value includes the following steps S601~S604.

[0099] Step S601: Control the sixth power transistor Q6 to turn on.

[0100] Step S602: Control the fifth power transistor Q5 to conduct with the first voltage value, and detect the voltage between the first and second terminals of the sixth device group M6 to obtain the eleventh measurement value.

[0101] Step S603: Control the fifth power transistor Q5 to conduct with the second voltage value, and detect the voltage between the first and second terminals of the sixth device group M6 to obtain the twelfth measurement value.

[0102] Step S604: Generate the sixth calculated value based on the eleventh and twelfth measured values.

[0103] For example, the fifth calculated value can be the difference between the eleventh and twelfth measured values, which can be called the sixth difference, Delta6. The sixth difference, Delta6, is used to determine whether the sixth power transistor Q6 has failed.

[0104] The specific operation of obtaining the sixth calculated value using the fifth control circuit DT5 and the sixth control circuit DT6 can be referred to the above embodiment for obtaining the second calculated value, and will not be repeated here.

[0105] For example, in some embodiments, the determination of whether each power transistor has failed can be obtained by comparing the absolute values ​​of the first difference Delta1, the second difference Delta2, the third difference Delta3, the fourth difference Delta4, the fifth difference Delta5, and the sixth difference Delta6 with a first threshold and a second threshold, respectively. For example, if the absolute value of the difference is greater than the first threshold and less than the second threshold (the second threshold is greater than the first threshold), the corresponding power transistor is determined not to have failed; if the absolute value is less than the first threshold or greater than the second threshold, the corresponding power transistor is determined to have failed.

[0106] Alternatively, in other embodiments, after obtaining the first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, and the sixth calculated value, a reference value can be generated based on at least three (e.g., three, four, five, or six) of the first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, and the sixth calculated value; and the first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, and the sixth calculated value are compared with the reference value respectively, and the power transistor corresponding to the comparison result is used to determine whether a fault has occurred.

[0107] For example, in some embodiments, the reference value is the root mean square value, square root value, or average value of the first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, and the sixth calculated value.

[0108] For example, when the calculated values ​​are the differences between the measured values, the reference values ​​can be the root mean square, square root, or average of the first difference Delta1, the second difference Delta2, the third difference Delta3, the fourth difference Delta4, the fifth difference Delta5, and the sixth difference Delta6.

[0109] Therefore, by comparing multiple power devices (e.g.) Figure 3 The voltage measurement deviation of the six power devices in the system can detect power devices with lifespan or damage risk, avoiding the difficulty of setting thresholds due to factors such as needing to preset damage thresholds or power device batch fluctuations or aging.

[0110] For example, in some embodiments, the absolute value of the difference between the first calculated value and the reference value is compared with a first threshold and a second threshold. If the absolute value is greater than the first threshold and less than the second threshold (the second threshold is greater than the first threshold), it is determined that the first power transistor has not failed. If the absolute value is less than the first threshold or greater than the second threshold, it is determined that the first power transistor has failed.

[0111] For example, the reference value is set as DX, the absolute value of the difference between the first calculated value and the reference value is |Delta1-DX|, the first threshold is T1, and the second threshold is T2. If T2 > |Delta1-DX| > T1, then it is determined that the first power transistor has not failed. If |Delta1-DX| < T1 or |Delta1-DX| > T2, then it is determined that the first power transistor has failed.

[0112] Similarly, the absolute value of the difference between the second calculated value and the reference value is compared with the first threshold and the second threshold. If the absolute value is greater than the first threshold and less than the second threshold (the second threshold is greater than the first threshold), it is determined that the second power transistor Q2 is not faulty. If the absolute value is less than the first threshold or greater than the second threshold, it is determined that the second power transistor Q2 is faulty.

[0113] For example, if T2 > |Delta2-DX| > T1, then the second power transistor Q2 is determined to be not faulty; if |Delta2-DX| < T1 or |Delta2-DX| > T2, then the second power transistor Q2 is determined to be faulty.

[0114] Similarly, the absolute value of the difference between the third calculated value and the reference value is compared with the first threshold and the second threshold. If the absolute value is greater than the first threshold and less than the second threshold (the second threshold is greater than the first threshold), it is determined that the third power transistor Q3 is not faulty. If the absolute value is less than the first threshold or greater than the second threshold, it is determined that the third power transistor Q3 is faulty.

[0115] For example, if T2 > |Delta3-DX| > T1, then the third power transistor Q3 is determined to be not faulty; if |Delta3-DX| < T1 or |Delta3-DX| > T2, then the third power transistor Q3 is determined to be faulty.

[0116] Similarly, the absolute value of the difference between the fourth calculated value and the reference value is compared with the first threshold and the second threshold. If the absolute value is greater than the first threshold and less than the second threshold (the second threshold is greater than the first threshold), it is determined that the fourth power transistor Q4 is not faulty. If the absolute value is less than the first threshold or greater than the second threshold, it is determined that the fourth power transistor Q4 is faulty.

[0117] For example, if T2 > |Delta4-DX| > T1, then the fourth power transistor Q4 is determined to be not faulty; if |Delta4-DX| < T1 or |Delta4-DX| > T2, then the fourth power transistor Q4 is determined to be faulty.

[0118] Similarly, the absolute value of the difference between the fifth calculated value and the reference value is compared with the first threshold and the second threshold. If the absolute value is greater than the first threshold and less than the second threshold (the second threshold is greater than the first threshold), it is determined that the fifth power transistor Q5 is not faulty. If the absolute value is less than the first threshold or greater than the second threshold, it is determined that the fifth power transistor Q5 is faulty.

[0119] For example, if T2 > |Delta5-DX| > T1, then the fifth power transistor Q5 is determined to be not faulty; if |Delta5-DX| < T1 or |Delta5-DX| > T2, then the fifth power transistor Q5 is determined to be faulty.

[0120] Similarly, the absolute value of the difference between the sixth calculated value and the reference value is compared with the first threshold and the second threshold. If the absolute value is greater than the first threshold and less than the second threshold (the second threshold is greater than the first threshold), it is determined that the sixth power transistor Q6 is not faulty. If the absolute value is less than the first threshold or greater than the second threshold, it is determined that the sixth power transistor Q6 is faulty.

[0121] For example, if T2 > |Delta6-DX| > T1, then the sixth power transistor Q6 is determined to be not faulty; if |Delta6-DX| < T1 or |Delta6-DX| > T2, then the sixth power transistor Q6 is determined to be faulty.

[0122] For example, in some embodiments, the detection method further includes generating an alarm signal if a power transistor malfunctions. The alarm signal can be displayed in the form of text or sound to alert the user.

[0123] For example, a first alarm signal is generated when at least one of the first, second, third, fourth, fifth, and sixth power transistors fails; or, a first alarm signal is generated when the first power transistor fails, a second alarm signal is generated when the second power transistor fails, a third alarm signal is generated when the third power transistor fails, a fourth alarm signal is generated when the fourth power transistor fails, a fifth alarm signal is generated when the fifth power transistor fails, and a sixth alarm signal is generated when the sixth power transistor fails. This allows the user to promptly detect whether any power transistors have failed.

[0124] For example, in the above embodiment, the first detection circuit includes two device groups in the in-phase half-bridge as an example for illustration; in other embodiments, the two device groups in the out-of-phase half-bridge can also be divided into one detection circuit, for example, the first device group M1 and the sixth device group M6 are divided into one detection circuit, the third device group M3 and the second device group M2 are divided into one detection circuit, the fifth device group M1 and the fourth device group M4 are divided into one detection circuit; or, the first device group M1 and the fourth device group M4 are divided into one detection circuit, the third device group M3 and the second device group M2 are divided into one detection circuit, the fifth device group M5 and the sixth device group M6 are divided into one detection circuit, etc., and the method basically the same as that in the above embodiment is used to detect whether the power transistors of each device group have failed. The embodiments of this disclosure do not specifically limit the division of the detection circuit.

[0125] In addition, it should be noted that the detection order of the measurement values ​​of each power transistor in the embodiments of this disclosure is not limited, as long as the required measurement values ​​can be obtained.

[0126] At least one embodiment of this disclosure also provides a drive system for detecting whether a power transistor in a switching circuit has failed. For example, the drive system can be used to drive a motor or similar device. Figure 8 A schematic diagram of the drive system is shown, such as Figure 8 As shown, the drive system includes a drive circuit 100 and a processor CU, such as a microprocessor. For example, the controller CU sends first data DATA1 to the drive circuit 100 and receives second data DATA2 through an interface. For example, the first data includes instructions, such as a detection instruction, a power-on instruction, etc., and the second data includes various detection values ​​acquired by the drive circuit 100, such as the first detection value and the second detection value.

[0127] For example, refer to Figure 2 The switching circuit includes a first detection circuit, which includes a first device group M1 and a second device group M2. The first device group M1 includes a first power transistor Q1, and the second device group M2 includes a second power transistor Q2. The driving circuit includes a first control circuit DT1 and a second control circuit DT2.

[0128] The first control circuit DT1 has a first terminal (e.g., a first detection terminal DESAT1) and a second terminal (e.g., a first output terminal OUT1). The first terminal of the first control circuit DT1 is coupled to the first terminal (e.g., the second electrode C) of the first power transistor Q1 through a first diode D1. The second terminal of the first control circuit DT1 outputs a first output signal to the control terminal G of the first power transistor Q1. The second control circuit DT2 has a first terminal (e.g., a second detection terminal DESAT1) and a second terminal (e.g., a second output terminal OUT2). The first terminal of the second control circuit DT2 is coupled to the first terminal (e.g., the second electrode C) of the second power transistor Q2 through a second diode D2. The second terminal of the second control circuit DT2 outputs a second output signal to the control terminal G of the second power transistor Q2.

[0129] For example, the first terminal (e.g., the second terminal C) of the first device group M1 is coupled to the high-side bus VB, and the second terminal (e.g., the first terminal E) is coupled to the first switch node SW1. The first terminal (e.g., the second terminal C) of the second device group M2 is coupled to the first switch node SW1, and the second terminal (e.g., the first terminal E) is coupled to the low-side bus GND.

[0130] When the drive circuit operates in the power transistor state detection state, the first output signal controls the first power transistor Q1 to turn on, and the second output signal controls the second power transistor Q2 to turn on with the first voltage value V1 and the second voltage value V2, respectively. The first control circuit DT1 (through the first detection terminal DESAT1) detects the voltage between the first terminal and the second terminal of the first device group M1 to obtain the corresponding first measurement value and second measurement value. The processor CU generates a first calculated value based on the first measurement value and the second measurement value, and determines whether the first power transistor Q1 has failed based on the first calculated value.

[0131] For example, the specific method for determining whether the first power transistor Q1 has failed based on the first calculated value can be found in the above method embodiment, and will not be repeated here.

[0132] For example, when the drive circuit is in the power transistor state detection state, the second output signal controls the second power transistor Q2 to turn on, and the first output signal controls the first power transistor Q1 to turn on with the first voltage value V1 and the second voltage value V2 respectively. The second control circuit DT1 (through the second detection terminal DESAT1) detects the voltage between the first terminal and the second terminal of the second device group M2 to obtain the corresponding third and fourth measurement values. The controller CU generates a second calculated value based on the third and fourth measurement values ​​and determines whether the second power transistor Q2 has failed based on the second calculated value.

[0133] For example, the specific method for determining whether the second power transistor Q2 has failed based on the second calculated value can be found in the above method embodiment, and will not be repeated here.

[0134] For example, such as Figure 2 As shown, the switching circuit also includes a second detection circuit and a third detection circuit, and the driving circuit also includes a third control circuit DT3 and a fourth control circuit DT4. The third control circuit DT3 and the fourth control circuit DT4 have the same structure as the first control circuit DT and the second control circuit DT. That is, the third control circuit DT3 has a first terminal (e.g., the third detection terminal DESAT3) and a second terminal (e.g., the third output terminal OUT3). The first terminal of the third control circuit DT3 is coupled to the first terminal (e.g., the second electrode C) of the third power transistor Q3 through the third diode D3. The second terminal of the third control circuit DT3 outputs a third output signal to the control terminal G of the third power transistor Q1. The fourth control circuit DT4 has a first terminal (e.g., the fourth detection terminal DESAT4) and a second terminal (e.g., the fourth output terminal OUT4). The first terminal of the fourth control circuit DT4 is coupled to the first terminal (e.g., the second electrode C) of the fourth power transistor Q4 through the fourth diode D4. The second terminal of the fourth control circuit DT4 outputs a fourth output signal to the control terminal G of the fourth power transistor Q4.

[0135] For example, the first terminal (e.g., the second terminal C) of the third device group M3 is coupled to the high-side bus VB, and the second terminal (e.g., the first terminal E) is coupled to the second switch node SW2. The first terminal (e.g., the second terminal C) of the fourth device group M4 is coupled to the second switch node SW2, and the second terminal (e.g., the first terminal E) is coupled to the low-side bus GND.

[0136] The third control circuit DT3 and the fourth control circuit DT4 are configured to perform the same operations on the third power transistor Q3 and the fourth power transistor Q4 in the second detection loop as on the first power transistor Q1 and the second power transistor Q2 in the first detection loop, to obtain the third calculated value and the fourth calculated value.

[0137] For example, such as Figure 2 As shown, the driving circuit also includes a fifth control circuit DT5 and a sixth control circuit DT6. The fifth control circuit DT5 and the sixth control circuit DT6 have the same structure as the first control circuit DT1 and the second control circuit DT2. That is, the fifth control circuit DT5 has a first terminal (e.g., the fifth detection terminal DESAT5) and a second terminal (e.g., the fifth output terminal OUT5). The first terminal of the fifth control circuit DT5 is coupled to the first terminal (e.g., the second electrode C) of the fifth power transistor Q5 through the fifth diode D5. The second terminal of the fifth control circuit DT5 outputs a fifth output signal to the control terminal G of the fifth power transistor Q5. The sixth control circuit DT6 has a first terminal (e.g., the sixth detection terminal DESAT6) and a second terminal (e.g., the sixth output terminal OUT6). The first terminal of the sixth control circuit DT6 is coupled to the first terminal (e.g., the second electrode C) of the sixth power transistor Q6 through the sixth diode D6. The second terminal of the sixth control circuit DT6 outputs a sixth output signal to the control terminal G of the sixth power transistor Q6.

[0138] For example, the first terminal (e.g., the second terminal C) of the fifth device group M5 is coupled to the high-side bus VB, and the second terminal (e.g., the first terminal E) is coupled to the third switch node SW3. The first terminal (e.g., the second terminal C) of the fifth device group M5 is coupled to the third switch node SW3, and the second terminal (e.g., the first terminal E) is coupled to the low-side bus GND.

[0139] The fifth control circuit DT5 and the sixth control circuit DT6 perform the same operations on the fifth power transistor Q5 and the sixth power transistor Q6 in the third detection circuit as on the first power transistor Q1 and the second power transistor Q2 in the first detection circuit, to obtain the fifth calculated value and the sixth calculated value.

[0140] The processor CU determines whether the first power transistor Q1, the second power transistor Q2, the third power transistor, the fourth power transistor, the fifth power transistor, and the sixth power transistor are faulty based on the first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, and the sixth calculated value.

[0141] For example, a reference value is generated based on at least three of the first, second, third, fourth, fifth, and sixth calculated values; the first, second, third, fourth, fifth, and sixth calculated values ​​are compared with the reference values, and the corresponding power transistor is determined to be faulty based on the comparison result.

[0142] For example, in some embodiments, the reference value is the root mean square value, square root value, or average value of the first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, and the sixth calculated value.

[0143] For example, each calculated value can be the difference between two measured values ​​corresponding to each power transistor. In this case, the reference value can be the root mean square value, square root value, or average value of the difference corresponding to each power transistor.

[0144] For example, in some embodiments, the absolute values ​​of the differences between the first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, and the sixth calculated value and the reference value are compared with the first threshold and the second threshold. If the absolute value is greater than the first threshold and less than the second threshold (the second threshold is greater than the first threshold), it is determined that the corresponding power transistor has not failed. If the absolute value is less than the first threshold or greater than the second threshold, it is determined that the corresponding power transistor has failed.

[0145] For example, when at least one of the first, second, third, fourth, fifth, and sixth power transistors fails, the controller CU generates a first alarm signal; or, when the first power transistor fails, the controller CU generates a first alarm signal; when the second power transistor fails, the controller CU generates a second alarm signal; when the third power transistor fails, the controller CU generates a third alarm signal; when the fourth power transistor fails, the controller CU generates a fourth alarm signal; when the fifth power transistor fails, the controller CU generates a fifth alarm signal; and when the sixth power transistor fails, the controller CU generates a sixth alarm signal. Thus, the user can promptly know whether any power transistors have failed.

[0146] This driving system can implement the detection method provided in the embodiments of this disclosure and achieve essentially the same technical effect. For details, please refer to the embodiments of the above detection method, which will not be repeated here.

[0147] For example, the processor CU can be a microprocessor, a central processing unit (CPU), a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The central processing unit (CPU) can be an x86 or ARM architecture, etc. The embodiments of this disclosure do not limit the specific form of the processor CU.

[0148] At least one embodiment of this disclosure provides a method for detecting whether a power transistor in a switching circuit has failed, wherein the switching circuit includes multiple device groups, each device group includes a power transistor, and the detection method includes steps S701 to S705.

[0149] Step S701: Control the power transistor of the first device group to turn on, wherein the first device group is the device group under test among multiple device groups, and the other device groups among multiple device groups are control device groups;

[0150] Step S702: By controlling the conduction state of the control device group, the current flowing through the power transistor of the first device group is controlled to be the first current, and the voltage between the first terminal and the second terminal of the first device group is detected to obtain the first measurement value;

[0151] Step S703: By controlling the conduction state of the control device group, the current flowing through the power transistor of the first device group is controlled to be a second current, which is different from the first current. The voltage between the first terminal and the second terminal of the first device group is detected to obtain a second measurement value.

[0152] Step S704: Generate a first calculated value based on the first measured value and the second measured value; and

[0153] Step S705: Determine whether the power transistor of the first device group has failed based on the first calculated value.

[0154] For example, in step S701, the first device group is the device group to be detected among multiple device groups, and the remaining device groups among multiple device groups are control device groups. For example, at least one of the remaining device groups is selected to cooperate with the device group to be detected to form a detection circuit and perform the above detection. At this time, the unselected device groups among the remaining device groups can be controlled to be in a closed state.

[0155] For example, in some embodiments, in Figure 2 In the embodiments, the first device group M1 is the device group to be detected, and a second device group M2 that is in phase with the first device group M1 can be selected to cooperate with the first device group M1 to achieve the following: Figure 1 and Figure 5 The operation shown; alternatively, a fourth device group M4 or a sixth device group M6, which is out of phase with the first device group M1, can be selected to cooperate with the first device group M1 to achieve the operation shown. Figure 1 and Figure 5 Alternatively, the same operation can be performed, or the fourth device group M4 and the sixth device group M6, which are out of phase with the first device group M1, can be selected to cooperate with the first device group M1 to achieve the same operation as... Figure 1 and Figure 5 Similar operations.

[0156] For example, by selecting fourth device group M4 and sixth device group M6, which are out of phase with the first device group M1, to cooperate with the first device group M1, a connection can be achieved. Figure 1 and Figure 5 In similar operation scenarios, the second device group M2, the third device group M3, and the fifth device group M5 are in the off state. At this time, the detection steps may include S801~S805.

[0157] Step S801: Control the first power transistor of the first device group M1 to be turned on, and the power transistors of the other device groups to be turned off;

[0158] Step S802: Control the fourth power transistor Q4 of the fourth device group M4 to turn on with the first voltage value, and control the sixth power transistor Q6 of the sixth device group M6 to turn on with the second voltage value. At this time, the current flowing through the first power transistor Q1 of the first device group M1 is the first current. Detect the voltage between the first terminal and the second terminal of the first device group M1 to obtain the first measurement value.

[0159] Step S803: Control the fourth power transistor Q4 of the fourth device group M4 to turn on with the third voltage value, and control the sixth power transistor Q6 of the sixth device group M6 to turn on with the fourth voltage value. At this time, the current flowing through the first power transistor Q1 of the first device group M1 is the second current. The second current is different from the first current. Detect the voltage between the first terminal and the second terminal of the first device group M1 to obtain the second measurement value.

[0160] Step S804: Generate a first calculated value based on the first measured value and the second measured value; and

[0161] Step S805: Determine whether the power transistor of the first device group M1 has failed based on the first calculated value.

[0162] For example, the first voltage value can be equal to the second voltage value, and the third voltage value can be equal to the fourth voltage value. Alternatively, the first voltage value may not be equal to the third voltage value, and / or the second voltage value may not be equal to the fourth voltage value.

[0163] For example, the method for determining whether the power transistor of the first device group M1 has failed based on the first calculated value can refer to the above embodiment, and will not be repeated here.

[0164] For example, the detection method also includes performing the same operation as the first device group M1 on the remaining device groups in the multiple device groups to determine whether the power transistors in the remaining device groups have failed.

[0165] For example, such as Figure 2 As shown, multiple device groups include a first device group M1, a second device group M2, a third device group M3, a fourth device group M4, a fifth device group M5, and a sixth device group M6. The detection method further includes: performing the same operation as the first device group M1 on the second device group M2, the third device group M3, the fourth device group M4, the fifth device group M5, and the sixth device group M6 respectively to obtain the second calculated value of the second device group M2, the third calculated value of the third device group M3, the fourth calculated value of the fourth device group M4, the fifth calculated value of the fifth device group M5, and the sixth calculated value of the sixth device group M6 respectively; and determining whether the first power transistor Q1 of the first device group M1, the second power transistor Q2 of the second device group M2, the third power transistor Q3 of the third device group M3, the fourth power transistor Q4 of the fourth device group M4, the fifth power transistor Q5 of the fifth device group M5, and the sixth power transistor Q6 of the sixth device group M6 have failed based on the first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, and the sixth calculated value.

[0166] For example, for the second device group M2, the third device group M3 and the fifth device group M5, which are out of phase with the second device group M2, can be selected to cooperate with the second device group M2 to achieve the same operation as steps S801-S805, thereby obtaining the second calculated value, and judging whether the second power transistor Q2 of the second device group M2 has failed based on the second calculated value.

[0167] For the third device group M3, the second device group M2 and the sixth device group M6, which are out of phase with the third device group M3, can be selected to cooperate with the third device group M3 to achieve the same operation as steps S801-S805, thereby obtaining the third calculated value, and judging whether the third power transistor Q3 of the third device group M3 has failed based on the third calculated value.

[0168] For the fourth device group M4, the first device group M1 and the fifth device group M5, which are out of phase with the fourth device group M4, can be selected to cooperate with the fourth device group M4 to achieve the same operation as steps S801-S805, thereby obtaining the fourth calculated value, and judging whether the fourth power transistor Q4 of the fourth device group M4 has failed based on the fourth calculated value.

[0169] For the fifth device group M5, the second device group M2 and the fourth device group M4, which are out of phase with the fifth device group M5, can be selected to cooperate with the fifth device group M5 to achieve the same operation as steps S801-S805, thereby obtaining the fifth calculated value, and judging whether the fifth power transistor Q5 of the fifth device group M5 has failed based on the fifth calculated value.

[0170] For the sixth device group M6, the first device group M1 and the third device group M3, which are out of phase with the sixth device group M6, can be selected to cooperate with the sixth device group M6 to achieve the same operation as steps S801-S805, thereby obtaining the sixth calculated value, and judging whether the sixth power transistor Q6 of the sixth device group M6 has failed based on the sixth calculated value.

[0171] For example, in some embodiments, a reference value is generated based on at least three (e.g., three, four, five, or six) of a first calculated value, a second calculated value, a third calculated value, a fourth calculated value, a fifth calculated value, and a sixth calculated value; and the first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, and the sixth calculated value are compared with the reference value respectively, and the power transistor of the corresponding device group is determined based on the comparison result. For example, the specific determination method can be referred to the above embodiments, and will not be repeated here.

[0172] For example, in other embodiments, different voltage configurations may be used to obtain the various measurements.

[0173] For example, such as Figure 2As shown, by selecting the fourth device group M4 and the sixth device group M6, which are out of phase with the first device group M1, to cooperate with the first device group M1, a connection is achieved. Figure 1 and Figure 5 In similar operation scenarios, the second device group M2, the third device group M3, and the fifth device group M5 are in the off state. At this time, the detection steps may include S901~9805.

[0174] Step S901: Turn on the first power transistor Q1 of the first device group M1, and turn off the power transistors of the other device groups;

[0175] Step S902: Control the fourth power transistor Q4 of the fourth device group M4 to turn on with the first voltage value. At this time, the current flowing through the first power transistor of the first device group M1 is the first current. Detect the voltage between the first terminal and the second terminal of the first device group M1 to obtain the first measurement value.

[0176] Step S903: Control the fourth power transistor Q4 of the fourth device group M4 to turn on with the second voltage value, and control the sixth power transistor Q6 of the sixth device group M6 to turn on with the third voltage value. At this time, the current flowing through the first power transistor Q1 of the first device group M1 is the second current. The second current is different from the first current. Detect the voltage between the first terminal and the second terminal of the first device group M1 to obtain the second measurement value.

[0177] Step S904: Generate a first calculated value based on the first measured value and the second measured value; and

[0178] Step S905: Determine whether the power transistor of the first device group M1 has failed based on the first calculated value.

[0179] For example, the first voltage value can be equal to the second voltage value, and the third voltage value can be equal to or not equal to the second voltage value, as long as the second current flowing through the first power transistor Q1 of the first device group M1 is different from the first current.

[0180] At this time, the detection method further includes: performing the same operation as the first device group M1 on the second device group M2, the third device group M3, the fourth device group M4, the fifth device group M5, and the sixth device group M6 respectively, to obtain the second calculated value of the second device group M2, the third calculated value of the third device group M3, the fourth calculated value of the fourth device group M4, the fifth calculated value of the fifth device group M5, and the sixth calculated value of the sixth device group M6 respectively; and determining whether the first power transistor Q1 of the first device group M1, the second power transistor Q2 of the second device group M2, the third power transistor Q3 of the third device group M3, the fourth power transistor Q4 of the fourth device group M4, the fifth power transistor Q5 of the fifth device group M5, and the sixth power transistor Q6 of the sixth device group M6 have failed based on the first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, and the sixth calculated value.

[0181] For specific judgment methods, please refer to the above embodiments, which will not be repeated here.

[0182] For example, in some embodiments, the driving circuit is configured to drive a first device, such as a... Figure 3 In the motor PMSM, or in other embodiments, the first device can also be an inverter driver, various high-power motors, etc.; responding to the detection command includes responding to the start command of the first device PMSM. That is, when the first device receives the start command, it first checks whether the power transistors are faulty. If it is detected that none of the power transistors in the drive circuit are faulty, that is, they are in a healthy state, then the first device is driven to work; when it is detected that all power devices in the switching circuit are faulty, an alarm signal is issued, and the first device is no longer driven to work.

[0183] For example, when a PMSM motor is used in a new energy vehicle, the response to detection commands includes: responding to the start command of the new energy vehicle, so that when it is detected that all power transistors in the drive circuit are in a healthy state, the new energy vehicle is driven to drive; when a fault is detected in a power device in the drive circuit, an alarm signal is issued, and the new energy vehicle cannot drive.

[0184] In the monitoring method provided in this embodiment, for each device group, the two voltage measurements can characterize the impedance of the power transistor in the device group. Therefore, when the increase in the impedance of the power transistor exceeds a set threshold, it is determined that the power transistor may have a problem and is close to failure. Thus, an alarm is issued in advance to avoid the occurrence of faults and to avoid online faults. For example, it can prevent faults from occurring during motor operation, such as when the motor is used in new energy vehicles, to prevent the new energy vehicles from breaking down on the road.

[0185] In the monitoring method provided in this embodiment, the half-bridge power module generates its own excitation current without external injection; by measuring the relative deviation of the voltage instead of the absolute value of the voltage (the absolute value is difficult to set and will drift with temperature and time), more accurate measurement results can be obtained; by measuring the voltage instead of the current of the power transistor, the system design can be simplified (high-precision current sensors or Hall sensors are not required); by measuring the voltage difference (without gate voltage) of the same power transistor twice, errors in the measurement path (such as deviations in the detection path DESAT, voltage differences of components such as diodes, and offsets of the voltage detection device) are eliminated.

[0186] Furthermore, the monitoring method provided in this disclosure embodiment can be a power-on detection method. When the system (e.g., a new energy vehicle) is powered on and before the motor rotates, each power transistor and drive circuit is controlled by the system, and the impedance of each power transistor is monitored sequentially. Moreover, the control circuit DT can be implemented by using an existing circuit in the drive circuit through configuration program control. For example, if the drive circuit is originally configured with a desaturation detection (Desat detection) circuit, the control circuit DT can be reused to implement the above-mentioned monitoring method provided in this disclosure embodiment. Furthermore, the voltage measurement value detected by this circuit can characterize the on-resistance of the power transistor, avoiding the detection of high-voltage current (traditional impedance detection requires calculating voltage divided by current).

[0187] In the monitoring method provided in this disclosure, by measuring the same device group / power transistor twice under different currents and calculating the difference, it is possible to avoid measurement path deviations (e.g., deviations in the on-state voltage drop of high-voltage diodes along the measurement path) or fluctuations in the current controlled by the voltage configuration due to time, circuit aging, or temperature fluctuations. Furthermore, in some embodiments, by comparing multiple power transistors (e.g., ... Figure 3 The voltage measurement deviation of the six power transistors in the system can detect power transistors with a risk of lifespan loss or damage, avoiding the difficulty of setting thresholds due to factors such as presetting damage thresholds or batch fluctuations or aging of power transistors.

[0188] At least one embodiment of this disclosure also provides an electronic device. Figure 9 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this disclosure, such as... Figure 9 As shown, the electronic device includes a processor 201 and a memory 202. For example, the processor 201 and the memory 202 are connected via a bus 203. The memory 202 stores computer-executable instructions; the processor 201 executes the computer-executable instructions, causing the processor 201 to perform the method provided in this embodiment for detecting whether a power transistor in a switching circuit has failed.

[0189] For example, memory 202 is used to non-transitory store computer-executable instructions, and processor 201 can control other components in the electronic device to perform desired functions. For example, processor 201 can be a central processing unit (CPU), a network processor (NP), or a digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The central processing unit (CPU) can be an x86 or ARM architecture, etc. The embodiments of this disclosure do not limit the specific form of processor 201.

[0190] For example, memory 202 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer-executable instructions may be stored on the computer-readable storage medium, and processor 201 may execute the computer-executable instructions to implement various functions of the electronic device.

[0191] For example, the electronic device can implement the steps of the health monitoring method provided in the embodiments of this disclosure and achieve the corresponding technical effects. For details, please refer to the embodiments of the above-mentioned health monitoring method, which will not be repeated here.

[0192] At least one embodiment of this disclosure also provides a computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the above-described method for detecting whether a power transistor in a switching circuit has malfunctioned.

[0193] This disclosure provides a computer program product, including a computer program that, when executed by a processor, implements the method described above for detecting whether a power transistor in a switching circuit has malfunctioned.

[0194] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0195] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0196] The aforementioned computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform the methods shown in the above embodiments.

[0197] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0198] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0199] The units or modules described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units or modules do not necessarily limit the specific unit itself.

[0200] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), and so on.

[0201] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0202] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0203] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0204] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A method for detecting whether a power transistor in a switching circuit has malfunctioned, wherein, The switching circuit includes a first detection circuit, the first detection circuit includes a first device group and a second device group, the first device group includes a first power transistor, and the second device group includes a second power transistor; the method includes: Control the first power transistor to turn on; The second power transistor is turned on by controlling the first voltage value, and the voltage between the first terminal and the second terminal of the first device group is detected to obtain the first measurement value; The second power transistor is turned on by controlling the second voltage value, and the voltage between the first terminal and the second terminal of the first device group is detected to obtain the second measurement value; A first calculated value is generated based on the first measured value and the second measured value; and Determine whether the first power transistor has malfunctioned based on the first calculated value.

2. The detection method as described in claim 1, further comprising: Control the second power transistor to turn on; The first power transistor is turned on by controlling the first voltage value, and the voltage between the first and second terminals of the second device group is detected to obtain a third measurement value. The first power transistor is turned on by controlling the second voltage value, and the voltage between the first and second terminals of the second device group is detected to obtain a fourth measurement value. A second calculated value is generated based on the third and fourth measured values; as well as Determine whether the second power transistor has malfunctioned based on the second calculated value.

3. The detection method according to claim 1 or 2, wherein, The first device group is coupled to the high-side bus and the first switching node, and the second device group is coupled to the first switching node and the low-side bus, or The first device group is coupled to the high-side bus and the first switch node, and the second device group is coupled to the second node and the low-side bus.

4. The detection method according to claim 2, wherein, The switching circuit further includes a second detection circuit and a third detection circuit, and the method further includes: Perform the same operations on the third and fourth power transistors in the second detection circuit as on the first and second power transistors in the first detection circuit to obtain the third and fourth calculated values; Perform the same operations on the fifth and sixth power transistors in the third detection loop as on the first and second power transistors in the first detection loop to obtain the fifth and sixth calculated values; and Based on the first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, and the sixth calculated value, it is determined whether the first power transistor, the second power transistor, the third power transistor, the fourth power transistor, the fifth power transistor, and the sixth power transistor have malfunctioned.

5. The detection method according to claim 4, wherein, Determining whether the first power transistor, the second power transistor, the third power transistor, the fourth power transistor, the fifth power transistor, and the sixth power transistor have malfunctioned based on the first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, and the sixth calculated value includes: At least three of the following calculated values—the first, the second, the third, the fourth, the fifth, and the sixth—are used to generate reference values; and The first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, the sixth calculated value, and the reference value are compared, and the corresponding power transistor is determined to be faulty based on the comparison result.

6. The detection method according to claim 5, wherein, The reference value is the root mean square value, square root value, or average value of the first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, and the sixth calculated value.

7. The detection method according to claim 5, wherein, The calculations are compared with the first, second, third, fourth, fifth, and sixth values, and the reference value. Based on the comparison results, it is determined whether the corresponding power transistor has malfunctioned. The absolute value of the difference between the first calculated value and the reference value is compared with a first threshold and a second threshold. If the absolute value is greater than the first threshold and less than the second threshold, it is determined that the first power transistor is not faulty. If the absolute value is less than the first threshold or greater than the second threshold, it is determined that the first power transistor is faulty, wherein the second threshold is greater than the first threshold.

8. The detection method according to any one of claims 1-7, wherein, The first device group further includes a first diode, the anode of which is coupled to a first terminal of the first device group, and the second device group further includes a second diode, the anode of which is coupled to a first terminal of the second device group.

9. The detection method according to any one of claims 1-7, further comprising: When the first power transistor fails, a first alarm signal is generated.

10. A drive system for detecting whether a power transistor in a switching circuit has malfunctioned, wherein, The switching circuit includes a first detection circuit, which includes a first device group and a second device group. The first device group includes a first power transistor, and the second device group includes a second power transistor. The driving system includes a driving circuit and a processor. The driving circuit includes: A first control circuit has a first terminal and a second terminal, wherein the first terminal of the first control circuit is coupled to the first terminal of the first power transistor via a first diode, and the second terminal of the first control circuit outputs a first output signal to the control terminal of the first power transistor; and The second control circuit has a first terminal and a second terminal, wherein the first terminal of the second control circuit is coupled to the first terminal of the second power transistor through a second diode, and the second terminal of the second control circuit outputs a second output signal to the control terminal of the second power transistor. When the driving circuit is in the power transistor state detection state, the first output signal controls the first power transistor to turn on, and the second output signal controls the second power transistor to turn on with a first voltage value and a second voltage value, respectively. The first control circuit detects the voltage between the first terminal and the second terminal of the first device group to obtain the corresponding first measurement value and second measurement value. The processor generates a first calculated value based on the first measured value and the second measured value; and determines whether the first power transistor has malfunctioned based on the first calculated value.

11. The drive system according to claim 10, wherein, When the driving circuit is in the power transistor state detection state, the second output signal controls the second power transistor to turn on, and the first output signal controls the first power transistor to turn on with the first voltage value and the second voltage value respectively. The second control circuit detects the voltage between the first terminal and the second terminal of the second device group to obtain the corresponding third measurement value and fourth measurement value. The processor generates a second calculated value based on the third and fourth measured values; And determine whether the second power transistor has malfunctioned based on the second calculated value.

12. The drive system according to claim 11, wherein, The switching circuit further includes a second detection circuit and a third detection circuit, and the driving circuit further includes: The third and fourth control circuits have the same structure as the first and second control circuits. They perform the same operations on the third and fourth power transistors in the second detection circuit as on the first and second power transistors in the first detection circuit to obtain the third and fourth calculated values. The fifth and sixth control circuits have the same structure as the first and second control circuits. They perform the same operations on the fifth and sixth power transistors in the third detection circuit as on the first and second power transistors in the first detection circuit to obtain the fifth and sixth calculated values. The processor determines whether the first power transistor, the second power transistor, the third power transistor, the fourth power transistor, the fifth power transistor, and the sixth power transistor have malfunctioned based on the first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, and the sixth calculated value.

13. The drive system according to claim 12, wherein, Determining whether the first power transistor, the second power transistor, the third power transistor, the fourth power transistor, the fifth power transistor, and the sixth power transistor have malfunctioned based on the first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, and the sixth calculated value includes: At least three of the following calculated values—the first, the second, the third, the fourth, the fifth, and the sixth—are used to generate reference values; and The first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, the sixth calculated value, and the reference value are compared, and the corresponding power transistor is determined to be faulty based on the comparison result.

14. The drive system according to claim 13, wherein, The reference value is the root mean square value, square root value, or average value of the first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, and the sixth calculated value.

15. The drive system according to claim 10, for driving a motor.

16. A method for detecting whether a power transistor in a switching circuit has malfunctioned, wherein, The switching circuit includes multiple device groups, each device group including a power transistor, and the method includes: The power transistor of the first device group is turned on, wherein the first device group is the device group under test among the plurality of device groups, and the remaining device groups among the plurality of device groups are control device groups; By controlling the conduction state of the control device group, the current flowing through the power transistor of the first device group is controlled to be a first current, and the voltage between the first terminal and the second terminal of the first device group is detected to obtain a first measurement value. By controlling the conduction state of the control device group, the current flowing through the power transistor of the first device group is controlled to be a second current, which is different from the first current. The voltage between the first terminal and the second terminal of the first device group is detected to obtain a second measurement value. A first calculated value is generated based on the first measured value and the second measured value; and Based on the first calculated value, determine whether the power transistor of the first device group has failed.

17. The method of claim 16, further comprising: Perform the same operation as the first device group on the remaining device groups to determine whether the power transistors in the remaining device groups have failed.

18. The method according to claim 16, wherein, The plurality of device groups includes a first device group, a second device group, a third device group, a fourth device group, a fifth device group, and a sixth device group, and the method further includes: The same operation as the first device group is performed on the second device group, the third device group, the fourth device group, the fifth device group, and the sixth device group respectively to obtain the second calculated value of the second device group, the third calculated value of the third device group, the fourth calculated value of the fourth device group, the fifth calculated value of the fifth device group, and the sixth calculated value of the sixth device group respectively. Based on the first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, and the sixth calculated value, it is determined whether the power transistors of the first device group, the second device group, the third device group, the fourth device group, the fifth device group, and the sixth device group have malfunctioned.

19. The detection method according to claim 18, wherein, Determining whether the power transistors of the first device group, the second device group, the third device group, the fourth device group, the fifth device group, and the sixth device group have malfunctioned based on the first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, and the sixth calculated value includes: At least three of the following calculated values—the first, the second, the third, the fourth, the fifth, and the sixth—are used to generate reference values; and The first calculated value, the second calculated value, the third calculated value, the fourth calculated value, the fifth calculated value, the sixth calculated value, and the reference value are compared, and the power transistor of the corresponding device group is determined to be faulty based on the comparison result.

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