Delay processing architecture for ultrasonic chip

Abstract

The invention provides a delay processing architecture for an ultrasonic chip, and the architecture comprises an ultrasonic core array which comprises a first ultrasonic core region and a second ultrasonic core region which are split along a horizontal axis, and each ultrasonic core region comprises a plurality of ultrasonic module arrays; each ultrasonic module comprises a plurality of ultrasonic sub-arrays; the double-zone time delay center comprises a first time delay zone and a second time delay zone, the first time delay zone is used for generating a time delay signal of the first ultrasonic core zone, and the second time delay zone is used for generating a time delay signal of the second ultrasonic core zone; wherein each time delay partition comprises a plurality of time delay calculation centers, each time delay calculation center is connected to a plurality of ultrasonic modules, ultrasonic sub-arrays in the ultrasonic modules are cascaded, and the time delay calculation centers are used for generating time delay signals of the ultrasonic sub-arrays in the corresponding ultrasonic modules. Different complexity and real-time requirements of delay can be adapted only by adjusting the command queue, and hardware modules do not need to be modified, so that the development period is greatly shortened.

Description

Technical Field

[0001] This invention relates to ultrasonic chips, and more specifically, to a delay processing architecture for ultrasonic chips. Background Technology

[0002] As computing tasks and data processing demands become increasingly complex, traditional processors and general-purpose computing platforms are gradually revealing significant performance bottlenecks, especially in scenarios requiring massive numerical computations and high-density data processing, such as scientific computing, real-time signal processing, and large-scale big data analysis. The computing speed and energy efficiency of existing hardware platforms are no longer sufficient to meet the demands for high-efficiency processing. To address this challenge, there is an urgent need to optimize the computational flow of polynomial algorithms through dedicated hardware acceleration solutions, thereby breaking through performance bottlenecks and improving overall computing performance.

[0003] In the field of hardware implementation of polynomial computation, the core idea of ​​the traditional technical approach is to customize dedicated hardware computation modules for specific polynomials. These modules are usually composed of hardware acceleration units (such as multipliers and adders) combined in a cascaded or parallel manner, directly performing operations on each term in the polynomial. For example, for polynomials of different orders or coefficient ranges, designers need to manually select hardware structures according to their complexity, including matching multipliers and adders with different bit widths, or adjusting the connection logic of the arithmetic units; for special operations such as division, they are mostly implemented directly in hardware or combined with lookup tables (LUTs) for local optimization.

[0004] However, existing hardware acceleration methods have multiple shortcomings and deficiencies in practical applications, specifically in the following five aspects:

[0005] (1) Specialized hardware design and lack of flexibility: Because a dedicated computing module needs to be designed for each polynomial, the adaptability of the hardware system is severely limited. When business requirements change or new types of polynomials are introduced, the hardware must be redesigned or adjusted on a large scale, which not only consumes a lot of R&D time and resources, but also significantly increases development costs and time.

[0006] (2) There are bottlenecks in computational efficiency and insufficient adaptability. Although dedicated hardware is optimized for specific computing scenarios, its performance advantages are difficult to fully realize when dealing with polynomials with complex structures or dynamic changes. Especially in high-precision computing scenarios or when dealing with complex polynomials with multi-factor multiplication terms, existing designs often form computational bottlenecks due to problems such as insufficient adaptability of computing units and low data flow efficiency.

[0007] (3) Low utilization of hardware resources and waste: In most designs, core hardware resources such as multipliers and adders need to be statically configured according to the operation requirements of specific polynomials. However, in actual operation, these resources are often in a non-full-load state due to changes in task load or adjustments to the polynomial structure. Since the hardware modules cannot dynamically and adaptively adjust resource allocation, it ultimately leads to inefficient use of resources, increasing hardware costs and energy consumption.

[0008] (4) Poor system scalability and high iteration cost: The design logic of the current hardware module is deeply coupled with the structure of the target polynomial. Once the order, coefficient type or operation rules of the polynomial change, a large-scale reconstruction of the hardware architecture is usually required, rather than a local adjustment. This strong coupling makes it difficult for the system to quickly adapt to new requirements, and its scalability is severely limited.

[0009] (5) High maintenance complexity and high stability risk: As the number of dedicated hardware modules increases, the complexity of their management and maintenance increases exponentially. Due to the implicit dependencies between modules, updating or modifying a single module may trigger a chain reaction in the entire design system, which not only increases the maintenance difficulty but also increases the system stability risk.

[0010] In summary, current ultrasonic signal delay processing solutions based on polynomial algorithms are generally customized for specific polynomial structures and algorithmic logic, resulting in a severe lack of versatility. Once the application scenario changes or the algorithmic logic iterates, the hardware architecture often needs to be redesigned. This not only prolongs the development cycle and increases time costs but also greatly limits the flexibility of the solution in multiple application fields. Furthermore, existing hardware acceleration designs face key challenges during chip-level implementation, such as timing convergence difficulties, excessive chip power consumption, and a surge in design complexity. These problems collectively lead to a significant decrease in the scalability and adaptability of existing technologies, making it difficult to match the ever-evolving algorithmic requirements, thus hindering their large-scale application in fields such as ultrasonic signal processing. Therefore, developing an ultrasonic signal delay processing solution that combines high versatility and high computational efficiency has become an urgent industry need. This solution must maintain stable operation under different algorithmic logics and application scenarios while reducing hardware development and maintenance costs. Summary of the Invention

[0011] In view of the shortcomings of the prior art, the purpose of this invention is to provide a delay processing architecture for ultrasound chips.

[0012] The delay processing architecture for an ultrasound chip provided by the present invention includes:

[0013] An ultrasound core array includes a first ultrasound core region and a second ultrasound core region divided along a horizontal axis, each of the ultrasound core regions including multiple ultrasound module arrays; each ultrasound module including multiple ultrasound sub-arrays.

[0014] The dual-zone delay center includes a first delay zone and a second delay zone. The first delay zone is used for generating the delay signal of the first ultrasound core area, and the second delay zone is used for generating the delay signal of the second ultrasound core area.

[0015] Each of the delay partitions includes multiple delay calculation centers, each delay calculation center is connected to several ultrasound modules, and the ultrasound subarrays within the ultrasound modules are cascaded. The delay calculation center is used to generate delay signals for the corresponding ultrasound subarrays within the ultrasound modules.

[0016] Preferably, the ultrasonic subarray includes: ultrasonic transceiver elements, digital units, beamforming units, and gain amplifiers;

[0017] Multiple ultrasonic transceiver array elements are used to drive the transducer array elements to emit ultrasonic waves and to receive the echo electrical signals generated by the transducer array elements after receiving ultrasonic waves.

[0018] The beamforming unit is used to perform beamforming based on multiple echo electrical signals from different array elements within the same subarray to enhance the echo electrical signals.

[0019] The gain amplifier is used to amplify the electrical signal after beamforming;

[0020] The digital unit is used to control the order in which the ultrasonic transceiver array element transmits ultrasonic waves and receives echo electrical signals according to the delay signal.

[0021] Preferably, the delay signal includes a transmit delay signal and a receive delay signal;

[0022] The ultrasonic transceiver array element includes:

[0023] The pulse transmitting circuit is used to generate a pulse electrical signal based on the transmission delay signal to drive the transducer array elements to emit ultrasonic waves;

[0024] The echo receiving circuit is used to sequentially receive and amplify the echo electrical signal generated by the transducer array element after receiving ultrasonic waves, based on the received delay signal.

[0025] A switching switch is used to switch the connection or disconnection of the transducer array element with the pulse transmitting circuit and the echo receiving circuit.

[0026] Preferably, the delay calculation center includes:

[0027] The computation scheduling unit serves as the global control center for delayed computation. On the one hand, it issues operation commands to the arithmetic computation unit to drive delayed computation; on the other hand, it receives write status information of external registers from the result output control unit to adjust the computation rhythm.

[0028] The arithmetic calculation unit is used to perform multiplication and accumulation operations based on the operation command, convert the operation command into basic intermediate data required for delay calculation, and provide it to the channel delay calculation unit;

[0029] The channel delay calculation unit is used to receive the basic intermediate data, complete the final calculation of the channel delay, generate a delay signal, and transmit it to the result output control unit.

[0030] The result output control unit is used to receive the delay signal, output the delay signal to the external register in an orderly manner, and at the same time feed back the write status information of the external register to the calculation scheduling unit.

[0031] Preferably, the computation scheduling unit includes:

[0032] A finite state machine is used to receive the start signal for delayed computation, output the start operation signal and the current stage completion signal, so as to control the state switching of the entire computation process;

[0033] The command storage unit is used to classify and store command queues for different delay calculation tasks, including the transmit delay command queue and the receive delay command queue.

[0034] The command counter is used to track the execution progress of the command queue and control the selection of the command queue at different computation stages.

[0035] The command queue selector is used to select the command queue corresponding to the current stage according to the control of the command counter, and output the operation command to the arithmetic calculation unit.

[0036] Preferably, the arithmetic calculation unit includes:

[0037] The command parser is used to parse the operation commands from the scheduling unit and generate cumulative multiplication and addition calculation instructions;

[0038] The multiply-accumulate unit is used to perform multiply-accumulate operations on the command queue according to the multiply-accumulate calculation instructions to generate the subarray transmit delay signal, the X and Y direction subarray transmit delay signals, and the X and Y direction subarray receive intermediate values;

[0039] The trimmer is used to trim the transmission delay signal of the subarray and output it to the result output control unit.

[0040] Preferably, the channel delay calculation unit includes:

[0041] Multiple sets of parallel computing units, each of which includes multiple basic computing components, are used to calculate the output channel transmission delay signal based on the X and Y direction subarray transmission delay signals, and to calculate the output subarray reception delay signal and the channel reception delay signal based on the X and Y direction subarray reception intermediate values;

[0042] Multiple basic arithmetic components, including adders, absolute value calculators, rounders, integer calculators, minimum value calculators, maximum value calculators, left shifters, and right shifters.

[0043] Preferably, the result output control unit includes:

[0044] A receive delay register is used to temporarily store the channel receive delay signal and the subarray receive delay signal;

[0045] The transmit delay register is used to temporarily store the transmit delay signal of the channel and the transmit delay signal of the subarray;

[0046] A scheduler is used to control the sequential writing of the transmit delay signal and the receive delay signal into an external register;

[0047] The output shifter is used to output the received delay signal and the transmitted delay signal, and at the same time to feed back the write status information of the external register to the computing and scheduling unit.

[0048] Preferably, the generation of the command queue includes:

[0049] Obtain the polynomials used to calculate the delays of ultrasonic transmission and reception;

[0050] The polynomial is split and sorted to obtain the order of calculation for each term;

[0051] Each item generates a command, forming the command queue.

[0052] Preferably, the process of splitting and sorting the polynomial includes:

[0053] When multiplying multiple factors, it is necessary to break it down into multiple steps of multiplying two factors at a time and store the product in a temporary register. The product is then accumulated after all factors have been multiplied.

[0054] For a polynomial containing subpolynomials, the subpolynomials are calculated first.

[0055] Compared with the prior art, the present invention has the following beneficial effects:

[0056] This invention constructs a distributed parallel architecture by setting up multiple delay calculation centers that work synchronously in a dual-partition delay center. Each delay calculation center processes the delay calculation of two adjacent ultrasound sub-arrays in parallel. At the same time, it designs dual independent write interfaces to realize a pipeline mechanism that enables parallel calculation and writing. Based on the write status feedback of external registers, the calculation is temporarily paused when there is a risk of data overwrite, avoiding idle waste and ensuring that the delay parameters are updated in real time, perfectly supporting the dynamic real-time imaging of the heart by transthoracic ultrasound.

[0057] This invention employs a general multiply-accumulate architecture based on a command queue, decomposing all polynomials into "A×B / C" operations. Division operations are replaced by shift operations. Each delay calculation center requires only one multiply-accumulate unit, significantly optimizing hardware resource utilization, reducing power consumption and cost, while improving development efficiency and design flexibility. Its generalized architecture can adapt to diverse polynomial calculation needs in ultrasonic signal delays. Only the command queue needs to be adjusted to accommodate different delay complexities and real-time requirements without modifying hardware modules, thereby greatly shortening the development cycle and enhancing system robustness. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort. Other features, objects, and advantages of the present invention will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0059] Figure 1 This is a schematic diagram illustrating the application scenario of the transthoracic ultrasound imaging system in an embodiment of the present invention;

[0060] Figure 2 This is a schematic diagram illustrating the working principle of the transthoracic ultrasound chip in an embodiment of the present invention;

[0061] Figure 3 This is a schematic diagram of the delay processing architecture for an ultrasonic chip in an embodiment of the present invention;

[0062] Figure 4 This is a schematic diagram of the delay calculation center module in an embodiment of the present invention;

[0063] Figure 5 This is a schematic diagram of the computational scheduling unit in an embodiment of the present invention;

[0064] Figure 6 This is a schematic diagram of the arithmetic calculation unit in an embodiment of the present invention;

[0065] Figure 7This is a schematic diagram of the channel delay calculation unit in an embodiment of the present invention;

[0066] Figure 8 This is a schematic diagram of the result output control unit in an embodiment of the present invention. Detailed Implementation

[0067] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0068] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0069] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0070] The technical solutions of the present invention and how they solve the above-mentioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0071] Figure 1 This is a schematic diagram illustrating the application scenario of the transthoracic ultrasound imaging system in an embodiment of the present invention, such as... Figure 1As shown, during transthoracic ultrasound, an ultrasound probe 100 is placed on the surface of the chest wall. Ultrasound waves "penetrate" the chest wall to observe the structure, movement, and blood flow of the heart in real time. The ultrasound probe 100 is connected to the main unit via a connecting cable 200. The ultrasound probe 100 emits high-frequency ultrasound waves (typically 2-7 MHz). These ultrasound waves penetrate the chest wall and lung edges in longitudinal wave form, eventually reaching the heart and surrounding structures. When ultrasound waves propagate through human tissue, they are reflected due to encountering different tissue interfaces. The probe not only emits ultrasound waves but also acts as a receiver. When the reflected ultrasound waves (echoes) reach the probe, they are sensed by its internal piezoelectric transducer. The mechanical vibration of the received echoes is converted into a weak electrical signal. This electrical signal is then transmitted to the ultrasound instrument, amplified, filtered, and digitally processed, ultimately transforming into a real-time dynamic image.

[0072] Figure 2 This is a schematic diagram illustrating the working principle of the transthoracic ultrasound chip in an embodiment of the present invention, as shown below. Figure 2 As shown, when ultrasound is transmitted via the transthoracic ultrasound chip provided by this invention, the transmitting beamformer delays and adjusts the phase of the electrical pulse to direct the beam towards the target area. The pulse generator generates a high-voltage pulse based on the delay and phase of the electrical pulse, which triggers the transducer to vibrate and transmit ultrasound. During ultrasound reception, the ultrasound waves are reflected by tissue and act on the transducer, generating a signal through the piezoelectric effect. The signal amplifier amplifies and reduces the noise of the weak electrical signal output by the transducer, improving the signal-to-noise ratio. The receiving beamformer performs phase compensation on the electrical signals received by each array element to superimpose and enhance the target echo. The target echo is transmitted to the ultrasound control console through the output channel, thereby realizing image reconstruction and real-time display.

[0073] When the delay of different transducers reaching the focal point is calculated based on the focal point of the ultrasonic transmission and reception, the delay of the ultrasonic signal is determined by calculating the polynomial corresponding to the delay, that is, by calculating and processing the delay of the ultrasonic signal.

[0074] After obtaining the polynomial corresponding to the ultrasonic signal delay, several general forms of the polynomial are as follows:

[0075] (1) General polynomial:

[0076] a×b / 2 x +c×d / 2 y +e×f / 2 z +...

[0077] (2) Polynomials involving the multiplication of two or more factors:

[0078] f = a × b / 2 x +c×d / 2 y +e×f×g / 2 z+...

[0079] (3) Nested polynomials:

[0080] a×b / 2 x +c×d / 2 y +e×((f) / 2 z +...

[0081] The nested sub-polynomials are:

[0082] f = g × h / 2 x +i×j / 2 y +k×l / 2 z +...

[0083] By carefully analyzing the composition of each term in the above polynomial and the overall operation process, it can be found that the calculation of polynomials essentially uses multiplication and addition as the basic operations. The calculation of the entire polynomial can be completed through several multiplication and addition operations.

[0084] Figure 3 This is a schematic diagram of the delay processing architecture for an ultrasonic chip in an embodiment of the present invention, as shown below. Figure 3 As shown, the delay processing architecture for ultrasound chips provided by the present invention includes:

[0085] An ultrasound core array includes a first ultrasound core region and a second ultrasound core region divided along a horizontal axis, each of the ultrasound core regions including multiple ultrasound module arrays; each ultrasound module including multiple ultrasound sub-arrays.

[0086] The dual-zone delay center includes a first delay zone and a second delay zone. The first delay zone is used for generating the delay signal of the first ultrasound core area, and the second delay zone is used for generating the delay signal of the second ultrasound core area.

[0087] Each of the delay partitions includes multiple delay calculation centers, each delay calculation center is connected to several ultrasound modules, and the ultrasound subarrays within the ultrasound modules are cascaded. The delay calculation center is used to generate delay signals for the corresponding ultrasound subarrays within the ultrasound modules.

[0088] In this embodiment of the invention, the first delay partition and the second delay partition perform the same delay calculation logic, with only the input parameters adapted according to the spatial position differences of the subarray.

[0089] Each delay partition contains multiple delay calculation centers with consistent structure. All delay calculation centers share the same set of calculation commands and cover the delay calculation of the ultrasound modules in all subarrays through differentiated input parameters. Moreover, multiple delay calculation centers work synchronously to meet timing requirements.

[0090] In this embodiment of the invention, the dual-partition delay center adopts a distributed deployment, adapted to the chip layout plan, and is divided into a top delay partition and a bottom delay partition, corresponding to the first and second ultrasound core areas of the ultrasound core array, respectively. The structures and calculation processes of the two delay partitions are completely identical, only adapting different input parameters due to the spatial differences of the subarrays they serve. Each delay partition contains 11 structurally identical delay calculation centers, all of which share a unified set of calculation commands and achieve division of labor coverage through differentiated input parameters. Each delay calculation center is responsible for the delay calculation of two adjacent subarray columns. The 11 delay calculation center units work synchronously, which can complete the delay calculation tasks of 22 ultrasound modules, meeting the system timing requirements.

[0091] In this embodiment of the invention, the ultrasonic subarray includes: ultrasonic transceiver array elements, digital units, beamforming units, and gain amplifiers;

[0092] Multiple ultrasonic transceiver array elements are used to drive the transducer array elements to emit ultrasonic waves and to receive the echo electrical signals generated by the transducer array elements after receiving ultrasonic waves.

[0093] The beamforming unit is used to perform beamforming based on multiple echo electrical signals from different array elements within the same subarray to enhance the echo electrical signals.

[0094] The gain amplifier is used to amplify the electrical signal after beamforming;

[0095] The digital unit is used to control the order in which the ultrasonic transceiver array element transmits ultrasonic waves and receives echo electrical signals according to the delay signal.

[0096] The delay signal includes a transmit delay signal and a receive delay signal;

[0097] The ultrasonic transceiver array element includes:

[0098] The pulse transmitting circuit is used to generate a pulse electrical signal based on the transmission delay signal to drive the transducer array elements to emit ultrasonic waves;

[0099] The echo receiving circuit is used to receive and amplify the echo electrical signal generated by the transducer array element after receiving the ultrasonic wave, based on the received delay signal.

[0100] A switching switch is used to switch the connection or disconnection of the transducer array element with the pulse transmitting circuit and the echo receiving circuit.

[0101] Figure 4 This is a schematic diagram of the delay calculation center module in an embodiment of the present invention, as shown below. Figure 4 As shown, the delay calculation center includes:

[0102] The computation scheduling unit serves as the global control center for delayed computation. On the one hand, it issues operation commands to the arithmetic computation unit to drive delayed computation; on the other hand, it receives write status information of external registers from the result output control unit to adjust the computation rhythm.

[0103] The arithmetic calculation unit is used to perform multiplication and accumulation operations based on the operation command, convert the operation command into basic intermediate data required for delay calculation, and provide it to the channel delay calculation unit;

[0104] The channel delay calculation unit is used to receive the basic intermediate data, complete the final calculation of the channel delay, generate a delay signal, and transmit it to the result output control unit.

[0105] The result output control unit is used to receive the delay signal, output the delay signal to the external register in an orderly manner, and at the same time feed back the write status information of the external register to the calculation scheduling unit.

[0106] Figure 5 This is a schematic diagram of the calculation scheduling unit in an embodiment of the present invention, as shown below. Figure 5 As shown, the computing scheduling unit includes:

[0107] A finite state machine is used to receive the start signal for delayed computation, output the start operation signal and the current stage completion signal, so as to control the state switching of the entire computation process;

[0108] The command storage unit is used to classify and store command queues for different delay calculation tasks, including the transmit delay command queue and the receive delay command queue.

[0109] The command counter is used to track the execution progress of the command queue and control the selection of the command queue at different computation stages.

[0110] The command queue selector is used to select the command queue corresponding to the current stage according to the control of the command counter, and output the operation command to the arithmetic calculation unit.

[0111] In this embodiment of the invention, the generation of the command queue includes:

[0112] Obtain the polynomials used to calculate the delays of ultrasonic transmission and reception;

[0113] The polynomial is split and sorted to obtain the order of calculation for each term;

[0114] Each item generates a command, forming a command queue.

[0115] When a term in a polynomial involves the multiplication of multiple factors, it needs to be broken down into multiple steps of multiplying two factors at a time. Each step can still be performed using a multiply-add unit, described sequentially by multiple commands. In the case of multiplying multiple factors, after multiplying two numbers, it is not necessary to immediately add the result to the previous accumulation; instead, it is necessary to wait until all factors of that term have been multiplied before performing the accumulation. This requires a temporary register to store the intermediate calculation results.

[0116] For example, if a term is the product of three numbers A × B × C, then two commands are generated: command A × B = D and command D × C, or command B × C = E and command E × A. Thus, in this invention, any polynomial operation can be completed using only a multiplication-accumulation unit with two multipliers as input.

[0117] Similarly, for polynomials containing subpolynomials, the calculation order needs to be adjusted. The subpolynomials should be calculated first, and their results should be used as the current sum for subsequent calculations.

[0118] Furthermore, to meet precision requirements, the bit width of the multiplication factors in a polynomial is usually large. To reduce the bit width of the final result, a division operation is often required after the multiplication operation. To reduce the complexity of hardware implementation, the divisor is usually converted into a power of 2 form, so that a shift operation can replace the division operation, thereby improving computational efficiency. Based on the above breakdown of the calculation steps, a basic multiplication-accumulation operation can be represented in a general form, for example: opcode1×opcode2 / 2^N.

[0119] Furthermore, specific computational steps can be represented as commands using parameterization. Each command describes a multiplication-accumulation operation, and a polynomial typically consists of multiple multiplication-accumulation operations. Therefore, the computation process of a polynomial can be represented by a command queue consisting of several commands. During polynomial computation, these commands are executed sequentially.

[0120] Figure 6 This is a schematic diagram of the arithmetic calculation unit in an embodiment of the present invention, such as... Figure 6 As shown, the arithmetic calculation unit includes:

[0121] The command parser is used to parse the operation commands from the scheduling unit and generate cumulative multiplication and addition calculation instructions;

[0122] The multiply-accumulate unit is used to perform multiply-accumulate operations on the command queue according to the multiply-accumulate calculation instructions to generate the subarray transmit delay signal, the X and Y direction subarray transmit delay signals, and the X and Y direction subarray receive intermediate values;

[0123] The trimmer is used to trim the transmission delay signal of the subarray and output it to the result output control unit.

[0124] In this embodiment of the invention, a complete command includes parameters such as opcode1, opcode2, RS, ACC, RP, and INCR, representing a specific multiplication-accumulation operation. The entire polynomial calculation process is completed by a command queue consisting of several commands. The length of the command queue depends on the complexity of the polynomial and the number of multiplication-accumulation operations it contains.

[0125] The parameters for each command typically include the following:

[0126] opcode1 and opcode2: represent the two numbers that need to be multiplied;

[0127] RS: The number of bits to shift right, corresponding to division by a power of 2. The exponent of the power is equal to the number of bits shifted right.

[0128] ACC: Used to indicate whether the current calculation result needs to be added to the previous accumulated result. ACC=1 indicates that it needs to be added, and ACC=0 indicates that it does not need to be added. This usually occurs in scenarios where all factors of a certain term need to be multiplied before being added.

[0129] RP: Indicates whether the current result of the operation should directly replace the accumulated sum, rather than being added to it. RP=1 indicates replacement, which is common in scenarios where the final result of a subpolynomial is calculated and used as the current accumulated sum.

[0130] Specifically, suppose there is a nested polynomial with a partial form like A×(ACC+B)+......, where the parentheses contain a sub-polynomial. At this point, the sub-polynomial has reached its final calculation step, requiring the accumulated value ACC to be added to the last product B. The result of this addition is used as a multiplier for a term in the parent polynomial and multiplied by A. The product obtained at this point is a partial sum obtained from the entire polynomial calculation up to this point, so the accumulated sum needs to be replaced by this partial sum and added to subsequent product terms.

[0131] In other words, when calculating a subpolynomial, the sum reflects the sum of the subpolynomials. However, after the subpolynomial is calculated, the sum reflects the sum of the parent polynomial. Therefore, in the storage unit, the sum of the subpolynomials is replaced by the sum of the parent polynomials. If the sum of the subpolynomials is not replaced, the parent polynomial also occupies a storage unit for the accumulated value, reducing the reuse of hardware resources.

[0132] For example, in the equation A × (ACC + B), A is a factor, and (ACC + B) is a sub-polynomial. When the sub-polynomial is calculated, the accumulated value ACC equals the result of the entire polynomial. At this point, the accumulated value ACC is used as a factor of one of the terms in the parent polynomial and multiplied and added to A. Afterward, the storage unit that originally stored the accumulated value ACC for calculating the sub-polynomial is used to store the accumulated value ACC for calculating the parent polynomial.

[0133] INCR: Indicates whether the index value of the lookup table needs to be pointed to the next item. INCR=1 means that the index value needs to be incremented.

[0134] The lookup table is a lookup table for the command queue. After a command is executed, the index value of the lookup table is incremented.

[0135] When a factor of a term comes from a lookup table, the calculation order of the term is determined according to the order of the factors in the lookup table. A lookup table is a form of factor organization. For example, there exists a lookup table L with 5 factors, L = (3, 2, 5, 1, 8), where the part in parentheses represents the five factors. The corresponding value needs to be found using an index; for example, L[0] is 3, L[1] is 2, and so on.

[0136] In this embodiment of the invention, factors do not necessarily have to appear in the form of a lookup table; this is only to illustrate that the method of this application supports factors appearing in the form of a lookup table. If no factor appears in the form of a lookup table, then INCR = 0.

[0137] In this embodiment of the invention, a command queue-based design method is used to implement polynomial computation, which significantly reduces the complexity of hardware implementation and improves hardware versatility. In traditional designs, each polynomial may require a dedicated hardware computation module, while the command queue-based design method only requires a single general-purpose multiply-accumulate computation unit. When the polynomial is adjusted or changed, no hardware modification is needed; only the corresponding command queue needs to be regenerated and input into the hardware for execution. This hardware-software separation design method not only reduces the workload of hardware design but also significantly improves design flexibility and scalability.

[0138] Figure 7 This is a schematic diagram of the channel delay calculation unit in an embodiment of the present invention, as shown below. Figure 7 As shown, the channel delay calculation unit includes:

[0139] Multiple sets of parallel computing units, each of which includes multiple basic computing components, are used to calculate the output channel transmission delay signal based on the X and Y direction subarray transmission delay signals, and to calculate the output subarray reception delay signal and the channel reception delay signal based on the X and Y direction subarray reception intermediate values;

[0140] Multiple basic arithmetic components, including adders, absolute value calculators, rounders, integer calculators, minimum value calculators, maximum value calculators, left shifters, and right shifters.

[0141] In this embodiment of the invention, the receiving delay signal is written only after all the transmit delay signals have been written to the register, or the transmit delay signal is written only after all the receiving delay signals have been written to the register. The order in which the transmit delay signals are written to the register is as follows: first, the transmit delay signals of the subarray are written, and then the transmit delay signals of the channel are written. The order in which the receiving delay signals are written to the register is as follows: first, the fine receiving delay signal is written, and then the coarse receiving delay signal is written. The transmit delay signals of the subarray and the transmit delay signals of the channel are concatenated, and the coarse receiving delay signal is concatenated with the fine receiving delay signal.

[0142] In this embodiment of the invention, since the calculation speed of the delay signal is faster than the writing speed of the external register, the newly calculated delay signal may cover the delay signal that has not yet been fully written to the external register.

[0143] Therefore, the computation scheduling unit needs to pause the currently ongoing computation based on the external register write status fed back by the result output control unit. When the risk of data overwriting is imminent, the computation process will pause at the step before calculating the next delayed signal, and will only resume computation after the potentially overwritten delayed signal has been completely written to the external register, thereby minimizing idle time.

[0144] Figure 8 This is a schematic diagram of the result output control unit in an embodiment of the present invention, as shown below. Figure 8 As shown, the result output control unit includes:

[0145] A receive delay register is used to temporarily store the channel receive delay signal and the subarray receive delay signal;

[0146] The transmit delay register is used to temporarily store the transmit delay signal of the channel and the transmit delay signal of the subarray;

[0147] A scheduler is used to control the sequential writing of the transmit delay signal and the receive delay signal into an external register;

[0148] The output shifter is used to output the received delay signal and the transmitted delay signal, and at the same time to feed back the write status information of the external register to the computing and scheduling unit.

[0149] In this embodiment of the invention, the output shifter is provided with a first write port and a second write port, each corresponding to an ultrasound module, to realize pipelined operation of delay calculation and writing. While performing the current type of delay calculation, the writing of the previous round of calculation results is completed. To address the risk of data overwriting caused by the calculation speed exceeding the external register writing speed, the calculation scheduling unit establishes a dynamic pause mechanism by receiving feedback on the external register write status from the result output control unit. When it is detected that a new calculation result may overwrite incompletely written old data, the calculation process is paused before the next calculation starts, and resumed only after the risky data is completely written to the register, minimizing idle calculation time.

[0150] In this embodiment of the invention, a distributed parallel architecture is constructed by setting up multiple delay calculation centers that work synchronously in a dual-partition delay center. Each delay calculation center processes the delay calculation of two adjacent ultrasound sub-arrays in parallel. At the same time, dual independent write interfaces are designed to realize a pipeline mechanism for parallel calculation and writing. Based on the feedback of the external register write status, the calculation is temporarily paused when there is a risk of data overwrite, avoiding idle waste and ensuring that the delay parameters are updated in real time, perfectly supporting the dynamic real-time imaging of the heart by transthoracic ultrasound.

[0151] This invention employs a general multiply-accumulate architecture based on a command queue, decomposing all polynomials into "A×B / C" operations. Division operations are replaced by shift operations. Each delay calculation center requires only one multiply-accumulate unit, significantly optimizing hardware resource utilization, reducing power consumption and cost, and improving development efficiency and design flexibility. Its generalized architecture can adapt to diverse polynomial calculation needs in ultrasonic signal delays. Only the command queue needs to be adjusted to accommodate different delay complexities and real-time requirements without modifying hardware modules, thereby greatly shortening the development cycle and enhancing system robustness.

[0152] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0153] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A delay processing architecture for an ultrasonic chip, characterized in that, include: An ultrasound core array includes a first ultrasound core region and a second ultrasound core region divided along a horizontal axis, each of the ultrasound core regions including multiple ultrasound module arrays; each ultrasound module including multiple ultrasound sub-arrays. The dual-zone delay center includes a first delay zone and a second delay zone. The first delay zone is used for generating the delay signal of the first ultrasound core area, and the second delay zone is used for generating the delay signal of the second ultrasound core area. Each of the delay partitions includes multiple delay calculation centers, each delay calculation center is connected to several ultrasound modules, and the ultrasound subarrays within the ultrasound modules are cascaded. The delay calculation center is used to generate delay signals for the corresponding ultrasound subarrays within the ultrasound modules.

2. The delay processing architecture for an ultrasonic chip according to claim 1, characterized in that, The ultrasonic subarray includes: ultrasonic transceiver array elements, digital units, beamforming units, and gain amplifiers. Multiple ultrasonic transceiver array elements are used to drive the transducer array elements to emit ultrasonic waves and to receive the echo electrical signals generated by the transducer array elements after receiving ultrasonic waves. The beamforming unit is used to perform beamforming based on multiple echo electrical signals from different array elements within the same subarray to enhance the echo electrical signals. The gain amplifier is used to amplify the electrical signal after beamforming; The digital unit is used to control the order in which the ultrasonic transceiver array element transmits ultrasonic waves and receives echo electrical signals according to the delay signal.

3. The delay processing architecture for an ultrasonic chip according to claim 2, characterized in that, The delay signal includes a transmit delay signal and a receive delay signal; The ultrasonic transceiver array element includes: The pulse transmitting circuit is used to generate a pulse electrical signal based on the transmission delay signal to drive the transducer array elements to emit ultrasonic waves; The echo receiving circuit is used to sequentially receive and amplify the echo electrical signal generated by the transducer array element after receiving ultrasonic waves, based on the received delay signal. A switching switch is used to switch the connection or disconnection of the transducer array element with the pulse transmitting circuit and the echo receiving circuit.

4. The delay processing architecture for an ultrasonic chip according to claim 1, characterized in that, The delay calculation center includes: The computation scheduling unit serves as the global control center for delayed computation. On the one hand, it issues operation commands to the arithmetic computation unit to drive delayed computation; on the other hand, it receives write status information of external registers from the result output control unit to adjust the computation rhythm. The arithmetic calculation unit is used to perform multiplication and accumulation operations based on the operation command, convert the operation command into basic intermediate data required for delay calculation, and provide it to the channel delay calculation unit; The channel delay calculation unit is used to receive the basic intermediate data, complete the final calculation of the channel delay, generate a delay signal, and transmit it to the result output control unit. The result output control unit is used to receive the delay signal, output the delay signal to the external register in an orderly manner, and at the same time feed back the write status information of the external register to the calculation scheduling unit.

5. The delay processing architecture for an ultrasonic chip according to claim 4, characterized in that, The computation scheduling unit includes: A finite state machine is used to receive the start signal for delayed computation, output the start operation signal and the current stage completion signal, so as to control the state switching of the entire computation process; The command storage unit is used to classify and store command queues for different delay calculation tasks, including the transmit delay command queue and the receive delay command queue. The command counter is used to track the execution progress of the command queue and control the selection of the command queue at different computation stages. The command queue selector is used to select the command queue corresponding to the current stage according to the control of the command counter, and output the operation command to the arithmetic calculation unit.

6. The delay processing architecture for an ultrasonic chip according to claim 4, characterized in that, The arithmetic calculation unit includes: The command parser is used to parse the operation commands from the scheduling unit and generate cumulative multiplication and addition calculation instructions; The multiply-accumulate unit is used to perform multiply-accumulate operations on the command queue according to the multiply-accumulate calculation instructions to generate the subarray transmit delay signal, the X and Y direction subarray transmit delay signals, and the X and Y direction subarray receive intermediate values; The trimmer is used to trim the transmission delay signal of the subarray and output it to the result output control unit.

7. The delay processing architecture for an ultrasonic chip according to claim 6, characterized in that, The channel delay calculation unit includes: Multiple sets of parallel computing units, each of which includes multiple basic computing components, are used to calculate the output channel transmission delay signal based on the X and Y direction subarray transmission delay signals, and to calculate the output subarray reception delay signal and the channel reception delay signal based on the X and Y direction subarray reception intermediate values; Multiple basic arithmetic components, including adders, absolute value calculators, rounders, integer calculators, minimum value calculators, maximum value calculators, left shifters, and right shifters.

8. The delay processing architecture for an ultrasonic chip according to claim 7, characterized in that, The result output control unit includes: A receive delay register is used to temporarily store the channel receive delay signal and the subarray receive delay signal; The transmit delay register is used to temporarily store the transmit delay signal of the channel and the transmit delay signal of the subarray; A scheduler is used to control the sequential writing of the transmit delay signal and the receive delay signal into an external register; The output shifter is used to output the received delay signal and the transmitted delay signal, and at the same time to feed back the write status information of the external register to the computing and scheduling unit.

9. The delay processing architecture for an ultrasonic chip according to claim 5, characterized in that, The generation of the command queue includes: Obtain the polynomials used to calculate the delays of ultrasonic transmission and reception; The polynomial is split and sorted to obtain the order of calculation for each term; Each item generates a command, forming the command queue.

10. The delay processing architecture for an ultrasonic chip according to claim 9, characterized in that, The process of splitting and sorting the polynomial includes: When multiplying multiple factors, it is necessary to break it down into multiple steps of multiplying two factors at a time and store the product in a temporary register. The product is then accumulated after all factors have been multiplied. For a polynomial containing subpolynomials, the subpolynomials are calculated first.

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