Memory device, manufacturing method thereof, and memory cell

Abstract

A memory device includes a plurality of memory cells, word lines, a plurality of bit lines, and a plurality of source lines. Each memory cell includes a one-time programmable (OTP) element and a plurality of select transistors. The word line is connected to a gate terminal of the select transistor of the memory cell. The bit line is connected in parallel between the first node and a first OTP element terminal of the OTP element of the memory cell. The source lines are connected in parallel and connect a second source / drain terminal of the select transistor of the memory cell to the second node. The embodiment of the invention also discloses a method for manufacturing the memory device and a memory unit.

Description

Technical Field

[0001] Embodiments of this application relate to memory devices and methods of manufacturing the same, as well as memory cells. Background Technology

[0002] Memory devices are responsible for storing and retrieving data. They come in various forms and can be programmable or non-programmable. Programmable memory devices, such as RAM (Random Access Memory) devices, allow data to be written to and rewritten multiple times, making them suitable for applications requiring frequent updates. On the other hand, non-programmable memory devices, such as OTP (One-Time Programmable) memory devices, can only be written to once. Such devices can be used in a variety of applications where data needs to be kept secure and cannot be altered. Regardless of their programmability, memory devices facilitate the reading of the data stored within them, enabling electronic systems to access and use information as needed. Summary of the Invention

[0003] One aspect of this application provides a memory device, including: a plurality of memory cells, each including a one-time programmable element and a plurality of select transistors; word lines connected to the gate terminals of the select transistors of the memory cells; a plurality of bit lines connected in parallel between a first node and a first one-time programmable element terminal of the one-time programmable element of the memory cell; and a plurality of source lines connected in parallel and connecting a second source / drain terminal of the select transistor of the memory cell to a second node.

[0004] Another aspect of this application provides a memory cell including: a one-time programmable element and a plurality of selection transistors, wherein the one-time programmable element has a first one-time programmable element terminal connected to one or more bit lines, and each of the selection transistors has a gate terminal connected to a word line, a first source / drain terminal connected to a second one-time programmable element terminal connected to the one-time programmable element, and a second source / drain terminal connected to one or more source lines, wherein the bit lines or source lines are connected in parallel.

[0005] Another aspect of this application provides a method for manufacturing a memory device, the method comprising:

[0006] Fabricating memory cells above a substrate, the memory cells including one-time programmable elements and one or more selection transistors; and

[0007] A conductive material is deposited to form a plurality of metal layers stacked one on top of another, wherein the plurality of metal layers include: a first metal layer including at least one source line connecting the select transistor to a first node; a second metal layer including a word line connected to the gate terminal of the select transistor; and a third metal layer including a plurality of bit lines connected in parallel between a second node and the one-time programmable element. Attached Figure Description

[0008] Various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings.

[0009] Figure 1 These are schematic circuit diagrams illustrating exemplary memory devices according to various embodiments of the present invention;

[0010] Figure 2A This is a schematic circuit diagram illustrating exemplary memory cells according to various embodiments of the present invention;

[0011] Figure 2B This is a schematic timing diagram illustrating exemplary relationships between word line signals, bit line signals, and source line signals according to various embodiments of the present invention;

[0012] Figure 3 This is a schematic circuit diagram illustrating another exemplary memory cell according to various embodiments of the present invention;

[0013] Figure 4 This is a schematic layout diagram illustrating exemplary wires of a memory cell according to various embodiments of the present invention;

[0014] Figure 5 This is a schematic layout diagram illustrating another exemplary conductor according to various embodiments of the present invention;

[0015] Figure 6A This is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present invention;

[0016] Figure 6B This is a schematic timing diagram illustrating exemplary relationships between word line signals, bit line signals, and source line signals according to various embodiments of the present invention;

[0017] Figure 7 This is a schematic layout diagram illustrating another exemplary conductor according to various embodiments of the present invention;

[0018] Figure 8 This is a schematic layout diagram illustrating another exemplary conductor according to various embodiments of the present invention;

[0019] Figure 9 This is a schematic layout diagram illustrating another exemplary conductor according to various embodiments of the present invention;

[0020] Figure 10 This is a schematic layout diagram illustrating another exemplary conductor according to various embodiments of the present invention;

[0021] Figure 11 This is a schematic layout diagram illustrating another exemplary conductor according to various embodiments of the present invention;

[0022] Figure 12 This is a schematic layout diagram illustrating another exemplary wire of a memory cell according to various embodiments of the present invention;

[0023] Figure 13 This is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present invention;

[0024] Figure 14 This is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present invention;

[0025] Figure 15 This is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present invention;

[0026] Figure 16 This is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present invention;

[0027] Figure 17 This is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present invention;

[0028] Figure 18 This is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present invention;

[0029] Figure 19 This is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present invention;

[0030] Figure 20 This is a flowchart illustrating exemplary methods for manufacturing memory devices according to various embodiments of the present invention; and

[0031] Figure 21 This is a schematic cross-sectional view illustrating another exemplary memory device according to various embodiments of the present invention. Detailed Implementation

[0032] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0033] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “top,” “bottom,” etc., may be used herein to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0034] A memory device includes multiple memory cells, such as an array arranged in rows and columns, facilitating data storage and retrieval. The memory device can be programmable or non-programmable. Programmable memory devices, such as RAM (Random Access Memory) devices, allow data to be written and rewritten multiple times, making them suitable for applications requiring frequent updates, such as those in RAM devices. Non-programmable memory devices, such as OTP (One-Time Programmable) memory devices, can only be written to once, ensuring data permanence and security, and preventing modification. They are useful in a variety of applications where data needs to be kept secure and cannot be altered.

[0035] However, OTP memory devices can sometimes fail to program. For example, during a programming operation, a programming voltage is applied to the memory cell of the OTP memory device via a bit line. The bit line may have a higher wiring resistance than expected (e.g., via a manufacturing defect), which limits the current required to program the memory cell, causing programming failure.

[0036] In some of the examples described herein, the systems and methods include memory devices comprising memory cells connected to two or more bit lines. To reduce overall wiring resistance, the bit lines are connected in parallel. This parallel arrangement increases the likelihood of successfully programming the memory cells.

[0037] Figure 1 This is a schematic circuit diagram illustrating an exemplary memory device according to various embodiments of the present invention. An exemplary memory device 100, such as an OTP memory device, includes a plurality of memory cells 110, a plurality of word lines (WL0-WLn), and a plurality of bit lines (BL0-BLn). An OTP memory device is a memory device that permanently stores bits of data that cannot be changed once written. For example, each memory cell 110 includes an OTP element. In this exemplary embodiment, the OTP element includes an initially non-conductive antifuse (e.g., Figure 2A The antifuse 210 represents logic "0" (or "1"). When programmed, for example by applying a high voltage or current, the antifuse becomes conductive, representing a programming bit, such as logic "1" (or "0").

[0038] Memory cells 110 can be arranged in an array of rows and columns. Memory cells 110 in each row are connected to their respective word lines (WL0-WLn). Similarly, memory cells 110 in each column are connected to their respective bit lines (BL0-BLn). For example, each bit line (BL0-BLn) is connected to a voltage node (e.g., Figure 3 The memory device 100 is located between the VDD node and the memory cell 110 in the corresponding column. In this exemplary embodiment, the memory device 100 also includes a plurality of source lines (SL0-SLn), each connecting the memory cell 110 in the column to a ground (or VSS) node.

[0039] Memory cell 110 stores bits, logic "0" or "1", and undergoes a permanent and irreversible change upon writing or programming. This change occurs, for example, when a high voltage (i.e., a programming voltage) is applied to the corresponding bit line (BL0-BLn), ensuring that memory cell 110 cannot be reprogrammed (i.e., the bits stored therein cannot be overwritten). Word lines (WL0-WLn) enable access to the corresponding memory cell 110 by asserting them during read / write operations.

[0040] In some embodiments, the memory cells 110 in each column are connected between two or more bit lines (BL[0]) in parallel and two or more source lines (SL[0]) in parallel. This parallel configuration can reduce the total wiring resistance of the bit lines (BL[0]) and the total wiring resistance of the source lines (SL[0]), thereby minimizing the wiring resistance that impedes current flow. The lower resistance in the wiring helps ensure that sufficient programming voltage or current can be reliably delivered to the memory cells 110, thereby increasing the likelihood of successfully programming the antifuse to its conductive state.

[0041] To read memory cell 110, for example, by applying a high word line (WL) signal, the word line corresponding to the desired row, such as word line (WL[0]), is asserted. Then, bit lines, such as bit line BL[0], are used to detect the state of memory cell 110. If the antifuse is programmed, it will exhibit distinct electrical characteristics, such as decreased resistance or increased current, indicating that a conductive path has been established. This characteristic corresponds to the programming logic state, representing logic "1" (or "0"). The increase in current or decrease in resistance is due to the formation of a permanent and non-reprogrammable conductive path on the antifuse. Conversely, if the antifuse remains unprogrammed (i.e., unchanged), it maintains its high resistance state, and memory cell 110 presents a different electrical signal corresponding to logic "0" (or "1"). The absence of a conductive path results in higher resistance or lower current. Programming data, reflecting the state of memory cell 110, is read by sensing the voltage or current level on the bit line (BL[0]). By further processing these voltage or current levels, such as amplification, the bits stored in memory cell 110 can be accurately retrieved to determine whether memory cell 110 holds logic "1" or "0".

[0042] In an alternative embodiment, the OTP element includes a fuse. Unlike an antifuse, which creates a conductive path during programming, the fuse is initially conductive and becomes non-conductive when "blown" or programmed.

[0043] Figure 2A This is a schematic circuit diagram illustrating an exemplary memory cell 200 according to various embodiments of the present invention. Figure 2A As shown, the exemplary memory cell 200, such as memory cell 110, takes the form of a four-transistor-one-resistor (4T1R) memory cell and includes an OTP element 210 and four select transistors 220 (for simplicity, Figure 2A (Only one selection transistor is marked in the image). OTP element 210 has a first OTP element terminal connected to two or more bit lines (BLs). For example, each bit line (BL) is connected to a voltage node, such as... Figure 3 The VDD node. The memory cell 200 also includes an interconnect 230 that connects the bit lines (BL) in parallel. The first OTP element terminal of the OTP element 210 is connected to the interconnect 230.

[0044] In this exemplary embodiment, the OTP element 210 includes an antifuse in the form of a magnetic tunnel junction (MTJ), a dielectric breakdown antifuse, a phase change material-based antifuse, a resistive switching element, any other type of antifuse technology that transitions from a high-resistance state to a low-resistance state during programming or writing, or a combination thereof.

[0045] In this exemplary embodiment, the select transistor 220 is a field-effect transistor (FET) and has a gate terminal, a first source / drain terminal, and a second source / drain terminal. The gate terminals are connected to each other and to a word line (WL). The first source / drain terminals of the select transistor 220 are connected to each other and to a second OTP element terminal of the OTP element 210. For example, the memory cell 200 also includes an interconnect 240 connecting the first source / drain terminals to each other. The second OTP element terminal of the OTP element 210 is connected to the interconnect 240. The second source / drain terminals of the select transistor 220 are connected to each other and to two or more source lines (SL). For example, each source line (SL) is connected to a ground (or VSS) node. The memory cell 200 also includes an interconnect 250 connecting the source lines (SL) in parallel. The second source / drain terminals of the select transistor 220 are connected to each other and to the interconnect 250.

[0046] In some embodiments, each select transistor 220 is an n-type metal-oxide-semiconductor FET. In other embodiments, at least one of the select transistors 220 is a p-type metal-oxide-semiconductor FET. In alternative embodiments, the memory cell 200 includes planar transistors, gate-all-around (GAA) transistors, back-end metal-oxide-semiconductor transistors, any suitable transistors, or combinations thereof.

[0047] As described above, memory cell 200 uses a combination of OTP element 210 and select transistor 220 to permanently store bits within it by changing the state of OTP element 210. For example, before programming, OTP element 210 is untouched, i.e., no conductive path passes through it, resulting in high resistance. In this state, OTP element 210 behaves like an open circuit, preventing significant current flow. The absence of a conductive path indicates that logic "0" (or "1") is stored in memory cell 200. During write or programming operations, select transistor 220 is activated by a high (or low) word line (WL) signal ('1') at the word line (WL), thereby enabling access to memory cell 200. For example, Figure 2BThis is a schematic timing diagram illustrating exemplary relationships between word line (WL) signals, bit line (BL) signals, and source line (SL) signals according to various embodiments of the present invention. Memory cell 200 is then connected between the bit line (BL) and the source line (SL). A programming voltage, i.e., a higher voltage, is then applied to the bit line (BL), memory cell 200, and source line (SL), allowing current to flow. This current can permanently alter the structure of the OTP element 210, for example, creating conductive paths and reducing its resistance to a low (or programmed) state. This programmed state represents a logic "1" (or "0") stored in memory cell 200. Because the bit lines (BL) are connected in parallel, the total wiring resistance of the bit lines (BL) is reduced. Additionally, because the source lines (SL) are connected in parallel, the total wiring resistance of the source lines is also reduced. This reduction in wiring resistance improves the efficiency of current flow, thereby increasing the likelihood of successfully programming memory cell 200.

[0048] During a read operation, a high (or low) word line (WL) signal at the word line (WL) activates the select transistor 220, and the memory cell 200 is connected between the bit line (BL) and the source line (SL). Instead of a higher programming voltage for programming, a much lower read voltage is applied across the bit line (BL), memory cell 200, and source line (SL). If the OTP element 210 is being programmed (i.e., it is in a low-resistance state), current flows through it, and the sense amplifier connected to the memory cell 200 interprets the bit stored in the memory cell 200 as a logic "1" (or "0"). Otherwise, i.e., the OTP element 210 is non-conductive, there is essentially no current or no current flowing through it. In this state, the sense amplifier interprets the bit stored in the memory cell 200 as a logic "0" (or "1").

[0049] In an alternative embodiment, the source line (SL) is connected to the VDD node, and the bit line (BL) is connected to the ground (or VSS) node. In some embodiments, the memory cell 200 is connected between a single source line (SL) and a plurality of bit lines (BL) connected in parallel. In other embodiments, the memory cell 200 is connected between a single bit line (BL) and a plurality of source lines (SL) connected in parallel.

[0050] In some embodiments, the memory cell 200 further includes one or more floating OTP elements 260-280. Each OTP element 260-280 has a first OTP element terminal connected to a bit line (BL) and a second floating OTP element terminal (i.e., the second OTP element terminal is not electrically connected to the memory cell 200).

[0051] Although the memory cell 200 is exemplified as a 4T1 R memory cell, it should be understood that, upon reading this disclosure, the memory cell 200 may include any number of OTP elements and selection transistors, such as 1T1 R, 2T2R, 1T1 C (one transistor, one capacitor), 1T1 MTJ (one transistor, one magnetic tunnel junction), etc.

[0052] In an alternative embodiment, the OTP element 210 includes a fuse. Unlike an antifuse, which creates a conductive path during programming, the fuse is initially conductive and becomes non-conductive when "blown" or programmed.

[0053] Figure 3 This is a schematic circuit diagram illustrating another exemplary memory cell 300 according to various embodiments of the present invention. Figure 3 As shown, an exemplary memory cell 300, such as memory cell 200, includes an OTP element 310 and a select transistor 320. The OTP element 310 has a first OTP element terminal connected to two or more bit lines (BLs). For example, each bit line (BL) is connected to a voltage (VDD) node. The memory cell 300 also includes interconnects 330 that connect the bit lines (BLs) in parallel. The first OTP element terminal of the OTP element 310 is connected to the interconnect 330. The select transistor 320 has a gate terminal, a first source / drain terminal, and a second source / drain terminal. The gate terminal is connected to a word line (WL). The first source / drain terminal of the select transistor 320 is connected to a second OTP element terminal of the OTP element 310. The second source / drain terminal of the select transistor 320 is connected to two or more source lines (SLs). For example, each source line (SL) is connected to a ground (or VSS) node. The memory cell 300 also includes interconnects 350 that connect the source lines (SLs) in parallel. The second source / drain terminal of the selection transistor 320 is connected to the interconnect 350. In this exemplary embodiment, the OTP element 310 is an antifuse.

[0054] Based on the above description, further reference Figure 2BDuring a write or program operation, the select transistor 320 is activated by a high (or low) word line (WL) signal at the word line (WL), thereby enabling access to the memory cell 300. At this time, the memory cell 300 is connected between the bit line (BL) and the source line (SL). A programming voltage is then applied to the bit line (BL), the memory cell 300, and the source line (SL), allowing current to flow. This current can permanently alter the structure of the OTP element 310, for example, creating a conductive path and reducing its resistance to a low (or programmed) state. This programmed state represents a logic "1" (or "0") stored in the memory cell 300. Because the bit lines (BL) are connected in parallel, the total wiring resistance of the bit lines (BL), such as the equivalent wiring resistances 360 and 370, is reduced. Similarly, because the source lines (SL) are connected in parallel, the total wiring resistance of the source lines (SL), such as the equivalent wiring resistances 380 and 390, is also reduced. This reduction in wiring resistance can improve the efficiency of current flow, thereby increasing the likelihood of successfully programming memory cell 300.

[0055] Figure 4 This is a schematic layout diagram illustrating exemplary wiring of a memory cell (e.g., memory cell 200) according to various embodiments of the present invention. Figure 4 As shown, the exemplary layout 400 includes two or more bit lines (BLs), word lines (WLs), interconnects (ILs), and two or more vias (VIAs). The bit lines (BLs) are spaced apart along a first direction (x) and each extends along a second direction (y) transverse to the first direction (x). In some embodiments, the bit lines (BLs) are formed in the same metal layer, for example, in a metal layer (M6).

[0056] The word lines (WL) and interconnects (IL) each extend along a first direction (x) and are spaced apart along a second direction (y). In some embodiments, the word lines (WL) and interconnects (IL) are formed in the same metal layer, for example, in metal layers (M1 and / or M7).

[0057] Each of the vias (VIA) extends along a third direction (z) transverse to the first and second directions (x, y), and connects a corresponding bit line (BL) to an interconnect (IL). Since the bit lines (BL) are connected to the same interconnect (IL), they are connected in parallel. This parallel connection reduces the total wiring resistance of the bit lines (BL), thereby increasing the likelihood of successfully programming the memory cell 200.

[0058] In some embodiments, layout 400 also includes two or more source lines connected in parallel (e.g., Figure 2AThe source line (SL) is constructed similarly to the one described above for the bit line (BL). Accordingly, for the sake of brevity, a detailed description of the source line (SL) is omitted here.

[0059] In this exemplary embodiment, bit lines (BL), source lines (SL), word lines (WL), interconnects (IL), and vias (VIA) are formed by depositing conductive materials, such as copper (Cu), aluminum (AL), other suitable metals or alloys thereof, over memory cells 200 to establish electrical connections.

[0060] In some embodiments, the bit lines (BL) (and / or source lines SL) have a width (w) substantially the same as the word lines (WL). In such embodiments, the interconnects (IL) may have a width (W) substantially the same as the word lines (WL). In other embodiments, the bit lines (BL) (and / or source lines SL) may have a width different from the word lines (WL). For example, Figure 5 This is a schematic layout diagram illustrating another exemplary wiring of a memory cell (e.g., memory cell 200) according to various embodiments of the present invention. Figure 5 As shown, the bit line (BL) (and / or source line SL) has a width (w1) that is larger than the width (w2) of the word line (WL). This configuration can further reduce the total wiring resistance of the bit line (BL) and / or the total wiring resistance of the source line (SL).

[0061] Figure 6A This is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present invention. Figure 6A As shown, an exemplary memory device 600, such as memory device 100, includes a plurality of memory cells, such as memory cells 610-640, arranged in an array of rows and columns. Memory cells 610-640 in each row are connected to corresponding word lines (WL[0], WL[1]). Similarly, memory cells 610-640 in each column are connected between corresponding bit lines (BL[0], BL[1]) and corresponding source lines (SL[0], SL[1]). Since memory cells 610-640 are similar in construction and operation, only memory cell 610 will be described. Memory cell 610, such as memory cell 200, takes the form of a 4T1R memory cell and includes an OTP element 650 and four select transistors 660. For simplicity, in Figure 6AOnly one select transistor 660 is marked in the diagram. The OTP element 650 has a first OTP element terminal connected to two or more bit lines (BL[0]). For example, each bit line (BL[0]) is connected to a VDD node. The memory cell 610 also includes interconnects 670 that connect the bit lines (BL[0]) in parallel. The first OTP element terminal of the OTP element 650 is connected to interconnect 670.

[0062] Select transistor 660 has a gate terminal, a first source / drain terminal, and a second source / drain terminal. The gate terminals are connected to each other and to word lines (WL[0]). The first source / drain terminals of select transistor 660 are connected to each other and to a second OTP element terminal of OTP element 650. For example, memory cell 610 also includes an interconnect 680 connecting the first source / drain terminals of select transistor 660 to each other. The second OTP element terminal of OTP element 650 is connected to interconnect 680. The second source / drain terminals of select transistor 660 are connected to each other and to two or more source lines (SL[0]). For example, each source line (SL[0]) is connected to a ground (or VSS) node. Memory cell 610 also includes an interconnect 690 connecting the source lines (SL) in parallel. The second source / drain terminals of select transistor 660 are connected to each other and to interconnect 690.

[0063] As described above, the total wiring resistance of the bit lines (BL[0]) is reduced because they are connected in parallel. Furthermore, the total wiring resistance of the source lines (SL[0]) is also reduced because they are connected in parallel. This reduction in wiring resistance improves the efficiency of current flow, thereby increasing the likelihood of successfully programming the memory cell 610.

[0064] During a write or program operation, the select transistor 650 is activated by the high word line (WL[0]) signal ('1') at the word line (WL[0]), thereby enabling access to the memory cell 610. For example, Figure 6BThis is a schematic timing diagram illustrating exemplary relationships between word line (WL) signals, bit line (BL) signals, and source line (SL) signals according to various embodiments of the present invention. Memory cell 610 is then connected between the bit line (BL[0]) and the source line (SL[0]). A programming voltage (Vprog), i.e., a higher voltage, is then applied to the bit line (BL[0]), memory cell 610, and source line (SL[0]), allowing current to flow. This current can permanently alter the structure of the OTP element 650, for example, creating conductive paths and reducing its resistance to a low (or programmed) state. This programmed state represents a logic "1" (or "0") stored in memory cell 610. Because the bit lines (BL[0]) are connected in parallel, the total wiring resistance of the bit lines (BL[0]) is reduced. Additionally, because the source lines (SL[0]) are connected in parallel, the total wiring resistance of the source lines (SL[0]) is also reduced. This reduction in wiring resistance can improve the efficiency of current flow, thereby increasing the likelihood of successfully programming the memory cell 610.

[0065] During a read operation, the high word line (WL[0]) signal at the word line (WL[0]) activates the select transistor 660, and the memory cell 610 is connected between the bit line (BL[0]) and the source line (SL[0]). Instead of a higher programming voltage for programming, a much lower read voltage is applied across the bit line (BL[0]), the memory cell 610, and the source line (SL[0]). If the OTP element 650 is programmed (i.e., it is in a low-resistance state), current flows through it, and the sense amplifier connected to the memory cell 610 interprets the bit stored in the memory cell 610 as a logic "1" (or "0"). Otherwise, i.e., the OTP element 650 is non-conductive, there is essentially no current or no current flowing through it. In this state, the sense amplifier interprets the bit stored in the memory cell 610 as a logic "0" (or "1").

[0066] Read and write operations on other memory cells are similar to those described above in conjunction with memory cell 610. For example, the next write operation on another memory cell 620-640 asserts the word line (WL[1]) with a high word line (WL[1]) signal, while a programming voltage (Vprog) is applied to the bit line (BL[1]), memory cells 620-640, and source line (SL[1]).

[0067] Figure 7 This is a schematic layout diagram illustrating another exemplary wiring of a memory device (e.g., memory device 600) according to various embodiments of the present invention. Figure 7As shown, the exemplary layout 700 includes two or more bit lines (BL[0]), two or more bit lines (BL[1]), multiple word lines (e.g., WL[0] and WL[1]), multiple interconnects (e.g., IL[0] and IL[1]), two or more vias (VIA[0]), and two or more vias (VIA[1]). The bit lines (BL[0], BL[1]) are arranged alternately along a first direction (x) and each extends along a second direction (y) transverse to the first direction (x).

[0068] The word lines (WL[0], WL[1]) and interconnects (IL[0], IL[1]) each extend along a first direction (x) and are arranged alternately along a second direction (y). In some embodiments, the word lines (WL[0], WL[1]) and interconnects (IL[0], IL[1]) are formed in the same metal layer, for example, in metal layers (M1 and / or M7).

[0069] Each of the vias (VIA[0]) extends along a third direction (z) transverse to the first and second directions (x, y) and connects a corresponding bit line (BL[0]) to an interconnect (IL[0]). Similarly, each of the vias (VIA[1]) extends along a third direction (z) and connects a corresponding bit line (BL[1]) to an interconnect (IL[1]). Since the bit lines (BL[0], BL[1]) are connected to the same interconnect (IL[0], IL[1]), the bit lines (BL[0], BL[1]) are connected in parallel. This parallel connection can reduce the total wiring resistance of the bit lines (BL[0], BL[1]), thereby increasing the probability of successfully programming the memory cell 200.

[0070] Furthermore, since the bit lines (BL[0],BL[1]) are arranged alternately along the first direction (x), and since the word lines (WL[0],WL[1]) and interconnects (IL[0],IL[1]) are arranged alternately along the second direction (y), this configuration can increase the distance between vias (VIA[0],VIA[1]), thereby preventing violations of via spacing requirements.

[0071] In some embodiments, layout 700 also includes two or more source lines connected in parallel (e.g., Figure 6A SL[0]), and two or more source lines connected in parallel (e.g., Figure 6A The source lines (SL[0],SL[1]) are constructed similarly to those described above for the combined bit lines (BL[0],BL[1]). Accordingly, for the sake of brevity, a detailed description of the source lines (SL[0],SL[1]) is omitted here.

[0072] Figure 8 This is a schematic layout diagram illustrating another exemplary wiring of a memory device (e.g., memory device 600) according to various embodiments of the present invention. Figure 8 As shown, the exemplary layout 800 includes two or more bit lines BL[0], two or more bit lines BL[1], multiple word lines (e.g., WL[0] and WL[1]), multiple interconnects (e.g., IL[0] and IL[1]), two or more vias VIA[0], and two or more vias VIA[1]. The bit lines (BL[0], BL[1]) are arranged alternately along a first direction (x) and each extends along a second direction (y) transverse to the first direction (x).

[0073] The word lines (WL[0], WL[1]) and interconnects (IL[0], IL[1]) each extend along a first direction (x) and are arranged alternately along a second direction (y). In some embodiments, the word lines (WL[0], WL[1]) and interconnects (IL[0], IL[1]) are formed in the same metal layer, for example, in metal layers (M1 and / or M7).

[0074] Each of the vias (VIA[0]) extends along a third direction (z) transverse to the first and second directions (x, y) and connects a corresponding bit line (BL[0]) to an interconnect (IL[0]). Similarly, each of the vias (VIA[1]) extends along a third direction (z) and connects a corresponding bit line (BL[1]) to an interconnect (IL[1]). Since the bit lines (BL[0], BL[1]) are connected to the same interconnect (IL[0], IL[1]), the bit lines (BL[0], BL[1]) are connected in parallel. This parallel connection can reduce the total wiring resistance of the bit lines (BL[0], BL[1]), thereby increasing the probability of successfully programming the memory cell 200.

[0075] Furthermore, since the word lines (WL[0], WL[1]) and interconnects (IL[0], IL[1]) are arranged alternately along the second direction (y), this structure can increase the distance between vias (VIA[0], VIA[1]). This increase in spacing helps to prevent violations of via spacing requirements.

[0076] In some embodiments, layout 800 also includes two or more source lines connected in parallel (e.g., Figure 6AThe source lines (e.g., SL[0] and SL[1]) are constructed similarly to those described above for the combined bit lines (BL[0] and BL[1]). Accordingly, for the sake of brevity, a detailed description of the source lines (SL[0] and SL[1]) is omitted here.

[0077] Figure 9 This is a schematic layout diagram illustrating another exemplary wire arrangement of a memory cell according to various embodiments of the present invention. Figure 9 As shown, the exemplary layout 900 includes two or more bit lines (BL[0]-BL[3]), multiple word lines (e.g., word lines WL[0]-WL[3]), multiple interconnects (e.g., IL[0]-IL[3]), and two or more vias (VIA[0]-VIA[3]). The bit lines (BL[0]-BL[3]) are arranged alternately along a first direction (x) and each extends along a second direction (y) transverse to the first direction (x).

[0078] The word lines (WL[0]-WL[3]) and interconnects (IL[0]-IL[3]) each extend along a first direction (x) and are arranged alternately along a second direction (y). In some embodiments, the word lines (WL[0]-WL[3]) and interconnects (IL[0]-IL[3]) are formed in the same metal layer, for example, in metal layers (M1 and / or M7).

[0079] Each of the vias (VIA[0]) extends along a third direction (z) transverse to the first and second directions (x, y) and connects a corresponding bit line (BL[0]) to an interconnect (IL[0]). Similarly, each of the vias (VIA[1]-VIA[3]) extends along a third direction (z) and connects a corresponding bit line (BL[1]-BL[3]) to an interconnect (IL[1]-IL[3]). Since the bit lines (BL[0]-BL[3]) are connected to the same interconnect (IL[0]-IL[3]), the bit lines (BL[0]-BL[3]) are connected in parallel. This parallel connection can reduce the total wiring resistance of the bit lines (BL[0]-BL[3]), thereby increasing the likelihood of successfully programming the memory cell.

[0080] Furthermore, since the bit lines (BL[0]-BL[3]) are arranged alternately along the first direction (x), and since the word lines (WL[0]-WL[3]) and interconnects (IL[0]-IL[3]) are arranged alternately along the second direction (y), this configuration can increase the distance between vias (VIA[0], VIA[1]). This increase in spacing helps to prevent violations of via spacing requirements.

[0081] In some embodiments, layout 900 further includes two or more source lines (e.g., SL[0]-SL[3]) connected in parallel. The source lines (SL[0]-SL[3]) are constructed similarly to those described above for the combined bit lines (BL[0]-BL[3]). Accordingly, for the sake of brevity, a detailed description of the source lines (SL[0]-SL[3]) is omitted here.

[0082] Figure 10 This is a schematic layout diagram illustrating another exemplary wire arrangement of a memory cell according to various embodiments of the present invention. Figure 10 As shown, the exemplary layout 1000 includes two or more bit lines (BLs), multiple word lines (e.g., word lines WL[0]-WL[3]), multiple interconnects (e.g., interconnects IL[0]-IL[3]), and two or more vias (VIAs). For simplicity, Figure 10 Only one via (VIA) is marked. Bit lines (BL) are arranged along a first direction (x) and each extends along a second direction (y) transverse to the first direction (x).

[0083] The word lines (WL[0]-WL[3]) and interconnects (IL[0]-IL[3]) each extend along a first direction (x) and are arranged alternately along a second direction (y). In some embodiments, the word lines (WL[0]-WL[3]) and interconnects (IL[0]-IL[3]) are formed in the same metal layer, for example, in metal layers (M1 and / or M7).

[0084] Each of the vias (VIA) extends along a third direction (z) transverse to the first and second directions (x, y) and connects a corresponding bit line (BL) to an interconnect (IL[0]-IL[3]). Since the bit lines (BL) are connected to the same interconnect (IL[0]-IL[3]), the bit lines (BL) are connected in parallel. This parallel connection reduces the total wiring resistance of the bit lines (BL), thereby increasing the likelihood of successfully programming the memory cell.

[0085] Furthermore, since the word lines (WL[0]-WL[3]) and interconnects (IL[0]-IL[3]) are arranged alternately along the second direction (y), this configuration can increase the distance between vias (VIA) along the second direction (y). This increased spacing helps prevent violations of via spacing requirements.

[0086] In some embodiments, layout 1000 also includes two or more source lines (e.g., SL) connected in parallel. The source lines (SL) are constructed similarly to those described above in conjunction with bit lines (BL). Accordingly, for the sake of brevity, a detailed description of the source lines SL is omitted here.

[0087] Figure 11 This is a schematic layout diagram illustrating another exemplary wire arrangement of a memory device according to various embodiments of the present invention. Figure 11 As shown, the exemplary layout 1100 includes two or more bit lines (BLs), multiple word lines (e.g., word lines WL[0]-WL[3]), multiple interconnects (e.g., interconnects IL[0]-IL[3]), and two or more vias (VIAs). For simplicity, Figure 11 Only one via (VIA) is marked. Bit lines (BL) are arranged along a first direction (x) and each extends along a second direction (y) transverse to the first direction (x).

[0088] The word lines (WL[0]-WL[3]) and interconnects (IL[0]-IL[3]) each extend along a first direction (x) and are arranged alternately along a second direction (y). In some embodiments, the word lines (WL[0]-WL[3]) and interconnects (IL[0]-IL[3]) are formed in the same metal layer, for example, in metal layers (M1 and / or M7).

[0089] Each of the vias (VIA) extends along a third direction (z) transverse to the first and second directions (x, y) and connects an alternating bit line (BL) to an interconnect (IL[0]-IL[3]). Since the bit lines (BL) are connected to the same interconnects (IL[0]-IL[3]), they are connected in parallel. As described above, this parallel connection reduces the total wiring resistance of the bit lines (BL), thereby increasing the likelihood of successfully programming the memory cell.

[0090] Furthermore, because the alternating bit lines are connected to the interconnects (IL[0]-IL[3]), and because the word lines (WL[0]-WL[3]) and interconnects (IL[0]-IL[3]) are arranged alternately along the second direction (y), this configuration can increase the distance between vias (VIAs) along the first and second directions (x,y). This increased spacing helps prevent violations of via spacing requirements.

[0091] In some embodiments, layout 1100 also includes two or more source lines (e.g., SLs) connected in parallel. The source lines (SLs) are constructed similarly to those described above in conjunction with bit lines (BLs). Therefore, for the sake of brevity, a detailed description of the source lines (SLs) is omitted here.

[0092] Figure 12 This is a schematic layout diagram illustrating another exemplary wire arrangement of a memory device according to various embodiments of the present invention. Figure 12As shown, the exemplary layout 1200 includes two or more bit lines (BLs), multiple word lines (e.g., WL[0]-WL[3]), multiple interconnects (e.g., IL[0]-IL[3]), and two or more vias (VIAs). For simplicity, Figure 12 Only one via (VIA) is marked. Bit lines (BL) are arranged along a first direction (x) and each extends along a second direction (y) transverse to the first direction (x).

[0093] The word lines (WL[0]-WL[3]) and interconnects (IL[0]-IL[3]) each extend along a first direction (x) and are arranged alternately along a second direction (y). In some embodiments, the word lines (WL[0]-WL[3]) and interconnects (IL[0]-IL[3]) are formed in the same metal layer, for example, in metal layers (M1 and / or M7).

[0094] Each of the vias (VIA) extends along a third direction (z) transverse to the first and second directions (x, y) and connects a subset of corresponding bit lines (BL) to interconnects (IL[0]-IL[3]). Since the bit lines (BL) are connected to the same interconnects (IL[0]-IL[3]), the bit lines (BL) are connected in parallel. As described above, this parallel connection can reduce the total wiring resistance of the bit lines (BL), thereby increasing the likelihood of successfully programming memory cells.

[0095] Furthermore, since a subset of bit lines are connected to interconnects (IL[0]-IL[3]), and since word lines (WL[0]-WL[3]) and interconnects (IL[0]-IL[3]) are arranged alternately along the second direction (y), this configuration can increase the distance between vias (VIAs) along the first and second directions (x,y). This increased spacing helps prevent violations of via spacing requirements.

[0096] In some embodiments, layout 1200 also includes two or more source lines (e.g., SLs) connected in parallel. The source lines (SLs) are constructed similarly to those described above in conjunction with bit lines (BLs). Therefore, for the sake of brevity, a detailed description of the source lines (SLs) is omitted here.

[0097] Figure 13 This is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present invention. Figure 13As shown, the exemplary memory device 1300 includes a plurality of memory cells (e.g., memory cells 1310-1340), each including cell portions 1310a-1310d, 1320a-1320d, 1330a-1330d, and 1340a-1340d. In this exemplary embodiment, cell portions 1310a-1310d, 1320a-1320d, 1330a-1330d, and 1340a-1340d of one memory cell 1310-1340 are separated from cell portions 1310a-1310d, 1320a-1320d, 1330a-1330d, and 1340a-1340d of other memory cells 1310-1340. For example, unit portions 1310a-1310d, 1320a-1320d, 1330a-1330d, and 1340a-1340d are arranged in an array of rows and columns. Unit portions 1310a, 1310b, 1320a, and 1320b are arranged alternately along the first row and are each connected to a word line (WL[1]). Unit portions 1330a, 1330b, 1340a, and 1340b are arranged alternately along the second row and are each connected to a word line (WL[0]). Unit portions 1310c, 1310d, 1320c, and 1320d are arranged alternately along the third row and are each connected to a word line (WL[1]). Unit portions 1330c, 1330d, 1340c, and 1340d are arranged alternately along the fourth row and are each connected to a word line (WL[0]).

[0098] Similarly, cell portions 1310a, 1310c, 1330a, and 1330c are arranged alternately along the first column and each is connected between two or more bit lines (BL[1]) and two or more source lines (SL[1]). Cell portions 1320a, 1320c, 1340a, and 1340c are arranged alternately along the second column and each is connected between two or more bit lines (BL[0]) and two or more source lines (SL[0]). Cell portions 1310b, 1310d, 1330b, and 1330d are arranged alternately along the third column and each is connected between two or more bit lines (BL[1]) and two or more source lines (SL[1]). Cell portions 1320b, 1320d, 1340b, and 1340d are arranged alternately along the fourth column and are each connected between two or more bit lines (BL[0]) and two or more source lines (SL[0]). This configuration of the memory device 1300 simplifies the layout design of the wires (e.g., bit lines, source lines, and word lines) of the memory device 1300.

[0099] Figure 14This is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present invention. Figure 14 As shown, the exemplary memory device 1400 includes a plurality of memory cells, such as memory cells 1410-1480, each constituting a plurality of memory cells merged into a single memory cell. Since memory cells 1410-1480 are structurally similar, only one (e.g., memory cell 1410) will be described. Memory cell 1410 includes a plurality of memory cells 1490. For simplicity, Figure 14 Only one memory cell 1490 is marked in the diagram. Each memory cell 1490 is connected to multiple word lines (WL) that are connected to each other, and is connected between two or more bit lines (BL[0]) connected in parallel and two or more source lines (SL[0]) connected in parallel. This configuration of the memory device 1400 simplifies the layout design of its wires (e.g., bit lines, source lines, and word lines).

[0100] In some embodiments, memory cell 1410 is connected between a single source line (SL[0]) and a plurality of bit lines (BL[0]) connected in parallel. In other embodiments, memory cell 1410 is connected between a single bit line (BL[0]) and a plurality of source lines (SL[0]) connected in parallel.

[0101] Figure 15 This is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present invention. Figure 15 As shown, the exemplary memory device 1500 includes a plurality of memory cells, such as memory cells 1510-1580, each constituting a plurality of memory cells merged into a single memory cell. Since memory cells 1510-1580 are structurally similar, only one (e.g., memory cell 1510) will be described. Memory cell 1510 includes a plurality of memory cells 1590. For simplicity, Figure 15 Only one memory cell 1590 is marked in the diagram. Each memory cell 1590 is connected to a corresponding word line (WL[0]-WL[n]) and is connected between two or more bit lines (BL) connected in parallel and two or more source lines (SL) connected in parallel. This configuration of the memory device 1500 simplifies the layout design of its wires (e.g., bit lines, source lines, and word lines).

[0102] Figure 16 This is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present invention. Figure 16As shown, the exemplary memory device 1600 includes a plurality of memory cells, such as memory cells 1610 and 1620, each constituting a plurality of memory cells merged into a single memory cell. Since memory cells 1610 and 1620 are structurally similar, only one (e.g., memory cell 1610) will be described. Memory cell 1610 includes a plurality of memory cells 1690. For simplicity, Figure 16 Only one memory cell 1690 is marked in the diagram. Each memory cell 1690 is connected to multiple word lines (WL[0]) that are connected to each other, and is connected between two or more bit lines (BL) connected in parallel and two or more source lines (SL) connected in parallel. This configuration of the memory device 1600 simplifies the layout design of its wires (e.g., bit lines, source lines, and word lines).

[0103] Figure 17 This is a schematic diagram illustrating another exemplary memory device according to various embodiments of the present invention. Figure 17 As shown, the exemplary memory device 1700 includes a plurality of memory cells, such as memory cells 1710 and 1720, each constituting a plurality of memory cells merged into a single memory cell. Since memory cells 1710 and 1720 are structurally similar, only one (e.g., memory cell 1710) will be described. Memory cell 1710 includes a plurality of memory cells 1790. For simplicity, Figure 17 Only one memory cell 1790 is marked in the diagram. Each memory cell 1790 is connected to multiple word lines (WL) that are connected to each other, and is connected between two or more bit lines (BL[0]) connected in parallel and two or more source lines (SL[0]) connected in parallel. This configuration of the memory device 1700 simplifies the layout design of its wires (e.g., bit lines, source lines, and word lines).

[0104] In some embodiments, memory cell 1710 is connected between a single source line (SL[0]) and a plurality of bit lines (BL[0]) connected in parallel. In other embodiments, memory cell 1710 is connected between a single bit line (BL[0]) and a plurality of source lines (SL[0]) connected in parallel.

[0105] Figure 18 This is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present invention. Figure 18As shown, the exemplary memory device 1800 includes a plurality of memory cells, such as memory cells 1810 and 1820. Each memory cell 1810 and 1820 is divided into a plurality of cell portions, such as cell portions 1810a, 1810b, 1820a, and 1820b. Cell portions 1810a and 1810b are separated by cell portion 1820a. Similarly, cell portions 1820a and 1820b are separated by cell portion 1810b.

[0106] Furthermore, each memory cell 1810, 1820 constitutes multiple memory cells merged into a single memory cell. Since memory cells 1810, 1820 are structurally similar, only one will be described (e.g., memory cell 1810). Memory cell 1810 includes multiple memory cells 1890. For simplicity, Figure 18 Only one memory cell 1890 is marked in the diagram. Each memory cell 1890 is connected to multiple word lines (WL) that are connected to each other, and is connected between two or more bit lines (BL[0]) connected in parallel and two or more source lines (SL[0]) connected in parallel. This configuration of the memory device 1800 simplifies the layout design of its wires (e.g., bit lines, source lines, and word lines).

[0107] In some embodiments, memory cells 1810 and 1820 are connected between a single source line (SL[0], SL[1]) and a plurality of bit lines (BL[0], BL[1]) connected in parallel. In other embodiments, memory cell 1810 is connected between a single bit line (BL[0], BL[1]) and a plurality of source lines (SL[0], SL[1]) connected in parallel. In some embodiments, memory cell 1810 is connected between a single source line (SL[0], SL[1]) and a plurality of bit lines (BL[0], BL[1]) connected in parallel. In other embodiments, memory cell 1810 is connected between a single bit line (BL[0], BL[1]) and a plurality of source lines (SL[0], SL[1]) connected in parallel.

[0108] Figure 19 This is a schematic diagram illustrating another exemplary memory device according to various embodiments of the present invention. Figure 19 As shown, the exemplary memory device 1900 includes a plurality of memory cells, such as memory cells 1910 and 1920. Each memory cell 1910 and 1920 is divided into a plurality of cell portions, such as cell portions 1910a, 1910b, 1920a, and 1920b. Cell portions 1910a and 1910b are separated by cell portion 1920a. Similarly, cell portions 1920a and 1920b are separated by cell portion 1910b.

[0109] Furthermore, each memory cell 1910, 1920 constitutes multiple memory cells merged into a single memory cell. Since memory cells 1910, 1920 are structurally similar, only one will be described (e.g., memory cell 1910). Memory cell 1910 includes multiple memory cells 1990. For simplicity, Figure 19 Only one memory cell 1990 is marked in the diagram. Each memory cell 1990 is connected to multiple word lines (WL[0]) that are connected to each other, and is connected between two or more bit lines (BL) connected in parallel and two or more source lines (SL) connected in parallel. This construction of the memory device 1900 simplifies the layout design of its wires (e.g., bit lines, source lines, and word lines).

[0110] Figure 20 This is a flowchart of an exemplary method 2000 for manufacturing a memory device according to various embodiments of the present invention. Further reference will now be made for ease of understanding. Figures 1-19 Describes an exemplary method 2000. It should be understood that method 2000 is applicable to... Figures 1-19 Other than the structure. Furthermore, it should be understood that in alternative embodiments of method 2000, additional operations may be provided before, during, and after method 2000, and some of the operations described below may be replaced or cancelled.

[0111] In operation 2010, device fabrication tools fabricate memory cells (e.g., memory cells 110, 200, 300, 610) over a substrate. For example, Figure 21 This is a schematic cross-sectional view illustrating another exemplary memory device 2100 according to various embodiments of the present invention. Figure 21 As shown, an exemplary memory device 2100 (e.g., memory devices 100-1900) includes a substrate 2110, multiple metal layers (M0-M7), and multiple vias (V0-V6). The substrate 2110 may be made of silicon, germanium, group II / IV semiconductors, other suitable substrate materials, or alloys thereof. Device fabrication tools are used to dope the substrate 2110 to create source and drain regions (S,D) in the active portion of the substrate 2110. The device fabrication tools then deposit conductive material to form a metal deposit (MD) over the top surface of the source and drain regions (S,D) and a metal gate (MG) over the top surface of the gate region between the source and drain regions (S,D). The source and drain regions (S,D) and the metal gate (MG) constitute a selection transistor (e.g., selection transistors 220, 320, 660).

[0112] Next, in operation 2020, the device fabrication system deposits additional conductive material to form metal layers (e.g., metal layers M0-M7) stacked one on top of the other. For example, each metal layer (M0, M2) includes at least one source line (SL) connecting a selection transistor to a ground (or VSS) node. Metal layers (M1, M3, M5, M7) include multiple word lines (WL), each connected to a corresponding metal gate (MG). Metal layers (M4, M6) include multiple bit lines (BL) connecting the VDD node to OTP elements 2120 of the memory cell (e.g., OTP elements 260, 310, 650). In this exemplary embodiment, metal layers (M1, M3, M5, M7) also include interconnects (e.g., interconnects 230, 330, 670) connecting the bit lines (BL) in parallel. Vias (V0-V6) interconnect the metal layers (M0-M7). Examples of conductive materials include copper (Cu), aluminum (AL), other suitable metals, or alloys thereof.

[0113] In some embodiments, the memory device includes a plurality of memory cells, word lines, a plurality of bit lines, and a plurality of source lines. Each memory cell includes an one-time programmable (OTP) element and a plurality of select transistors. The word lines are connected to the gate terminal of the select transistor of the memory cell. The bit lines are connected in parallel between a first node and a first OTP element terminal of the OTP element of the memory cell. The source lines are connected in parallel and connect a second source / drain terminal of the select transistor of the memory cell to a second node. In some embodiments, the parallel connection of the bit lines reduces the total wiring resistance to facilitate programming of the one-time programmable element. In some embodiments, the bit lines are arranged along a first direction and each extends along a second direction transverse to the first direction; and the word lines extend along the first direction, the memory device further includes: interconnects parallel to the word lines; and a plurality of vias connecting two or more bit lines to the interconnects. In some embodiments, the bit lines are arranged along a first direction and each extends along a second direction transverse to the first direction; and the word lines extend along the first direction, the memory device further includes: interconnects parallel to the word lines; and a plurality of vias connecting two or more bit lines to the interconnects. In some embodiments, the two or more bit lines are adjacent to each other. In some embodiments, the distance between the vias is greater than the distance between the adjacent bit lines. In some embodiments, the one-time programmable element includes an antifuse that is initially in a non-conductive state and is configured to become permanently conductive when a programming voltage is applied to the memory cell through the bit lines and the source lines; and the antifuse is formed of a material configured to break down to form a conductive path when a programming voltage is applied to the memory cell through the bit lines and the source lines. In some embodiments, a selection transistor is configured to provide access to the memory cell during programming and read operations when a high or low selection signal is applied to the word line. In some embodiments, the memory device further includes a sense amplifier connected to the bit lines and configured to detect the state of the one-time programmable element during a read operation.In some embodiments, the plurality of memory cells include a first memory cell and a second memory cell, and the memory device further includes: a second word line connected to the gate terminal of the select transistor of the first memory cell and the second memory cell; a plurality of second bit lines connected in parallel, wherein the one-time programmable element of the first memory cell and the one-time programmable element of the second memory cell are connected between the second bit lines and the first source / drain terminals of the select transistor of the first memory cell and the second memory cell; and a plurality of second source lines connected in parallel and connecting the second source / drain terminals of the select transistor of the first memory cell and the second memory cell to the ground node.

[0114] In another embodiment, the memory cell includes one-time programmable (OTP) elements and a plurality of select transistors. The OTP element has a first OTP element terminal connected to one or more bit lines. Each select transistor has a gate terminal connected to a word line, a first source / drain terminal connected to a second OTP element terminal of the OTP element, and a second source / drain terminal connected to one or more source lines, wherein the bit lines are connected in parallel or the source lines are connected in parallel. In some embodiments, the memory cell further includes one or more pseudo-one-time programmable elements, each of which has: a first one-time programmable element terminal connected to the one or more bit lines, and a floating second one-time programmable element terminal. In some embodiments, the memory cell further includes: a first interconnect interconnecting the bit lines; a second interconnect interconnecting the source lines; and a third interconnect interconnecting the first source / drain terminals of the select transistors. In some embodiments, the bit lines are formed in the same metal layer; the word lines are formed in one or more metal layers; and the first interconnect is formed in the same metal layer as the word lines. In some embodiments, the source lines are formed in the same metal layer; the word lines are formed in one or more metal layers; and the second interconnect is formed in the same metal layer as the word lines. In some embodiments, the memory cell further includes at least one pseudo-one-time programmable element having: a first one-time programmable element terminal connected to the one or more bit lines, and a floating second one-time programmable element terminal.

[0115] In another embodiment, a method of manufacturing a memory device includes: fabricating a memory cell over a substrate; forming two or more bit lines connected in parallel between a first node and a first one-time programmable (OTP) element terminal of an OTP element of the memory cell by depositing conductive material in a first metal layer over the memory cell; depositing conductive material in at least one of a second metal layer below the first metal layer and a third metal layer above the first metal layer to form a word line connected to a gate terminal of a select transistor; and depositing conductive material to form at least one source line. The at least one source line connects a second source / drain terminal of the select transistor to a second node.

[0116] Embodiments of this application provide a method for manufacturing a memory device, the method comprising: fabricating a memory cell over a substrate, the memory cell including a one-time programmable element and one or more selection transistors; and depositing conductive material to form a plurality of metal layers stacked one on top of another, wherein the plurality of metal layers include: a first metal layer including at least one source line connecting the selection transistor to a first node; a second metal layer including a word line connected to a gate terminal of the selection transistor; and a third metal layer including a plurality of bit lines connected in parallel between a second node and the one-time programmable element. In some embodiments, the method further comprises: connecting the bit lines in parallel by depositing conductive material in the same metal layer as the word lines to form interconnects; and forming a plurality of vias, each of the vias connecting a corresponding bit line to the interconnect. In some embodiments, the method further comprises: connecting the source lines in parallel by depositing conductive material to form interconnects; and forming a plurality of vias, each of the vias connecting a corresponding source line to the interconnect. In some embodiments, the method further includes forming one or more pseudo-one-time programmable elements, each of the pseudo-one-time programmable elements having: a first one-time programmable element terminal connected to the bit line, and a second floating one-time programmable element terminal. In some embodiments, the memory cells constitute a plurality of memory cells, each memory cell being connected to the word line and connected between the two or more bit lines and the at least one source line.

[0117] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A memory device, comprising: Multiple memory cells, each including a one-time programmable element and multiple selection transistors; Word lines are connected to the gate terminals of the select transistors of the memory cells of the plurality of memory cells; Multiple bit lines are connected in parallel between the first node and the first one-time programmable element terminal of the one-time programmable element of the memory cell; as well as Multiple source lines are connected in parallel and connect the second source / drain terminals of the selection transistor of the memory cell to a second node.

2. The memory device according to claim 1, wherein, The parallel connection of the bit lines reduces the total wiring resistance, thereby facilitating the programming of the one-time programmable element.

3. The memory device according to claim 1, wherein: The bit lines are arranged along a first direction and each extends along a second direction transverse to the first direction; as well as The word line extends along the first direction, and the memory device further includes: Interconnect lines, parallel to the word lines; and Multiple vias connect two or more bit lines to the interconnect.

4. The memory device according to claim 3, wherein, The two or more bit lines are adjacent to each other.

5. The memory device according to claim 3, wherein, The distance between the vias is greater than the distance between adjacent bit lines.

6. The memory device according to claim 1, wherein: The one-time programmable element includes an antifuse that is initially in a non-conductive state and is configured to become permanently conductive when a programming voltage is applied to the memory cell through the bit line and the source line. as well as The antifuse is formed of a material configured to break down and form a conductive path when a programming voltage is applied to the memory cell through the bit line and the source.

7. The memory device according to claim 1, wherein, The selection transistor is configured to provide access to the memory cell during programming and read operations when a high or low selection signal is applied to the word line.

8. The memory device according to claim 1, further comprising: A sensing amplifier is connected to the bit line and configured to detect the state of the one-time programmable element during a read operation.

9. A memory cell, comprising: A one-time programmable element having a first one-time programmable element terminal connected to one or more bit lines; as well as A plurality of select transistors, each of the select transistors having a gate terminal connected to a word line, a first source / drain terminal connected to a second one-time programmable element terminal connected to the one-time programmable element, and a second source / drain terminal connected to one or more source lines, wherein the bit lines or source lines are connected in parallel.

10. A method for manufacturing a memory device, the method comprising: A memory cell is fabricated above a substrate, the memory cell comprising: One-time programmable elements; and One or more selection transistors; and A conductive material is deposited to form a plurality of metal layers stacked one on top of another, wherein the plurality of metal layers comprises: A first metal layer, the first metal layer including at least one source line connecting the selected transistor to a first node; A second metal layer, the second metal layer including word lines connected to the gate terminal of the select transistor; and A third metal layer, comprising a plurality of bit lines connected in parallel between the second node and the one-time programmable element.

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