High-gain wide-swing floating inverting amplifier circuit

Abstract

The invention belongs to the technical field of amplifiers. The invention provides a floating inverting amplifier circuit with high gain and wide swing. According to the embodiment of the invention, a first-stage amplifier of the multi-layer sleeve type FIA is cascaded with a second-stage amplifier (conventional FIA) serving as an output stage, and the input end and the output end of the output stage are connected through a first feedback network and a second feedback network to form a closed-loop negative feedback form. A feedback resistor and a feedback capacitor are connected in series to serve as a feedback network, and output stages are connected into a closed-loop negative feedback mode, so that the cascade connection stability of the first-stage amplifier and the second-stage amplifier of the multilayer sleeve type FIA can be effectively improved. While the advantages of low power consumption and high energy efficiency of full-dynamic design are kept, the problem that high gain and wide swing design of an existing floating inverting amplifier cannot be achieved at the same time is solved.

Description

Technical Field

[0001] This disclosure relates to the field of amplifier technology, and more particularly to a high-gain, wide-swing floating inverting amplifier circuit. Background Technology

[0002] The floating inverting amplifier (FIA) is a fully dynamic amplifier circuit, first proposed in reference [1], and has good output common-mode characteristics. Compared with the operational transconductance amplifier (OTA), the FIA ​​can provide a faster settling speed and can realize a fully dynamic circuit design, which greatly reduces the power consumption of the circuit and shows a broad application prospect in low-power, high-efficiency analog front-end circuits and analog-to-digital converter circuits.

[0003] The conventional FIA structure proposed in reference [1] (i.e., "XY Tang, B. Kasap, LX Shen, XX Yang, W. Shi, and N. Sun, "An Energy-Efficient Comparator with Dynamic Floating InverterPre-Amplifier," 2019 Symposium on Vlsi Circuits, pp. C140–C141, 2019.") has a relatively small gain, generally less than 30 dB, which is difficult to meet the needs of most systems. To improve gain, a sleeve-type floating inverting amplifier circuit (CFIA) was proposed in reference [2] (i.e., "RSA Kumar, N. Krishnapura, and P. Banerjee, “Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier,” IEEE Journal of Solid-State Circuits, vol.57, no. 11, pp. 3384–3395, Nov, 2022.”). The schematic diagram of CFIA is shown below. Figure 1 As shown, this circuit structure can only boost the FIA ​​gain to around 50 dB, but it limits the FIA ​​output swing. To improve the gain, the number of CFIA layers can be increased, i.e., more sleeve MOS devices can be added, but this will further limit the output swing. Furthermore, according to the FIA's operating principle, the MOS devices in the FIA ​​need to quickly enter the weak inversion region during the operating phase, therefore... Figure 1The size of the MCP / MCN components is much larger than that of the MP / MN components, which leads to an increase in the output load capacitance of the CFIA. Due to the large output parasitic capacitance, when the CFIA is used as the preamplifier in a cascaded amplifier structure, it can cause stability problems. This is because the increase in the output load capacitance of the CFIA is not enough to change the position of the system poles and separate them. Instead, it will pull the secondary poles closer to the dominant stage point, resulting in a deterioration of the system phase margin.

[0004] Therefore, it is necessary to improve one or more of the problems existing in the above-mentioned related technical solutions.

[0005] It should be noted that this section is intended to provide background or context for the technical solutions of this disclosure as set forth in the claims. The description herein does not constitute an admission that it is prior art simply because it is included in this section. Summary of the Invention

[0006] The purpose of this disclosure is to provide a high-gain, wide-swing floating inverting amplifier circuit, thereby overcoming, at least to some extent, one or more problems caused by limitations and defects in related technologies.

[0007] According to an embodiment of this disclosure, a high-gain, wide-swing floating inverting amplifier circuit is provided, comprising: The system comprises a first-stage amplifier, a second-stage amplifier, a first feedback network, and a second feedback network. The first feedback network includes a first feedback resistor and a first feedback capacitor connected in series. The second feedback network includes a second feedback resistor and a second feedback capacitor connected in series. The first-stage amplifier is a multi-layer sleeve-type FIA. The IP1 input terminal of the first-stage amplifier is connected to V. in+ Electrical connection: The IN1 input terminal of the first-stage amplifier is connected to V. in- Electrically connected, the ON1 output of the first-stage amplifier and the IP2 input of the second-stage amplifier are connected to the ON2 output of the second-stage amplifier and V through the first feedback network. out+ Electrically connected, the OP1 output of the first-stage amplifier and the IN2 input of the second-stage amplifier are connected to the OP2 output of the second-stage amplifier and V through the second feedback network. out- Electrical connection.

[0008] Furthermore, the first-stage amplifier includes: First energy storage capacitor C res1 First transistor M P1 Second transistor M P1 First transistor M CP1 Second transistor M CP1 First transistor M CP2 Second transistor M CP2 First transistor M N1Second transistor M N1 First transistor M CN1 Second transistor M CN1 First transistor M CN2 Second transistor M CN2 ;in, First energy storage capacitor C res1 First end, first reset switch φ RST The first end and the first amplifying switch φ AMP The first terminal is electrically connected, and the first reset switch φ RST The second terminal is connected to the power supply V DD Electrical connection, first amplification switch φ AMP The second terminal, the first transistor M P1 The source and second transistor M P1 The source electrical connection, the first transistor M P1 The drain and the first transistor M CP1 The source electrical connection, the first transistor M CP1 The drain and the first transistor M CP2 The source is electrically connected to the second transistor M. P1 The drain and the second transistor M CP1 The source is electrically connected to the second transistor M. CP1 The drain and the second transistor M CP2 The source electrical connection, the first transistor M CP1 The gate and the second transistor M CP1 gate and V BP1 Terminal electrical connection, first transistor M CP2 The gate and the second transistor M CP2 gate and V BP2 Terminal electrical connection, first transistor M CP2 The drain of the first transistor M CN2 The drain and the third reset switch φ RST The first terminal is electrically connected, and the second transistor M CP2 The drain of the second transistor M CN2 The drain and the fourth reset switch φ RST The first terminal is electrically connected, and the third reset switch φ RST The second and fourth reset switches φ RST The first end and V CM Terminal electrical connection; First energy storage capacitor C res1 The second end, the second reset switch φ RST The first end and the second amplifying switch φ AMP The first terminal is electrically connected, and the second reset switch φ RST The second terminal is grounded, and the second amplifying switch φ AMPThe second terminal, the first transistor M N1 The source and second transistor M N1 The source is electrically connected to a transistor M. N1 The drain and the first transistor M CN1 The source electrical connection, the first transistor M CN1 The drain and the first transistor M CN2 The source is electrically connected to the second transistor M. N1 The drain and the second transistor M CN1 The source is electrically connected to the second transistor M. CN1 The drain and the second transistor M CN2 The source electrical connection, the first transistor M CN1 The gate and the second transistor M CN1 gate and V BN1 Terminal electrical connection, first transistor M CN2 The gate and the second transistor M CN2 gate and V BN2 Terminal electrical connection; First transistor M P1 The gate and the first transistor M N1 gate and V in+ Electrical connection, second transistor M P1 The gate and the second transistor M N1 gate and V in- Electrical connection.

[0009] Furthermore, the second-stage amplifier includes: Second energy storage capacitor C res2 First transistor M P2 Second transistor M P2 First transistor M N2 Second transistor M N2 ;in, Second energy storage capacitor C res2 First terminal, fifth reset switch φ RST The first end and the third amplifying switch φ AMP The first terminal is electrically connected, and the fifth reset switch φ RST The second terminal is connected to the power supply V DD Electrical connection, third amplification switch φ AMP The second terminal, the first transistor M P2 The source and second transistor M P2 The source electrical connection, the first transistor M P2 The gate, the first transistor M N2 The gate and the fourth reset switch φ RST The first terminal is electrically connected, and the second transistor M P2 The gate, the second transistor M N2The gate and the third reset switch φ RST The first terminal is electrically connected, the first transistor M P2 The drain of the first transistor M N2 The drain and the seventh reset switch φ RST The first terminal is electrically connected, and the second transistor M P2 The drain of the second transistor M N2 The drain and the eighth reset switch φ RST The first terminal is electrically connected, and the seventh reset switch φ RST The second terminal and the eighth reset switch φ RST The second end and V CM Terminal electrical connection, second energy storage capacitor C res2 The second end, the sixth reset switch φ RST The first end and the fourth amplifying switch φ AMP The first terminal is electrically connected, and the sixth reset switch φ RST The second terminal is connected to ground, and the fourth amplifying switch φ AMP The second terminal, the first transistor M N2 The source and second transistor M N2 The source electrode is connected.

[0010] Furthermore, the first terminal of the first feedback network is connected to the first transistor M P2 gate and V out+ Electrical connection, the second terminal of the first feedback network is connected to the first transistor M P2 The drain is electrically connected; the first terminal of the second feedback network is connected to the second transistor M. P2 gate and V out- Electrical connection, the second terminal of the second feedback network is connected to the second transistor M. P2 The drain connection.

[0011] Furthermore, the operating timing of this floating inverting amplifier includes a reset phase and an amplification phase; wherein, During the reset phase, the reset clock is high and the amplification clock is low, corresponding to all reset switches φ. RST Close, all amplifying switches φ AMP Disconnect the first energy storage capacitor C of the first stage amplifier and the second stage amplifier. res1 Second energy storage capacitor C res2 Both ends are reset to the power supply voltage and ground respectively, and all outputs are reset to common-mode level; During the amplification phase, the amplification clock is high and the reset clock is low, corresponding to all amplification switches φ. AMP Close, all reset switches φ RST Disconnect the first energy storage capacitor C of the first stage amplifier and the second stage amplifier. res1Second energy storage capacitor C res2 The two ends of the amplifier are connected to supply power to the amplifier, enabling the amplifier to perform voltage amplification.

[0012] Furthermore, the first energy storage capacitor C res1 Second energy storage capacitor C res2 The capacitance value depends on the transconductance of each component during the amplification stage. and Confirmed, transconductance and It is related to the system's requirements for the speed and accuracy of the amplifier.

[0013] Furthermore, the first feedback capacitor and the second feedback capacitor are identical, and their capacitance values ​​are:

[0014] in, For the transconductance of the first stage amplifier, For the load capacitor of the output stage, It is the ratio of the unity gain frequency to the second pole frequency.

[0015] Furthermore, the first feedback resistor and the second feedback resistor are the same and satisfy the following conditions:

[0016] in, This is the transconductance of the second-stage amplifier.

[0017] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects: In the embodiments of this disclosure, the high-gain, wide-swing floating inverting amplifier circuit described above, on the one hand, cascades the first-stage amplifier of the multilayer sleeve-type FIA ​​with the second-stage amplifier as the output stage, and connects the input and output terminals of the output stage through a first feedback network and a second feedback network, forming a closed-loop negative feedback. The method of using a feedback resistor and a feedback capacitor in series as the feedback network to connect the output stage in a closed-loop negative feedback form can effectively improve the stability of the cascaded first-stage and second-stage amplifiers of the multilayer sleeve-type FIA. While maintaining the advantages of low power consumption and high energy efficiency inherent in the fully dynamic design, it solves the problem that existing floating inverting amplifier designs cannot simultaneously achieve high gain and wide swing. On the other hand, during the reset phase, the reset clock is high and the amplification clock is low. All corresponding reset switches are closed and all amplification switches are open. The first and second energy storage capacitors of the first and second stage amplifiers are reset to the power supply voltage and ground, respectively. At the same time, all outputs are reset to the common-mode level. During the amplification phase, the amplification clock is high and the reset clock is low. All corresponding amplification switches are closed and all reset switches are open. The first and second energy storage capacitors of the first and second stage amplifiers are connected to the amplifier to supply power, enabling the amplifier to perform voltage amplification. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0019] Figure 1 A circuit diagram of a sleeve-type floating inverting amplifier circuit in an exemplary embodiment of this disclosure is shown; Figure 2 A schematic diagram of a high-gain, wide-swing floating inverting amplifier circuit is shown in an exemplary embodiment of the present disclosure; Figure 3 A schematic diagram illustrating a method for improving the stability of a two-stage cascaded amplifier according to an exemplary embodiment of the present disclosure is shown. Figure 4 The complete circuit of the high-gain wide-swing floating inverting amplifier in an exemplary embodiment of this disclosure is shown; Figure 5 This diagram illustrates the operating timing of a high-gain, wide-swing floating inverting amplifier in an exemplary embodiment of this disclosure. Figure 6 A comparison graph showing the gain as a function of output swing in an exemplary embodiment of this disclosure is shown; Figure 7This diagram illustrates a comparison of the frequency response of gain and phase in an exemplary embodiment of this disclosure. Figure 8 A phase margin comparison diagram is shown in the exemplary embodiments of this disclosure. Detailed Implementation

[0020] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0021] Furthermore, the accompanying drawings are merely illustrative diagrams of embodiments of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0022] This example implementation provides a high-gain, wide-swing floating inverting amplifier circuit. (Reference) Figure 2 As shown, the high-gain, wide-swing floating inverting amplifier circuit may include: The system comprises a first-stage amplifier, a second-stage amplifier, a first feedback network, and a second feedback network. The first feedback network includes a first feedback resistor and a first feedback capacitor connected in series. The second feedback network includes a second feedback resistor and a second feedback capacitor connected in series. The first-stage amplifier is a multi-layer sleeve-type FIA. The IP1 input terminal of the first-stage amplifier is connected to V. in+ Electrical connection: The IN1 input terminal of the first-stage amplifier is connected to V. in- Electrically connected, the ON1 output of the first-stage amplifier and the IP2 input of the second-stage amplifier are connected to the ON2 output of the second-stage amplifier and V through the first feedback network. out+ Electrically connected, the OP1 output of the first-stage amplifier and the IN2 input of the second-stage amplifier are connected to the OP2 output of the second-stage amplifier and V through the second feedback network. out- Electrical connection.

[0023] The high-gain, wide-swing floating inverting amplifier circuit described above addresses the issue of cascading the first-stage amplifier of a multi-layer sleeve-type FIA ​​with the second-stage amplifier (which serves as the output stage). The first and second feedback networks connect the input and output terminals of the output stage, forming a closed-loop negative feedback loop. Using a feedback resistor and capacitor in series as the feedback network to connect the output stage in a closed-loop negative feedback configuration effectively improves the stability of the cascaded first and second-stage amplifiers in the multi-layer sleeve-type FIA. This approach maintains the low power consumption and high energy efficiency advantages of the fully dynamic design while resolving the inherent trade-off between high gain and wide swing in existing floating inverting amplifier designs. On the other hand, during the reset phase, the reset clock is high and the amplification clock is low. All corresponding reset switches are closed and all amplification switches are open. The first and second energy storage capacitors of the first and second stage amplifiers are reset to the power supply voltage and ground, respectively. At the same time, all outputs are reset to the common-mode level. During the amplification phase, the amplification clock is high and the reset clock is low. All corresponding amplification switches are closed and all reset switches are open. The first and second energy storage capacitors of the first and second stage amplifiers are connected to the amplifier to supply power, enabling the amplifier to perform voltage amplification.

[0024] Below, we will refer to Figures 2 to 8 The various parts of the high-gain, wide-swing floating inverting amplifier circuit described in this example embodiment will be explained in more detail.

[0025] In one embodiment, the novel high-gain, wide-swing floating inverting amplifier (i.e., high-gain, wide-swing floating inverting amplifier circuit) proposed in this application is as follows: Figure 2 As shown, its main implementation method is to cascade a multi-layer sleeve-type FIA ​​(i.e., the first-stage amplifier) ​​with a conventional FIA (i.e., the second-stage amplifier), while using a negative feedback structure to solve the stability problem of the two-stage amplifier cascade.

[0026] Using a multi-layer sleeve-type FIA ​​can improve... Figure 1 The gain of the amplifier circuit shown is increased, but the output swing of the amplifier is further limited. To address the problem that the output swing of a multi-layer sleeve FIA ​​decreases with the increase of the number of sleeve layers, this application uses a conventional FIA as the output stage and cascades it with a multi-layer sleeve FIA.

[0027] Cascading a multi-layer sleeve FIA ​​as a preamplifier and a conventional FIA as an output stage directly can lead to stability issues. This is because the size of the sleeve components in the multi-layer sleeve FIA ​​is relatively smaller than that of the input components. P / M NThe increase in magnitude will lead to a larger parasitic capacitance, resulting in an increase in the output capacitance of the first-stage amplifier. However, the increase in magnitude is not enough to swap the positions of the dominant and secondary poles and separate the two poles, which will instead lead to a deterioration in the phase margin.

[0028] Figure 3 (a) illustrates a method to improve the stability of a two-stage cascaded amplifier by connecting a feedback capacitor (C) to the second stage amplifier. c ). Figure 3 The feedback capacitor (C) connected in (a) c This can be equivalent to connecting one capacitor (C1) and one capacitor (C2) to the first stage output terminal and the second stage output terminal respectively, such as Figure 3 As shown in (b) above, the expressions for C1 and C2 are as follows: (1) (2) Where A2 is the DC gain of the second-stage amplifier. From equations (1) and (2), it can be seen that... Figure 2 The method shown can significantly increase the equivalent capacitance at the output of the first-stage amplifier, thereby changing the order of the dominant and secondary poles of the two-stage cascaded amplifier and separating the two poles. This compensates for the system's phase margin, thus improving the stability of the two-stage cascaded amplifier. This method is called "Miller compensation" and is commonly used in the design of two-stage cascaded over-the-air (OTA) amplifiers.

[0029] To address the stability issues of cascaded systems, this application is based on... Figure 3 (a) proposes to incorporate the feedback resistor (R) z ) and feedback capacitor (C c The feedback network formed by the series connection is connected to the input and output terminals of the output stage in the form of negative feedback, so that the output stage is connected in the form of closed-loop negative feedback, such as... Figure 2 As shown.

[0030] In one specific embodiment, the complete circuit structure of the high-gain, wide-swing floating inverting amplifier proposed in this application is as follows: Figure 4 As shown. The specific circuit connection method is as follows: The first-stage amplifier includes: First energy storage capacitor C res1 First transistor M P1 Second transistor M P1 First transistor M CP1 Second transistor M CP1 First transistor M CP2 Second transistor M CP2 First transistor M N1 Second transistor M N1First transistor M CN1 Second transistor M CN1 First transistor M CN2 Second transistor M CN2 ;in, First energy storage capacitor C res1 First end, first reset switch φ RST The first end and the first amplifying switch φ AMP The first terminal is electrically connected, and the first reset switch φ RST The second terminal is connected to the power supply V DD Electrical connection, first amplification switch φ AMP The second terminal, the first transistor M P1 The source and second transistor M P1 The source electrical connection, the first transistor M P1 The drain and the first transistor M CP1 The source electrical connection, the first transistor M CP1 The drain and the first transistor M CP2 The source is electrically connected to the second transistor M. P1 The drain and the second transistor M CP1 The source is electrically connected to the second transistor M. CP1 The drain and the second transistor M CP2 The source electrical connection, the first transistor M CP1 The gate and the second transistor M CP1 gate and V BP1 Terminal electrical connection, first transistor M CP2 The gate and the second transistor M CP2 gate and V BP2 Terminal electrical connection, first transistor M CP2 The drain of the first transistor M CN2 The drain and the third reset switch φ RST The first terminal is electrically connected, and the second transistor M CP2 The drain of the second transistor M CN2 The drain and the fourth reset switch φ RST The first terminal is electrically connected, and the third reset switch φ RST The second and fourth reset switches φ RST The first end and V CM Terminal electrical connection; First energy storage capacitor C res1 The second end, the second reset switch φ RST The first end and the second amplifying switch φ AMP The first terminal is electrically connected, and the second reset switch φ RST The second terminal is grounded, and the second amplifying switch φ AMP The second terminal, the first transistor M N1The source and second transistor M N1 The source is electrically connected to a transistor M. N1 The drain and the first transistor M CN1 The source electrical connection, the first transistor M CN1 The drain and the first transistor M CN2 The source is electrically connected to the second transistor M. N1 The drain and the second transistor M CN1 The source is electrically connected to the second transistor M. CN1 The drain and the second transistor M CN2 The source electrical connection, the first transistor M CN1 The gate and the second transistor M CN1 gate and V BN1 Terminal electrical connection, first transistor M CN2 The gate and the second transistor M CN2 gate and V BN2 Terminal electrical connection; First transistor M P1 The gate and the first transistor M N1 gate and V in+ Electrical connection, second transistor M P1 The gate and the second transistor M N1 gate and V in- Electrical connection.

[0031] The second-stage amplifier includes: Second energy storage capacitor C res2 First transistor M P2 Second transistor M P2 First transistor M N2 Second transistor M N2 ;in, Second energy storage capacitor C res2 First terminal, fifth reset switch φ RST The first end and the third amplifying switch φ AMP The first terminal is electrically connected, and the fifth reset switch φ RST The second terminal is connected to the power supply V DD Electrical connection, third amplification switch φ AMP The second terminal, the first transistor M P2 The source and second transistor M P2 The source electrical connection, the first transistor M P2 The gate, the first transistor M N2 The gate and the fourth reset switch φ RST The first terminal is electrically connected, and the second transistor M P2 The gate, the second transistor M N2 The gate and the third reset switch φ RSTThe first terminal is electrically connected, the first transistor M P2 The drain of the first transistor M N2 The drain and the seventh reset switch φ RST The first terminal is electrically connected, and the second transistor M P2 The drain of the second transistor M N2 The drain and the eighth reset switch φ RST The first terminal is electrically connected, and the seventh reset switch φ RST The second terminal and the eighth reset switch φ RST The second end and V CM Terminal electrical connection, second energy storage capacitor C res2 The second end, the sixth reset switch φ RST The first end and the fourth amplifying switch φ AMP The first terminal is electrically connected, and the sixth reset switch φ RST The second terminal is connected to ground, and the fourth amplifying switch φ AMP The second terminal, the first transistor M N2 The source and second transistor M N2 The source electrode is connected.

[0032] The first terminal of the first feedback network is connected to the first transistor M. P2 gate and V out+ Electrical connection, the second terminal of the first feedback network is connected to the first transistor M P2 The drain is electrically connected; the first terminal of the second feedback network is connected to the second transistor M. P2 gate and V out- Electrical connection, the second terminal of the second feedback network is connected to the second transistor M. P2 The drain connection.

[0033] A multi-layer sleeve-type FIA ​​is cascaded with a conventional FIA as the output stage, with a feedback resistor (R) z ) and feedback capacitor (C c The series connection is then used to connect the input and output terminals of the output stage, forming a closed-loop negative feedback configuration. The timing design of the high-gain, wide-swing floating inverting amplifier proposed in this application is as follows: Figure 5 As shown, the operation is divided into two phases: a reset phase and an amplification phase. During the reset phase, the reset clock is high and the amplification clock is low, corresponding to all φ... RST Switch (i.e., reset switch φ) RST ) closed, φ AMP Switch (i.e., amplifying switch φ) AMP Disconnect the capacitors (C) of the first and second stage amplifiers. res1 and C res2 The two ends of the circuit are reset to the power supply voltage (V). DD ) and ground, while all outputs are reset to common-mode level (VCM During the amplification stage, the amplification clock (φ) AMP ) is high level, reset clock (φ) RST ) is low level, corresponding to φ AMP When the switch is closed, φ RST When the switch is open, the energy storage capacitors (C) of the first and second stage amplifiers... res1 and C res2 The two ends of the amplifier are connected to supply power to the amplifier, enabling the amplifier to perform voltage amplification.

[0034] During the amplification phase, the transconductance of both sleeve-type and conventional FIA is expressed as follows: (3) (4) Where n represents the process parameter; U T This is the thermal voltage, which is positively correlated with temperature, and is approximately 26 mV at room temperature; I AMP (0 + ) by storage capacitor (C res The value of ) is determined by the transconductance. Assume the transconductance of the first-stage amplifier is G. m1 (t), the transconductance G of the second-stage amplifier m2 (t), the load capacitance of the output stage is C. L It can be obtained that during the amplification stage, the frequency of the high-gain, wide-swing floating inverting amplifier proposed in this application corresponds to the unity-gain frequency (ω). ta ) and secondary pole frequency (ω) p2 ), and zero frequency (ω) z The expression for ) is: (5) (6) (7) According to the principles of control, the unity gain frequency (ω) ta ) and secondary pole frequency (ω) p2 ) needs to satisfy: ω ta <ω p2 The specific numerical relationship is obtained from the system's phase margin requirements. Assume that the unity-gain frequency (ω) is obtained based on the system requirements. ta ) and secondary pole frequency (ω) p2 The relationship is ω ta =kω p2 (0 < k < 1), combining equations (5) and (6), the feedback capacitor (C) can be obtained. c The expression for ) is: (8) in, It is the ratio of unity gain frequency to the second pole frequency, which is determined by the system's stability requirements.

[0035] Based on the system's requirements for amplifier operating speed, the transconductance of the first and second stage amplifiers can be determined, and thus the feedback capacitor (C) can be determined. c The capacitance value of the amplifier can be determined based on equations (3) and (4) after determining the transconductance of each stage of the amplifier. res1 and C res2 The capacitance value of the storage capacitor (C). res1 and C res2 Given a fixed size, you only need to increase the size of all MOS devices to ensure that these devices quickly enter the weak inversion region during the amplification stage.

[0036] Because it is necessary to ensure that the zero point is located in the left half-plane, i.e., ω z <0, according to equation (7) we can obtain: (9) The minimum value of Rz can be determined by equation (9). Generally, the feedback resistor Rz can be appropriately increased according to the actual simulation situation to ensure that the system can remain stable under boundary conditions.

[0037] In one specific embodiment, this application proposes a novel high-gain wide-swing floating inverting amplifier circuit structure. To verify the effectiveness of this application, based on a 130nm CMOS process, under the same load, the gain of the proposed high-gain wide-swing FIA and a conventional CFIA as a function of output swing were designed and simulated, as follows: Figure 6 As shown. Figure 6 Simulation results show that the high-gain wide-swing FIA proposed in this application significantly improves both gain and output swing compared to the conventional CFIA. Figure 7 This demonstrates the effect of using different values ​​of R during the initial stage of the amplified phase. z With C c The frequency response of the amplifier's gain and phase under the condition of compensation with and without negative feedback structure; Figure 8 It shows a comparison of the system phase margin under different conditions. Figure 7 and 8 The simulation results show that the frequency compensation using the negative feedback structure proposed in this application can effectively improve the phase margin of the multi-layer sleeve-type FIA ​​and the conventional FIA cascade structure, and ensure the stability of the amplifier.

[0038] The high-gain, wide-swing floating inverting amplifier circuit described above addresses the issue of cascading the first-stage amplifier of a multi-layer sleeve-type FIA ​​with the second-stage amplifier (which serves as the output stage). The first and second feedback networks connect the input and output terminals of the output stage, forming a closed-loop negative feedback loop. Using a feedback resistor and capacitor in series as the feedback network to connect the output stage in a closed-loop negative feedback configuration effectively improves the stability of the cascaded first and second-stage amplifiers in the multi-layer sleeve-type FIA. This approach maintains the low power consumption and high energy efficiency advantages of the fully dynamic design while resolving the inherent trade-off between high gain and wide swing in existing floating inverting amplifier designs. On the other hand, during the reset phase, the reset clock is high and the amplification clock is low. All corresponding reset switches are closed and all amplification switches are open. The first and second energy storage capacitors of the first and second stage amplifiers are reset to the power supply voltage and ground, respectively. At the same time, all outputs are reset to the common-mode level. During the amplification phase, the amplification clock is high and the reset clock is low. All corresponding amplification switches are closed and all reset switches are open. The first and second energy storage capacitors of the first and second stage amplifiers are connected to the amplifier to supply power, enabling the amplifier to perform voltage amplification.

[0039] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0040] In the embodiments of this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0041] In embodiments of this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0042] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0043] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A high-gain, wide-swing floating inverting amplifier circuit, characterized in that, include: The system comprises a first-stage amplifier, a second-stage amplifier, a first feedback network, and a second feedback network. The first feedback network includes a first feedback resistor and a first feedback capacitor connected in series. The second feedback network includes a second feedback resistor and a second feedback capacitor connected in series. The first-stage amplifier is a multi-layer sleeve-type FIA. The IP1 input terminal of the first-stage amplifier is connected to V. in+ Electrical connection: The IN1 input terminal of the first-stage amplifier is connected to V. in- Electrically connected, the ON1 output of the first-stage amplifier and the IP2 input of the second-stage amplifier are connected to the ON2 output of the second-stage amplifier and V through the first feedback network. out+ Electrically connected, the OP1 output of the first-stage amplifier and the IN2 input of the second-stage amplifier are connected to the OP2 output of the second-stage amplifier and V through the second feedback network. out- Electrical connection.

2. The high-gain, wide-swing floating inverting amplifier circuit according to claim 1, characterized in that, The first-stage amplifier includes: First energy storage capacitor C res1 First transistor M P1 Second transistor M P1 First transistor M CP1 Second transistor M CP1 First transistor M CP2 Second transistor M CP2 First transistor M N1 Second transistor M N1 First transistor M CN1 Second transistor M CN1 First transistor M CN2 Second transistor M CN2 ;in, First energy storage capacitor C res1 First end, first reset switch φ RST The first end and the first amplifying switch φ AMP The first terminal is electrically connected, and the first reset switch φ RST The second terminal is connected to the power supply V DD Electrical connection, first amplification switch φ AMP The second terminal, the first transistor M P1 The source and second transistor M P1 The source electrical connection, the first transistor M P1 The drain and the first transistor M CP1 The source electrical connection, the first transistor M CP1 The drain and the first transistor M CP2 The source is electrically connected to the second transistor M. P1 The drain and the second transistor M CP1 The source is electrically connected to the second transistor M. CP1 The drain and the second transistor M CP2 The source electrical connection, the first transistor M CP1 The gate and the second transistor M CP1 gate and V BP1 Terminal electrical connection, first transistor M CP2 The gate and the second transistor M CP2 The gate and V BP2 Terminal electrical connection, first transistor M CP2 The drain of the first transistor M CN2 The drain and the third reset switch φ RST The first terminal is electrically connected, and the second transistor M CP2 The drain of the second transistor M CN2 The drain and the fourth reset switch φ RST The first terminal is electrically connected, and the third reset switch φ RST The second and fourth reset switches φ RST The first end and V CM Terminal electrical connection; First energy storage capacitor C res1 The second end, the second reset switch φ RST The first end and the second amplifying switch φ AMP The first terminal is electrically connected, and the second reset switch φ RST The second terminal is grounded, and the second amplifying switch φ AMP The second terminal, the first transistor M N1 The source and second transistor M N1 The source is electrically connected to a transistor M. N1 The drain and the first transistor M CN1 The source electrical connection, the first transistor M CN1 The drain and the first transistor M CN2 The source is electrically connected to the second transistor M. N1 The drain and the second transistor M CN1 The source is electrically connected to the second transistor M. CN1 The drain and the second transistor M CN2 The source electrical connection, the first transistor M CN1 The gate and the second transistor M CN1 The gate and V BN1 Terminal electrical connection, first transistor M CN2 The gate and the second transistor M CN2 The gate and V BN2 Terminal electrical connection; First transistor M P1 The gate and the first transistor M N1 The gate and V in+ Electrical connection, second transistor M P1 The gate and the second transistor M N1 The gate and V in- Electrical connection.

3. The high-gain, wide-swing floating inverting amplifier circuit according to claim 2, characterized in that, The second-stage amplifier includes: Second energy storage capacitor C res2 First transistor M P2 Second transistor M P2 First transistor M N2 Second transistor M N2 ;in, Second energy storage capacitor C res2 First terminal, fifth reset switch φ RST The first end and the third amplifying switch φ AMP The first terminal is electrically connected, and the fifth reset switch φ RST The second terminal is connected to the power supply V DD Electrical connection, third amplification switch φ AMP The second terminal, the first transistor M P2 The source and second transistor M P2 The source electrical connection, the first transistor M P2 The gate, the first transistor M N2 The gate and the fourth reset switch φ RST The first terminal is electrically connected, and the second transistor M P2 The gate, the second transistor M N2 The gate and the third reset switch φ RST The first terminal is electrically connected, the first transistor M P2 The drain of the first transistor M N2 The drain and the seventh reset switch φ RST The first terminal is electrically connected, and the second transistor M P2 The drain of the second transistor M N2 The drain and the eighth reset switch φ RST The first terminal is electrically connected, and the seventh reset switch φ RST The second terminal and the eighth reset switch φ RST The second end and V CM Terminal electrical connection, second energy storage capacitor C res2 The second end, the sixth reset switch φ RST The first end and the fourth amplifying switch φ AMP The first terminal is electrically connected, and the sixth reset switch φ RST The second terminal is connected to ground, and the fourth amplifying switch φ AMP The second terminal, the first transistor M N2 The source and second transistor M N2 The source electrode is connected.

4. The high-gain, wide-swing floating inverting amplifier circuit according to claim 3, characterized in that, The first terminal of the first feedback network is connected to the first transistor M. P2 gate and V out+ Electrical connection, the second terminal of the first feedback network is connected to the first transistor M P2 The drain is electrically connected; the first terminal of the second feedback network is connected to the second transistor M. P2 gate and V out- Electrical connection, the second terminal of the second feedback network is connected to the second transistor M. P2 The drain connection.

5. The high-gain, wide-swing floating inverting amplifier circuit according to claim 4, characterized in that, The operating timing of this floating inverting amplifier includes a reset phase and an amplification phase; wherein... During the reset phase, the reset clock is high and the amplification clock is low, corresponding to all reset switches φ. RST Close, all amplifying switches φ AMP Disconnect the first energy storage capacitor C of the first stage amplifier and the second stage amplifier. res1 Second energy storage capacitor C res2 Both ends are reset to the power supply voltage and ground respectively, and all outputs are reset to common-mode level; During the amplification phase, the amplification clock is high and the reset clock is low, corresponding to all amplification switches φ. AMP Close, all reset switches φ RST Disconnect the first energy storage capacitor C of the first stage amplifier and the second stage amplifier. res1 Second energy storage capacitor C res2 The two ends of the amplifier are connected to supply power to the amplifier, enabling the amplifier to perform voltage amplification.

6. The high-gain, wide-swing floating inverting amplifier circuit according to claim 5, characterized in that, First energy storage capacitor C res1 Second energy storage capacitor C res2 The capacitance value depends on the transconductance of each component during the amplification stage. and Confirmed, transconductance and It is related to the system's requirements for the speed and accuracy of the amplifier.

7. The high-gain, wide-swing floating inverting amplifier circuit according to claim 6, characterized in that, The first feedback capacitor and the second feedback capacitor are the same, and their capacitance values ​​are: in, For the transconductance of the first stage amplifier, For the load capacitor of the output stage, It is the ratio of the unity gain frequency to the second pole frequency.

8. The high-gain, wide-swing floating inverting amplifier circuit according to claim 7, characterized in that, The first feedback resistor and the second feedback resistor are the same, and satisfy the following: in, This is the transconductance of the second-stage amplifier.

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