Electronic circuit and method of operating electronic circuit

Abstract

A circuit (1) is specified, comprising a power thyristor device (2), in which-a gate (21) of the power thyristor device (2) is connected to an internal reference (10) of the circuit (1) via a first switch (31); and-the cathode (22) of the power thyristor device (2) is connected to an internal reference (10) of the circuit (1) via a second switch (32). Further, a method of operating a circuit (1) is specified.

Description

Technical Field

[0001] This disclosure relates to a circuit and a method of operating the circuit. Background Technology

[0002] Thyristors are well-suited for power applications because they can be used to switch electrical signals with high current and / or high voltage. Summary of the Invention

[0003] Embodiments of this disclosure relate to a method for improving the capabilities of circuits including thyristor devices.

[0004] According to an embodiment, a circuit includes a power thyristor device, wherein the gate of the power thyristor device is connected to an internal reference of the circuit via a first switch. The cathode of the power thyristor device is connected to the internal reference of the circuit via a second switch.

[0005] Therefore, if the first and second switches are in a conductive on state, the gate is electrically connected to the cathode. By means of the first and second switches, the blocking capability of the power thyristor device can be ensured to be maintained at all times. Specifically, the blocking capability can be maintained during the circuit's startup mode as well as during shutdown or failure modes.

[0006] During normal operation of the circuit, the first switch and / or the second switch can be put into a non-conductive open state (or blocking state), so that there is no low-impedance interconnect between the cathode and gate of the power thyristor device.

[0007] For example, power thyristor devices are configured to operate at a high current of at least 100 A and / or at a high voltage of at least 1000 V.

[0008] The internal reference of a circuit is specifically the power level to which all the circuit's supply voltages reference. In particular, both positive and negative voltage levels may exist relative to the internal reference. The internal reference may be at ground potential or separate from ground potential.

[0009] According to another embodiment of the circuit, the power thyristor device is a gate-commutated thyristor.

[0010] A gate-commutated thyristor can be turned on and off by applying a gate signal to its gate.

[0011] According to another embodiment of the circuit, the first switch and / or the second switch are semiconductor devices. Semiconductor devices can provide extremely reliable switching because they are insensitive to vibration. In particular, they are less susceptible to vibration than relays.

[0012] Specifically, the first switch and / or the second switch can be normally open semiconductor devices. Therefore, the first switch and / or the second switch are conductive if no voltage is applied to the respective gate.

[0013] If both the first and second switches are normally open semiconductor devices, the circuit provides an electrical connection between the cathode and gate of the power thyristor device when no voltage is applied to the gate of these switches. This helps ensure the complete blocking capability of the power thyristor device when the gate is not energized.

[0014] According to another embodiment of the circuit, the first and second switches are depletion-mode n-channel field-effect transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs). This type of transistor is conductive if no voltage is applied to its gate.

[0015] A depletion-mode n-channel field-effect transistor can be turned off by applying a negative voltage between the gate and source of the transistor.

[0016] According to another embodiment of the circuit, a resistor configured to limit the discharge current is arranged in the current path through the second switch between the cathode and the internal reference. The resistor limits the discharge current during the circuit's off-state. For example, the resistor is arranged between the cathode and the second switch. For example, the resistance of the resistor is at least 0.1 Ω or at least 1 Ω. Alternatively or additionally, the resistance may be at most 30 Ω, at most 20 Ω, or at most 7 Ω. Alternatively or additionally, the gate voltage of the second switch can be controlled to limit the discharge current. In this case, the resistor can be omitted or used as a shunt resistor.

[0017] According to another embodiment of the circuit, the circuit further includes a gate control unit configured to control the gate of the power thyristor, a first switch, and a second switch. The gate control unit may provide one or more power supplies (particularly power supplies with different voltage levels), and / or monitors and control logic and / or drivers and / or trigger circuitry and / or back porch circuitry or other active or passive components. For example, the gate control unit is configured to provide different pulse patterns during different operating modes. In other words, the circuit is configured to operate in multiple operating modes.

[0018] According to another embodiment of the circuit, the circuit is configured as an integrated gate commutated thyristor (IGCT). The IGCT specifically includes a power thyristor device and a gate cell for controlling the power thyristor device.

[0019] However, in contrast to conventional IGCTs, the first and second switches of the circuit can be used to provide high DC blocking and / or dV / dt robustness in all operating modes, especially even when the IGCT is not energized or the gate voltage is off.

[0020] According to another embodiment of the circuit, the circuit further includes a capacitor cell connected to the gate via a third switch. Specifically, the capacitor cell is configured to cut off current supplied to the gate of the thyristor device. For example, the capacitor cell includes multiple capacitors connected in parallel.

[0021] For example, the gate control unit is configured to control the third switch.

[0022] According to another embodiment of the circuit, the third switch includes a normally closed semiconductor device. For example, the third switch includes multiple semiconductor devices connected in parallel.

[0023] For example, a normally closed semiconductor device is an enhancement-mode field-effect transistor. Therefore, if the third switch is brought into its on state, the capacitor cell is partially discharged as long as there is charge in the thyristor device. In other words, the charge drawn from the capacitor cell is equal to or at least substantially equal to the charge inside the thyristor device between the gate and cathode.

[0024] Furthermore, if the second switch is in its on state, the capacitor cell can be discharged, for example, via a resistor.

[0025] The circuit can be configured to operate in different operating modes, such as startup mode and / or normal operating mode and / or shutdown or failure mode.

[0026] During all these operating modes, the complete blocking capability of the power thyristor device can be ensured, especially by means of the pulse mode that provides an electrical short circuit between the gate and cathode of the power thyristor device when needed.

[0027] Furthermore, a method for operating the circuit as described above is described in detail.

[0028] According to an embodiment of the circuit, the circuit operates in startup mode, wherein the first switch is turned off after the capacitor has been charged. Specifically, the second switch is already turned off when the first switch is turned off.

[0029] After the first switch has been turned off, the circuit can be operated in normal operating mode. In normal operating mode, the power thyristor device can be turned on and off by applying an appropriate signal to its gate.

[0030] According to another embodiment of the method, the second switch is turned off before the first switch is turned off. Specifically, the second switch may be turned off before the capacitor cell is charged.

[0031] During startup mode, the on state of the first switch ensures the blocking capability of the power thyristor device. During normal operation, the power thyristor device can be turned off by partially discharging the capacitor cell via the third switch. The charge drawn from the capacitor cell can be equal to or at least substantially equal to the charge inside the thyristor device between the gate and cathode. Furthermore, the thyristor device can be turned on when a signal is applied to the gate of the thyristor device from the gate control unit.

[0032] According to another embodiment of the method, the circuit is operated in a shutdown or failure mode, wherein the first and second switches are turned on when the capacitor cell is at least partially discharged.

[0033] At the start of the discharge process, the capacitor cell can provide sufficient power to operate the gate control unit. If the power decreases, it is no longer sufficient to maintain or deliver the backshoulder current or to turn on the power thyristor device. In this case, the gate cell will no longer respond to the input signal.

[0034] If the power thyristor device is in its on state, the gate control unit will turn off the power thyristor device by opening its off-channel via a third switch.

[0035] Furthermore, the first switch will be put into its conductive state, thereby electrically connecting the gate to the internal reference.

[0036] Furthermore, the second switch is turned on, thereby connecting the cathode to the internal reference. This can occur before, during, or shortly after the control logic of the gate control unit is de-energized. In this state, any remaining charge in the capacitor cell is discharged.

[0037] According to another embodiment of the method, during a shutdown or failure mode, the first switch is turned on before the second switch.

[0038] Therefore, the gate is connected to the internal reference before the cathode.

[0039] By employing appropriate pulse modes, this method allows for ensuring good DC blocking capability and high dV / dt robustness in all operating modes of the circuit. In particular, reliable blocking behavior of the power thyristor device can be ensured if the circuit is not powered and / or if no voltage is applied to the gate.

[0040] Furthermore, the circuit possesses black-start capability. This specifically means that the unpowered gate of the power thyristor device can withstand a voltage ramp with a slope of at least 100 V / μs.

[0041] Therefore, the first and second switches ensure a low-impedance connection between the gate and cathode of the power thyristor device when the gate is not energized. In particular, black-start capability requires no electricity or any kind of energy storage.

[0042] For example, the circuit can be configured for high-voltage direct current (HVDC) applications. For example, circuit 1 can be configured for a modular multilevel converter (MMC).

[0043] Therefore, the characteristics and advantages of combining circuit descriptions can also be applied to this method, and vice versa.

[0044] Each feature described in connection with one embodiment may be combined with one or more features described in connection with another embodiment, unless the embodiments are contradictory. Attached Figure Description

[0045] The accompanying drawings are included to provide further understanding. In the drawings, elements with the same structure and / or function may be referenced by the same reference numerals. It will be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0046] In the attached diagram: Figure 1 A schematic representation of a circuit according to an embodiment is shown; Figure 2 A schematic representation of a circuit according to an embodiment is shown; Figure 3 An exemplary illustration shows a pulse pattern during startup mode in an embodiment of the method according to the operating circuit; and Figure 4 An exemplary illustration shows the pulse pattern during a shutdown or failure mode of an embodiment of the method according to the operating circuit. Detailed Implementation

[0047] While this disclosure is open to various modifications and alternatives, its details are illustrated by way of example in the accompanying drawings and will be described in detail. However, it should be understood that this disclosure is not intended to be limited to the specific embodiments described. Rather, it is intended to cover all modifications, equivalents, and alternatives that fall within the scope of this disclosure as defined by the appended claims.

[0048] exist Figure 1In an exemplary embodiment, circuit 1 includes a power thyristor device 2, wherein the gate 21 of the power thyristor device 2 is connected to an internal reference 10 of circuit 1 via a first switch 31. The cathode 22 of the power thyristor device 2 is connected to the internal reference 10 of circuit 1 via a second switch 32.

[0049] Therefore, if the first switch 31 and the second switch 32 are in a conductive on state, the gate 21 and cathode 22 of the power thyristor device 2 are connected to the same internal reference 10 of the circuit 1.

[0050] exist Figure 1 In an exemplary embodiment, the first switch 31 and the second switch 32 are normally open semiconductor devices, such as depletion-mode n-channel MOSFETs.

[0051] exist Figure 1 In this configuration, the internal reference 10 is at ground potential. However, this is not necessary. Instead, the internal reference can be isolated from ground electrical potential.

[0052] Circuit 1 further includes capacitor unit 7. During normal operation of circuit 1, if the third switch 33 arranged in the turn-off channel line 53 is in its on state, capacitor unit 7 can provide current to cut off power thyristor device 2.

[0053] In contrast, during normal operation of circuit 1, the first switch 31 and the second switch 32 are in their open state.

[0054] However, during startup mode and / or shutdown or failure mode, the first switch 31 and the second switch 32 may be in the ON state, thereby providing an electrical connection between the cathode 22 and the gate 21 of the power thyristor device 2 to ensure the blocking capability of the power thyristor device during these operating modes.

[0055] This will combine Figure 3 and Figure 4 To provide a more detailed description.

[0056] Circuit 1 further includes a resistor 6 arranged in the current path through the second switch between the cathode 22 of circuit 1 and the internal reference 10.

[0057] For example, the resistance of resistor 6 is in the range of 0.1 Ω to 20 Ω.

[0058] Figure 1 The description also applies to Figure 2 . Figure 2 Further details of circuit 1, configured as an integrated gate-commutated thyristor, are shown.

[0059] Circuit 1 includes a power thyristor device 1 and a gate unit 4 having a gate control unit 40.

[0060] For example, the gate control unit 40 includes one or more power supplies. Further, for example, the gate control unit 40 may include monitors and control logic and / or drivers and / or trigger circuitry and backseat circuitry. During operation of circuit 1, circuit 1 is externally connected via input power line 41. Further, the gate control unit 40 is configured to receive input signal 42 and output output signal 43.

[0061] Cathode line 52 connects gate control unit 40 to cathode 22 of power thyristor device. Gate line 51 connects gate control unit 40 to gate 21 of power thyristor device 2.

[0062] Furthermore, the gate unit 4 includes a first switch 31, a second switch 32, a third switch 33, and so on. Figure 1 The capacitor unit 7 is described. In particular, the circuit is configured to operate in different operating modes.

[0063] The third switch 33 is a normally closed semiconductor device. During normal operation of circuit 1, the power thyristor device 2 can be turned off by applying a gate voltage to the gate of the third switch 33.

[0064] Figure 3 The diagram illustrates the pulse pattern during the startup mode of circuit 1.

[0065] The figure schematically illustrates the gate cell power 80 as a function of time, the signal level 81 at the second switch, the signal level 82 at the first switch, the signal level 83 for turning off the channel, and the capacitor voltage 84 with a maximum voltage 840.

[0066] Startup mode 85 is illustrated as an arrow extending between the shaded lines. During startup mode, capacitor unit 9 is charged. Afterward, the circuit can operate in its normal operating mode 86.

[0067] like Figure 3 As shown in the diagram, the gate unit power 80 is first activated to power the gate control unit 40.

[0068] Subsequently, the second switch 32 is put into its blocking state by applying a HIGH signal to the gate of the second switch 32. As illustrated by capacitor voltage 84, capacitor cell 9 is fully charged during startup mode 85.

[0069] Before, during, or after the charging of capacitor cell 7, but at least before the IGCT begins operation (arrow 86), the turn-off channel 83 is opened (HIGH signal). This is illustrated by the shaded area. Further shaded area illustration: If the corresponding signal is applied to the IGCT during startup mode, the power thyristor device 2 can be directly turned on at the start of normal operation mode 86. For example, the signal can be received as an optical signal via optical fiber. Then, the turn-off channel 83 (third switch) is closed, and a gate signal is applied. For example, a trigger current and a backshoulder current are applied to the gate of the power thyristor device 2.

[0070] After the capacitor cell 7 is charged and the channel 83 (third switch) is turned off to its conducting mode by the applied HIGH signal, the first switch 31 is turned off (HIGH signal). Once the capacitor cell 7 is fully charged, the circuit 1 is ready for normal operation, wherein the power thyristor device 2 can be turned on and off by switching the third switch 33 to its conducting state, or by any trigger current or backseat current applied by the gate control unit 40 to turn on the power thyristor or keep the power thyristor in the conducting state.

[0071] Needless to say, the gate control unit 40 can perform additional functions and / or provide additional signals, such as re-triggering.

[0072] Figure 4 An example of a pulse mode for the shutdown or failure mode of circuit 1 is illustrated.

[0073] The off point 87 is illustrated as an arrow extending between two shaded lines.

[0074] During the shutdown or failure mode 87, capacitor cell 7 is discharged, as illustrated by capacitor voltage 84. At the start of the discharge process, the signal to shut down channel 83 can be either HIGH or LOW. This is in Figure 4 The image is illustrated by the shaded area.

[0075] Once the capacitor voltage 84 has dropped to a certain value, circuit 1 will be unable to maintain or deliver the backseat current or turn on the power thyristor device 2. The gate control unit 40 will be unable to respond to the input signal.

[0076] When the gate 21 of the power thyristor device 2 is in its on state by a signal applied to the gate 21, the gate control unit 4 will turn off the power thyristor device 2 by opening the switching channel. Then, the first switch 31 is turned on (LOW signal) to electrically connect the gate 21 of the power thyristor device 2 to the internal reference 10.

[0077] The second switch 32 switches to its on state (LOW signal), thereby providing an electrical short circuit between the cathode 22 and the internal reference 10. This occurs before, during, or shortly after the control logic is de-energized. At this time, the turn-off channel signal level 83 switches to the LOW level, causing the third switch 33 to be in its off state.

[0078] The remaining charge in capacitor cell 7 can be discharged via second switch 32 and resistor 6. Resistor 6 can also be omitted. For example, the discharge current can be limited by applying an appropriate signal to the gate of second switch 32.

[0079] Different operating modes are illustrated: Circuit 1 provides reliable DC blocking and / or dV / dt robustness for all operating modes.

[0080] Furthermore, circuit 1 possesses full black-start capability, which is required for various applications. In particular, black-start capability does not require any electricity or any kind of energy storage.

[0081] Circuit 1 can be configured for HVDC applications. For example, Circuit 1 can be configured for a modular multilevel converter.

[0082] As stated Figures 1 to 4 The embodiments shown represent exemplary embodiments of improved circuits and methods; therefore, they do not constitute a complete list of all embodiments according to improved circuits and methods. For example, actual circuits and methods may differ from the illustrated embodiments in terms of arrangement, electrical components, and signals.

[0083] Figure Labels 1. Circuit 10 Internal Reference 2 Power Thyristor Devices 21 gate 22 Cathode 23 Anode 31 First Switch 32 Second Switch 33 Third Switch 4 gate units 40 Gate Control Unit 41 Input power line 42 Input Signal 43 Output signal 51 gate lines 52 Cathode wire 53 Shutdown of the trench line 6 Resistors 7 Capacitor Units 80 gate cell power 81 Signal level at the second switch 82 Signal level at the first switch 83. Channel shut-off signal level 84 Capacitor Voltage 840 Maximum voltage 85 Startup Mode 86. Standard Mode 87 Shutdown or Failure Mode

Claims

1. A circuit (1) comprising a power thyristor device (2), wherein, - The gate (21) of the power thyristor device (2) is connected to the internal reference (10) of the circuit (1) via a first switch (31); and - The cathode (22) of the power thyristor device (2) is connected to the internal reference (10) of the circuit (1) via a second switch (32).

2. The circuit according to claim 1, in, The power thyristor device (2) is a gate-commutated thyristor.

3. The circuit according to claim 1 or 2, in, The first switch (31) and the second switch (32) are normally open semiconductor devices.

4. The circuit according to any one of the preceding claims, in, The first switch (31) and the second switch (32) are depletion mode n-channel field-effect transistors.

5. The circuit according to any one of the preceding claims, in, A resistor (6) configured to limit the discharge current is arranged in the current path through the second switch (32) between the cathode (22) and the internal reference (10).

6. The circuit according to any one of the preceding claims, in, The circuit (1) further includes a gate control unit (40) configured to control the gate (21), the first switch (31) and the second switch (32) of the power thyristor device (2).

7. The circuit according to any one of the preceding claims, in, The circuit (1) is configured as an integrated gate-commutated thyristor.

8. The circuit according to any one of the preceding claims, in, The circuit (1) further includes a capacitor unit (7) connected to the gate (21) via a third switch (33).

9. The circuit according to claim 8, in, The third switch (33) includes a normally closed semiconductor device.

10. A method of operating the circuit according to claim 8 or 9, wherein, The circuit (1) is capable of operating in multiple operating modes.

11. The method according to claim 10, in, The circuit (1) is operated in startup mode (85), wherein the first switch (31) is turned off after the capacitor unit (7) has been charged.

12. The method according to claim 11, in, Before the first switch (31) is turned off, the second switch (32) is turned off.

13. The method according to claim 11, in, The circuit (1) is operated in a shutdown or failure mode (87), wherein the first switch (31) and the second switch (32) are turned on when the capacitor unit (7) is at least partially discharged.

14. The method according to claim 13, in, The first switch (31) is in the on state before the second switch (32).

Images