Image sensor using hybrid shutter driving method for sharing memory area

Abstract

Disclosed is an image sensor including a first photodiode, a second photodiode, a storage region including a first capacitor and a second capacitor, a first pixel signal generator circuit, and a second pixel signal generator circuit. A first pixel signal generator circuit configured to convert a voltage corresponding to the charge of the first photodiode stored in the storage area into a first pixel signal based on a first mode signal; and a first pixel signal generator circuit configured to convert a voltage corresponding to the charge of the first photodiode into a second pixel signal based on the second mode signal, and configured to transfer at least a portion of the charge of the first photodiode to the storage region based on the second mode signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0148550, filed on October 28, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The exemplary embodiments of this disclosure described herein relate to image sensors, and more specifically, to image sensors using a hybrid shutter driving method for a shared storage area. Background Technology

[0004] Image sensors convert light received through photodiodes into electrical signals. Complementary metal-oxide-semiconductor (CMOS) image sensors offer various advantages over other image sensors, such as ease of or simplicity of operation, lower power consumption, and the ability to integrate signal processing circuitry into a single chip.

[0005] With the rapid increase in the use of CMOS image sensors, there is a growing expectation that image sensors can improve performance while maintaining size, or be miniaturized / reduced in size while maintaining performance. Summary of the Invention

[0006] The exemplary embodiments of this disclosure provide an image sensor using a hybrid shutter driving method with a shared storage region.

[0007] According to some example embodiments of this disclosure, an image sensor includes a first photodiode, a second photodiode, a storage region including a first capacitor and a second capacitor, a first pixel signal generator circuit that converts a voltage corresponding to the charge of the first photodiode stored in the storage region into a first pixel signal based on a first mode signal, and a second pixel signal generator circuit that converts a voltage corresponding to the charge of the first photodiode into a second pixel signal based on a second mode signal, and simultaneously reads out the pixel signal corresponding to the first photodiode and the pixel signal corresponding to the second photodiode based on the first mode signal, and sequentially reads out the pixel signal corresponding to the first photodiode and the pixel signal corresponding to the second photodiode based on the second mode signal, and the first pixel signal generator circuit is configured to transfer at least a portion of the charge of the first photodiode to the storage region based on the second mode signal.

[0008] According to some exemplary embodiments of this disclosure, an image sensor includes a first capacitor, a second capacitor, a first transistor connected between a photodiode and a floating diffusion node and having a gate configured to receive a transmitted signal, a second transistor connected between the first node and the floating diffusion node and having a gate configured to receive a first reset signal, and a third transistor connected between the first node and a first power supply terminal. The first power supply terminal and the second power supply terminal are connected together and have a gate configured to receive a second reset signal. A fourth transistor is connected between the first power supply terminal and the second power supply terminal and has a gate configured to receive a third reset signal. A fifth transistor is connected between the third power supply terminal and the second node and has a gate connected to the floating diffusion node. A sixth transistor is connected between the second node and the first column line and has a gate configured to receive a selection signal. A seventh transistor is connected between the second node and the storage node and has a gate configured to receive a switch signal. An eighth transistor is connected between the storage node and one end of the first capacitor and has a gate configured to receive a first sampling signal. A ninth transistor is connected between the storage node and one end of the second capacitor and has a gate configured to receive a second sampling signal. A tenth transistor is connected between the first node and the second node or between the first node and the storage node and has a gate configured to receive a second switch signal. The other end of the first capacitor and the other end of the second capacitor are respectively connected to the second power supply terminal.

[0009] According to some example embodiments of this disclosure, an image sensor includes a storage region and a floating diffusion region. The storage region includes a first capacitor and a second capacitor. The storage region is configured to store charge overflowing from a photodiode using a global shutter method and to transfer the charge overflowing from the photodiode to at least one of the first capacitor and the second capacitor using a rolling shutter method.

[0010] According to some example embodiments of this disclosure, an image capture method includes: determining whether to operate using a first method or a second method; based on determining to operate using the first method, sending a first mode signal to a pixel circuit or based on determining to operate using the second method, sending a second mode signal to the pixel circuit; based on the pixel circuit receiving the first mode signal, collecting charge in a photodiode of the pixel circuit during an exposure time; storing charge in a floating diffusion region of the pixel circuit in a storage region of the pixel circuit and converting a voltage corresponding to the stored charge into a first pixel signal; based on the pixel circuit receiving the second mode signal, storing at least some of the floating diffusion regions of the pixel circuit in the storage region of the pixel circuit, converting a voltage corresponding to the charge in the floating diffusion regions into a second pixel signal, and converting a voltage corresponding to the charge in the expanded floating diffusion regions into a third pixel signal; outputting at least one pixel signal from the first pixel signal to the third pixel signal; and converting the output at least one pixel signal from the first pixel signal to the third pixel signal into a corresponding digital signal. The storage region includes a first capacitor and a second capacitor. Attached Figure Description

[0011] The above and other objects and features of this disclosure will become apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0012] Figure 1 This is a block diagram illustrating an image sensor according to some example embodiments of the present disclosure.

[0013] Figure 2 This is a diagram illustrating the global shutter method.

[0014] Figure 3 This is a diagram illustrating the rolling shutter method.

[0015] Figure 4 This is a diagram illustrating an image sensor according to some example embodiments of the present disclosure.

[0016] Figure 5 yes Figure 4 Detailed block diagram of the first pixel circuit.

[0017] Figure 6 These are some example embodiments based on this disclosure. Figure 5 The circuit diagram of the first pixel circuit.

[0018] Figure 7 It is shown Figure 5 The circuit diagram of the first pixel circuit operating in a global shutter method.

[0019] Figure 8 This is a diagram that conceptually illustrates the role of the capacitor shared with the floating diffusion region in the rolling shutter method.

[0020] Figure 9 It is shown Figure 5 The circuit diagram of the first pixel circuit operating in the rolling shutter method.

[0021] Figure 10 These are some example embodiments based on this disclosure. Figure 5 The circuit diagram of the first pixel circuit.

[0022] Figure 11 These are some example embodiments based on this disclosure. Figure 5 The circuit diagram of the first pixel circuit.

[0023] Figure 12 These are some example embodiments based on this disclosure. Figure 5 The circuit diagram of the first pixel circuit.

[0024] Figure 13 It describes the rolling shutter method. Figure 12 The circuit diagram for reading out the first pixel circuit.

[0025] Figure 14 It describes the rolling shutter method. Figure 13 The timing diagram for reading out the first pixel circuit.

[0026] Figure 15 This is a flowchart describing a method of operating an image sensor according to some example embodiments of the present disclosure. Detailed Implementation

[0027] Hereinafter, exemplary embodiments of the present disclosure will be described clearly and in detail so that those skilled in the art can readily implement the present disclosure.

[0028] The components described with reference to the terms used in the detailed description or claims, and the functional blocks shown in the drawings, can be implemented using software, hardware, or a combination thereof. For example, software can be machine code, firmware, embedded code, and application software. Hardware can include electrical circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, passive components, or combinations thereof.

[0029] Any or all elements described with reference to the accompanying drawings may communicate with any or all other elements described with reference to the accompanying drawings. For example, any element may communicate unidirectionally and / or bidirectionally and / or broadcastly with any or all other elements in the drawings to transfer and / or exchange and / or receive information such as, but not limited to, data and / or commands in a manner such as serial and / or parallel via a bus such as a wireless and / or wired bus (not shown). The information may be encoded in various formats, such as analog and / or digital formats.

[0030] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, the numerical values ​​intended to be associated include manufacturing or operational tolerances (e.g., ±10%) around said numerical value. Furthermore, when the terms “approximately” and “substantially” are used in conjunction with geometry, it is intended that the precision of the geometry is not required, but rather the tolerance of the shape is within the scope of this disclosure. Moreover, regardless of whether numerical values ​​or shapes are modified to “about” or “substantially”, it should be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) around said numerical value or shape.

[0031] As described herein, any electronic device and / or portion thereof according to any example embodiment may include one or more instances of processing circuitry, may be included in one or more instances of processing circuitry, and / or may be implemented by one or more instances of processing circuitry, such as hardware including logic circuitry; hardware / software combinations, such as a processor executing software; or any combination thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field-programmable gate array (FPGA) and programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, the processing circuitry may include a non-transitory computer-readable storage device (e.g., a memory), such as a DRAM device, storing a program of instructions, and a processor (e.g., a CPU) configured to execute the program of instructions to implement functions and / or methods performed by some or all of any device, system, module, unit, controller, circuit, architecture, and / or portion thereof according to any example embodiment and / or any portion thereof.

[0032] Figure 1 This is a block diagram illustrating an image sensor 100 according to some example embodiments of the present disclosure. Reference Figure 1 The image sensor 100 may include a pixel array 110, a line decoder 120, an analog-to-digital converter (ADC) circuit 130, a control circuit 140, and an image signal processor 150.

[0033] Pixel array 110 may include multiple pixel circuits (PIXs) and may be in the form of a matrix comprising multiple pixel rows and multiple pixel columns. In other words, each of the multiple pixel circuits (PIXs) may be arranged along both row and column directions. Pixel circuits located in the same column may be connected to the same column line (CL). Pixel circuits located in the same row may be connected to the same reset line. Each of the multiple pixel circuits (PIXs) of pixel array 110 may output a pixel signal that depends on the intensity or amount of light received from the outside. In this case, the pixel signal may be an analog signal corresponding to the intensity or amount of light received from the outside. Figure 1 The pixel array 110 is shown as comprising 16 pixel circuits (PIX) arranged in 4 rows and 4 columns, but the scope of this disclosure is not limited thereto, and the number of multiple pixel circuits (PIX) may be less or more than the number described above, and the arrangement structure may also be different from the arrangement structure described above.

[0034] The pixel circuit (PIX) according to some example embodiments of this disclosure can operate in a hybrid shutter method. The pixel circuit (PIX) can operate in a shutter method optimized for the performance and power consumption of the image sensor 100, depending on the required operating mode of the image sensor 100. For example, when high-resolution photography using the image sensor 100 is required, the pixel circuit (PIX) can operate in a rolling shutter method, and when video recording is performed, the pixel circuit (PIX) can operate in a global shutter method.

[0035] The structure and operation of the pixel circuit PIX are described in detail below with reference to the accompanying drawings.

[0036] The line decoder 120 can provide pixel drive signals to the pixel array 110, such as a line selection signal XR, a reset signal RS, a transfer signal TG, and a float control signal FG. Under the control of the control circuit 140, the line decoder 120 can select one row of the pixel array 110. The line decoder 120 can generate the line selection signal XR to select one row from multiple rows. Furthermore, the line decoder 120 can activate the reset signal RS, the transfer signal TG, and the float control signal FG in a predetermined (or, alternatively, desired or selected) order with respect to the pixel circuit PIX corresponding to the selected row. Thereafter, the reset level signal and the sense level signal generated from the pixel circuit PIX of the selected row can be provided to the analog-to-digital converter circuit 130.

[0037] The analog-to-digital converter (ADC) circuit 130 can convert the reset level signal and the sense level signal into a digital signal DS for output. For example, the ADC circuit 130 can sample the reset level signal and the sense level signal using a correlated double sampling (CDS) method and convert the sampled signal into a digital signal DS. For this purpose, the ADC circuit 130 may also include a correlated double sampler (not shown). The ADC circuit 130 may also include an output buffer circuit (not shown) that latches and outputs the digital signal DS. The output buffer circuit can temporarily store the converted digital signal DS and can output the digital signal DS in response to the control of the control circuit 140.

[0038] The control circuit 140 can control the pixel array 110, the line decoder 120, the analog-to-digital converter circuit 130, etc. The control circuit 140 may include a timing controller (not shown). The timing controller can supply control signals such as clock signals and timing control signals to the operation of the pixel array 110, the line decoder 120, the analog-to-digital converter circuit 130, etc. The control circuit 140 may include logic control circuitry, a phase-locked loop circuit, a timing control circuit, and a communication interface circuit.

[0039] Image sensors 100 according to some example embodiments of this disclosure can share a storage area in pixel circuits (PIX) in both global shutter and rolling shutter methods, thereby reducing the area of ​​the pixel circuits (PIX) while maintaining performance, or improving performance within the same area. A more detailed description will follow later. For example, according to some example embodiments, based on the methods described above, the reliability, operating parameters, speed, accuracy, and / or power efficiency of the image sensor can be increased. Therefore, the improved devices and methods overcome the shortcomings of conventional devices and methods while reducing resource consumption and / or improving image accuracy, operating parameters, and resource allocation (e.g., latency).

[0040] Figure 2 This is a diagram illustrating the global shutter method. (Reference) Figure 2 This conceptually illustrates the global shutter method.

[0041] In the global shutter method, the signal photoelectrically converted by the photoelectric element of each pixel circuit (hereinafter, target pixel circuit) in the target area is simultaneously (e.g., at the same time or approximately at the same time) transferred to the floating diffusion node, and then the digital signal of the corresponding pixel can be output from the sequentially selected row.

[0042] In detail, in the global shutter method, the image sensor can simultaneously (e.g., at the same time or approximately at the same time) reset the target pixel circuit, and then simultaneously (e.g., at the same time or approximately at the same time) transfer the charge corresponding to the light received by the photodiode during the same time period to the floating diffusion node. Thereafter, the pixel signals of the target pixel circuit can be read out sequentially according to the rows selected in the order.

[0043] Figure 3 This is a diagram illustrating the rolling shutter method. (Reference) Figure 3 This conceptually illustrates the rolling shutter method.

[0044] In the rolling shutter method, and Figure 2 Unlike the global shutter method, image sensors can sequentially reset and read out target pixel circuits row by row.

[0045] Figure 4 This is a diagram illustrating an image sensor according to some example embodiments of the present disclosure. Reference Figure 4 The pixel array 110 includes a first pixel circuit PIX1 and a second pixel circuit PIX2, and Figure 1 The image sensor 100 may also include a multiplexer (MUX) 115.

[0046] The first pixel circuit PIX1 and the second pixel circuit PIX2 can be arranged in the same column. The first pixel circuit PIX1 may include a first photodiode PD1, a first pixel signal generator circuit, a first storage area, and the second pixel signal generator circuit. The first pixel signal generator circuit may be at least partially associated with a global shutter method. The first storage area may include at least one capacitor. The second pixel signal generator circuit may be at least partially associated with a rolling shutter method. (See later...) Figure 5 A more detailed description of this is provided.

[0047] The second pixel circuit PIX2 may include a second photodiode PD2, a third pixel signal generator circuit, a second storage area, and a fourth pixel signal generator circuit. The third pixel signal generator circuit, the second storage area, and the fourth pixel signal generator circuit may correspond to the first pixel signal generator circuit, the first storage area, and the second pixel signal generator circuit of the first pixel circuit PIX1, respectively.

[0048] The first pixel signal generator circuit and the third pixel signal generator circuit can be connected to the multiplexer 115 via the first column line CL11. The second pixel signal generator circuit and the fourth pixel signal generator circuit can be connected to the multiplexer 115 via the second column line CL12.

[0049] Multiplexer 115 can be connected to analog-to-digital converter circuit 130 via first integrated column line CL1. Multiplexer 115 can multiplex pixel signals received from first column line CL11 and second column line CL12 so as to provide them to analog-to-digital converter circuit 130 via first integrated column line CL1.

[0050] The analog-to-digital converter circuit 130 can convert the pixel signals received from the multiplexer 115 into digital signals DS. The analog-to-digital converter circuit 130 can then provide the converted digital signals DS to... Figure 1 Image signal processor 150.

[0051] Figure 5 yes Figure 4 Detailed block diagram of the first pixel circuit PIX1. (See reference) Figure 5 The first pixel circuit PIX1 may include a first photodiode PD1, a first pixel signal generator circuit, a first storage area, and a second pixel signal generator circuit.

[0052] The first photodiode PD1 can receive light and generate a charge corresponding to the intensity or amount of the received light.

[0053] The first storage region may include at least one capacitor. For example, the first storage region may include a first capacitor and a second capacitor.

[0054] The first pixel signal generator circuit can perform the following operations based on the first mode signal MS1. The first pixel signal generator circuit can store the charge of the first photodiode PD1 (e.g., charge overflowing from the first photodiode PD1) in a first storage region. Thereafter, the first pixel signal generator circuit can convert the voltage corresponding to the charge stored in the first storage region into a first pixel signal PS1.

[0055] In some example embodiments, the first pixel signal generator circuit can store the charge corresponding to the reset level signal from the charge of the first photodiode PD1 in a first capacitor, and can store the charge corresponding to the sensing level signal in a second capacitor. In this case, the reset level signal and the sensing level signal can each represent a sampling signal used in the correlated double sampling method.

[0056] In some example embodiments, the first mode signal MS1 may correspond to a global shutter method. For example, the first mode signal MS1 may correspond to a gating signal of at least one transistor of the first pixel circuit PIX1.

[0057] In some example embodiments, the first pixel signal generator circuit can convert the voltage corresponding to the charge stored in the first capacitor into a reset level signal for the first pixel signal PS1. Furthermore, the first pixel signal generator circuit can convert the voltage corresponding to the charge stored in the second capacitor into a sensing level signal for the first pixel signal PS1.

[0058] The second pixel signal generator circuit can perform the following operations based on the second mode signal MS2. The second pixel signal generator circuit can transfer the charge of the first photodiode PD1 to the storage region. Specifically, the second pixel signal generator circuit can transfer the charge overflowing from the first photodiode PD1 to the floating diffusion region and the storage region.

[0059] In some example embodiments, the second pixel signal generator circuit can form a charge transfer path between the floating diffusion region and the storage region. Reference will be made later. Figure 5 and Figure 10 A more detailed description follows. The first storage region can be used as an extended electrostatic capacitance of the floating diffusion region.

[0060] For example, the first storage region may include a first capacitor and a second capacitor. In this case, the charge overflowing from the first photodiode PD1 can be transferred to the extended floating diffusion region (the floating diffusion region and the first storage region). See later... Figure 8 and Figure 9 Describe it in more detail.

[0061] The second pixel signal generator circuit can convert the voltage corresponding to the charge in the floating diffusion region into a second pixel signal PS2. The second pixel signal generator circuit can also convert the voltage corresponding to the charge in the first storage region into a third pixel signal PS3.

[0062] In some example embodiments, the first storage region may include a first capacitor and a second capacitor. The second pixel signal generator circuit may store the charge overflowing from the first photodiode PD1 in at least one of the floating diffusion region, the first capacitor, and the second capacitor.

[0063] In some example embodiments, the second mode signal MS2 may correspond to a rolling shutter method. For example, the second mode signal MS2 may correspond to the gating signal of at least one transistor of the first pixel circuit PIX1.

[0064] The second pixel signal generator circuit can have a floating diffusion region with extended electrostatic capacitance by using a first capacitor and a second capacitor. Therefore, the performance of an image sensor operating in a rolling shutter method can be improved.

[0065] In some example embodiments, the first mode signal MS1 and the second mode signal MS2 may be activated at different times. For example, the image sensor may activate the first mode signal MS1 during a first time period and activate the second mode signal MS2 during a second time period that does not overlap with the first time period.

[0066] The first pixel signal generator circuit can be connected to Figure 4 The first column line CL11. The first pixel signal generator circuit can output the first pixel signal PS1 through the first column line CL11.

[0067] The second pixel signal generator circuit can be connected to Figure 4 The second column line CL12. The second pixel signal generator circuit can output the second pixel signal PS2 and the third pixel signal PS3 through the second column line CL12.

[0068] In some example embodiments, Figure 1 The analog-to-digital converter circuit 130 can convert the first pixel signal PS1, the second pixel signal PS2, and the third pixel signal PS3 into a first digital signal, a second digital signal, and a third digital signal, respectively.

[0069] For example, in the rolling shutter method, Figure 1 The image signal processor 150 can generate an image signal corresponding to the first pixel circuit PIX1 based on signal processing operations of the second and third digital signals. In this case, an image signal with reduced noise can be generated. The image signal of the first pixel circuit PIX1 can be combined with the image signals of other pixels to generate image data that can be stored or displayed.

[0070] refer to Figure 5 The first pixel signal generator circuit, the first storage area, and the second pixel signal generator circuit are shown as separate components, but the scope of this disclosure is not limited thereto. The first pixel signal generator circuit may include the first storage area and / or the second pixel signal generator circuit. Alternatively, the second pixel signal generator circuit may include the first pixel signal generator circuit and / or the first storage area.

[0071] In some example embodiments, the first pixel signal generator circuit can generate a third pixel signal PS3 based on the second mode signal MS2, and can output the third pixel signal PS3 through the first column line CL11. See later. Figures 12 to 14 Describe it in more detail.

[0072] Figure 6 These are some example embodiments based on this disclosure. Figure 5The circuit diagram of the first pixel circuit, PIX1. (Reference) Figure 6 The diagram shows a detailed circuit diagram of the first pixel circuit, PIX1.

[0073] The first pixel circuit PIX1 may include transistors TR1 to TR12, a first capacitor C1, and a second capacitor C2.

[0074] The first transistor TR1 can be connected between the first photodiode PD1 and the floating diffusion node FD, and can include a gate for receiving the transmitted signal TG.

[0075] The second transistor TR2 can be connected between the first node N1 and the floating diffusion node FD, and can include a gate that receives the first reset signal RS1.

[0076] The third transistor TR3 can be connected between the first node N1 and the first power supply terminal, and can include a gate for receiving the second reset signal RS2. In this case, the first power supply terminal can receive the first power supply voltage VDD1.

[0077] The fourth transistor TR4 can be connected between the first power supply terminal and the second power supply terminal, and can include a gate for receiving the third reset signal RS3. In this case, the second power supply terminal can receive the second power supply voltage VDD2. When the first pixel circuit PIX1 operates in a rolling shutter method based on the second mode signal MS2, the fourth transistor TR4 can perform the function of resetting the first capacitor C1 and the second capacitor C2.

[0078] The fifth transistor TR5 can be connected between the third power supply terminal and the second node N2, and can include a gate connected to the floating diffusion node FD. In this case, the third power supply terminal can receive the third power supply voltage VDD3. The fifth transistor TR5 can function as a source follower, outputting the voltage of the floating diffusion node FD. The fifth transistor TR5 can also be referred to as the first source follower transistor.

[0079] A sixth transistor TR6 can be connected between the second node N2 and the second column line CL12, and can include a gate for receiving the first selection signal SEL1. When the sixth transistor TR6 performs a readout operation, the voltage of the first node N1 can be transferred to the second column line CL12. Additionally, the sixth transistor TR6 can perform an on / off function with respect to the second column line CL12. For example, when 0V is input to the gate of the sixth transistor TR6, the second column line CL12 can be turned off.

[0080] The seventh transistor TR7 can be connected between the second node N2 and the storage node SN, and can include a gate that receives the first switching signal SW1.

[0081] The eighth transistor TR8 can be connected between the storage node SN and one end of the first capacitor C1, and can include a gate for receiving the first sampling signal SMP1.

[0082] The ninth transistor TR9 can be connected between one end of the storage node SN and the second capacitor C2, and can include a gate for receiving the second sampling signal SMP2.

[0083] The tenth transistor TR10 can be connected between the first node N1 and the storage node SN, and can include a gate that receives the second switching signal SW2.

[0084] The eleventh transistor TR11 can be connected between the fourth power supply terminal and the third node N3, and can include a gate connected to the storage node SN. In this case, the fourth power supply terminal can receive the fourth power supply voltage VDD4. The eleventh transistor TR11 can function as a source follower, outputting the voltage of the storage node SN. The eleventh transistor TR11 can also be referred to as the second source follower transistor.

[0085] The twelfth transistor TR12 can be connected between the third node N3 and the first column line CL11, and can include a gate for receiving the second selection signal SEL2. When the twelfth transistor TR12 performs a readout operation, the voltage of the third node N3 can be transferred to the first column line CL11. Additionally, the twelfth transistor TR12 can perform an on / off function regarding the first column line CL11. For example, when 0V is input to the gate of the twelfth transistor TR12, the first column line CL11 can be turned off.

[0086] The other end of the first capacitor C1 can be connected to the second power supply terminal. The other end of the second capacitor C2 can also be connected to the second power supply terminal. In other words, the first capacitor C1 and the second capacitor C2 can be connected in parallel between the storage node SN and the second power supply terminal while the eighth transistor TR8 and the ninth transistor TR9 are turned on.

[0087] For ease of description, although not shown, the first pixel circuit PIX1 may also include at least one transistor (also referred to as a pre-charge transistor) associated with pre-charging between the second node N2 and the ground power supply or between the storage node SN and the ground power supply. The pre-charge transistor can perform a biasing function during a dump operation. For example, in global shutter mode, the image sensor can store the voltage of the second node N2 in the first capacitor C1 or the second capacitor C2 via a dump operation.

[0088] Each of the gating signals of transistors TR1 to TR12 can be controlled according to the sequence determined by the mode signal.

[0089] Figure 7 It is shown Figure 5 The diagram shows the first pixel circuit, PIX1, operating using the global shutter method. (Reference) Figure 7 The circuit diagram of the first pixel circuit PIX1, which operates using the global shutter method, is shown. Figure 7 The components can be respectively with Figure 6 Components with the same reference symbol correspond to each other.

[0090] The first pixel circuit PIX1 can turn off the fourth transistor TR4 and the tenth transistor TR10 based on the first mode signal.

[0091] In this configuration, the precharge transistor (not shown) can maintain the bias of the first pixel circuit PIX1 to dump the charge of the floating diffusion node FD to the first capacitor C1 and the second capacitor C2.

[0092] The first pixel circuit PIX1 can store the charge corresponding to the global reset voltage Vr in the first capacitor C1, and can store the charge corresponding to the global pixel voltage Vs in the second capacitor C2.

[0093] Subsequently, a readout operation can be performed while the eighth transistor TR8 and the ninth transistor TR9 are sequentially turned on again. Specifically, when the eighth transistor TR8 is turned on, the global reset voltage Vr stored in the first capacitor C1 is transferred to the storage node SN. When the ninth transistor TR9 is turned on, the global pixel voltage Vs stored in the second capacitor C2 is transferred to the storage node SN. The eleventh transistor TR11 can sequentially amplify the global reset voltage Vr and the global pixel voltage Vs of the storage node SN, and the amplified voltage can be output as the first pixel signal PS1 through the turned-on twelfth transistor TR12.

[0094] The first pixel circuit PIX1 can output the first pixel signal PS1 through the first column line CL11.

[0095] Figure 8 This diagram conceptually illustrates the role of the capacitor shared with the floating diffuser region (FD) in the rolling shutter method. (Reference) Figure 8 The flow of charge is described in the cases where there is a capacitor C1 or C2 shared with the floating diffusion region FD and in the case where there is no capacitor.

[0096] Photodiodes (PDs) can have higher potential levels than floating diffusion regions (FDs). Therefore, Figure 6The photodiode PD generates a charge corresponding to the received light, and some of the charge generated by the photodiode PD overflows and is transferred to the floating diffusion region FD.

[0097] In this scenario, as the intensity or amount of light received by the photodiode PD increases, the charge transferred from the photodiode PD may exceed the electrostatic capacitance of the floating diffusion region FD. This overflowing charge from the floating diffusion region FD can cause noise as leakage current, thereby degrading the image sensor's performance.

[0098] Conversely, the capacitance of the floating diffusion region FD can be increased when a capacitor C1 or C2 is electrically connected (or shared) with the floating diffusion region FD. Specifically, the charge overflowing from the photodiode PD can be transferred to the floating diffusion region FD, the first capacitor C1, and the second capacitor C2.

[0099] In other words, the charge overflowing from the photodiode PD can be transferred to an extended floating diffusion region, which has a capacitance that is the sum of the capacitances of the floating diffusion region FD, the first capacitor C1, and the second capacitor C2. Therefore, leakage current caused by the charge overflowing from the photodiode PD can be eliminated or reduced.

[0100] In this case, not only the charge that was not transferred to the floating diffusion region FD of capacitors C1 and C2, but also the charge that was transferred to the floating diffusion region FD of capacitors C1 and C2 can be read out and used to generate image signals, thereby reducing noise or distortion in the image signals.

[0101] Figure 9 It is shown Figure 5 The circuit diagram for the first pixel circuit PIX1 operating in the rolling shutter method is shown below. (Reference) Figure 9 In the rolling shutter method, the flow and readout operation of charge transferred from the first pixel circuit PIX1 to the floating diffusion node FD can be described. Figure 9 The components can be respectively with Figure 6 Components with the same reference symbol correspond to each other.

[0102] Based on the second mode signal, the first pixel circuit PIX1 can operate as follows.

[0103] First, the seventh transistor TR7 can be turned off by the first switching signal SW1, and the tenth transistor TR10 can be turned on by the second switching signal SW2. Furthermore, at least one of the eighth transistor TR8 and the ninth transistor TR9 can be turned on by the first sampling signal SMP1 and the second sampling signal SMP2. In other words, a charge transfer path can be formed between at least one of the first capacitor C1 and the second capacitor C2 and the floating diffusion node FD.

[0104] The charge overflowing from the first photodiode PD1 can be transferred to the floating diffusion node FD, the first capacitor C1, and the second capacitor C2. In this case, the first capacitor C1 and the second capacitor C2 can be used as extended electrostatic capacitances for the floating diffusion node FD. Specifically, the first capacitor C1 and the second capacitor C2 can extend the floating diffusion region FD, as shown in the reference. Figure 8 As stated above.

[0105] Subsequently, the first pixel circuit PIX1 can perform a readout operation. Specifically, the fifth transistor TR5 amplifies the voltage of the floating diffusion node FD. The turned-on sixth transistor TR6 outputs the amplified voltage as the second pixel signal PS2 through the second column line CL12.

[0106] The charge stored in the first capacitor C1 can be transferred to the storage node SN by turning on the eighth transistor TR8 again through the first sampling signal SMP1.

[0107] The charge stored in the second capacitor C2 can be transferred to the storage node SN by turning on the ninth transistor TR9 again through the second sampling signal SMP2.

[0108] The eleventh transistor TR11 can amplify the voltage of the storage node SN. The twelfth transistor TR12 can be turned on by the second selection signal SEL2, and the amplified voltage is output through the first column line CL11 as the third pixel signal PS3.

[0109] The second pixel signal PS2 and the third pixel signal PS3 are each converted into digital signals by an analog-to-digital converter circuit, and the converted digital signals can be converted into image signals corresponding to the first pixel circuit PIX1 by signal processing operations in the image signal processor.

[0110] The image sensor according to this disclosure can use the same capacitor used in the global shutter method when operating in the rolling shutter method. Therefore, the image sensor does not need to have a separate capacitor to improve the performance of the rolling shutter method, for example, to increase the electrostatic capacitance of the floating diffusion region FD. Thus, the performance of the image sensor can be improved within the same area, or the occupied area can be reduced while maintaining the performance of the image sensor.

[0111] Furthermore, although not shown separately, in some example embodiments, the image sensor according to this disclosure may shut off the fourth transistor TR4, the seventh transistor TR7, and the tenth transistor TR10 based on a third mode signal. For example, to optimize power consumption, the image sensor may operate with a rolling shutter method that does not use capacitors C1 and C2 in the extended floating diffusion region FD.

[0112] Figure 10 These are some example embodiments based on this disclosure. Figure 5 The circuit diagram of the first pixel circuit, PIX1. (Reference) Figure 10 The diagram illustrates some example embodiments where the tenth transistor TR10 is connected to the second node N2. Figure 10 The remaining components can be combined with Figure 6 Components with the same reference symbol correspond to each other.

[0113] For ease of explanation, the following ellipses and Figure 6 Repeated description.

[0114] The tenth transistor TR10 can be connected between the first node N1 and the second node N2.

[0115] Based on the first mode signal, i.e., in the global shutter method, the tenth transistor TR10 can be turned off by the second switch signal SW2, and the fourth transistor TR4 can be turned off by the third reset signal RS3. The charge of the floating diffusion node FD corresponding to the reset voltage can be stored in the first capacitor C1 through the seventh transistor TR7 and the storage node SN. The charge of the floating diffusion node FD corresponding to the pixel voltage can be stored in the second capacitor C2 through the seventh transistor TR7 and the storage node SN.

[0116] The readout operation based on the first mode signal can be combined with... Figure 5 The same applies to the first capacitor C1 and the second capacitor C2. The charge stored in the first capacitor C1 and the charge stored in the second capacitor C2 can be sequentially amplified by the eleventh transistor TR11 and can be output to the first column line CL11 as the first pixel signal through the twelfth transistor TR12.

[0117] Based on the second mode signal, i.e., in the rolling shutter method, the seventh transistor TR7 can be turned off by the first switch signal SW1, and the tenth transistor TR10 can be turned on by the second switch signal SW2. The fourth transistor TR4 can be turned on by the third reset signal RS3 to reset the first capacitor C1 and the second capacitor C2.

[0118] In this configuration, the charge overflowing from the first photodiode PD1 can be stored in the floating diffusion node FD, the first capacitor C1, and the second capacitor C2. Specifically, a first portion of the charge overflowing from the first photodiode PD1 can be transferred to the floating diffusion node FD, a second portion can be transferred to the first capacitor C1 sequentially through the tenth transistor TR10, the seventh transistor TR7, and the storage node SN, and a third portion can be transferred to the second capacitor C2 sequentially through the tenth transistor TR10, the seventh transistor TR7, and the storage node SN.

[0119] The readout operation based on the second-mode signal can be combined with... Figure 5 The same applies to the charge at the floating diffusion node FD. The voltage corresponding to the charge can be amplified by the fifth transistor TR5 and output as the second pixel signal to the second column line CL12 via the sixth transistor TR6. The voltage corresponding to the charge transferred to the first capacitor C1 and the second capacitor C2 can be amplified by the eleventh transistor TR11 and output as the third pixel signal to the first column line CL11 via the twelfth transistor TR12.

[0120] Figure 11 These are some example embodiments based on this disclosure. Figure 5 The circuit diagram of the first pixel circuit, PIX1. (Reference) Figure 11 The diagram shows some example embodiments in which the tenth transistor TR10 is connected to one end of the first capacitor C1. Figure 11 The remaining components can be combined with Figure 6 Components with the same reference symbol correspond to each other.

[0121] For ease of description, the following ellipses are omitted. Figure 6 Repeated description.

[0122] The tenth transistor TR10 can be connected to one end of the first node N1 and one end of the first capacitor C1 and the second capacitor C2. Below, some example embodiments of the tenth transistor TR10 being connected to one end of the first node N1 and the first capacitor C1 will be described.

[0123] Based on the first mode signal, that is, in the global shutter method, it can be combined with... Figure 10 Similarly, the charge of the floating diffusion node FD corresponding to the reset voltage is stored in the first capacitor C1. Furthermore, the charge of the floating diffusion node FD corresponding to the pixel voltage can be stored in the second capacitor C2.

[0124] The readout operation based on the first mode signal can be combined with... Figure 10 The same as in [the previous sentence].

[0125] Based on the second mode signal, i.e., in the rolling shutter method, the seventh transistor TR7 can be turned off by the first switch signal SW1, and the tenth transistor TR10 can be turned on by the second switch signal SW2. The fourth transistor TR4 can be turned on by the third reset signal RS3 to reset the first capacitor C1.

[0126] In this case, the first part of the charge overflowing from the first photodiode PD1 can be transferred to the floating diffusion node FD, and the second part can be transferred to the first capacitor C1 through the floating diffusion node FD and the tenth transistor TR10.

[0127] The readout operation based on the second mode signal is as follows. The voltage corresponding to the charge of the floating diffusion node FD can be amplified by the fifth transistor TR5 and output as the second pixel signal to the second column line CL12 through the sixth transistor TR6.

[0128] Furthermore, the voltage corresponding to the charge transferred to the first capacitor C1 can be amplified by the eleventh transistor TR11 and can be output as the third pixel signal to the first column line CL11 via the twelfth transistor TR12.

[0129] As referenced above Figure 5 , Figure 10 and Figure 11 The tenth transistor TR10, which is turned on / off depending on the first mode signal and the second mode signal, can be connected within the first pixel circuit PIX1 in various ways, and the scope of this disclosure is not limited thereto. All connections of the tenth transistor TR10 that can create a charge flow path between at least one of the first capacitor C1 and the second capacitor C2 and the floating diffusion node FD can be included within the scope of this disclosure.

[0130] refer to Figures 12 to 14 The document describes some example embodiments in which, in the rolling shutter method, both the second pixel signal PS2 and the third pixel signal PS3 are output through the second column line CL12.

[0131] Figure 12 These are some example embodiments based on this disclosure. Figure 5 The circuit diagram of the first pixel circuit, PIX1. (Reference) Figure 12 The first pixel circuit PIX1 also includes a thirteenth transistor TR13 connected between the storage node SN and the fourth node N4, and includes a gate for receiving the third switching signal SW3. Figure 12 The components can be respectively with Figure 6 Components with the same reference symbol correspond to each other.

[0132] For ease of description, the following ellipses are omitted. Figure 6 Repeated description.

[0133] The seventh transistor, TR7, is connected between the second node N2 and the fourth node N4. The gate terminal of the eleventh transistor, TR11, is connected to the fourth node N4. Figure 12 In some example embodiments shown, a thirteenth transistor TR13 is added and connected between the storage node SN and the fourth node N4.

[0134] When the thirteenth transistor TR13 is turned on by the third switch signal SW3 Figure 12 The first pixel circuit PIX1 has the same Figure 6The first pixel circuit PIX1 has the same structure and can operate in the same way.

[0135] Based on the first mode signal, i.e., in the global shutter method, the thirteenth transistor TR13 can be turned on by the third switch signal SW3. Therefore, the reset voltage stored in the first capacitor C1 can be read out through the first column line CL11. Furthermore, the pixel voltage stored in the second capacitor C2 can be read out through the first column line CL11.

[0136] Based on the second mode signal, i.e., in rolling shutter mode, the first pixel circuit PIX1 can operate as follows: The seventh transistor TR7 can be turned off, and the tenth transistor TR10 can be turned on. A first portion of the charge overflowing from the first photodiode PD1 can be transferred to the floating diffusion node FD, a second portion can be transferred to the first capacitor C1 via the floating diffusion node FD, the tenth transistor TR10, and the storage node SN, and a third portion can be transferred to the second capacitor C2 via the floating diffusion node FD, the tenth transistor TR10, and the storage node SN.

[0137] In the readout operation based on the second mode signal, the thirteenth transistor TR13 can be turned off to output the third pixel signal to the second column line CL12. This will be referenced below. Figure 13 Detailed description.

[0138] Figure 13 It describes the rolling shutter method. Figure 12 The image shows the readout of the first pixel circuit, PIX1. (Reference) Figure 13 This describes the readout path in the rolling shutter method when the thirteenth transistor TR13 is turned off by the third switch signal SW3.

[0139] For ease of description, the following ellipses are omitted. Figure 12 Repeated description.

[0140] In a readout operation based on the second mode signal (e.g., rolling shutter method readout), the thirteenth transistor TR13 can be turned off by the third switch signal SW3.

[0141] First, when the second transistor TR2 is turned off by the first reset signal RS1, the voltage corresponding to the charge of the floating diffusion node FD can be amplified by the fifth transistor TR5 and can be output to the second column line CL12 as the second pixel signal PS2 through the sixth transistor TR6.

[0142] Next, firstly, the second transistor TR2 can be turned on via the first reset signal RS1, the eighth transistor TR8 can be turned on again via the first sampling signal SMP1, and the ninth transistor TR9 can be turned on again via the second sampling signal SMP2. In this state, the charge stored in the first capacitor C1 and the second capacitor C2 is transferred to the floating diffusion node FD through the storage node SN and the second transistor TR2 (since the thirteenth transistor TR13 is turned off, the voltage of the storage node SN may not be amplified by the eleventh transistor TR11).

[0143] The voltage corresponding to the charge in the first capacitor C1 and the second capacitor C2 (e.g., the charge stored in the first capacitor C1 and the second capacitor C2 and then transferred to the floating diffusion node FD) can be amplified by the fifth transistor TR5. The amplified voltage can be output as the third pixel signal PS3 to the second column line CL12 through the turned-on sixth transistor TR6.

[0144] The following describes the detailed operation sequence of the readout operation of the second pixel signal PS2 and the third pixel signal PS3, which are sequentially output through the second column line CL12.

[0145] Figure 14 It describes the rolling shutter method. Figure 13 The timing diagram for the readout of the first pixel circuit PIX1. (Reference) Figure 14 This illustrates a method for describing signals based on a second mode passing through the same column line (e.g., Figure 13 The timing diagram of the operation of the second column line (CL12) sequentially outputting the second pixel signal PS2 and the third pixel signal PS3. Figure 14 The signals can be respectively with Figure 13 Signals with the same reference symbol correspond to each other.

[0146] In the following text, reference will be made to Figure 13 and Figure 14 Describe the read operation over time.

[0147] The first power supply voltage VDD1 can have a first voltage level V1 from the first time t1 to the second time t2 and from the eighth time t8 to the thirteenth time t13. Furthermore, the first power supply voltage VDD1 can have a second voltage level V2 from the second time t2 to the eighth time t8. The first voltage level V1 can be lower than the second voltage level V2.

[0148] The second power supply voltage VDD2 can have a third voltage level V3 from the first time t1 to the second time t2 and from the third time t3 to the thirteenth time t13. In addition, the second power supply voltage VDD2 can have a fourth voltage level V4 from the second time t2 to the third time t3.

[0149] The period from the first time t1 to the second time t2 can be called the reset period, the period from the second time t2 to the third time t3 can be called the exposure period, the period from the third time t3 to the eighth time t8 can be called the readout period of the second pixel signal PS2, and the period from the eighth time t8 to the thirteenth time t13 can be called the readout period of the third pixel signal PS3.

[0150] From the first time t1 to the second time t2, the transmission signal TG, the first reset signal RS1, the second reset signal RS2, and the third reset signal RS3 can be at a high level. Therefore, the second transistor TR2, the third transistor TR3, and the fourth transistor TR4 can be turned on at the first time t1, and the third transistor TR3 and the fourth transistor TR4 can be turned off at the second time t2. Therefore, the first pixel circuit PIX1 can be reset.

[0151] From the second time t2 to the third time t3, the first photodiode PD1 can receive light and convert the received light into corresponding charge. In this case, the charge generated in the first photodiode PD1 can be transferred to the floating diffusion node FD, the first capacitor C1, and the second capacitor C2 (e.g., similar to...). Figure 8 (Extended floating diffusion region). The charge of the photodiode PD can be transferred to at least one of the first capacitor C1 and the second capacitor C2, and the capacitor to which the charge is transferred can be determined depending on the first sampling signal SMP1 and the second sampling signal SMP2.

[0152] At the third time t3, the first selection signal SEL1 can change from low to high. While the first selection signal SEL1 is high, the sixth transistor TR6 can be turned on. In this case, the second column line CL12 can be turned on.

[0153] From the second time t2 to the fourth time t4, the second transistor TR2 can be turned on because the first reset signal RS1 is at a high level. At the fourth time t4, the first reset signal RS1 can change from a high level to a low level. Therefore, the second transistor TR2 can be turned off.

[0154] Between the fourth time t4 when the second transistor TR2 is turned off and the fifth time t5 when the transmission signal TG changes from low level to high level, the first pixel circuit PIX1 can output the first reset voltage V_RST1 of the second pixel signal PS2 corresponding to the voltage of the floating diffusion node FD through the second column line CL12.

[0155] In some example embodiments, the first pixel circuit PIX1 can read out the first reset voltage V_RST1 after a predetermined (or alternatively, desired or selected) time has elapsed since the second transistor TR2 was turned off at a fourth time t4. For example, the predetermined (or alternatively, desired or selected) time could be the circuit settling time.

[0156] From the fifth time t5 to the sixth time t6, the transmitted signal TG can have a high level.

[0157] At time t6, the transmission signal TG can change from high to low. In this case, the first transistor TR1 can be turned off.

[0158] Between the sixth time t6 and the seventh time t7, the first pixel voltage V_SIG1 of the second pixel signal PS2, which corresponds to the voltage of the floating diffusion node FD, can be output through the second column line CL12.

[0159] At time t7, the first reset signal RS1 can change from low to high. In this case, the second transistor TR2 can be turned on. In this case, the floating diffusion node FD can be electrically connected to the first capacitor C1 or the second capacitor C2 (e.g., a path through which charge can be transferred can be formed). The first reset signal RS1 can be high from time t7 to time t13, and therefore, the second transistor TR2 can also remain on.

[0160] At time t9, the transmission signal TG can change from low to high. From time t9 to time t10, the transmission signal TG can be at a high level. At time t10, the transmission signal TG can change from high to low. Therefore, the first transistor TR1 can be turned on at time t9 and then turned off at time t10.

[0161] Between the tenth time t10 and the eleventh time t11, the first pixel circuit PIX1 can read out the voltage corresponding to the charge transferred to the extended floating diffusion region (e.g., the charge transferred to the floating diffusion node FD, the first capacitor C1, and the second capacitor C2), as the second pixel voltage V_SIG2 of the third pixel signal PS3. Furthermore, since the first selection signal SEL1 is high, the first pixel circuit PIX1 can output the second pixel voltage V_SIG2 via the second column line CL12.

[0162] In some example embodiments, the first pixel circuit PIX1 can read out the second pixel voltage V_SIG2 after a predetermined (or alternatively, desired or selected) time has elapsed since the tenth time t10 when the first transistor TR1 is turned off. For example, the predetermined (or alternatively, desired or selected) time may be the circuit settling time.

[0163] At time eleven (t11), the second reset signal RS2 and the third reset signal RS3 can change from low to high. From time eleven (t11) to time twelfth (t12), the second reset signal RS2 and the third reset signal RS3 can each be at a high level. At time twelfth (t12), the second reset signal RS2 and the third reset signal RS3 can change from high to low. Therefore, the third transistor TR3 and the fourth transistor TR4 can be turned on at time eleven (t11) and turned off at time twelfth (t12). That is, the first capacitor C1 and the second capacitor C2 can be reset.

[0164] Between the twelfth time t12 and the thirteenth time t13, the first pixel circuit PIX1 can read the voltage of the floating diffusion node FD as the second reset voltage V_RST2 of the third pixel signal PS3. In this case, since the first selection signal SEL1 is high, the first pixel circuit PIX1 can output the second reset voltage V_RST2 through the second column line CL12.

[0165] In some example embodiments, during the time period when the first photodiode PD1 receives light, the second power supply voltage VDD2 may have a fourth voltage level V4 that is lower than the third voltage level V3, so that no leakage current occurs in the peripheral components of the second power supply terminal.

[0166] In some example embodiments, the third reset signal RS3 is high from the first time t1 to the second time t2 and from the eleventh time t11 to the twelfth time t12, enabling the fourth transistor TR4 to be turned on. In this case, the first voltage level V1 can be the same as the third voltage level V3.

[0167] Figure 15 This is a flowchart describing a method of operating an image sensor according to some example embodiments of the present disclosure. (Reference) Figure 15 This section will describe methods for operating an image sensor. An image sensor can be used with... Figure 1 The image sensor 100 is compatible.

[0168] In operation S110, the image sensor can determine whether to operate using the global shutter method or the rolling shutter method. When the image sensor determines to operate using the global shutter method, the image sensor can proceed to operation S121. Conversely, when the image sensor determines to operate using the rolling shutter method, the image sensor can proceed to operation S131.

[0169] In some example embodiments, the image sensor may select one of a global shutter method or a rolling shutter method according to a predetermined (or, alternatively, desired or selected) method.

[0170] In this scenario, when the global shutter method is selected, the image sensor can provide a first mode signal to the pixel circuitry. This first mode signal can correspond to a control signal that causes the pixel circuitry to operate using the global shutter method.

[0171] Conversely, when the rolling shutter method is selected, the image sensor can provide a second mode signal to the pixel circuitry. This second mode signal can correspond to a control signal that causes the pixel circuitry to operate in the rolling shutter method.

[0172] In operation S121, the image sensor can store the charge of the floating diffusion region in the storage region.

[0173] In some example embodiments, the storage area may include a first capacitor and a second capacitor.

[0174] For example, an image sensor can store the charge corresponding to the reset voltage in a first capacitor and the charge corresponding to the pixel voltage in a second capacitor.

[0175] In operation S122, the image sensor can convert the voltage corresponding to the charge stored in the storage area into a first pixel signal.

[0176] In operation S131, the image sensor can transfer at least some of the charge from the photodiode to the storage area.

[0177] In some example embodiments, the charge overflowing from the photodiode can be transferred to the floating diffusion region and the storage region.

[0178] In some example embodiments, the storage area may include a first capacitor and a second capacitor, and in operation S131, the image sensor may transfer charge to at least one of the first capacitor and the second capacitor.

[0179] In some example embodiments, the image sensor may use a first capacitor and a second capacitor as an extended floating diffusion region.

[0180] In operation S132, the image sensor can convert the voltage corresponding to the charge of the floating diffusion region into a second pixel signal.

[0181] In operation S133, the image sensor can convert the voltage corresponding to the charge of the extended floating diffusion region into a third pixel signal.

[0182] In some example embodiments, the image sensor can output a first pixel signal via a first column line and a second pixel signal via a second column line. In this case, a third pixel signal can be output via either the first or the second column line.

[0183] In some example embodiments, the image sensor can sequentially output second pixel signals and third pixel signals via a second column line.

[0184] According to some example embodiments of this disclosure, an image sensor using a hybrid shutter driving method with a shared storage region is provided.

[0185] Furthermore, since the storage area used to store signals during global shutter operation can be used to expand the capacitance of the floating diffusion region during rolling shutter operation, an image sensor is provided that reduces size, cost, and power consumption while maintaining performance, or improves the performance of rolling shutter operation while maintaining the same size.

[0186] The above description describes detailed embodiments for carrying out this disclosure. Embodiments that simply modify or readily modify the design, as well as some of the example embodiments described above, may be included in this disclosure. Furthermore, techniques that can be readily modified and implemented using the above embodiments may be included in this disclosure. Therefore, the scope of this disclosure should not be limited to the above embodiments and should be defined not only by the claims described later but also by claims equivalent to those of this disclosure.

Claims

1. An image sensor, comprising: First photodiode; Second photodiode; The storage area includes a first capacitor and a second capacitor; The first pixel signal generator circuit is configured to convert a voltage corresponding to the charge of the first photodiode stored in the storage area into a first pixel signal based on a first mode signal; and The second pixel signal generator circuit is configured to convert the voltage corresponding to the charge of the first photodiode into a second pixel signal based on a second mode signal. Specifically, based on the first mode signal, the pixel signal corresponding to the first photodiode and the pixel signal corresponding to the second photodiode are read out simultaneously. Specifically, based on the second mode signal, the pixel signal corresponding to the first photodiode and the pixel signal corresponding to the second photodiode are read out sequentially, and The first pixel signal generator circuit is configured to transfer at least a portion of the charge of the first photodiode to the storage region based on the second mode signal.

2. The image sensor according to claim 1, wherein, Based on the second mode signal, the first pixel signal generator circuit is configured to form a charge transfer path between at least one of the first capacitor and the second capacitor and the floating diffusion region, and to use the storage region as an extended electrostatic capacitance of the floating diffusion region.

3. The image sensor according to claim 1, wherein, Based on the second mode signal, the second pixel signal generator circuit is configured to convert the voltage corresponding to the charge of the floating diffusion region into the second pixel signal, and Based on the second mode signal, the first pixel signal generator circuit is configured to convert the voltage corresponding to the charge of the storage region into a third pixel signal.

4. The image sensor according to claim 3, further comprising: An analog-to-digital converter circuit is configured to convert the first pixel signal, the second pixel signal, and the third pixel signal into a first digital signal, a second digital signal, and a third digital signal, respectively. The first column line is connected to the first pixel signal generator circuit; and The second column of lines is connected to the second pixel signal generator circuit, and Wherein, the first pixel signal generator circuit is configured to output the third pixel signal to the analog-to-digital converter circuit through the first column line, and The second pixel signal generator circuit is configured to output the second pixel signal to the analog-to-digital converter circuit via the second column line.

5. The image sensor according to claim 3, further comprising: An analog-to-digital converter circuit is configured to convert the second pixel signal and the third pixel signal into a second digital signal and a third digital signal, respectively. and An image signal processor is configured to generate an image signal corresponding to the first photodiode based on signal processing operations of the second digital signal and the third digital signal.

6. The image sensor according to claim 1, wherein, Based on the second mode signal, the second pixel signal generator circuit is configured as follows: During the first time period, the voltage corresponding to the charge of the floating diffusion region in the charge of the first photodiode is converted into the second pixel signal; as well as During a second time period following the first time period, the voltage corresponding to the charge of the storage region in the charge of the first photodiode is converted into a third pixel signal.

7. The image sensor according to claim 6, further comprising: An analog-to-digital converter circuit is configured to convert the first pixel signal, the second pixel signal, and the third pixel signal into a first digital signal, a second digital signal, and a third digital signal, respectively. and The second column of lines is connected to the second pixel signal generator circuit, and The second pixel signal generator circuit is configured to output the second pixel signal and the third pixel signal to the analog-to-digital converter circuit via the second column line.

8. The image sensor according to claim 1, further comprising: An analog-to-digital converter circuit is configured to convert the first pixel signal into a first digital signal using a correlated double sampling method.

9. The image sensor according to claim 8, wherein, Based on the first mode signal, the first pixel signal generator circuit is configured to store the charge corresponding to the reset voltage in the first capacitor and the charge corresponding to the pixel voltage in the second capacitor.

10. The image sensor according to claim 1, wherein, The first mode signal and the second mode signal are activated at different times.

11. The image sensor according to claim 1, wherein, The second pixel signal generator circuit includes: A first transistor is connected between the first photodiode and the floating diffusion node, and has a gate configured to receive a transmitted signal. A second transistor is connected between the floating diffusion node and the first node, and has a gate configured to receive a first reset signal; A third transistor is connected between the first node and the first power supply terminal and has a gate configured to receive a second reset signal. A fourth transistor, connected between the first and second power supply terminals, and having a gate configured to receive a third reset signal; and The tenth transistor, connected between the first node and the memory node, has a gate configured to receive a second switching signal, and At least one of the first capacitor and the second capacitor is connected in parallel between the storage node and the second power supply terminal.

12. The image sensor according to claim 11, wherein, The tenth transistor is turned off based on the second switching signal corresponding to the first mode signal, and the tenth transistor is turned on based on the second switching signal corresponding to the second mode signal.

13. An image sensor, comprising: First capacitor; Second capacitor; The first transistor is connected between the photodiode and the floating diffusion node, and has a gate configured to receive a transmitted signal; A second transistor is connected between the first node and the floating diffusion node, and has a gate configured to receive a first reset signal; A third transistor is connected between the first node and the first power supply terminal and has a gate configured to receive a second reset signal. A fourth transistor is connected between the first power supply terminal and the second power supply terminal, and has a gate configured to receive a third reset signal; The fifth transistor is connected between the third power terminal and the second node, and has a gate connected to the floating diffusion node; The sixth transistor is connected between the second node and the first column line and has a gate configured to receive a selection signal; The seventh transistor is connected between the second node and the memory node and has a gate configured to receive a switching signal; An eighth transistor is connected between the storage node and one end of the first capacitor and has a gate configured to receive a first sampling signal; A ninth transistor is connected between the storage node and one end of the second capacitor, and has a gate configured to receive a second sampling signal; and A tenth transistor, connected between the first node and the second node, or between the first node and the memory node, and having a gate configured to receive a second switching signal, and The other end of the first capacitor and the other end of the second capacitor are respectively connected to the second power supply terminal.

14. The image sensor according to claim 13, wherein, Based on the first mode signal, the fourth transistor and the tenth transistor are turned off, and the seventh transistor is turned on.

15. The image sensor according to claim 13, wherein, Based on the second mode signal, the seventh transistor is turned off and the tenth transistor is turned on.

16. The image sensor according to claim 13, wherein, Based on the first mode signal, the fourth and tenth transistors are turned off, and the seventh transistor is turned on. Specifically, based on the second mode signal, the seventh transistor is turned off, and the tenth transistor is turned on, and The first mode signal and the second mode signal are activated at different times.

17. The image sensor according to claim 13, wherein, Based on the second mode signal, the seventh transistor is turned off, and the tenth transistor is turned on, and Based on the second mode signal, the second transistor is turned on and configured to increase the capacitance of the floating diffusion node.

18. An image sensor, comprising: The storage area includes a first capacitor and a second capacitor. The storage area is configured as follows: The charge overflowing from the photodiode is stored using a global shutter method, and The charge overflowing from the photodiode is transferred to at least one of the first capacitor and the second capacitor and the floating diffusion region using a rolling shutter method.

19. The image sensor according to claim 18, wherein, The storage region is configured to form a charge transfer path between at least one of the first capacitor and the second capacitor and the floating diffusion region based on the rolling shutter method, and the storage region is configured to serve as an extended electrostatic capacitance of the floating diffusion region.

20. The image sensor according to claim 18, wherein, The image sensor is configured to, In the global shutter method: The voltage corresponding to the charge stored in the first capacitor is converted into a reset voltage for the first pixel signal; as well as The voltage corresponding to the charge stored in the second capacitor is converted into the pixel voltage of the first pixel signal, and In the rolling shutter method: The voltage corresponding to the charge of the floating diffusion region that was not transferred to the storage region is converted into a second pixel signal; as well as The voltage corresponding to the charge transferred to the storage region is converted into a third pixel signal.

Images