Processing method of super-flat silicon wafer and silicon wafer

Abstract

The invention relates to the technical field of semiconductor manufacturing, and discloses a processing method of a super-flat silicon wafer and the silicon wafer. The method comprises the following steps: firstly, carrying out a double-sided polishing process, forming a silicon wafer with consistent bowl-shaped morphology by adjusting parameters such as a gap of a polishing pad and back pressure of the silicon wafer, and controlling the overall flatness of the silicon wafer to be 60-120nm; according to the method, the measurement result of the overall flatness of the silicon wafer is graded, in the chemical mechanical polishing process, machining is conducted through a multi-area pressure formula according to the grading result, the pressure formula controls the pressure intensity of each pressure area of a polishing head, the removal amount of the edge of the silicon wafer is larger than that of a center area, and therefore accurate correction of the silicon wafers with different initial shapes is achieved. Through the combination of morphology control construction, grading identification and multi-formula customized correction, the processing problem that the overall morphology of the silicon wafer is inconsistent is effectively solved, the processing yield of the super-flat silicon wafer is improved to 50% or above from about 0.5% or below, and the high yield of the super-flat silicon wafer is achieved.

Description

A method for processing ultra-flat silicon wafers and the silicon wafer itself. Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, specifically to a processing method and a silicon wafer for an ultra-flat silicon wafer, particularly to an ultra-flat silicon wafer with a global flatness (GBIR) of <60nm. Background Technology

[0002] With the development of advanced semiconductor processes (such as 5 nanometers and below), chip manufacturing has placed extremely stringent requirements on the global back surface referenced ideal plane range (GBIR) and the site front surface referenced least sQuares range (SFQR) of silicon substrates. Among these, the demand for ultra-flat silicon wafers (usually referring to global back surface referenced ideal plane range < 60nm) has increased dramatically.

[0003] Currently, the standardized process flow for 12-inch polished wafers typically employs a double-sided polishing (DSP) followed by single-sided chemical mechanical polishing (CMP). In existing technologies, especially in silicon wafer development for advanced processes, there exists a prevalent and deeply ingrained technical bias: the belief that the core optimization goal of the DSP process should prioritize ensuring optimal surface flatness (SFQR) to meet the extreme requirements of uniform topography within minute areas in processes such as photolithography. Guided by this bias, process developers tend to use a single, fixed recipe in the DSP stage designed to minimize SFQR.

[0004] However, the inventors' in-depth research revealed that this "prioritizing SFQR optimization" strategy often sacrifices control over the overall silicon wafer topography (GBIR) consistency. Due to inherent fluctuations in silicon wafer material, stress distribution, and equipment conditions, a DSP process that prioritizes optimizing local SFQR may achieve good local flatness in some wafers, but the overall topography (such as bowl-shaped or saddle-shaped) of the processed wafers exhibits significant inconsistencies and unpredictability. Specifically, this manifests as huge differences in GBIR values ​​and their radial profiles between different wafers, and even between wafers in the same batch.

[0005] The inconsistency in the overall morphology of the silicon wafers after DSP (Digital Semiconductor Processing) presents a fundamental challenge to the subsequent critical CMP (Chemical Mechanical Polishing) correction process. Existing CMP processes typically employ a fixed, single-pressure formulation. When a fixed CMP removal profile is applied to a batch of silicon wafers with varying initial global morphologies and discrete GBIR (GBIR) values ​​(typically scattered across a wide range of 100nm to 300nm), its correction effect is inevitably limited and random. As a result, the proportion of silicon wafers ultimately meeting the ultra-flat GBIR < 60nm specification is extremely low, with a yield typically around 0.5%, failing to meet the economic requirements for large-scale mass production.

[0006] Therefore, there is an urgent need in this field for a new method that can overcome the above-mentioned technical biases and solve the problem of global morphology consistency control of silicon wafers from a system level, so as to achieve high yield and stable production of ultra-flat silicon wafers. Summary of the Invention

[0007] The purpose of this invention is to overcome the biases and shortcomings of existing technologies and provide a method for processing ultra-flat silicon wafers and the resulting ultra-flat silicon wafers. This method constructs a topography feedback control loop, abandoning the traditional priority optimization SFQR, and builds a silicon substrate flatness control model that achieves initial topography uniformity in the early stage and precise correction by grading and partitioning in the later stage, thereby achieving an order-of-magnitude improvement in the yield of ultra-flat silicon wafer processing.

[0008] To achieve the above-mentioned objectives, the present invention adopts the following technical solution. A processing method for ultra-flat silicon wafers, the core of which lies in constructing a feedback control system that achieves high-yield ultra-flat silicon wafers through morphology stabilization, parameter digitization and classification, and finally, customized classification and precise regional correction. First, a stable and predictable initial morphology is actively shaped in the DSP stage. Then, "feedforward" identification is performed through measurement classification. Finally, in the CMP stage, a preset "feedback" correction formula that precisely matches the identification results is invoked to achieve active compensation polishing of the global morphology. Specifically, the following steps are performed sequentially: Step 1, Active Formation of Initial Morphology: The silicon wafer undergoes double-sided polishing (DSP) processing. In this step, the traditional parameter settings aimed at optimizing a single local flatness (SFQR) are abandoned, and instead, obtaining a highly consistent standard bowl-shaped global morphology is prioritized as the control objective. By coordinating and adjusting two key process parameters—polishing pad gap (GAP) and silicon wafer back pressure (SK)—the overall deformation and material removal distribution of the silicon wafer are controlled. This results in the silicon wafer processed by DSP not only forming a standard bowl-shaped morphology where the central region is slightly lower than the edge region (as shown in Figure 1, which is a schematic diagram of the ideal bowl-shaped morphology of the silicon wafer after DSP processing in this embodiment of the invention), but also stably controlling its Global Flatness Indicator (GBIR) value within a preset, relatively wide first range.min to GBIR max within the range of, where 60 ≤ GBIR min < GBIR max ≤ 140 nm to ensure a relatively consistent initial morphology; preferably, the GBIR value of the silicon wafer after DSP processing is between 60 nm and 120 nm. This step aims to provide a batch of silicon wafers with consistent initial morphological characteristics for subsequent processing, laying a predictable and consistent morphological foundation for subsequent differential precision correction.

[0009] Step 2, Quantitative identification and grading of morphological parameters: After completing the active shaping step of the initial morphology and before performing the final chemical mechanical polishing (CMP), a geometric parameter measurement session with 100% full inspection is introduced. A non-contact optical morphology measuring instrument is used to quantitatively obtain the global flatness (GBIR) value of each silicon wafer. Subsequently, according to the different GBIR values, the silicon wafers are sorted into different CMP process paths. Specifically, multiple grading intervals are set based on the magnitude of the GBIR value. For example, silicon wafers with GBIR values within the range of 60 nm to 120 nm are divided into at least two, preferably four consecutive and non-overlapping grades in ascending order of the numerical value. For example: The first grade (Grade A): GBIR value is in the range of 60 nm ≤ GBIR ≤ 75 nm; The second grade (Grade B): GBIR value is in the range of 75 nm < GBIR ≤ 90 nm; The third grade (Grade C): GBIR value is in the range of 90 nm < GBIR ≤ 105 nm; The fourth grade (Grade D): GBIR value is in the range of 105 nm < GBIR ≤ 120 nm.

[0010] This grading step realizes the quantification and classification of the initial morphological differences of the silicon wafers, providing precise input conditions for subsequent customized processing.

[0011] Step 3, Customized morphological correction based on grading: This step is the key to achieving ultra-flat silicon wafers. A chemical mechanical polishing (CMP) device equipped with a polishing head with multi-region independently controllable pressure is used. For each specific grade determined in the above grading step, a unique multi-region pressure recipe is preset and stored.

[0012] Each of the pressure recipes defines a specific combination of pressures applied to multiple pressure control zones (such as zones Z5 to Z1) from the central region to the edge region of the polishing head. The common feature of all pressure recipes is that the set pressure values increase from the central region to the edge region of the polishing head, so that the material removal rate of the silicon wafer during the CMP process gradually increases from the center to the edge, realizing targeted compensating polishing for the standard bowl-shaped morphology.

[0013] Furthermore, for wafers with higher initial GBIR values ​​(i.e., more pronounced bowl-shaped morphology), the pressure formulation applied to the edge region of the polishing head exerts a higher pressure than the formulation used for wafers with lower initial GBIR values. For example, the fourth pressure formulation designed for fourth-grade (D-grade) wafers has a higher set pressure in the outermost edge zone (Z1) than the first pressure formulation designed for first-grade (A-grade) wafers in the corresponding edge zone. This differentiated pressure setting results in differentiated edge removal, ensuring that wafers with different initial morphologies can be corrected to the same ultra-flat specification with GBIR < 60 nm.

[0014] The present invention also provides an ultra-flat silicon wafer prepared according to the above processing method, wherein the ultra-flat silicon wafer is a polished silicon wafer with a GBIR value of less than 60nm, especially a large-size polished silicon wafer of 12 inches.

[0015] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects: The present invention actively compensates for the fluctuations of materials and previous processes through the control logic of "morphology shaping - identification and classification - classification and partitioning multi-formula customization and correction", which solves the fundamental problem that traditional fixed formula processes cannot cope with morphological differences.

[0016] The technical effect is improved by orders of magnitude: This method increases the processing yield of ultra-flat silicon wafers from less than 1% to more than 50%, making large-scale and economical production of ultra-flat silicon wafers possible.

[0017] Synergistic effect of front and back processes: The "stability" of step 1 is the premise of effective "grading" in step 2, and the "precise grading" of step 2 is the basis for achieving "precise correction" in step 3. The three constitute an organic whole, producing a synergistic effect far exceeding the simple superposition of each part. Attached Figure Description

[0018] Figure 1 is a schematic diagram of the ideal bowl-shaped morphology of the silicon wafer after DSP processing in various embodiments of the present invention.

[0019] Figure 2 shows the pressure response curves of the multi-zone adjustable pressure polishing head used in the CMP steps of various embodiments of the present invention. In the figure, the horizontal axis "radial position of silicon wafer" refers to the distance from the center of the silicon wafer; the vertical axis "removal amount" refers to the amount of material removed from the surface of the silicon wafer by polishing; the title "Pressure Response Curve" refers to the pressure response curve of the polishing head area.

[0020] Figure 3 is a comparison of the radial standardized removal curves of silicon wafers corresponding to four different CMP pressure formulations in Example 1 of the present invention. In the figure, "Recipe 1", "Recipe 2", "Recipe 3" and "Recipe 4" refer to "first pressure formulation", "second pressure formulation", "third pressure formulation" and "fourth pressure formulation", respectively.

[0021] Figure 4 Schematic diagram of the morphology of the silicon wafer after CMP processing in Embodiment 1 of the present invention. Specific Embodiments

[0022] The present invention will be described in detail below with reference to the accompanying drawings and embodiments. The following embodiments are provided to better understand the present invention and are not intended to limit its protection scope.

[0023] Embodiment 1

[0024] In this embodiment, the method for preparing a super-flat silicon wafer based on topography grading and multi-formula pressure control of the present invention is used to polish the silicon wafer. The goal of this embodiment is to process a 12-inch (300 mm) super-flat silicon wafer, and its final GBIR value needs to be less than 60 nm. The specific steps are as follows: Step 1, DSP processing and topography control: Prepare the silicon wafer processed by the previous process, and the previous process refers to: slicing, grinding, chamfering and cleaning. Use a double-sided polishing machine to perform double-sided polishing (DSP) on the silicon wafer. When adjusting the GAP and SK values of the DSP machine to make the output pressure of the platen within the range of UPAC: 28 - 30 bar and LPAC: 0.83 - 0.87 bar, it can ensure that the polished silicon wafer has a standard bowl-shaped morphology and GBIR < 120 nm. As shown in Figure 1, it is a schematic diagram of the ideal bowl-shaped morphology of the silicon wafer obtained after DSP processing in each embodiment of the present invention. The key to this step is to adjust the process parameters of the polishing pad gap (GAP) and the silicon wafer back pressure (SK), abandoning the traditional idea of only pursuing the optimal value of a single index, and instead giving priority to ensuring that the silicon wafer forms a stable and consistent standard bowl-shaped morphology. At this stage, the consistency of the bowl-shaped morphology is much more important than the specific value of GBIR because it is the basis for subsequent precise compensation.

[0025] Step 2, geometric parameter testing and grading: After the DSP process, use a high-precision silicon wafer morphology measuring instrument. In this embodiment, KLA Surfscan is used to test the geometric parameters of each silicon wafer, and 100% full inspection is adopted to obtain its GBIR value. According to the GBIR measurement results, the silicon wafers are accurately divided into four grades: The first grade (Grade A): The GBIR value is in the range of 60 nm ≤ GBIR ≤ 75 nm; The second grade (Grade B): The GBIR value is in the range of 75 nm < GBIR ≤ 90 nm; The third grade (Grade C): The GBIR value is in the range of 90 nm < GBIR ≤ 105 nm; The fourth grade (Grade D): The GBIR value is in the range of 105 nm < GBIR ≤ 120 nm.

[0026] Step 3, Customized CMP Processing (Core Invention Point) This step is crucial for achieving ultra-flat silicon wafers. In this step, CMP processing employs a multi-zone adjustable polishing head. By adjusting the output pressure of each zone of the polishing head, different radial removal curves of the silicon wafer can be obtained, ensuring that the removal amount gradually increases from the center to the edge of the silicon wafer. The principle is based on the equipment characteristics shown in Figure 2. Figure 2 is a pressure response curve of the multi-zone adjustable pressure polishing head used in the CMP step of various embodiments of the present invention. The figure shows the effect of applying high pressure (Z1 high pressure, Z2 high pressure, Z3 high pressure, Z4 high pressure, Z5 high pressure) and low pressure (Z1 low pressure, Z2 low pressure, Z3 low pressure, Z4 low pressure, Z5 low pressure) to different radial positions of the silicon wafer (i.e., the "pressure response" characteristics of the equipment) when each zone (a total of 5 zones, Z1, Z2, Z3, Z4, Z5) of the AMAT multi-zone polishing head used in this embodiment is applied individually.

[0027] Based on the aforementioned "pressure response" characteristics of the CMP equipment, four different pressure recipes were designed. Each pressure recipe corresponds to a different GBIR setting in step two. Each setting's recipe progressively increases the edge removal rate, and the increase in edge removal rate must be differentiated from the corresponding setting. Specific parameters are shown in the table below (pressure unit: psi):

[0028] Applying the pressure formulas from the table above to the polishing head results in four different radial removal curves, as shown in Figure 3. It can be seen that from Recipe 1 to Recipe 4, the relative removal rate (the increase in edge removal amount) at the silicon wafer edge (>100mm from the center) increases significantly. Specifically, Recipe 1 shows a slight increase in edge removal, used to correct the flattest A-grade silicon wafers, avoiding overcorrection. Recipe 4 shows the largest edge removal, used to forcefully correct the most prominent bowl-shaped D-grade silicon wafers, effectively removing the "raised" edges and making the overall surface flatter.

[0029] The graded silicon wafers (A, B, C, and D) were processed using CMP recipes 1, 2, 3, and 4, respectively. Figure 4 shows the resulting wafer morphology. As can be seen, by selecting the appropriate CMP recipe, the wafer edges changed from a raised shape to a collapsed shape, and the lowest point at the edge was not lower than the lowest point at the center, ensuring the minimum GBIR value. The statistical results after processing are as follows: the final GBIR of the grade A silicon wafer can be reduced to approximately 37.18nm.

[0030] B-grade silicon wafers can ultimately achieve a GBIR of approximately 43.37nm.

[0031] C-grade silicon wafers can ultimately achieve a GBIR of approximately 49.88nm.

[0032] The final GBIR of D-grade silicon wafers can be reduced to approximately 56.62nm.

[0033] All silicon wafers processed by the method in this embodiment consistently achieve a final GBIR value of less than 60nm, meeting the requirements for ultra-flat silicon wafers. The overall yield is improved from approximately 0.5% using traditional methods to 55%~65%, demonstrating the remarkable effectiveness of this invention.

[0034] Simultaneously, the local flatness (SFQR) and (ESFQR) of the aforementioned silicon wafers after CMP processing were tested. The average SFQR was 16.22nm (26*8mm, EE3mm), and the average ESFQR was 14.36nm (72 sectors@15mm), both showing improvement compared to the average SFQR of 20.28nm and the average ESFQR of 17.71nm after conventional processing. This is because although this processing method prioritizes stable GBIR values ​​during the DSP stage, it maintains a smaller GBIR while ensuring the wafer edges remain flat and do not curl, resulting in a smaller local flatness compared to conventional processing. In the CMP stage, the need to reduce GBIR and the higher edge pressure lead to wafer edge curling, causing some deterioration in local flatness. However, due to the precise control provided by graded processing, the degree of curling is manageable, and the parameter deterioration is limited. Ultimately, the statistical data still outperforms conventional processing.

[0035] Meanwhile, the processing method of this ultra-flat silicon wafer also provides ideas for the processing of silicon wafers with ultra-small local flatness requirements. The aforementioned DSP processing method and grading method remain unchanged. Only the pressure distribution curve needs to be adjusted in the CMP processing stage to reduce GBIR while ensuring that the edges do not curl (as shown in Figure 4, the edges are still in a raised state). This ensures that the SFQR value is as small as possible, making it possible to mass-produce products with SFQR and ESFQR less than 10nm.

[0036] Example 2

[0037] This embodiment employs a simplified and efficient processing method based on two-level partitioning. For certain production lines with high requirements for cost and control efficiency, a simplified partitioning strategy can be adopted. The specific steps are as follows: Step 1, DSP processing: Same as in Embodiment 1, the silicon wafer to be processed is a 12-inch silicon wafer that has undergone previous processes such as slicing, grinding, chamfering and cleaning. In this step, the silicon wafer is controlled to form a standard bowl-shaped morphology with GBIR of 60-120nm.

[0038] Step 2, Geometric Parameter Testing and Grading: In this embodiment, the silicon wafers are divided into only two grades: Low grade (L grade): GBIR value is between 60 nm and 90 nm; High grade (H grade): GBIR value is between 90 nm and 90 nm. <GBIR ≤ 120 nm。

[0039] Step 3, CMP processing: The same CMP equipment is used as in Example 1. Therefore, based on the equipment pressure response characteristics shown in Figure 2, two pressure formulations are designed for L and H respectively. The design principle is still that the pressure increases from the center to the edge, and the edge pressure (Z1 zone) of the H formulation is higher than that of the L formulation in this zone.

[0040] L-grade formula: Z5=1.0psi, Z4=1.04psi, Z3=1.08psi, Z2=1.13psi, Z1=2.54psi; H-grade formula: Z5=1.0psi, Z4=1.08psi, Z3=1.18psi, Z2=1.23psi, Z1=2.88psi.

[0041] After processing using this method, the final GBIR of both L-grade and H-grade silicon wafers can be corrected to <60nm. Although the overall yield (approximately 50%) is slightly lower than the four-grade classification in Example 1, it is still a significant improvement compared to the 0.5% yield of the traditional fixed-formula method, proving that even with simplified classification, the method of this invention can still achieve significantly better results than traditional technologies.

[0042] Example 3

[0043] This embodiment employs a more refined grading system to meet the ultra-high yield (>70%) requirement of a specific customer for ultra-flat silicon wafers with a GBIR <50nm. The implementation steps are as follows.

[0044] DSP fabrication: Same as in Example 1, the distribution range of GBIR is narrowed to 60-120nm to ensure the consistency of the initial morphology.

[0045] Geometric parameter testing and grading: More refined six-grading: Grade 1 (60-70nm), Grade 2 (70-80nm), Grade 3 (80-90nm), Grade 4 (90-100nm), Grade 5 (100-110nm), Grade 6 (110-120nm).

[0046] CMP processing: Six pressure gradient formulations, divided into Z1 to Z5 zones, were designed for each gear level. The Z1 zone pressures for gears 1 to 6 were set as follows: 2.40 psi, 2.53 psi, 2.66 psi, 2.80 psi, 2.92 psi, and 3.05 psi, respectively. This embodiment achieves "micron-level" correction of the morphology through more precise matching, enabling accurate control of edge collapse after processing.

[0047] Through the more refined graded matching process in this embodiment, more than 60% of the silicon wafers finally meet the stringent requirement of GBIR < 50nm, and the overall yield of meeting GBIR < 60nm is improved to over 75%.

[0048] It should be noted that the specific pressure parameters in the above embodiments are merely examples. Those skilled in the art can make adaptive adjustments based on the actual equipment model, polishing fluid type, and other conditions, while adhering to the core inventive concept of "gradually increasing pressure from the center area to the edge area, and using a recipe with higher edge pressure for silicon wafers with larger initial GBIR." All such adjustments should fall within the protection scope of this invention.

[0049] The above embodiments are intended to illustrate the essential content of the present invention, but are not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the essence and scope of protection of the present invention.

Claims

1. A method for processing ultra-flat silicon wafers, characterized in that, Including the following steps: Step S1: Perform double-sided polishing (DSP) on the incoming silicon wafer. Adjust the process parameters to form a bowl-shaped morphology on the silicon wafer, and control the global flatness (GBIR) of the double-sided polished silicon wafer within the GBIR range. min To GBIR max Within the range; where 60≤GBIR min <GBIR max ≤140nm; The incoming silicon wafer refers to the wafer to be polished after at least the cutting and grinding process; Step S2, measure the geometric parameters of the silicon wafer after the processing in step S1, and divide the silicon wafer into at least two grades according to the measured GBIR value; Step S3, according to the graded results of the silicon wafer, perform chemical mechanical polishing (CMP) processing using the corresponding multi-zone pressure formula; The multi-zone pressure formula refers to: by controlling the multi-zone polishing head, making the pressure of the polishing head in each zone different, so that the amount of material removed at the edge of the silicon wafer is greater than that in the center area, so as to correct the bowl-shaped morphology, and finally make the silicon wafer meet the requirements of an ultra-flat silicon wafer after the CMP processing, that is, the GBIR value of the silicon wafer is less than 60nm.

2. The processing method for ultra-flat silicon wafers according to claim 1, characterized in that, In the step S3, for the grading of the silicon wafers, silicon wafers of different grades are matched with different multi-region pressure recipes for the CMP processing; and for the grades with the GBIR values increasing from small to large, the edge removal capabilities of the matched multi-region pressure recipes also increase correspondingly.

3. The processing method for ultra-flat silicon wafers according to claim 2, characterized in that, The global flatness GBIR of the double-sided polished silicon wafers is controlled within 60 nm to 120 nm.

4. The processing method for ultra-flat silicon wafers according to claim 3, characterized in that, In the step S2, the silicon wafers are divided into four grades according to the GBIR values: Grade A: 60 nm ≤ GBIR ≤ 75 nm; Grade B: 75 nm < GBIR ≤ 90 nm; Grade C: 90 nm < GBIR ≤ 105 nm; Grade D: 105 nm < GBIR ≤ 120 nm.

5. The method for processing ultra-flat silicon wafers according to claim 4, characterized in that, In the step S3, for the silicon wafers of grades A, B, C, and D, the first pressure recipe, the second pressure recipe, the third pressure recipe, and the fourth pressure recipe with increasing edge removal capabilities are respectively adopted.

6. The method for processing ultra-flat silicon wafers according to claim 5, characterized in that, The multi-zone polishing head has at least five independent pressure control zones distributed from the center to the edge, namely Z5, Z4, Z3, Z2, and Z1; the first pressure recipe to the fourth pressure recipe all satisfy that the set pressure gradually increases from the Z5 zone to the Z1 zone.

7. The method for processing ultra-flat silicon wafers according to claim 6, characterized in that, The set pressure of the fourth pressure recipe in the Z1 zone is greater than the set pressure of the first pressure recipe in the Z1 zone.

8. The method for processing ultra-flat silicon wafers according to claim 1, characterized in that, In the step S1, the adjusted process parameters include the polishing pad gap GAP and the silicon wafer back pressure SK.

9. The method for processing ultra-flat silicon wafers according to claim 1, characterized in that, The ultra-flat silicon wafer processed by the method is a 12-inch silicon wafer.

10. The method for processing ultra-flat silicon wafers according to claim 1, characterized in that, After being processed by the method, the processing yield of the ultra-flat silicon wafer with a GBIR value less than 60 nm reaches more than 50%.

11. A silicon wafer, characterized in that, The silicon wafer is an ultra-flat silicon wafer prepared by the processing method according to any one of claims 1-10, and the GBIR value of the silicon wafer is less than 60 nm.

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