MVDR beam forming FPGA structure based on multi-mode systolic array and implementation method

Abstract

The invention discloses an MVDR beam forming FPGA structure based on a multi-mode systolic array and an implementation method. The FPGA structure comprises a data acquisition module used for obtaining a sampling matrix of a floating point type; the FSM scheduling module is used for performing scheduling control on the multi-port storage RAM, the multi-mode calculation module and the data stream; the multi-mode calculation module comprises a division unit, a negation unit, a delay unit, a cache unit and a systolic array unit formed by N * N PE units, and is used for performing covariance matrix solving, LDL decomposition, triangular matrix and diagonal matrix inversion and calculating an optimal weight according to the solved inverse matrix; each PE unit is used for carrying out floating point complex number multiplication and floating point complex number accumulation operation on input data; and the multi-port memory RAM is provided with an X-dimensional read port and a Y-dimensional read / write port. The resource overhead is small, and the real-time performance and the hardware cost can be both considered.

Description

FPGA Structure and Implementation Method for MVDR Beamforming Based on Multi-Mode Pulsating Array Technical Field

[0001] This invention belongs to the field of field programmable gate array technology, specifically relating to an FPGA structure and implementation method for MVDR beamforming based on a multi-mode pulsating array. Background Technology

[0002] The MVDR algorithm, a classic adaptive beamforming technique, is widely used in array signal processing in radar, sonar, and communication systems. Its core idea is to minimize the total output power of the array while maintaining distortion-free transmission of the desired signal, thereby suppressing interference and noise from other directions and effectively improving the signal-to-interference-plus-noise ratio (SINR). In the implementation of the MVDR algorithm, the covariance matrix of the received data needs to be estimated, and the optimal weight vector is calculated accordingly. By weighted summation of the received array signals, the beamformer can form a main lobe in the direction of the desired signal and nulls in the direction of interference signals, achieving spatial filtering. This process can be summarized into the following key steps: covariance matrix estimation, matrix inversion, and weight vector solving, among which matrix inversion is the most computationally intensive part.

[0003] Field-Programmable Gate Arrays (FPGAs), with their high parallel processing capabilities and reconfigurability, have become an important platform for implementing complex signal processing algorithms. In applications with extremely high real-time requirements, such as radar, using FPGAs to accelerate MVDR algorithms can effectively improve data processing throughput and reduce system latency. However, efficiently performing complex matrix operations in MVDR within limited hardware resources remains a key challenge in current engineering practice.

[0004] Currently, the hardware implementation of MVDR algorithms is mainly divided into two categories based on the different methods of covariance matrix estimation and weight calculation: one is the adaptive method based on recursive least squares (RLS), which updates the weight vector iteratively, avoiding direct matrix inversion and thus reducing computational complexity. However, the convergence time of RLS-MVDR has some uncertainty. Therefore, in real-time signal processing systems, sample matrix inversion (SMI) type MVDR methods are usually adopted. This type of method directly estimates the covariance matrix based on sampled data and performs inversion to solve for the weight vector. It has the advantages of fast convergence speed and strong interference suppression capability, and performs particularly well under steady-state conditions, thus it is more favored in engineering.

[0005] In existing SMI-MVDR hardware implementations, common solutions include matrix inversion based on the definition method and matrix decomposition and inversion operations based on a pipelined parallel architecture. The former has a simple implementation structure and is suitable for low-order matrices, but suffers from poor numerical stability and insufficient scalability when processing high-order matrices; the latter, although it can improve data throughput through high parallelization, requires a large amount of critical hardware resources such as DSPs, leading to increased system costs and integration difficulties.

[0006] In existing technologies, some solutions employ the SMI-MVDR algorithm to design a hardware implementation architecture. However, the solution for the inverse of the triangular matrix is ​​based on the definition method. While this method is simple to implement, it is only suitable for low-order matrix inversion and is difficult to handle large array signals in practical radar systems. Other solutions use a pipelining parallel design approach for their SMI-MVDR algorithm implementation hardware architecture. This approach offers high data throughput but consumes significant hardware resources. For example, using the DSP48 FPGA computing resources, completing a 6th-order matrix inversion using this method requires 1839 DSP48 chips. Among Xilinx's high-end Kintex 7 series FPGA chips, only the XC7K480T model has more than 1839 FPGA chips. This means that to deploy the MVDR algorithm in a system using this method, a separate FPGA chip must be added for the algorithm, or a flagship Xilinx FPGA chip must be selected to integrate the algorithm with the existing system. This significantly increases the hardware design complexity and cost of the system. In summary, existing FPGA implementations of MVDR algorithms generally suffer from high resource consumption and difficulty in balancing real-time performance with hardware cost. Summary of the Invention In order to solve the above-mentioned problems existing in the prior art, the present invention provides an FPGA structure and implementation method for MVDR beamforming based on a multi-mode pulsating array.

[0007] The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides an MVDR beamforming FPGA structure based on a multi-mode pulsating array. The FPGA structure includes: a data acquisition module for acquiring N-times sampled data and converting the data type of the acquired N-times sampled data to obtain a sampling matrix; an FSM scheduling module for scheduling and controlling the multi-port storage RAM, the multi-mode computing module, and the data stream respectively; and a multi-mode computing module including a division unit, an inversion unit, a delay unit, a buffer unit, and a pulsating array unit composed of N×N PE units, used for calculating the covariance matrix. Solving, LDL decomposition, triangular matrix and diagonal matrix The beam inverse is calculated, and the optimal weights are then calculated based on the inverse matrix and stored in the beam weight table. Here, N is a positive integer greater than 1, and each PE unit is used to perform floating-point complex number multiplication and floating-point complex number accumulation operations on the input data. The multi-port storage RAM has... X-dimensional read ports and A Y-dimensional read / write port is used for data reading and storage during the calculation process of the multi-mode computing module.

[0008] This invention also proposes a method for implementing an MVDR beamforming algorithm on an FPGA, applied to the aforementioned MVDR beamforming FPGA structure based on a multi-mode pulsating array. The method includes: S1, controlling the data acquisition module to acquire N-frame sampled data through an FSM scheduling module, converting the data type of the acquired N-frame sampled data to obtain a sampling matrix, and controlling the data acquisition module to store the sampling matrix in a multi-port RAM; S2, controlling the sampling matrix to enter the inversion unit and delay unit from the multi-port RAM through the FSM scheduling module, performing a conjugate transpose on the sampling matrix through the inversion unit to obtain a conjugate transposed sampling matrix, and delaying the output of the sampling matrix through the delay unit to align it in time with the conjugate transposed sampling matrix, and controlling the conjugate transposed sampling matrix and the sampling matrix to simultaneously enter the pulsating array unit from the X and Y dimensions through the FSM scheduling module, and performing matrix multiplication between the conjugate transposed sampling matrix and the sampling matrix through the pulsating array unit to obtain a covariance matrix. and the covariance matrix S3. Data is stored in a multi-port RAM; the FSM scheduling module controls the multi-port RAM to read / write data, and the division unit and delay unit perform division calculations and delay output of the corresponding data. The FSM scheduling module also controls the pulsating array unit to solve for the covariance matrix through iterative methods. diagonal matrix and the covariance matrix The updated triangular matrix with diagonal elements S4. The FSM scheduling module controls the reading / writing of data from the multi-port storage RAM, and also controls the pulsating array unit to solve for the triangular matrix through iterative recursion. inverse matrix and diagonal matrix The inverse matrix; S5, control the multi-port storage RAM to read data through the FSM scheduling module, and control the pulsating array unit through the FSM scheduling module, based on the triangular matrix. inverse matrix, diagonal matrix The inverse matrix, and the guide vector stored in the multi-port memory RAM. The optimal weights are generated and stored in the beam weight table.

[0009] Compared with existing technologies, the beneficial effects of this invention are as follows: 1) This invention designs a multi-mode systolic array unit, which, under the precise control of the scheduling module, serves multiple distinct computational steps such as covariance matrix calculation, LDL decomposition, and triangular matrix inversion. This strategy of "converting parallel structure into time-division multiplexing" fundamentally reduces the number of dedicated computing units (such as DSPs) required. Simultaneously, this invention deeply optimizes the PE units constituting the systolic array unit, further compressing the resource consumption of a single PE unit using techniques such as complex time-division processing. Therefore, when achieving the same function, this invention requires far less critical resources such as DSPs than existing technologies, enabling the entire MVDR algorithm to be easily integrated into a low-to-mid-range FPGA without replacing flagship chips or adding additional hardware, significantly reducing system size, power consumption, and total cost; 2) This invention introduces and optimizes the "LDL decomposition" and "recursive inversion" algorithms, decomposing the problem of inverting high-order matrices into a series of low-order matrix operations, and efficiently accelerates these low-order operations through the "parallel computing structure" of the systolic array unit. This not only ensures the algorithm's effective processing capability for high-order matrices but also significantly improves computation speed through tree-based recursive parallelization. Furthermore, the parallel read / write capability of the multi-port RAM in this invention ensures that storage bandwidth will not become a performance bottleneck when processing large-scale matrix data. Therefore, this invention maintains excellent real-time processing capabilities while significantly reducing resource consumption and successfully solves the shortcomings of existing technologies in efficiently processing high-order matrices.

[0010] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0011] Figure 1 is an exemplary architecture diagram of an MVDR beamforming FPGA structure based on a multi-mode pulsating array provided in an embodiment of the present invention; Figure 2 is a two-level state scheduling diagram of an FSM scheduling module provided in an embodiment of the present invention; Figure 3 is an internal structure diagram of a multi-mode computing module provided in an embodiment of the present invention; Figure 4 is a partial connection diagram between a multi-port storage RAM, a division unit, an inversion unit, a delay unit, and a pulsating array unit provided in an embodiment of the present invention; Figure 5 is an internal structure diagram of a PE unit provided in an embodiment of the present invention; Figure 6A is an exemplary matrix pair provided in an embodiment of the present invention. The schematic diagram of the first recursive operation during inversion; Figure 6B is an exemplary matrix pair provided by an embodiment of the present invention. The schematic diagram of the second recursive operation when finding the inverse. Detailed Implementation

[0012] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0013] This invention aims to address the problems of high resource consumption and difficulty in balancing real-time performance and hardware cost caused by the complexity and numerous matrix operations in the implementation of existing MVDR algorithms on FPGAs. This invention proposes a resource-friendly and streamlined hardware architecture for MVDR weight calculation, which can significantly reduce the demand for key resources such as DSP and BRAM in the FPGA while ensuring algorithm performance and real-time processing capabilities, thereby improving system integration and cost-effectiveness.

[0014] The present invention proposes an FPGA structure for MVDR beamforming based on a multi-mode pulsating array, which is used to implement the MVDR beamforming algorithm. Furthermore, the FPGA structure proposed in this invention implements the MVDR beamforming algorithm according to the mathematical principles of the MVDR beamforming algorithm. Therefore, before introducing the FPGA structure proposed in this invention, the mathematical principles of the MVDR beamforming algorithm will be briefly introduced first.

[0015] Since the mathematical principles are based on existing algorithms, only a brief description is provided. The MVDR optimization problem can be modeled as follows: ,in, The covariance matrix of the interference noise signal, for The directional steering vector. By using the Lagrange multiplier method to solve the above optimization problem, the optimal weight vector (i.e., the optimal weight value) can be obtained. The expression is: .

[0016] In the above formula, the guiding vector The covariance matrix of the ideal interference noise signal is determined by the array's hardware layout and structure, and can be pre-calculated and stored in the system. In practical engineering, the covariance matrix of the ideal interference noise signal... (abbreviated as) The covariance matrix of the sampling data (i.e., the sampling matrix) from a finite number of snapshots is usually unavailable. To replace, that is: Where N is the number of sampling snapshots of the array received signal. Therefore, the above formula... Become .

[0017] The above formula In FPGA implementation, it can be roughly divided into three steps: Step 1, the covariance matrix of the sampling matrix. Solving the problem; Step 2: Covariance matrix The inverse operation (i.e.) (Solution); Step 3, based on and Solving for the optimal weights Covariance matrix Solving this problem corresponds to the multiplication of two N*M matrices. Solving this corresponds to the matrix inversion operation. Weights The calculation corresponds to the matrix-vector multiplication operation and the dot division operation of vectors.

[0018] Implementing matrix inversion requires further algorithmic decomposition. The traditional principle of LU decomposition is to decompose a square matrix... It can be decomposed into the product of a lower triangular matrix L and an upper triangular matrix U, i.e. =LU. And when When matrix A is a positive definite symmetric square matrix, matrix A has a unique decomposition A=LDL. T The decomposition result can be solved using a block recursive method. For matrix A, it can be represented in the form of the following block matrix: , where vector submatrix LDL T The decomposition can be expressed as follows: Based on this, the calculations for each term in the above formula are readily obtained as follows: , Where vector s is the first column element in the decomposition matrix L (i.e., the lower triangular matrix L), Let be the diagonal elements of the first column of matrix D (i.e., diagonal matrix D). Based on this decomposition, the decomposition problem of an N-order matrix is ​​recursively simplified to N-1 order, and the new N-1 order matrix is ​​represented as follows: For the new matrix Repeating the above recursive process will solve for all elements in matrices L and D, thus obtaining matrices L and D. Next, we will focus on the inversion process of triangular matrices, specifically the upper triangular matrix. T is the transpose symbol, which can be decomposed into the following form: The inverse of this matrix is ​​represented as follows: Therefore, we can deduce the inverse of the entire large matrix by calculating the inverse of the second-order matrix at the diagonal of the higher-order matrix. Finally, we obtain the inverse of the original square matrix from the inverses of the submatrices, as follows: .

[0019] Therefore, the covariance matrix mentioned above As the aforementioned square array Using the above principles, the inverse matrix of the covariance matrix can be obtained. Solving for the covariance matrix, and then finding the inverse of the covariance matrix. Substitute into the formula for calculating the optimal weights By going through this process, the final optimal weight can be determined. Solve for it.

[0020] Based on this mathematical principle, the following sections will introduce the FPGA structure proposed in this invention and the methods used to implement the MVDR beamforming algorithm.

[0021] Figure 1 is an exemplary architecture diagram of an MVDR beamforming FPGA structure based on a multi-mode pulsating array provided in an embodiment of the present invention. As shown in Figure 1, the FPGA structure includes: a data acquisition module, an FSM scheduling module, a multi-mode computing module, and a multi-port storage RAM. The data acquisition module, the FSM scheduling module, the multi-mode computing module, and the multi-port storage RAM are interconnected.

[0022] The data acquisition module is used to collect N-times sampled data and convert the data type of the collected N-times sampled data to obtain a sampling matrix. Specifically, the data acquisition module consists of a FIFO and a threshold decision unit. The FIFO performs dynamic data buffering, and the threshold decision unit determines whether the current sampled data is clutter data through threshold detection. When the current data is not clutter data, the FIFO output data is selected and N-times sampled data is acquired. Then, the IP core converts the hexadecimal signed number into a 32-bit floating-point number according to the IEEE 754 standard, thus obtaining N-times sampled data with a 32-bit floating-point data type. This N-times sampled data is in matrix form and is called the sampling matrix.

[0023] The FSM scheduling module is used to schedule and control the multi-port RAM, multi-mode computing modules, and data streams separately. Specifically, the control of data streams and the use of each module are managed uniformly by the FSM scheduling module. The FSM scheduling module uses a two-level state machine to control the multi-port RAM, multi-mode computing modules, and data streams. The first-level state machine controls each sub-step of the MVDR beamforming algorithm, while the second-level state machine controls the more refined data stream scheduling in each sub-step. Through refined data flow control, idle resources can be fully utilized to significantly improve computational parallelism; at the same time, under the scheduling of the state machine, the key computing resource—the pulse array unit—is also time-division multiplexed, thereby significantly reducing the consumption of DSP resources. For example, Figure 2 is the two-level state scheduling diagram of the FSM scheduling module. As shown in Figure 2, the states of the first-level state machine include, in sequence, the idle state (IDLE), the covariance matrix solution state, the LDL decomposition state, the triangular matrix and diagonal matrix inversion state, and the optimal weight calculation state. Referring back to Figure 2, the states of the second-level state machine corresponding to the covariance matrix solution state are as follows: IDLE state, threshold detection state, sampling matrix calculation state, and sampling matrix storage state; the states of the second-level state machine corresponding to the LDL decomposition state are as follows: IDLE state and iterative operation state, where the iterative operation state represents the iterative solution of the covariance matrix. diagonal matrix The triangular matrix updated with diagonal elements The state, for example, when the covariance matrix When the matrix is ​​of order 12, iteratively solve the covariance matrix. diagonal matrix The triangular matrix updated with diagonal elements There are eleven iterations. Referring again to Figure 2, the states of the second-level state machine corresponding to the inversion states of the triangular and diagonal matrices are, in sequence: the IDLE state and the iterative recursive state. The iterative recursive state indicates that the triangular matrix is ​​solved using an iterative recursive method. The inverse matrix, and the solution of the diagonal matrix by division. The state of the inverse matrix, for example, when the matrix Solving for triangular matrices when the matrix is ​​of order 12 The inverse matrix involves three recursive operations.

[0024] The multi-mode computation module includes a division unit, an inversion unit, a delay unit, a buffer unit, and a systolic array unit consisting of N×N PE units. The multi-mode computation module is used to perform covariance matrix calculations. Solving, LDL decomposition, triangular matrix and diagonal matrix The beam inverse is calculated, and the optimal weights are then stored in the beam weight table based on the inverse matrix. Here, N is a positive integer greater than 1, and each PE unit is used to perform floating-point complex number multiplication and floating-point complex number accumulation operations on the input data. It should be noted that the covariance matrix... It is an M-order matrix, and M is a positive integer less than or equal to N. For example, Figure 3 is a schematic diagram of the internal structure of a multi-mode computing module. As shown in Figure 3, the pulsating array unit consists of 6×6 PE units.

[0025] Multi-port storage RAM has X-dimensional read ports and The multi-port RAM has six Y-dimensional read / write ports for data reading and storage during the computation process of the multi-mode computing module. For example, as shown in Figure 1, the multi-port RAM has six X-dimensional read ports and six Y-dimensional read / write ports. The multi-port RAM proposed in this invention defines a two-dimensional reg-type storage array. During matrix computation, data needs to be continuously read from various positions in the matrix. To avoid excessively long data read / write times blocking the computation process, the multi-port RAM of this invention can... X-dimensional read ports and A single matrix can be read from a Y-dimensional read / write port, or it can be read through... X-dimensional read ports and Two Y-dimensional read / write ports read in parallel. A matrix of order. Specifically, multi-port storage RAM. X-dimensional read ports and Each Y-dimensional read / write port is connected to the input and output of the division unit and the inversion unit. Furthermore, the output of the division unit is also connected to the input of the buffer unit. X-dimensional read ports and Each Y-dimensional read / write port is also connected to the input of the delay unit; the output of the division unit is connected to the first input of the X-dimensional MUX. Each X-dimensional read port is connected to the second input of the X-dimensional MUX; the output of the data acquisition module is connected to the third input of the X-dimensional MUX; the output of the X-dimensional MUX is connected to the data input (up_data_in) of each PE unit in the first row of the pulsating array unit; the output of the delay unit is connected to the first input of the Y-dimensional MUX; the output of the inverting unit is connected to the second input of the Y-dimensional MUX; the output of the data acquisition module is connected to the third input of the Y-dimensional MUX; the output of the buffer unit is connected to the fourth input of the Y-dimensional MUX; the output of the Y-dimensional MUX is connected to the second input (left_data_in) of each PE unit in the first column of the pulsating array unit; the control inputs (select0~4) of each PE unit are connected to the FSM scheduling module; and the control terminals of both the Y-dimensional and X-dimensional MUX are connected to the FSM scheduling module. For example, Figure 4 shows a partial connection diagram between the multi-port storage RAM, the division unit, the inverting unit, the delay unit, and the pulsating array unit; some of the above connections are not shown in Figure 4. As shown in Figure 4, the multi-port storage RAM is located to the left of the division unit, the inversion unit, and the delay unit. Furthermore, the MUX located on the top of the systolic array is called the X-dimensional MUX, and the MUX located to the left of the systolic array is called the X-dimensional MUX.

[0026] Each PE unit consists of multiple MUXs, multiple D flip-flops, a real multiplication unit, a real addition unit, a timing unit, and a register unit. The real addition unit performs real addition operations and is implemented using the Add mode of the Xilinx Floating-point IP core. The real multiplication unit performs real multiplication operations and is implemented using the Multiply mode of the Xilinx Floating-point IP core. Specifically, each PE unit includes: 11 MUXs m1~m11, 10 D flip-flops D1~D10, one timing unit, one register unit, one first real addition unit float_multiply, one second real addition unit float_add, and one real multiplication unit float_add.

[0027] For example, Figure 5 is a schematic diagram of the internal structure of a PE unit. As shown in Figure 5, the first input terminal of MUX m1 is connected to the data input terminal up_data_in, the second input terminal of MUX m1 is connected to the data input terminal down_data_in, the control terminal of MUX m1 is connected to the control input terminal select3, and the output terminal of MUX m1 is simultaneously connected to the first input terminal of MUX m3 and the D terminal of D flip-flop D1; the Q terminal of D flip-flop D1 is simultaneously connected to the D terminal of D flip-flop D2 and the second input terminal of MUX m3, the Q terminal of D flip-flop D2 is simultaneously connected to the D terminal of D flip-flop D3 and the third input terminal of MUX m3, the Q terminal of D flip-flop D3 is connected to the fourth input terminal of MUX m3, and the output terminal of MUX m3 is connected to one input terminal of the real number multiplication unit float_multiply; the first input terminal of MUX m2 is connected to the data input terminal left_data_in, the second input terminal of MUX m2 is connected to the data input terminal right_data_in, the control terminal of MUX m2 is connected to the control input terminal select4, and the output terminal of MUX m2 is simultaneously connected to the first input terminal of MUX m3 and the second input terminal of D flip-flop D1 and the third input terminal of MUX m3; the Q terminal of D flip-flop D3 is connected to the fourth input terminal of MUX m3, and the output terminal of MUX m3 is connected to one input terminal of the real number multiplication unit float_multiply; the first input terminal of MUX m2 is connected to the data input terminal left_data_in, the second input terminal of MUX m2 is connected to the data input terminal right_data_in, the control terminal of MUX m2 is connected to the control input terminal select4, and the output terminal of MUX m2 is simultaneously connected to the first input terminal of MUX m3 and the second input terminal of D flip-flop D1 and the third input The first input terminal of MUX m4 is connected to the D terminal of D flip-flop D4; the Q terminal of D flip-flop D4 is simultaneously connected to the D terminal of D flip-flop D5 and the second input terminal of MUX m4; the Q terminal of D flip-flop D5 is simultaneously connected to the D terminal of D flip-flop D6 and the third input terminal of MUX m4; the Q terminal of D flip-flop D6 is connected to the fourth input terminal of MUX m4; the output terminal of MUX m4 is connected to another input terminal of the real number multiplication unit float_multiply; the control terminals of MUX m3 and MUX m4 are both connected to the output terminal of the timing unit; the output terminal of the real number multiplication unit float_multiply is simultaneously connected to the first input terminal of MUX m5 and the D terminal of D flip-flop D7; the Q terminal of D flip-flop D7 is simultaneously connected to the D terminal of D flip-flop D8 and the first input terminal of MUX m6; the Q terminal of D flip-flop D8 is simultaneously connected to the D terminal of D flip-flop D9 and the second input terminal of MUX m5; the Q terminal of D flip-flop D9 is connected to the second input terminal of MUX m6; MUX... The output of m5 is connected to one input of the first real number addition unit float_add, the output of MUX m6 is connected to the other input of the first real number addition unit float_add, and the output of the first real number addition unit float_add is connected to one input of the second real number addition unit float_add.The first input of MUX m7 is connected to the output of MUX m1. The second input of MUX m7 is simultaneously connected to the D terminal of D flip-flop D10, the other input of the second real number adder unit float_add, and the first input of MUX m10. The control terminal of MUX m7 is connected to the control input select1. The output of MUX m7 is connected to the input of MUX m8. The first output of MUX m8 is connected to the data output up_data_out, and the second output of MUX m8 is connected to the data output down_data_out. The Q terminal of D flip-flop D10 is connected to the output of MUX m9. The first input of MUX m9 is connected to the output of the second real number adder unit float_add. The second input of MUX m9 is connected to the output of the register cell. The control terminal of MUX m9 is connected to the control input select0, and the input of the register cell is connected to the data input left_data_in. The second input of MUX m10 is connected to the output of MUX m2. The control terminal of MUX m10 is connected to the control input select2. The output of m10 is connected to the input of MUX m11. The first output of MUX m11 is connected to the data output terminal left_data_out, and the second output of MUX m11 is connected to the data output terminal right_data_out. The control inputs select0~select4 are all connected to the FSM scheduling module.

[0028] As shown in Figure 5, in this invention, each PE unit receives multiple selection signals through multiple selection signal ports select0~4 to control the input / output source interface of the data stream and the interface for loading initial values ​​in multiplication-addition operations. Since the PE unit is the basic component of the systolic array unit, its design directly affects the performance and resource consumption of the entire systolic array unit. Therefore, this invention deeply optimizes the PE unit in terms of resources: because the data to be processed is complex, each multiplication operation requires four real number multiplications and two real number additions / subtractions. This invention, by performing multi-level pacing on the input data, allows the four real number multiplications and two real number additions to be completed by the same multiplication and addition unit in a time-sharing manner, significantly reducing resource consumption. In other words, this invention deeply optimizes the PE unit, the basic component of the systolic array unit: it proposes a time-sharing processing mechanism for complex data, enabling the PE unit to maintain its miniaturization while possessing high flexibility and high performance, suitable for various complex computational scenarios in the MVDR algorithm.

[0029] Specifically, in the pulsating array unit of this invention, the data input terminal up_data_in of each PE unit in the first row is connected to the output terminal of the X-dimensional MUX; the data output terminal down_data_out of each PE unit in the j-th row is connected to the data input terminal up_data_in of the (j+1)-th row; the data input terminal down_data_in of each PE unit in the j-th row is connected to the data output terminal up_data_out of the (j+1)-th row; the data input terminal left_data_in of each PE unit in the first column is connected to the output terminal of the Y-dimensional MUX; the data output terminal right_data_out of each PE unit in the j-th column is connected to the data input terminal left_data_in of each PE unit in the (j+1)-th column; the data input terminal left_data_in of each PE unit in the j-th column is connected to the data output terminal right_data_out of each PE unit in the (j+1)-th column; and the data input terminal right_data_in of each PE unit in the j-th column is connected to the data output terminal left_data_out of each PE unit in the (j+1)-th column; j is a positive integer, and the value of j is from 1 to N-1. The operating modes of the systolic array unit of this invention include: matrix multiplication-addition merging calculation mode, multiple low-order matrix parallel calculation mode, and three-matrix multiplication accelerated calculation mode. This multi-mode systolic array unit structure, through configurable PE units and data flow control, achieves time-division multiplexing of hardware resources, avoiding the traditional practice of designing multiple dedicated modules for different calculation steps, thereby significantly reducing DSP and logic resource consumption.

[0030] This invention also provides a method for implementing an MVDR beamforming algorithm on an FPGA, which is applied to the aforementioned MVDR beamforming FPGA structure based on a multi-mode pulsating array. The method includes: S1, controlling the data acquisition module to acquire N-frame sampling data via the FSM scheduling module, converting the data type of the acquired N-frame sampling data to obtain a sampling matrix, and controlling the data acquisition module to store the sampling matrix in a multi-port RAM.

[0031] S2. The FSM scheduling module controls the sampling matrix to enter the inversion unit and delay unit from the multi-port storage RAM respectively. The inversion unit performs conjugate transpose on the sampling matrix to obtain the conjugate transposed sampling matrix. The delay unit delays the output of the sampling matrix to align it with the conjugate transposed sampling matrix in time. The FSM scheduling module then controls the conjugate transposed sampling matrix and the sampling matrix to simultaneously enter the pulsation array unit from the X and Y dimensions respectively. The pulsation array unit performs matrix multiplication between the conjugate transposed sampling matrix and the sampling matrix to obtain the covariance matrix. and the covariance matrix Stored in multi-port RAM.

[0032] Specifically, the pulsating array unit performs matrix multiplication between the sampled matrices after their conjugate transpose, and after the operation, the result value temporarily stored in the PE unit of the pulsating array unit is output in parallel. Under the control of the scheduling module, the data stream (i.e., the covariance matrix) is then processed. Write the data in parallel row to the multi-port storage RAM.

[0033] S3. The FSM scheduling module controls the reading / writing of data from the multi-port RAM, and performs division calculations and delayed outputs of the corresponding data through the division and delay units. The FSM scheduling module also controls the pulsating array unit to solve for the covariance matrix through an iterative solution. diagonal matrix Covariance Matrix The updated triangular matrix with diagonal elements .

[0034] As explained in the mathematical principles above, LDL matrix decomposition is an iterative process. For an N-order matrix, N-1 iterations are required to complete the matrix decomposition calculation. Furthermore, as shown in Figure 2 above, the matrix iteration process is precisely controlled by a state machine. The specific iterative process is described below: Let matrix A be the N-order covariance matrix to be decomposed. , where i represents the current iteration cycle i, and i increments from 1 to N-1.

[0035] (3a) The upper triangular part of the i-th row element in the matrix stored in the multi-port storage RAM is read out by the state machine. Among them, Called a vector 'i' represents the current iteration, which increments from 1 to N-1. Representation matrix The matrix is ​​composed of the elements of the i-th row and the i-th to N-th columns; and the multi-port storage RAM, controlled by the state machine, stores the vector. The inputs flow into the division unit and the delay unit respectively, and the output of the delay unit (i.e., the vector) ) and the data stream after division (i.e. After alignment, the signals are simultaneously and separately input to the left and upper inputs of the pulsating array unit, respectively. The pulsating array unit then processes the output of the delay unit (i.e., the vector). ) and the data stream after division (i.e. Perform matrix multiplication to obtain the calculation result (i.e. Meanwhile, the data stream after the division unit operation ( Write back to the vector in multi-port storage RAM The storage location of the pulsating array cell, the calculation results (i.e. Write to the diagonal matrix in the cache unit The cache area.

[0036] (3b) Simultaneously with the above flow control, the state machine controls the remaining Ni interfaces of the multi-port storage RAM to read the matrix in parallel row by row. ,in, Represents the covariance matrix The matrix is ​​formed by the elements of row i+1 to row N, i+1 to column N. Then, Ni-way data (i.e. The input is inverted by the inverting unit, and the inverted value is used as the initial value to be loaded from the Y dimension of the systolic array into the register of the PE unit in the systolic array. Then, the delayed vector is controlled by the state machine. and the vector after division The pulse array unit is input from the left and top sides respectively, and the pulse array unit is controlled to... and Perform inner product operations, and then directly combine the inner product with the matrix loaded inside the PE unit. The initial values ​​of each element are added together to complete the operation. (3c) The above is completed in a clockwise manner in the pulse array unit. After the calculation, the result is stored in the multi-port RAM. If i is even, the state machine controls the multi-port RAM to read the calculation result row by row and input it into the inversion unit. The inversion unit then inverts the result again and writes it back to the matrix in the multi-port RAM. The storage location is determined to obtain a new N-1 order matrix. (3d) If i is odd, the state machine controls the multi-port RAM to read the calculation results row by row. Then input the division unit in the idle state to solve for the reciprocal and write it back to obtain a new N-1 order matrix. And prepare for the subsequent matrix inversion; (3e) Steps (3a) to (3d) describe the first iteration process i=1. After completing the first iteration operation through (3a) to (3d), the second iteration is controlled by the state machine. The specific iteration principle is as described in (3a) to (3d) above. However, unlike the first iteration, the matrix in (3a) in the second iteration is different. for Following the above iterative principle, after completing the (N-1)th iteration, the upper triangular matrix is ​​finally obtained. and diagonal matrix .

[0037] S4. The FSM scheduling module controls the reading / writing of data from the multi-port storage RAM, and also controls the pulsating array unit to solve the triangular matrix through iterative recursion. The inverse of the inverse matrix, and solving the diagonal matrix by division. The inverse matrix.

[0038] Finding the inverse of a triangular matrix is ​​a recursive process. Depending on the order of the matrix being inverted, different recursive procedures can be designed. For example, when N is 12, the inverses of fourth, sixth, and twelfth order matrices can be derived sequentially from the inverse of the second-order matrix on the diagonal. Step S3 has already completed the matrix... The calculation updates the second-order submatrices distributed on its diagonal to their inverses, therefore. Next, with N = 12, i.e. Taking a 12th-order matrix as an example, let's continue the explanation. The process of solving the inverse matrix: (4a) The state machine controls the multi-port storage RAM to retrieve the matrix in parallel from the X-dimensional multi-port storage RAM. and And extracting the matrix from the Y dimension and ,in, It is a matrix The submatrix formed by the elements of the first row and the second row in the first and second columns. , Similarly, and the matrix A matrix representing a second-order submatrix distributed on the diagonal that is inverse. Furthermore, the data is input into the upper left and lower left portions of the pulsating array unit, respectively, for the pulsating array unit to perform the first matrix operation. The pulsating array unit then... and Perform matrix multiplication operations, and at the same time, and Perform matrix multiplication. For example, in this step, the working principle of the pulsating array unit is shown in the left half of Figure 6A, where X1 represents the input matrix. Y1 represents the input matrix X2 represents the input matrix. Y2 represents the input matrix. clk represents the calculation cycle, where clk1 represents the first calculation cycle, clk2 represents the second calculation cycle, and so on. As shown in Figure 6A, in the first calculation cycle, starting from left to right, the PE unit covered by the first red dashed line works. In the second calculation cycle, the PE unit covered by the second red dashed line works. In the third calculation cycle, the PE unit covered by the third red dashed line works.

[0039] (4b) After the above two matrix multiplication operations are completed, the X-dimensional data stream of the pulsating array unit controlled by the state machine is changed to the calculation result stored in the internal register of the PE, and the Y-dimensional data stream is read from the Y-dimensional storage RAM. and The second matrix operation is performed by the pulsating array unit, wherein the pulsating array unit performs a second matrix operation on the pulsating array unit. and Perform matrix multiplication operations, and at the same time, and Perform matrix multiplication. For example, in this step, the working principle of the pulsating array unit is shown in the right half of Figure 6A, where Z1 represents the input matrix. Z2 represents the input matrix. Similarly, clk4~clk6 represent the 4th to 6th calculation cycles. In the 4th calculation cycle, the PE unit covered by the 4th red dashed line works; in the 5th calculation cycle, the PE unit covered by the 5th red dashed line works; and in the 6th calculation cycle, the PE unit covered by the 6th red dashed line works. Through (4a)~(4b), the calculations (X1*Y1)*Z1 and (X2*Y2)*Z2 are completed. As shown in Figure 6A, by using the PE units covered by the 3 red dashed lines in the left half of Figure 6A, the calculations can be completed simultaneously. Matrix multiplication and The matrix multiplication operation is completed, which is the first stage of the operation. After the first stage of the operation is completed, the matrix multiplication operation of (X1*Y1)*Z1 and the matrix multiplication operation of (X2*Y2)*Z2 can be completed simultaneously by using the PE unit covered by the three red dashed lines on the right half of Figure 6A, which is the second stage of the operation.

[0040] (4c) Write the resulting new matrices (X1*Y1)*Z1 and (X2*Y2)*Z2 back to the multi-port RAM. and The storage location is determined to solve for the inverse of two fourth-order matrices.

[0041] (4d) Steps (4a) to (4c) above constitute the first recursive operation. After completing the first recursive operation, the state machine controls the entry into the second recursive operation to solve for the inverse matrices of the two sixth-order matrices, and writes the solution back to the matrix in the multi-port storage RAM. and The storage location. For example, the two stages of the second recursive operation are shown in Figure 6B, where X1 represents... Y1 represents Z1 represents X2 represents Y2 represents Z2 represents Similarly, clk1~clk10 represent the 1st to 10th calculation cycles. Likewise, in the 1st calculation cycle, starting from left to right, the two PE units covered by the first red dashed line work; in the 2nd calculation cycle, the four PE units covered by the second red dashed line work; in the 3rd calculation cycle, the four PE units covered by the third red dashed line work, and so on. The remaining calculation cycles are shown in Figure 6B, which will not be elaborated here. As shown in Figure 6B, using the PE units covered by the 5 red dashed lines in the left half of Figure 6B, the calculation can be completed simultaneously. Matrix multiplication and The matrix multiplication operation is completed, which is the first stage of the operation. After the first stage of the operation is completed, the matrix multiplication operation of (X1*Y1)*Z1 and the matrix multiplication operation of (X2*Y2)*Z2 can be completed simultaneously by using the PE cells covered by the five red dashed lines on the right half of Figure 6B, which is the second stage of the operation.

[0042] (4e) After completing the second recursive operation via (4d), the third recursive operation is performed. In the third recursive operation, the state machine controls the multi-port memory RAM to retrieve data from the multi-port memory RAM. , , Perform multiplication operations and write the results back to the matrix in the multi-port storage RAM. The storage location of the matrix. This completes the inversion of the entire triangular matrix, thus obtaining the matrix. inverse matrix That is, a 12th order matrix is ​​obtained. inverse matrix .

[0043] It should be noted that diagonal matrices The process of solving the inverse matrix and The process of finding the inverse matrix is ​​performed simultaneously. Since the inverse matrix of a diagonal matrix only requires inverting the elements on the diagonal, it is found in the above... While the matrix is ​​recursively inverted, the FSM state scheduling module controls the elements on the diagonal of the diagonal matrix D stored in the cache unit to flow into the division unit in sequence to find the inversion, and then write them back to the cache unit.

[0044] S5. Data is read from the multi-port storage RAM via the FSM scheduling module, and the pulse array unit is controlled via the FSM scheduling module to achieve a triangular matrix-based operation. inverse matrix, diagonal matrix The inverse matrix, and the guide vector stored in the multi-port memory RAM. The optimal weights are generated and stored in the beam weight table.

[0045] Specifically, we obtain the triangular matrix. and diagonal matrix After obtaining the inverse matrix, the state machine controls the pulsating array unit according to... Solving the covariance matrix inverse matrix , express The inverse matrix, express The inverse matrix, express The inverse matrix. Then calculate sequentially. , , It is the conjugate transpose symbol. Final weight. After the calculation is completed, according to... Write it to the corresponding position in the beam weight table, then update. Repeat the above steps to complete the weight calculation for all directions.

[0046] As can be seen from the above implementation method, when the present invention utilizes the MVDR beamforming FPGA structure based on the multi-mode pulsating array to implement the MVDR beamforming algorithm, it can make full use of idle resources, simultaneously start multiple computing tasks, reduce the overall computing latency, and achieve efficient resource allocation and real-time processing.

[0047] Based on the above, the pulsating array unit designed in this invention has the following characteristics: 1) The pulsating array unit has a combined calculation structure for matrix multiplication and addition. Specifically, in the LDL matrix decomposition process, there are multiple... Calculation. The vector inner product can be calculated directly using the systolic array cells, while the additional matrix subtraction can be performed by loading the initial accumulation value into the PE cells of the systolic array, thus simultaneously reducing processing time and hardware area. See Figure 4 above for details.

[0048] 2) Parallel computation structure for multiple low-order matrices. In the process of inverting a triangular matrix, since its recursive process is a tree structure, multiple nodes at each level can perform multiplication operations in parallel. However, because the order of the matrix in the recursive process is always less than the original matrix, a significant amount of systolic array resources remain idle during the multiplication operation using the reused systolic array from the previous level. Therefore, this invention adds systolic array interfaces (i.e., down_data_in and right_data_in) to change the data flow direction of the systolic array, dividing it into two parts from top to bottom. This allows for the parallel computation of two low-order matrix multiplications, thereby reducing computation time without increasing hardware resources. See Figures 6A and 6B above for details.

[0049] 3) Accelerated Computation Structure for Three-Matrix Multiplication. In the process of inverting a triangular matrix, each recursive iteration of the inverse matrix requires multiplication of three matrices. Due to the use of a multiplexed systolic array, the calculation result must be output and temporarily stored after the first matrix multiplication, and the systolic array structure must be reset before the second matrix operation. Considering that the order of the recursive matrix is ​​less than or equal to half the original matrix order, the second matrix multiplication can be performed directly using the idle resources of the systolic array. The necessary modification to the systolic array is to change the output source of each PE output data stream to the PE calculation result, change the PE unit on the left side of the systolic array to a storage unit, and use the PE unit on the right side as a new computational structure to complete the second matrix operation. Based on this, the computation time of three-matrix multiplication can be further reduced, while the data flow control complexity is also reduced. See Figures 6A and 6B above for details.

[0050] This invention offers the following advantages: 1) Significantly reduces hardware resource consumption, improving system integration and economy: Existing technologies employ direct parallel computing, which, despite high throughput, requires 1839 DSP48 resources to invert a single 6th-order matrix. This almost exhausts all the computing resources of a high-end FPGA, preventing the algorithm from being integrated with other system functions on the same chip. Additional FPGAs or top-tier models must be used, greatly increasing hardware costs and design complexity. This invention achieves time-sharing multiplexing of key computing resources through the core innovation of a "multi-mode systolic array." Under the precise control of the scheduling module, the same systolic array structure serves multiple distinct computational steps, such as covariance matrix calculation, LDL decomposition, and triangular matrix inversion. This strategy of "converting parallel structures into time-sharing multiplexing" fundamentally reduces the number of dedicated computing units (such as DSPs) required. Simultaneously, deep optimization of the PE unit, employing complex time-sharing processing technology, further compresses the resource consumption of a single PE. Therefore, when achieving the same function, the present invention requires far less critical resources such as DSP than existing technologies, enabling the entire MVDR algorithm to be easily integrated into a low-to-mid-range FPGA without replacing flagship chips or adding extra hardware, thus significantly reducing the system size, power consumption and total cost.

[0051] 2) Balancing high performance and versatility, this invention solves the challenge of large-scale matrix processing: Existing technologies employ a "definition-based" inversion method, which, while simple in structure, suffers from computational complexity that increases exponentially with matrix order, making it difficult to handle large array signals (i.e., high-order matrices) in practical radar systems. This invention introduces and optimizes "LDL decomposition" and "recursive inversion" algorithms, decomposing the high-order matrix inversion problem into a series of low-order matrix operations. These low-order operations are then efficiently accelerated in hardware through a "parallel computing structure" and a "three-matrix acceleration structure" for multi-mode pulsating arrays. This not only ensures the algorithm's effective processing capability for high-order matrices but also significantly improves computational speed through tree-like recursive parallelization. Furthermore, the parallel read / write capability of the multi-port storage module ensures that storage bandwidth does not become a performance bottleneck when processing large-scale matrix data. Therefore, this solution maintains excellent real-time processing capabilities while significantly reducing resource consumption and successfully overcomes the shortcomings of existing technologies in efficiently processing high-order matrices.

[0052] The above two points enable the present invention to achieve an excellent balance between resources, efficiency and versatility, and ultimately achieve a resource-friendly, structurally simple and reliable MVDR hardware implementation scheme.

[0053] MVDR beamforming algorithms, with their high resolution and strong interference suppression capabilities, hold core value in fields requiring real-time spatial filtering. Combining the parallel computing, low latency, and high energy efficiency of FPGAs, their implementation schemes show broad application prospects. Specifically, this invention can be applied in the following areas: Radar field: In radar applications, platforms (such as aircraft and satellites) are susceptible to interference from ground clutter, enemy jammers, or other wireless communications. FPGA-based MVDR algorithms can form nulls in the direction of interference sources in real time, greatly improving the radar's survivability and detection capabilities in strong electronic warfare environments.

[0054] Wireless communication: In 5G / 6G and future communication systems, FPGAs can process data from a large number of antenna channels in parallel, calculate the optimal beam weights in real time, achieve accurate user tracking and spatial multiplexing, and improve network capacity and spectrum efficiency.

[0055] Acoustics and Audio Processing: The MVDR+FPGA solution can provide hearing aids with low-latency, high-quality voice enhancement, improving the user experience. In the design of conference systems / smart speakers, this solution can also achieve high-quality voice pickup, picking up only the voice of specific speakers and suppressing room reverberation, air conditioning noise, and other people's conversations.

[0056] Drone Swarming and Navigation: Reliable communication and sensing are required when drones fly in swarms. FPGA-implemented MVDR can be used for interference-resistant communication links, as well as for sound / RF source localization based on microphone arrays or RF signals, to achieve autonomous obstacle avoidance or cooperative localization.

[0057] Radio Astronomy: In large radio telescope arrays, massive amounts of data need to be processed and radio frequency interference from Earth needs to be suppressed. MVDR is an effective tool, and FPGA is often used as a front-end preprocessing unit.

[0058] Sonar Detection: Whether it's military sonar (detecting submarines and mines) or civilian sonar (seabed mapping, fisheries), both require detecting target signals amidst complex ocean noise and interference. MVDR algorithms can effectively improve detection performance, while FPGAs can meet the real-time requirements of shipboard / submarine-based systems.

[0059] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0060] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0061] In this specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple instances. While different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce a good effect.

[0062] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An FPGA structure for MVDR beamforming based on a multi-mode pulsating array, characterized in that, The FPGA structure includes: a data acquisition module for acquiring N-times sampled data and converting the data type of the acquired N-times sampled data to obtain a sampling matrix; an FSM scheduling module for scheduling and controlling the multi-port RAM, the multi-mode computing module, and the data stream; and a multi-mode computing module, including a division unit, an inversion unit, a delay unit, a buffer unit, and a pulsating array unit composed of N×N PE units, for performing covariance matrix calculations. Solving, LDL decomposition, triangular matrix and diagonal matrix The beam inverse is calculated, and the optimal weights are then calculated based on the inverse matrix and stored in the beam weight table. Here, N is a positive integer greater than 1, and each PE unit is used to perform floating-point complex number multiplication and floating-point complex number accumulation operations on the input data. The multi-port storage RAM has... X-dimensional read ports and A Y-dimensional read / write port is used for data reading and storage during the calculation process of the multi-mode computing module.

2. The MVDR beamforming FPGA structure based on a multi-mode pulsating array according to claim 1, characterized in that, The multi-port storage RAM X-dimensional read ports and Each Y-dimensional read / write port is connected to the input and output of the division unit and the inversion unit, and the output of the division unit is also connected to the input of the cache unit. X-dimensional read ports and Each Y-dimensional read / write port is also connected to the input of the delay unit; the output of the division unit is connected to the first input of the X-dimensional MUX. Each X-dimensional read port is connected to the second input of the X-dimensional MUX. The output of the data acquisition module is connected to the third input of the X-dimensional MUX. The output of the X-dimensional MUX is connected to the data input (up_data_in) of each PE unit in the first row of the pulsating array unit. The output of the delay unit is connected to the first input of the Y-dimensional MUX. The output of the inverting unit is connected to the second input of the Y-dimensional MUX. The output of the data acquisition module is connected to the third input of the Y-dimensional MUX. The output of the buffer unit is connected to the fourth input of the Y-dimensional MUX. The output of the Y-dimensional MUX is connected to the second input (left_data_in) of each PE unit in the first column of the pulsating array unit. The control input of each PE unit is connected to the FSM scheduling module. The control terminals of both the Y-dimensional MUX and the X-dimensional MUX are connected to the FSM scheduling module.

3. The MVDR beamforming FPGA structure based on a multi-mode pulsating array according to claim 2, characterized in that, In the pulsating array unit, the data input terminal up_data_in of each PE unit in the first row is connected to the output terminal of the X-dimensional MUX; the data output terminal down_data_out of each PE unit in the j-th row is connected to the data input terminal up_data_in of the (j+1)-th row; the data input terminal down_data_in of each PE unit in the j-th row is connected to the data output terminal up_data_out of the (j+1)-th row; the data input terminal left_data_in of each PE unit in the first column is connected to the output terminal of the Y-dimensional MUX; the data output terminal right_data_out of each PE unit in the j-th column is connected to the data input terminal left_data_in of each PE unit in the (j+1)-th column; the data input terminal left_data_in of each PE unit in the j-th column is connected to the data output terminal right_data_out of each PE unit in the (j+1)-th column; and the data input terminal right_data_in of each PE unit in the j-th column is connected to the data output terminal left_data_out of each PE unit in the (j+1)-th column; j is a positive integer, and the value of j is from 1 to N-1.

4. The MVDR beamforming FPGA structure based on a multi-mode pulsating array according to claim 1, characterized in that, Each PE unit consists of multiple MUXs, multiple D flip-flops, real number multiplication units, real number addition units, timing units, and register units.

5. The MVDR beamforming FPGA structure based on a multi-mode pulsating array according to claim 4, characterized in that, Each PE unit includes: 11 MUX m1~m11, 10 D flip-flops D1~D10, a timing unit, a register unit, a first real number addition unit, a second real number addition unit, and a real number multiplication unit.

6. The MVDR beamforming FPGA structure based on a multi-mode pulsating array according to claim 5, characterized in that, The first input of MUX m1 is connected to the data input up_data_in, the second input of MUX m1 is connected to the data input down_data_in, the control terminal of MUX m1 is connected to the control input select3, and the output of MUX m1 is simultaneously connected to the first input of MUX m3 and the D terminal of D flip-flop D1. The Q terminal of D flip-flop D1 is simultaneously connected to the D terminal of D flip-flop D2 and the second input of MUX m3, the Q terminal of D flip-flop D2 is simultaneously connected to the D terminal of D flip-flop D3 and the third input of MUX m3, the Q terminal of D flip-flop D3 is connected to the fourth input of MUX m3, and the output of MUX m3 is connected to one input of the real number multiplication unit. The first input of MUX m2 is connected to the data input left_data_in, the second input of MUX m2 is connected to the data input right_data_in, the control terminal of MUX m2 is connected to the control input select4, and the output of MUX m2 is simultaneously connected to the first input of MUX m3 and the second input of D flip-flop D1. The first input terminal of MUX m4 is connected to the D terminal of D flip-flop D4; the Q terminal of D flip-flop D4 is simultaneously connected to the D terminal of D flip-flop D5 and the second input terminal of MUX m4; the Q terminal of D flip-flop D5 is simultaneously connected to the D terminal of D flip-flop D6 and the third input terminal of MUX m4; the Q terminal of D flip-flop D6 is connected to the fourth input terminal of MUX m4; the output terminal of MUX m4 is connected to the other input terminal of the real number multiplication unit; the control terminals of MUX m3 and MUX m4 are both connected to the output terminal of the timing unit; the output terminal of the real number multiplication unit is simultaneously connected to the first input terminal of MUX m5 and the D terminal of D flip-flop D7; the Q terminal of D flip-flop D7 is simultaneously connected to the D terminal of D flip-flop D8 and the first input terminal of MUX m6; the Q terminal of D flip-flop D8 is simultaneously connected to the D terminal of D flip-flop D9 and the second input terminal of MUX m5; the Q terminal of D flip-flop D9 is connected to the second input terminal of MUX m6; the output terminal of MUX m5 is connected to one input terminal of the first real number addition unit; MUX... The output of m6 is connected to the other input of the first real number adder unit, and the output of the first real number adder unit is connected to one input of the second real number adder unit; the first input of MUX m7 is connected to the output of MUX m1, the second input of MUX m7 is simultaneously connected to the D terminal of D flip-flop D10, the other input of the second real number adder unit, and the first input of MUX m10; the control terminal of MUX m7 is connected to the control input terminal select1; the output of MUX m7 is connected to the input of MUX m8; the first output of MUX m8 is connected to the data output terminal up_data_out; and the second output of MUX m8 is connected to the data output terminal down_data_out.The Q terminal of D flip-flop D10 is connected to the output of MUX m9. The first input of MUX m9 is connected to the output of the second real number adder unit. The second input of MUX m9 is connected to the output of the register unit. The control terminal of MUX m9 is connected to the control input select0. The input of the register unit is connected to the data input left_data_in. The second input of MUX m10 is connected to the output of MUX m2. The control terminal of MUX m10 is connected to the control input select2. The output of MUX m10 is connected to the input of MUX m11. The first output of MUX m11 is connected to the data output left_data_out. The second output of MUX m11 is connected to the data output right_data_out. Control inputs select0~select4 are all connected to the FSM scheduling module.

7. The MVDR beamforming FPGA structure based on a multi-mode pulsating array according to claim 1, characterized in that, The FSM scheduling module is used to control the multi-port RAM, the multi-mode computing module, and the data flow using a two-level state machine. The first-level state machine sequentially includes the following states: idle state, covariance matrix solving state, LDL decomposition state, triangular and diagonal matrix inversion state, and optimal weight calculation state. The second-level state machine corresponding to the covariance matrix solving state sequentially includes the following states: idle state, threshold detection state, sampling matrix calculation state, and sampling matrix storage state. The second-level state machine corresponding to the LDL decomposition state sequentially includes the following states: idle state and iterative operation state, where the iterative operation state represents iteratively solving the covariance matrix. diagonal matrix Covariance Matrix The updated triangular matrix with diagonal elements The states of the second-level state machine corresponding to the states of inverting the triangular matrix and the diagonal matrix are: idle state and iterative recursion state, where the iterative recursion state indicates that the triangular matrix is ​​solved by iterative recursion. The inverse matrix, and the solution of the diagonal matrix by division. The state of the inverse matrix.

8. The MVDR beamforming FPGA structure based on a multi-mode pulsating array according to claim 1, characterized in that, The covariance matrix It is an M-order matrix, and M is a positive integer less than or equal to N.

9. The MVDR beamforming FPGA structure based on a multi-mode pulsating array according to claim 1, characterized in that, The multi-port storage RAM is also used for... X-dimensional read ports and A single matrix can be read from a Y-dimensional read / write port, or... X-dimensional read ports and Two Y-dimensional read / write ports read in parallel. 1-order matrix.

10. A method for implementing an MVDR beamforming algorithm on an FPGA, characterized in that, The method applied to the MVDR beamforming FPGA structure based on a multi-mode pulsating array as described in claims 1-9 includes: S1, controlling the data acquisition module to acquire N-times sampled data via an FSM scheduling module, converting the data type of the acquired N-times sampled data to obtain a sampling matrix, and controlling the data acquisition module to store the sampling matrix in a multi-port RAM; S2, controlling the sampling matrix to enter an inversion unit and a delay unit from the multi-port RAM via an FSM scheduling module, performing a conjugate transpose on the sampling matrix via the inversion unit to obtain a conjugate transposed sampling matrix, and delaying the output of the sampling matrix via the delay unit to align it in time with the conjugate transposed sampling matrix, and controlling the conjugate transposed sampling matrix and the sampling matrix to simultaneously enter the pulsating array unit from the X and Y dimensions via the FSM scheduling module, performing matrix multiplication between the conjugate transposed sampling matrix and the sampling matrix via the pulsating array unit to obtain a covariance matrix. and the covariance matrix S3. Data is stored in a multi-port RAM; the FSM scheduling module controls the multi-port RAM to read / write data, and the division unit and delay unit perform division calculations and delay output of the corresponding data. The FSM scheduling module also controls the pulsating array unit to solve for the covariance matrix through iterative methods. diagonal matrix and the covariance matrix The updated triangular matrix with diagonal elements S4. The FSM scheduling module controls the reading / writing of data from the multi-port storage RAM, and also controls the pulsating array unit to solve for the triangular matrix through iterative recursion. The inverse of the inverse matrix, and solving the diagonal matrix by division. The inverse matrix; S5, control the multi-port storage RAM to read data through the FSM scheduling module, and control the pulsating array unit through the FSM scheduling module to achieve the result based on the triangular matrix. inverse matrix, diagonal matrix The inverse matrix, and the guide vector stored in the multi-port memory RAM. The optimal weights are generated and stored in the beam weight table.

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