Power amplification assembly, power amplifier and communication equipment

Abstract

The invention provides a power amplification assembly, a power amplifier and communication equipment, relates to the technical field of communication, and aims to solve the problem that the integration degree of the power amplifier is relatively low, and miniaturization design is not facilitated. According to the power amplification assembly, a carrier transistor and a peak transistor are both located on a first surface of a substrate; the conducting layer is located on the sides, away from the substrate, of the carrier transistor and the peak transistor, and a first signal output terminal of the carrier transistor and a second signal output terminal of the peak transistor are connected with the conducting layer through a conducting structure. A conductive distance between a combining point between the first signal output terminal and the second signal output terminal and the second signal output terminal is less than or equal to [lambda] / 16. According to the power amplification assembly provided by the invention, the stacked structural design can be realized, impedance matching and phase matching between the carrier transistor and the peak transistor can be realized through the conductive structure and the conductive layer, and the power amplification assembly has the characteristics of better integration and miniaturization.

Description

A power amplifier component, a power amplifier, and a communication device. Technical Field

[0001] This application relates to the field of communication technology, and in particular to a power amplification component, a power amplifier, and a communication device. Background Technology

[0002] In communication equipment, signals typically need to be amplified by a power amplifier (PA) before being output to subsequent signal links. Furthermore, to improve the performance of communication equipment, complex modulation techniques are used to process the signal, resulting in a high peak-to-average power ratio (PAPR). This requires the power amplifier to maintain high efficiency over a wide output power back-off range. Doherty power amplifiers offer advantages such as simple circuit structure, good performance, and ease of implementation; therefore, they are widely used in various types of communication equipment for signal amplification.

[0003] However, the current circuit structure of Doherty power amplifiers is not conducive to the integration and miniaturization of Doherty power amplifiers. Summary of the Invention

[0004] This application provides a power amplifier component that is highly efficient and facilitates miniaturization and integrated design.

[0005] In a first aspect, this application provides a power amplifier component, including a substrate, a carrier transistor, a peak transistor, and a conductive layer. Both the carrier transistor and the peak transistor are located on a first surface of the substrate. The substrate can effectively carry the carrier transistor and the peak transistor. Alternatively, the substrate can also provide heat dissipation or grounding for the carrier transistor and the peak transistor. The conductive layer is located on the side of the carrier transistor and the peak transistor facing away from the substrate, thereby achieving a stacked structure design. The carrier transistor has a first signal output terminal for outputting a signal, and the peak transistor has a second signal output terminal for outputting a signal. The first and second signal output terminals are connected to the conductive layer through a conductive structure to achieve impedance matching and phase matching between the carrier transistor and the peak transistor, and also to combine the output signals of the carrier transistor and the peak transistor. The combining point between the first and second signal output terminals is located on the surface of the second signal output terminal. Alternatively, the conductive distance between the combining point and the second signal output terminal is less than or equal to λ / 16, where λ is the wavelength of the signal propagating in the conductive layer.

[0006] The convergence point refers to the location where the signal output by the carrier transistor and the signal output by the peak transistor meet or intersect.

[0007] In the power amplifier component provided in this application, both the carrier transistor and the peak transistor are located on the first surface of the substrate, and the conductive layer is located on the side of the carrier transistor and the peak transistor facing away from the substrate, thereby realizing a stacked structure design. This increases the design flexibility of the power amplifier component and allows for better form factor evolution. Furthermore, it facilitates the high-precision and flexible arrangement of conductive lines in the conductive layer to meet the impedance and phase matching requirements between the carrier transistor and the peak transistor. Additionally, it facilitates the high-precision and flexible arrangement of conductive lines in the conductive layer to meet the connection and matching requirements with subsequent links.

[0008] In one example, the parasitic capacitance in the carrier transistor, the parasitic capacitance in the peak transistor, and the conductive structure and conductive layer connected between the first and second signal output terminals together form a capacitor-inductor-capacitor impedance inverter network. This enables the integrated design of the power amplifier components and helps simplify the circuit structure.

[0009] In one example, the conductive layer includes a connecting line and a first combining line, and the conductive structure includes a first conductive structure and a second conductive structure. A first signal output terminal is connected to one end of the connecting line through the first conductive structure, and a second signal output terminal is connected to the other end of the connecting line through the second conductive structure. The conductive structure also includes a third conductive structure, and a first end of the first combining line is connected to the second signal output terminal through the third conductive structure.

[0010] Alternatively, the first end of the first combined line is connected to the second conductive structure, and the conductive distance between the first end of the first combined line and the second signal output terminal is less than or equal to λ / 16.

[0011] Alternatively, the first end of the first combined line is connected to the connecting line, and the conductive distance between the first end of the first combined line and the second signal output terminal is less than or equal to λ / 16.

[0012] In summary, in one example, the junction point can be located on the surface of the second signal output terminal or in the conductive layer. Alternatively, the junction point can also be located in the conductive structure.

[0013] In one example, the second end of the first combining line is the output of the power amplifier component to achieve effective output of the amplified signal.

[0014] In one example, the power amplifier component further includes an additional peak transistor, which includes a third signal output terminal. The conductive layer also includes a second combining line, and the conductive structure further includes a fourth conductive structure. A second end of the first combining line is connected to the third signal output terminal via the fourth conductive structure. A first end of the second combining line is connected to the fourth conductive structure.

[0015] Alternatively, the first end of the second merging route is connected to the first merging route.

[0016] Alternatively, the conductive structure may also include a fifth conductive structure, through which the first end of the second combined line is connected to the third signal output terminal.

[0017] In summary, there is good flexibility in the connection between the additional peak transistor and the second signal output terminal of the peak transistor.

[0018] In one example, when the first end of the second combining line is connected to the fourth conductive structure, or when the first end of the second combining line is connected to the first combining line, the conductive distance between the first end of the second combining line and the third signal output terminal is less than or equal to λ / 16. This causes the parasitic capacitance in the peak transistor, the parasitic capacitance in the additional peak transistor, and the conductive structure and conductive layer connected between the second and third signal output terminals to collectively form a capacitor-inductor-capacitor impedance inverter network. This enables the integrated design of power amplifier components and helps simplify the circuit structure.

[0019] In one example, the second end of the second combiner is the output of the power amplifier component to achieve effective output of the amplified signal.

[0020] In one example, the conductive layer includes conductive lines located in the same plane, or the conductive layer includes multiple layers of conductive lines stacked together. That is, the conductive layer may include conductive lines located in the same plane, or it may include multiple layers of conductive lines located in different planes.

[0021] In one example, the power amplifier component also includes a package. The package is located on one side of the substrate and covers the carrier transistor and the peak transistor. A conductive layer is located on the surface of the package to facilitate the fabrication of the conductive layer and to enable the integrated design of the power amplifier component.

[0022] In one example, the conductive structure penetrates the package and connects the conductive layer between the carrier transistor and the peak transistor.

[0023] The conductive structure includes at least one of fan-out conductors, metal vias, and conductive pillars, and has good flexibility.

[0024] In one example, the substrate includes a ground plane, and the ground signal terminals of both the carrier transistor and the peak transistor are connected to the ground plane. That is, the substrate can meet the grounding requirements of both the carrier transistor and the peak transistor.

[0025] In one example, the substrate includes a boss. A carrier transistor or peak transistor is located on the surface of the boss.

[0026] In one example, the conductive layer includes stubs for connecting bias circuitry. These stubs are connected to the signal output terminals of both the carrier transistor and the peak transistor to facilitate the application of bias voltages to them.

[0027] In one example, the power amplifier assembly also includes an input matching circuit. The input matching circuit is connected to the signal input terminals of the carrier transistor and the peak transistor to ensure effective matching between the carrier transistor and the peak transistor and the preceding circuitry.

[0028] Secondly, this application also provides a power amplifier including at least one of the aforementioned power amplification components. By configuring the aforementioned power amplification components in the power amplifier, it is beneficial to improve the miniaturization design of the power amplifier and to achieve better power amplification performance.

[0029] Thirdly, this application also provides a communication device, including a radio frequency (RF) circuit and the aforementioned power amplifier. The RF circuit transmits RF signals to the power amplifier, which amplifies the RF signals before outputting them. By configuring the aforementioned power amplifier in the communication device, the communication device achieves better communication performance. Attached Figure Description

[0030] Figure 1 is a schematic diagram of the structure of a Doherty power amplifier provided in an embodiment of this application;

[0031] Figure 2 is the equivalent circuit diagram of the impedance inverter line in Figure 1;

[0032] Figure 3 is a circuit diagram of a power amplifier component provided in an embodiment of this application;

[0033] Figure 4 is a three-dimensional structural schematic diagram of a power amplifier component provided in an embodiment of this application;

[0034] Figure 5 is a side view of a power amplifier component provided in an embodiment of this application;

[0035] Figure 6 is a schematic diagram of the planar structure of a power amplifier component provided in an embodiment of this application;

[0036] Figure 7 is a side view of another power amplifier component provided in an embodiment of this application;

[0037] Figure 8 is a side view of another power amplifier component provided in an embodiment of this application;

[0038] Figure 9 is a side view of another power amplifier component provided in an embodiment of this application;

[0039] Figure 10 is a three-dimensional structural schematic diagram of another power amplifier component provided in an embodiment of this application;

[0040] Figure 11 is a three-dimensional structural schematic diagram of another power amplifier component provided in an embodiment of this application;

[0041] Figure 12 is a three-dimensional structural schematic diagram of another power amplifier component provided in an embodiment of this application;

[0042] Figure 13 is a three-dimensional structural schematic diagram of another power amplifier component provided in an embodiment of this application;

[0043] Figure 14 is a schematic diagram of the planar structure of another power amplifier component provided in an embodiment of this application;

[0044] Figure 15 is a three-dimensional structural schematic diagram of another power amplifier component provided in an embodiment of this application;

[0045] Figure 16 is a schematic diagram of the application of a power amplifier component provided in an embodiment of this application;

[0046] Figure 17 is a schematic diagram of the planar structure of a power amplifier provided in an embodiment of this application. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0048] To facilitate understanding of the power amplifier components provided in the embodiments of this application, their application scenarios will be introduced first below.

[0049] The power amplification component provided in this application can be applied in electronic devices with radio frequency (RF) functionality. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, router, or other device with communication capabilities. Alternatively, the power amplification component can also be applied in a power amplifier, RF circuit, or antenna. In summary, the power amplification component provided in this application can be applied in a variety of devices or scenarios requiring signal amplification.

[0050] In simple terms, in communication equipment, signals typically need to be amplified by a power amplifier (PA) before being output to subsequent signal links. Furthermore, to improve the performance of communication equipment, complex modulation techniques are used to process the signal, resulting in a high peak-to-average power ratio (PAPR). This requires the power amplifier to maintain high efficiency over a wide output power back-off range.

[0051] The Doherty power amplifier is a power amplifier based on active load modulation technology. Compared to traditional power amplifiers, the Doherty power amplifier can achieve higher efficiency when the power amplifier is in backoff mode. In addition, the Doherty power amplifier has advantages such as simple circuit structure, good performance, and ease of implementation. Therefore, it is widely used in a variety of communication devices.

[0052] Figure 1 shows an exemplary schematic diagram of the Doherty power amplifier.

[0053] The Doherty power amplifier consists of a carrier transistor PA1, a peak transistor PA2, and an impedance inverter network.

[0054] Specifically, carrier transistor PA1 is also called the main power amplifier, and peak transistor PA2 can be called the auxiliary power amplifier. By configuring different gate voltages for carrier transistor PA1 and peak transistor PA2, carrier transistor PA1 can operate in Class AB, and peak transistor PA2 in Class C. The input RF signal can be split into two signals according to a certain power ratio and phase relationship using devices such as a power divider or input matching network. The two signals are input to carrier transistor PA1 from the first signal input terminal and to peak transistor PA2 from the second signal input terminal, respectively. When the Doherty power amplifier is in small-signal operation (or the RF signal power is low), only carrier transistor PA1 is active, and peak transistor PA2 is inactive. When the RF signal power reaches a certain threshold (or the RF signal power is high), both carrier transistor PA1 and peak transistor PA2 operate simultaneously.

[0055] The impedance inverter network includes an impedance inverter line Z1. The impedance inverter line Z1 is connected to the first signal output terminal of the carrier transistor PA1. The impedance inverter line Z1 is used to perform phase deflection and other processing on the signal output by the carrier transistor PA1 to achieve impedance matching and phase matching between the output terminals of the carrier transistor PA1 and the peak transistor PA2.

[0056] However, in current Doherty power amplifiers, the unreasonable circuit structure of the impedance inverter network hinders the integration and miniaturization of the Doherty power amplifier design.

[0057] For example, in current solutions, the impedance inverter network typically includes flying leads or bonding strips. These flying leads or bonding strips connect to the outputs of carrier transistor PA1 and peak transistor PA2 to achieve combining and impedance matching of their outputs. Generally, effective impedance matching can be achieved by designing parameters such as the number, length, and arc height of the flying leads or bonding strips. However, flying leads or bonding strips are three-dimensional, flexible structures, prone to deformation or misalignment, thus failing to guarantee good impedance matching. Furthermore, soldering flying leads or bonding strips can cause length variations, affecting impedance matching accuracy. Using flying leads or bonding strips requires reserving significant height space, hindering the miniaturization design of Doherty power amplifiers. Additionally, it also hinders the implementation of stacked structure designs and subsequent packaging, significantly restricting the miniaturization and integration of Doherty power amplifiers.

[0058] In addition, when there are many flying wires or bonding wires in the impedance inverter network, problems such as confusion and crossing are likely to occur, which significantly affects the working stability and ease of manufacturing of Doherty power amplifiers.

[0059] Alternatively, in some approaches, the impedance inverter network may include additional structures such as pads or microstrip lines. However, these additional structures introduce parasitic parameters, leading to problems such as increased matching losses and reduced efficiency.

[0060] Therefore, this application provides a power amplifier component that is highly efficient and facilitates miniaturization and integrated design.

[0061] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0062] It should be noted first that, in one example, the carrier transistor PA1 or the peak transistor PA2 can be a bipolar junction transistor (BJT), a field-effect transistor (FET), or other similar types. Furthermore, the carrier transistor PA1 or the peak transistor PA2 can be a transistor packaged using a quad flat no-leads package (QFN) or other well-known packaging technologies.

[0063] In the following example, a field-effect transistor (FET) in a QFN package, where both carrier transistor PA1 and peak transistor PA2 are used as an example, will be used for illustrative purposes. For example, carrier transistor PA1 includes a source, a gate, and a drain. The source is used for ground connection, the gate serves as a signal input terminal, and the drain serves as a signal output terminal. Similarly, peak transistor PA2 includes a source, a gate, and a drain. The source is used for ground connection, the gate serves as a signal input terminal, and the drain serves as a signal output terminal. Of course, the carrier transistor PA1, peak transistor PA2, and other transistors described in this application can be of other suitable types or package forms, which will not be elaborated here.

[0064] To facilitate understanding of the technical solution of this application, the circuit structure of the power amplifier component 10 will be introduced first below.

[0065] As shown in Figures 1 and 2, the impedance inverter line Z1 in the impedance inverter network of Figure 1 can be equivalent to the capacitor C-inductor L-capacitor C (CLC) network shown in Figure 2. That is, in one example, impedance matching and phase matching are achieved between the first signal output terminal of carrier transistor PA1 and the second signal output terminal of peak transistor PA2 through the impedance inverter line Z1. Of course, in other examples, the impedance inverter network may also include other impedance inverter lines connected to the front end of the output terminal, which will not be elaborated here.

[0066] In addition, there is a drain-source parasitic capacitance C1 at the first signal output terminal of the carrier transistor PA1, and a drain-source parasitic capacitance C2 at the second signal output terminal of the peak transistor PA2.

[0067] As shown in Figure 3, if the first signal output terminal and the second signal output terminal are connected by an inductor L, then the parasitic capacitance C1, the inductor L and the parasitic capacitance C1 together form a CLC network.

[0068] In this configuration, one end of inductor L is connected to the first signal output terminal of carrier transistor PA1, and the other end of inductor L is connected to the second signal output terminal of peak transistor PA2. Signal P1 from carrier transistor PA1 is output from the first signal output terminal and then transmitted from one end of inductor L to the other end. Signal P2 from peak transistor PA2 is output from the second signal output terminal and then merges with signal P1 at the second signal output terminal before finally being output from the output terminal.

[0069] In summary, the impedance inverter network in the figure absorbs the parasitic capacitance C1 in the carrier transistor PA1 and the parasitic capacitance C2 in the peak transistor PA2, thereby enabling efficient, compact, and minimalist integrated circuit design.

[0070] In the power amplifier component 10 provided in this application, the hardware structure has been reasonably adjusted based on the above-mentioned integrated circuit design, thus enabling integrated and miniaturized design.

[0071] As shown in Figure 4, in one example provided in this application, the power amplifier component 10 includes a carrier transistor PA1, a peak transistor PA2, a conductive layer 13, and a conductive structure.

[0072] Specifically, please refer to Figures 4, 5, and 6. Figure 4 is a three-dimensional structural schematic diagram of the power amplifier component 10; Figure 5 is a side view of Figure 4 and a plan view of Figure 4.

[0073] The carrier transistor PA1 has a first signal input terminal 11a for receiving signals and a first signal output terminal 11b for outputting signals. The peak transistor PA2 has a second signal input terminal 12a for receiving signals and a second signal output terminal 12b for outputting signals.

[0074] A radio frequency (RF) signal can be input to the carrier transistor PA1 from the first signal output terminal 11b. After the RF signal is amplified by the carrier transistor PA1, the amplified signal P1 is output from the first signal output terminal 11b. A radio frequency (RF) signal can also be input to the carrier transistor PA1 from the second signal output terminal 12b. After the RF signal is amplified by the carrier transistor PA1, the amplified signal P2 is output from the second signal output terminal 12b.

[0075] The first signal output terminal 11b and the second signal output terminal 12b are connected to the conductive layer 13 through a conductive structure. That is, the conductive structure can realize the signal connection between the carrier transistor PA1, the peak transistor PA2 and the conductive layer 13, so as to achieve impedance matching and phase matching between the carrier transistor PA1 and the peak transistor PA2. In addition, it can also realize the merging or combining of signals P1 and P2.

[0076] Specifically, in the examples provided in Figures 4 to 6, the conductive structure includes a first conductive structure 141 and a second conductive structure 142. The conductive layer 13 includes a connecting line 131 and a first merging line 132.

[0077] The first signal output terminal 11b is connected to one end of the connecting line 131 through the first conductive structure 141, and the second signal output terminal 12b is connected to the other end of the connecting line 131 through the second conductive structure 142. That is, the first signal output terminal 11b and the second signal output terminal 12b are electrically connected through the first conductive structure 141, the connecting line 131 and the second conductive structure 142.

[0078] Additionally, as shown in Figures 4 to 6, the conductive structure also includes a third conductive structure 143. The first end 1321 of the first combining line 132 is connected to the second signal output terminal 12b through the third conductive structure 143, and the second end 1322 of the first combining line 132 can serve as the output terminal of the power amplifier component 10.

[0079] Signal P1 is output from the first signal output terminal 11b, then transmitted through the first conductive structure 141, the connecting line 131, and the second conductive structure 142 to the surface of the second signal output terminal 12b. Signal P2 is output from the second signal output terminal 12b, and signal P2 and signal P1 are combined on the surface of the second signal output terminal 12b, then output through the third conductive structure 143 and the first combining line 132.

[0080] In other words, the whole consisting of the first conductive structure 141, the connecting line 131, and the second conductive structure 142 shown in Figures 4 to 6 can be considered as the inductor L in Figure 3. The parasitic capacitance C1 in the carrier transistor PA1, the parasitic capacitance C2 in the peak transistor PA2, and the inductor L formed by the first conductive structure 141, the connecting line 131, and the second conductive structure 142 together constitute a CLC network.

[0081] It should be noted that, in order to form this CLC network, the point where signals P1 and P2 converge must be located on or near the surface of the second signal output terminal 12b. This convergence point refers to the approximate location where signals P1 and P2 intersect or merge; signals P1 and P2 merge at this convergence point before being output together.

[0082] For example, in the examples provided in Figures 4 to 6, the second signal output terminal 12b is connected to the first combining line 132 via the third conductive structure 143. That is, signals P1 and P2 converge on the surface of the second signal output terminal 12b and are output from the first combining line 132 after passing through the third conductive structure 143. Therefore, in the examples provided in Figures 4 to 6, the merging point of signals P1 and P2 is located on the surface of the second signal output terminal 12b.

[0083] In other examples, the junction point of signals P1 and P2 is not limited to the surface of the second signal output terminal 12b; it can also be located near the second signal output terminal 12b. Here, "nearby" refers to any location where the conductive distance between the junction point and the second signal output terminal 12b is less than or equal to λ / 16. Here, λ is the wavelength of the signal as it propagates in the conductive layer 13 (such as the connecting line 131 or the first junction line 132).

[0084] It should be noted that conductive distance refers to the shortest transmission path of a signal. Alternatively, conductive distance is the actual distance the signal travels.

[0085] For example, when a signal is transmitted in a wire of physical length S, the conductive distance of the wire can be considered as the physical length S of the wire. Alternatively, when a signal is transmitted in a metal layer with a large area, the conductive distance can be considered as the straight-line distance between the input and output ends of the signal, or the actual transmission distance of the signal.

[0086] To facilitate understanding of the technical solution of this application, the following example illustrates the solution with the merging point located on the surface of the second signal output terminal 12b.

[0087] As shown in Figures 4 to 6, in one example provided in this application, the power amplifier component 10 further includes a substrate 15.

[0088] Both the carrier transistor PA1 and the peak transistor PA2 are located on the first surface of the substrate 15 (the upper surface in Figure 5). The conductive layer 13 is located on the side of the carrier transistor PA1 and the peak transistor PA2 away from the substrate 15, thereby realizing a stacked structure design, which can increase the design flexibility of the power amplifier component 10 and also achieve better morphological evolution.

[0089] In summary, in the example provided in this application, the connecting line 131, the first conductive structure 141, and the second conductive structure 142 in the conductive layer 13 enable signal connection between the output terminal of the carrier transistor PA1 (e.g., the first signal output terminal 11b) and the output terminal of the peak transistor PA2 (e.g., the second signal output terminal 12b). This allows the signal P1 output from the first output terminal of the carrier transistor PA1 and the signal P2 output from the second output terminal of the peak transistor PA2 to be effectively combined. The combined signals P1 and P2 are then output outward from the first combining line 132 in the conductive layer 13. That is, the parasitic capacitance C1 in the carrier transistor PA1, the parasitic capacitance C2 in the peak transistor PA2, and the first conductive structure 141, the second conductive structure 142, and the connecting line 131 connected between the first signal output terminal 11b and the second signal output terminal 12b together form a CLC network. This enables the integrated design of the power amplifier component 10 and helps simplify the circuit structure.

[0090] Furthermore, the connection line 131 and the first combining line 132 in the conductive layer 13 are located on the side of the carrier transistor PA1 and the peak transistor PA2 away from the substrate 15. Therefore, it is convenient to flexibly and with high precision set the connection line 131 in the conductive layer 13 to meet the impedance matching and phase matching between the carrier transistor PA1 and the peak transistor PA2. Additionally, it is also convenient to flexibly and with high precision set the first combining line 132 in the conductive layer 13 to meet the connection and matching requirements with subsequent links.

[0091] In one example, capacitors, inductors, or resistors may be connected in parallel or in series in connecting line 131. Similarly, capacitors, inductors, or resistors may be connected in parallel or in series in the first combining line 132.

[0092] In one example, the specific structure and arrangement of the conductive layer 13 can be varied.

[0093] For example, as shown in FIG7, in one example provided in this application, the power amplifier component 10 further includes a package 16. The package 16 is located on one side of the substrate 15, and the package 16 covers the carrier transistor PA1 and the peak transistor PA2, with a conductive layer 13 located on the surface of the package 16.

[0094] In one example, the package 16 may be made of a material with good insulation properties, such as plastic or ceramic. This application does not limit the specific material of the package 16 or the packaging process.

[0095] In one example, the conductive layer 13 can be fabricated using processes such as coating, vapor deposition, or etching. This application does not limit the specific fabrication method of the conductive layer 13.

[0096] Alternatively, it can be understood that, in the example provided in this application, forming the conductive layer 13 on the surface of the package 16 enables the stacking of the conductive layer 13 with the carrier transistor PA1 and the peak transistor PA2, which can improve the flexibility and precision of the conductive layer 13 during fabrication, thereby ensuring the overall performance of the power amplifier component 10.

[0097] Alternatively, the design of the connecting lines 131 in the conductive layer 13 offers good flexibility, allowing for high-precision setting of parameters such as inductive or capacitive properties. Furthermore, in some examples, the connecting lines 131 can also be connected to other devices such as capacitors and resistors, offering good scalability and ease of fabrication.

[0098] In addition, the type, location, and number of conductive structures can also be varied.

[0099] For example, as shown in Figure 4, in one example provided in this application, the first conductive structure 141, the second conductive structure 142, and the third conductive structure 143 are all fan-out conductors.

[0100] Please refer to Figures 4 and 7. In one manufacturing method, the first conductive structure 141, the second conductive structure 142, and the third conductive structure 143 can be formed using a fan-out process, connecting the first conductive structure 141 to the first signal output terminal 11b, and connecting the second conductive structure 142 and the third conductive structure 143 to the second signal output terminal 12b. Then, a package 16 is fabricated, and finally, a conductive layer 13 is fabricated on the surface of the package 16. That is, the conductive structures penetrate the package 16 and connect between the conductive layer 13 and the carrier transistor PA1 and the peak transistor PA2.

[0101] In other examples, the first conductive structure 141, the second conductive structure 142, or the third conductive structure 143 can also be conductive structures with good signal transmission performance, such as metal vias, conductive pillars, or wires. In specific applications, the type of conductive structure can be reasonably selected according to actual needs, which will not be elaborated upon here.

[0102] In one example, the substrate 15 can be made of a material with good thermal conductivity to provide good heat dissipation. The heat generated by the carrier transistor PA1 and the peak transistor PA2 during operation can be effectively transferred to the substrate 15, thereby allowing the carrier transistor PA1 and the peak transistor PA2 to operate within a lower temperature range.

[0103] Alternatively, in one example, substrate 15 may also include a ground plane or grounding circuit (not shown in the figure). The ground signal terminals of both carrier transistor PA1 and peak transistor PA2 are connected to the ground plane, thereby satisfying the grounding requirements of carrier transistor PA1 and peak transistor PA2.

[0104] Additionally, in the example provided in Figure 7, the carrier transistor PA1 and the peak transistor PA2 are located on the surface of the same substrate 15, and this surface is planar.

[0105] In other examples, the surface of substrate 15 may also have a groove or a boss structure. The carrier transistor PA1 or the peak transistor PA2 may be located in the groove, or the carrier transistor PA1 or the peak transistor PA2 may be located on the surface of the boss.

[0106] Alternatively, as shown in Figure 8, in another example provided in this application, the power amplifier component 10 may also have two substrates, namely substrate 15a and substrate 15b. Substrate 15a and peak transistor PA2 are both located on the surface of substrate 15b. Carrier transistor PA1 is located on the surface of substrate 15a.

[0107] In one example, substrates 15a and 15b may be made of the same material or different materials.

[0108] Furthermore, in the example provided above, the conductive layer 13 is a single-layer structure. That is, the connecting line 131 and the first merging line 132 are located in approximately the same plane.

[0109] In some other examples, conductive layer 13 may also be a multilayer structure.

[0110] For example, as shown in Figure 9, in another example provided in this application, the connecting line 131 includes three parts: a first segment 1311, a conductive structure 1313, and a second segment 1312. The first segment 1311 and the second segment 1312 are located in different planes, and the conductive structure 1313 connects the first segment 1311 and the second segment 1312. Furthermore, the first end 1311 and the first merging line 132 are located in approximately the same plane. In one implementation, the conductive structure 1313 can be a fan-out conductor, a conductive post, a metal via, etc., and this application does not impose any limitations on this.

[0111] The figure illustrates an example where conductive layer 13 comprises two layers; in other examples, conductive layer 13 may also have three or more layers. Furthermore, in conductive layer 13, the conductors between different layers can be supported by an encapsulation material. Alternatively, conductive layer 13 may include a support structure or support independent of the encapsulation body 16, which will not be elaborated here.

[0112] Additionally, it should be noted that when the conductive layer 13 is a single-layer structure, the conductive material or patterned circuit in the conductive layer 13 can cover the entire surface of the package 16. Alternatively, the conductive material or patterned circuit in the conductive layer 13 can also be located in a portion of the surface of the package 16. Furthermore, when the conductive layer 13 is a multi-layer structure, the area of ​​the conductive material or patterned circuit in different layers can be the same or different.

[0113] In the example above, the exemplary illustration is based on the scenario where the junction point of the carrier transistor PA1 and the peak transistor PA2 is located on the surface of the second signal output terminal 12b of the peak transistor PA2. In other examples, the junction point may also be located in the conductive structure or the conductive layer 13. When the junction point is located in the conductive structure or the conductive layer 13, the conductive distance between the junction point and the second signal output terminal 12b is less than or equal to λ / 16.

[0114] For example, as shown in Figures 10 and 11, in one example provided in this application, the merging point is located at the first end 1321 of the first merging route 132.

[0115] Specifically, in the example provided in Figure 10, the first end 1321 of the first combining line 132 is connected to the second conductive structure 142. Signal P1 is output from the first signal output terminal 11b, passes through the first conductive structure 141 and the connecting line 131, and is transmitted to the first end 1321 of the first combining line 132. Signal P2 is output from the second signal output terminal 12b, passes through the second conductive structure 142, and is transmitted to the first end 1321 of the first combining line 132. Signal P2 and signal P1 are combined at the first end 1321 of the first combining line 132, and then output from the second end 1322 after passing through the first combining line 132. In one example, the physical length of the second conductive structure 142 can be less than or equal to λ / 16 to satisfy the requirement that the conductive distance between the combining point and the second signal output terminal 12b is less than or equal to λ / 16.

[0116] Alternatively, in the example provided in Figure 11, the first end 1321 of the first combining line 132 is connected to the connecting line 131. Signal P1 is output from the first signal output terminal 11b and transmitted through the first conductive structure 141 and a portion of the connecting line 131 to the first end 1321 of the first combining line 132. Signal P2 is output from the second signal output terminal 12b and transmitted through the second conductive structure 142 and another portion 1314 of the connecting line 131 to the first end 1321 of the first combining line 132. That is, signal P2 and signal P1 are combined at the first end 1321 of the first combining line 132, and then output from the second end 1322 after passing through the first combining line 132. In one example, the total physical length of the second conductive structure 142 and the other portion 1314 of the connecting line 131 can be less than λ / 16 to satisfy the requirement that the conductive distance between the combining point and the second signal output terminal 12b is less than or equal to λ / 16.

[0117] In the examples provided in Figures 10 and 11, the first merging line 132 is connected to either the connecting line 131 or the second conductive structure 142, therefore, the third conductive structure 143 is omitted.

[0118] Alternatively, as shown in Figure 12, in another example provided in this application, the third conductive structure 143 can also be retained. For example, the second conductive structure 142 and the third conductive structure 143 can be connected by a connecting line 131. In this case, signal P1 is output from the first signal output terminal 11b and then transmitted through the first conductive structure 141, the connecting line 131, and the connecting line 131 to the first end 1321 of the first combining line 132. Signal P2 is output from the second signal output terminal 12b and then transmitted through the second conductive structure 142 to the first end 1321 of the first combining line 132. Signal P2 and signal P1 are combined at the first end 1321 of the first combining line 132, and then output from the second end 1322 after passing through the first combining line 132. In one example, the physical length of the second conductive structure 142 can be less than λ / 16 to meet the requirement that the conductive distance between the combining point and the second signal output terminal 12b is less than or equal to λ / 16.

[0119] In the example above, the power amplifier assembly 10 is illustrated by including two transistors: a carrier transistor PA1 and a peak transistor PA2. In other examples, the power amplifier assembly 10 may include more transistors.

[0120] For example, as shown in Figures 13 and 14, in one example provided in this application, the power amplifier component 10 further includes an additional peak transistor PA3, which includes a third signal input terminal 17a and a third signal output terminal 17b.

[0121] The conductive layer 13 also includes a second combing line 134, and the conductive structure also includes a fourth conductive structure 144 and a fifth conductive structure 145, both of which are connected to the third signal output terminal 17b.

[0122] Specifically, the second end 1322 of the first combining line 132 is connected to the fourth conductive structure 144. The first end 1341 of the second combining line 134 is connected to the fifth conductive structure 145, and the second end 1342 of the second combining line 134 serves as the output terminal of the power amplifier assembly 10. At this time, the entire power amplifier assembly 10 includes two combining points. For ease of distinction, these two combining points are described as the first combining point and the second combining point, respectively.

[0123] In the examples provided in Figures 13 and 14, the first merging point is located on the surface of the second signal output terminal 12b, and the second merging point is located on the surface of the third signal output terminal 17b.

[0124] Specifically, signal P1, output by carrier transistor PA1, is transmitted from the first signal output terminal 11b through the first conductive structure 141, connecting line 131, and second conductive structure 142 to the surface of the second signal output terminal 12b. Signal P2, output by peak transistor PA2, is output from the second signal output terminal 12b and combined with signal P1. The combined signals P1 and P2 are transmitted through the third conductive structure 143, the first combining line 132, and the fourth conductive structure 144 to the surface of the third signal output terminal 17b. Signal P3, output by additional peak transistor PA3, is output from the third signal output terminal 17b and combined with signals P1 and P2. The combined signals P1, P2, and P3 are transmitted through the fifth conductive structure 145 and the second combining line 134 and output from the second end 1342 of the second combining line 134.

[0125] In summary, in the examples provided in Figures 13 and 14, the requirement that the conductive distance between the first combining point and the second signal output terminal 12b is less than or equal to λ / 16 is met. Furthermore, the requirement that the conductive distance between the second combining point and the third signal output terminal 17b is also less than or equal to λ / 16 is also met.

[0126] In the example described above, the second combining point of peak transistor PA2 and additional peak transistor PA3 is located on the surface of the third signal output terminal 17b of additional peak transistor PA3. In other examples, the second combining point may also be located in the conductive structure or conductive layer 13. When the second combining point is located in the conductive structure or conductive layer 13, the conductive distance between the second combining point and the third signal output terminal 17b may be less than or equal to λ / 16. Alternatively, the conductive distance between the second combining point and the third signal output terminal 17b may also be greater than λ / 16.

[0127] For example, as shown in Figure 15, in one example provided in this application, the merging point is located at the first end 1341 of the second merging route 134.

[0128] Specifically, in the example provided in Figure 15, the first end 1341 of the second combining line 134 is connected to the fourth conductive structure 144. The combined signals P1 and P2 are output from the second signal output terminal 12b, then transmitted through the third conductive structure 143 and the first combining line 132 to the first end 1341 of the second combining line 134. Signal P3 is output from the third signal output terminal 17b, then transmitted through the fourth conductive structure 144 to the first end 1341 of the second combining line 134. Signal P3 is combined with signals P1 and P2 at the first end 1341 of the second combining line 134, and then output from the second end 1342 after passing through the second combining line 134.

[0129] In one example, the physical length of the fourth conductive structure 144 can be less than or equal to λ / 16 to satisfy the requirement that the conductive distance between the second junction point and the third signal output terminal 17b is less than or equal to λ / 16.

[0130] Alternatively, in one example, the conductive distance between the second junction point and the third signal output terminal 17b can also be greater than λ / 16.

[0131] Alternatively, in some examples, the first end 1341 of the second merging line 134 may also be connected to the first merging line 132.

[0132] In summary, when the first end 1341 of the second combining line 134 is connected to the fourth conductive structure 144, or when the first end 1341 of the second combining line 134 is connected to the first combining line 132, the conductive distance between the first end 1341 (or the second combining point) of the second combining line 134 and the third signal output terminal 17b can be less than or equal to λ / 16. Alternatively, the distance between the first end 1341 of the second combining line 134 and the third signal output terminal 17b can also be greater than λ / 16.

[0133] The example in Figure 15 illustrates a power amplifier assembly 10 including one additional peak transistor PA3. In other examples, the power amplifier may include two or more additional peak transistors PA3. For instance, when an additional peak transistor is added to the power amplifier assembly 10 shown in Figure 15, the signal output terminal of the newly added peak transistor can be connected to the second terminal 1342 of the second composite line 134 via a conductive structure. In summary, when the power amplifier assembly 10 includes multiple additional peak transistors, the multiple additional peak transistors can be sequentially connected via the conductive layer 13 and the conductive structure, which will not be elaborated further here.

[0134] In one example, multiple power amplifier components 10 can also be cascaded.

[0135] For example, as shown in Figure 16, one example provided in this application includes a pre-amplifier component and a final-amplifier component. The pre-amplifier component can be any of the power amplifier components shown in the above example, or it can be other types of power amplifier components.

[0136] The final stage power amplifier is similar to the one shown in Figure 6. The difference is that the final stage power amplifier includes a power divider, input matching circuit 1, input matching circuit 2, and stubs.

[0137] One end of the power divider is connected to the signal output terminal of the preamplifier via a connecting wire. Input matching circuit 1 is connected between the power divider and the first signal input terminal 11a of the carrier transistor PA1. Input matching circuit 2 is connected between the power divider and the second signal input terminal 12a of the peak transistor PA2.

[0138] The RF signal output from the preamplifier is split into two paths by a power divider and then transmitted to input matching circuit 1 and input matching circuit 2, respectively. One signal is transmitted to carrier transistor PA1 via input matching circuit 1. The other signal is transmitted to peak transistor PA2 via input matching circuit 2.

[0139] Input matching circuit 1 can achieve impedance matching between carrier transistor PA1 and preceding circuits (such as power dividers). Input matching circuit 2 can achieve impedance matching between carrier transistor PA1 and preceding circuits (such as power dividers). In specific settings, the power divider, input matching circuit 1, and input matching circuit 2 can be configured in the same or similar ways according to commonly used types, which will not be elaborated here.

[0140] In addition, the conductive layer 13 also includes stubs for connecting to external bias circuits. These stubs are connected to both the first signal output terminal 11b of the carrier transistor PA1 and the second signal output terminal 12b of the peak transistor PA2, allowing the bias signal applied by the external bias circuit to be transmitted to the carrier transistor PA1 and the peak transistor PA2, thus ensuring the normal operation of the entire final stage power amplifier assembly.

[0141] The location of the branches can be flexibly set according to actual needs. Alternatively, the branches and bias circuits can be set using currently common methods, which will not be elaborated here.

[0142] The example provided in Figure 16 illustrates two cascaded power amplifier components. Other examples may involve three or more cascaded power amplifier components, which will not be discussed further here.

[0143] The aforementioned power amplification components can be directly applied in power amplifiers, radio frequency circuits, or communication equipment.

[0144] Alternatively, in some examples, pads, capacitors, or other circuitry can be added to improve the ease of use of the power amplifier components.

[0145] For example, as shown in Figure 17, a power amplifier provided in this application includes a power amplification component 10. It also includes an integrated chip, a gate bias pad 1, a signal input pad, a gate bias pad 2, a drain bias pad, and a signal output pad. Additionally, it includes two capacitors, capacitor C01 and capacitor C02.

[0146] Specifically, the gate bias pad 1, signal input pad, and gate bias pad 2 are connected to the integrated chip via connecting lines. The integrated chip is also connected to the first signal input terminal 11a of the carrier transistor PA1 via connecting lines, and to the second signal input terminal 11a of the peak transistor PA2 via connecting lines.

[0147] Additionally, the stub is connected to the second signal output terminal 11b and the second signal output terminal 12b via connecting line 131. Furthermore, the stub is also connected to the drain bias pad. Moreover, a capacitor C01 is grounded along the path between the stub and the drain bias pad to ensure effective bias matching.

[0148] In addition, the second end of the first bonding line 132 is connected to the signal output pad through capacitor C02.

[0149] The gate bias pad 1 is used to connect with an external bias circuit to supply a bias voltage to the first signal input terminal 11a of the carrier transistor PA1, thereby controlling the operating state of the carrier transistor PA1.

[0150] The gate bias pad 2 is used to connect to an external bias circuit to supply a bias voltage to the second signal input terminal 12a of the peak transistor PA2, thereby controlling the operating state of the peak transistor PA2.

[0151] The drain bias pad is used to connect to an external bias circuit, thereby applying a bias voltage to the first signal output terminal 11b of the carrier transistor PA1 and the second signal output terminal 12b of the peak transistor PA2, thereby controlling the operating state of the carrier transistor PA1 and the peak transistor PA2.

[0152] An external signal source (such as an RF module) is connected to the signal input pad. The RF signal generated by the signal source is split into two paths after passing through the signal input pad and the integrated chip, and then transmitted to the carrier transistor PA1 and the peak transistor PA2 respectively. Finally, it is output from the signal output pad.

[0153] The integrated chip may include a power divider, input matching circuit, and gate bias circuit. In one implementation, the type or function of the integrated chip can be reasonably selected according to actual needs, which will not be elaborated here.

[0154] Capacitor C02 isolates the DC current input from the gate bias pad or drain bias pad, thereby ensuring that the output signal is an AC signal.

[0155] In specific settings, other circuits or integrated chips related to the power amplifier component 10 can be flexibly configured according to actual needs, which will not be elaborated here.

[0156] In summary, in one example, the amplifier may include any of the power amplification components 10 described above. Furthermore, the number of power amplification components 10 may be one, two, or more.

[0157] In addition, this application also provides a communication device. In one example, the communication device may specifically be a mobile phone, tablet computer, laptop computer, router, or other device with communication capabilities. The power amplifier component 10 can be configured independently within the communication device. Alternatively, the power amplifier component 10 can be configured within a power amplifier and then within the communication device.

[0158] In the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of different embodiments are consistent and can be referenced by each other. The technical features of different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0159] In this application, "multiple" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural.

[0160] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. The order of the process numbers described above does not imply the order of execution; the execution order of each process should be determined by its function and internal logic.

Claims

1. A power amplifier component, characterized in that, The device includes a substrate, a carrier transistor, a peak transistor, and a conductive layer. Both the carrier transistor and the peak transistor are located on a first surface of the substrate. The conductive layer is located on the side of the carrier transistor and the peak transistor facing away from the substrate. The carrier transistor has a first signal output terminal, and the peak transistor has a second signal output terminal. The first and second signal output terminals are connected to the conductive layer via a conductive structure. The junction point between the first and second signal output terminals is located on the surface of the second signal output terminal; or, the conductive distance between the junction point and the second signal output terminal is less than or equal to λ / 16, where λ is the wavelength of the signal transmitted in the conductive layer.

2. The power amplifier component according to claim 1, characterized in that, The parasitic capacitance in the carrier transistor, the parasitic capacitance in the peak transistor, and the conductive structure and conductive layer connected between the first signal output terminal and the second signal output terminal together form a capacitor-inductor-capacitor impedance inverter network.

3. The power amplifier assembly according to claim 1 or 2, characterized in that, The conductive layer includes a connecting line and a first combining line. The conductive structure includes a first conductive structure and a second conductive structure. The first signal output terminal is connected to one end of the connecting line through the first conductive structure, and the second signal output terminal is connected to the other end of the connecting line through the second conductive structure. The conductive structure further includes a third conductive structure, and the first end of the first combining line is connected to the second signal output terminal through the third conductive structure. Alternatively, the first end of the first combining line is connected to the second conductive structure, and the conductive distance between the first end of the first combining line and the second signal output terminal is less than or equal to λ / 16. Or, the first end of the first combining line is connected to the connecting line, and the conductive distance between the first end of the first combining line and the second signal output terminal is less than or equal to λ / 16.

4. The power amplifier component according to claim 3, characterized in that, The second end of the first combined line is the output end of the power amplifier component.

5. The power amplifier component according to claim 3, characterized in that, The power amplifier component further includes an additional peak transistor, the additional peak transistor including a third signal output terminal, and the conductive layer further includes a second combining line; the conductive structure further includes a fourth conductive structure; the second end of the first combining line is connected to the third signal output terminal through the fourth conductive structure; wherein, the first end of the second combining line is connected to the fourth conductive structure; or, the first end of the second combining line is connected to the first combining line; or, the conductive structure further includes a fifth conductive structure, and the first end of the second combining line is connected to the third signal output terminal through the fifth conductive structure.

6. The power amplifier component according to claim 5, characterized in that, When the first end of the second combining line is connected to the fourth conductive structure, or when the first end of the second combining line is connected to the first combining line, the conductive distance between the first end of the second combining line and the third signal output terminal is less than or equal to λ / 16.

7. The power amplifier assembly according to claim 5 or 6, characterized in that, The second end of the second combining line is the output end of the power amplifier component.

8. The power amplifier assembly according to any one of claims 1 to 7, characterized in that, The conductive layer includes conductive lines located on the same plane, or the conductive layer includes multiple layers of conductive lines stacked together.

9. The power amplifier assembly according to any one of claims 1 to 8, characterized in that, The power amplifier component further includes a package; the package is located on one side of the substrate and covers the carrier transistor and the peak transistor, and the conductive layer is located on the surface of the package.

10. The power amplifier assembly according to claim 9, characterized in that, The conductive structure passes through the package and is connected between the conductive layer and the carrier transistor and the peak transistor.

11. The power amplifier assembly according to any one of claims 1 to 10, characterized in that, The conductive structure includes at least one of a fan-out conductor, a metal via, and a conductive post.

12. The power amplifier assembly according to any one of claims 1 to 11, characterized in that, The substrate includes a ground layer, and the ground signal terminals of both the carrier transistor and the peak transistor are connected to the ground layer.

13. The power amplifier assembly according to any one of claims 1 to 12, characterized in that, The substrate includes a boss; the carrier transistor or the peak transistor is located on the surface of the boss.

14. The power amplifier assembly according to any one of claims 1 to 13, characterized in that, The conductive layer includes stubs for connecting the bias circuit; the stubs are connected to the signal output terminals of both the carrier transistor and the peak transistor.

15. The power amplifier assembly according to any one of claims 1 to 14, characterized in that, The power amplifier assembly further includes an input matching circuit; the input matching circuit is connected to the signal input terminal of the carrier transistor and the signal input terminal of the peak transistor.

16. A power amplifier, characterized in that, It includes at least one power amplifier component as described in any one of claims 1 to 15.

17. A communication device, characterized in that, It includes a radio frequency (RF) circuit and a power amplifier as described in claim 16, wherein the RF circuit is connected to the power amplifier.

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