Segmented driving level conversion circuit and control method thereof
By using a segmented driving level conversion circuit and two independent one-shot acceleration circuits, the overshoot and delay problems of traditional level converters under wide capacitive loads are solved, and low-latency, high-reliability signal transmission is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- DIOO MICROCIRCUITS CO LTD
- Filing Date
- 2026-01-15
- Publication Date
- 2026-05-01
AI Technical Summary
Traditional level converters suffer from signal mismatch, large delay and high power consumption when transmitting high-speed signals, making it difficult to meet the high-speed transmission requirements of SoC processes, especially when dealing with wide capacitive loads, where overshoot is severe.
The level conversion circuit employs segmented driving and includes two independent one-shot acceleration circuits, namely fast response and slow response acceleration paths. The output load is driven in parallel, and the appropriate acceleration path is selected according to the load capacitance to reduce transmission delay and overshoot.
It effectively reduces transmission delay and rise/fall time, reduces hardware overhead, improves circuit reliability, and avoids overshoot under different capacitor loads.
Smart Images
Figure CN121966546A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a level conversion circuit and its control method, particularly a segmented driving level conversion circuit and its control method, belonging to the field of semiconductor integrated circuit technology. Background Technology
[0002] Level conversion chips / devices are widely used in many fields such as consumer electronics, communications, industrial control and the Internet of Things. Their core advantage lies in their ability to efficiently adapt to signal conversion needs between different voltage domains, solving key problems in system interconnection.
[0003] Traditional level converters have limitations in terms of conversion speed, power consumption, and stability, making it difficult to achieve high-speed, low-power level conversion. Furthermore, some level converters suffer from signal mismatch and significant delays when processing high-speed signals, limiting the overall system performance. With the continuous iteration of SoC manufacturing processes, the demand for high-speed transmission is becoming increasingly urgent, necessitating new level conversion circuit architectures to achieve highly reliable high-speed signal transmission.
[0004] like Figure 4 The diagram shows a common level-shifting chip architecture, including a channel switch, a one-shot acceleration circuit, built-in pull-up resistors, and pull-up resistor control circuitry. Typically, the propagation delay of a level-shifting chip is directly related to the output load capacitance. A larger capacitance load results in a longer time for the one-shot circuit to charge the output from low to high, thus increasing the propagation delay. To reduce propagation delay, one approach is to increase the size of the driver transistor in the one-shot acceleration circuit and reduce the resistance when the one-shot acceleration circuit is turned on, thereby reducing the propagation delay. However, this approach has two significant drawbacks: 1) increased area; 2) increased overshoot. Furthermore, increasing the area of the driver transistor itself may also lead to overshoot in the one-shot logic circuit (…). Figure 4 The increased load seen by the rising edge detection circuit / falling edge detection circuit increases the one-shot turn-on time, which may limit its applicability to various scenarios. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to provide a segmented driving level conversion circuit and its control method, which can support wide capacitive loads.
[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A segmented-drive level conversion circuit includes a first-stage level conversion module at port A, a first-stage level conversion module at port B, a channel switch, a first pull-up one-shot acceleration circuit, a second pull-up one-shot acceleration circuit, a first pull-down one-shot acceleration circuit, and a second pull-down one-shot acceleration circuit. The two outputs of the first-stage level conversion module at port A are connected to the first pull-up one-shot acceleration circuit and the first pull-down one-shot acceleration circuit, respectively. The two outputs of the first-stage level conversion module at port B are connected to the second pull-up one-shot acceleration circuit and the second pull-down one-shot acceleration circuit, respectively. The input terminal of the first-stage level conversion module at port A is connected to one end of the channel switch at port A, and the input terminal of the first-stage level conversion module at port B is connected to the other end of the channel switch at port B. The first pull-up one-shot acceleration circuit, the second pull-up one-shot acceleration circuit, the first pull-down one-shot acceleration circuit, and the second pull-down one-shot acceleration circuit are respectively composed of a fast-response acceleration path and a slow-response acceleration path.
[0007] Furthermore, the first pull-up one-shot acceleration circuit includes a first pull-up one-shot path, a second pull-up one-shot path, a first pull-up resistor, and its control unit. The first pull-up one-shot path includes a first rising edge detection logic module and a first pull-up drive unit. The second pull-up one-shot path includes a second rising edge detection logic module and a second pull-up drive unit. The first pull-up drive unit, the second pull-up drive unit, and the first pull-up circuit and its control unit are connected in parallel on V. CCB Between port B and port A, one end of the first rising edge detection logic module is connected to the first level conversion module of port A, and the other end of the first rising edge detection logic module is connected to the first pull-up drive unit. One end of the second rising edge detection logic module is connected to the first level conversion module of port A, and the other end of the second rising edge detection logic module is connected to the second pull-up drive unit.
[0008] Furthermore, the second pull-up one-shot acceleration circuit includes a third pull-up one-shot path, a fourth pull-up one-shot path, and a second pull-up resistor and its control unit. The third pull-up one-shot path includes a third rising edge detection logic module and a third pull-up drive unit. The fourth pull-up one-shot path includes a fourth rising edge detection logic module and a fourth pull-up drive unit. The third pull-up drive unit, the fourth pull-up drive unit, and the second pull-up circuit and its control unit are connected in parallel on V. CCABetween port A and port B, one end of the third rising edge detection logic module is connected to the first-stage level conversion module of port B, and the other end of the third rising edge detection logic module is connected to the third pull-up drive unit. One end of the fourth rising edge detection logic module is connected to the first-stage level conversion module of port B, and the other end of the fourth rising edge detection logic module is connected to the fourth pull-up drive unit.
[0009] Furthermore, the first pull-down one-shot acceleration circuit includes a first pull-down one-shot path and a second pull-down one-shot path. The first pull-down one-shot path includes a first falling edge detection logic module and a first pull-down driving unit. The second pull-down one-shot path includes a second falling edge detection logic module and a second pull-down driving unit. The first pull-down driving unit and the second pull-down driving unit are connected in parallel between port B and ground. One end of the first falling edge detection logic module is connected to the first-stage level conversion module of port A, and the other end of the first falling edge detection logic module is connected to the first pull-down driving unit. One end of the second falling edge detection logic module is connected to the first-stage level conversion module of port A, and the other end of the second falling edge detection logic module is connected to the second pull-down driving unit.
[0010] Furthermore, the second pull-down one-shot acceleration circuit includes a third pull-down one-shot path and a fourth pull-down one-shot path. The third pull-down one-shot path includes a third falling edge detection logic module and a third pull-down driving unit. The fourth pull-down one-shot path includes a fourth falling edge detection logic module and a fourth pull-down driving unit. The third pull-down driving unit and the fourth pull-down driving unit are connected in parallel between port A and ground. One end of the third falling edge detection logic module is connected to the first-stage level conversion module of port B, and the other end of the third falling edge detection logic module is connected to the third pull-down driving unit. One end of the fourth falling edge detection logic module is connected to the first-stage level conversion module of port B, and the other end of the fourth falling edge detection logic module is connected to the fourth pull-down driving unit.
[0011] A control method for a segmented-drive level conversion circuit includes the following steps: When driving a small capacitor, the state relies on the channel switch to be on during times t1 to t2. The fast response acceleration path starts to activate at time t2. Due to the small output load capacitance, the fast response acceleration path directly pulls the output to V during times t2 to t4. CCB ; When driving a large capacitor, the state relies on the channel switch to be on during times t1 to t2. The fast response acceleration path starts to activate at time t2. Due to the large output load capacitance, the fast response acceleration path can only drive the output to V1 voltage before the slow response acceleration path starts. After time t3, the slow response acceleration path starts, and the one-shot acceleration circuit directly pulls the output to V1 during times t3 to t5. CCB .
[0012] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a segmented driving level conversion circuit and its control method. By using the segmented driving method, the output load is driven by two relatively independent one-shot acceleration circuits connected in parallel, which solves the overshoot problem of the prior art when the output capacitor load is small, reduces the transmission delay and rise / fall time, and has the advantages of low hardware overhead and high reliability. Attached Figure Description
[0013] Figure 1 This is a schematic diagram of a segmented driving level conversion circuit according to the present invention.
[0014] Figure 2 This is a graph showing the driving small capacitor of the control method for a segmented driving level conversion circuit according to the present invention.
[0015] Figure 3 This is a graph showing the driving curve of the large capacitor in the control method of the segmented driving level conversion circuit of the present invention.
[0016] Figure 4 This is a schematic diagram of the existing level conversion chip architecture. Detailed Implementation
[0017] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.
[0018] like Figure 1As shown, a segmented driving level conversion circuit of the present invention includes a first-stage level conversion module 1 at port A, a first-stage level conversion module 2 at port B, a channel switch 3, a first pull-up one-shot acceleration circuit, a second pull-up one-shot acceleration circuit, a first pull-down one-shot acceleration circuit, and a second pull-down one-shot acceleration circuit. The two outputs of the first-stage level conversion module 1 at port A are respectively connected to the first pull-up one-shot acceleration circuit and the first pull-down one-shot acceleration circuit. The two outputs of the first-stage level conversion module 2 at port B are respectively connected to the second pull-up one-shot acceleration circuit and the second pull-down one-shot acceleration circuit. The input terminal of the first-stage level conversion module 1 at port A is connected to one end of the channel switch 3 at port A, and the input terminal of the first-stage level conversion module 2 at port B is connected to the other end of the channel switch 3 at port B. The first pull-up one-shot acceleration circuit, the second pull-up one-shot acceleration circuit, the first pull-down one-shot acceleration circuit, and the second pull-down one-shot acceleration circuit are respectively composed of a fast response acceleration path and a slow response acceleration path.
[0019] The first pull-up one-shot acceleration circuit includes a first pull-up one-shot path, a second pull-up one-shot path, and a first pull-up resistor and its control unit 11. The first pull-up one-shot path includes a first rising edge detection logic module 4 and a first pull-up driving unit 9. The second pull-up one-shot path includes a second rising edge detection logic module 14 and a second pull-up driving unit 17. The first pull-up driving unit 9, the second pull-up driving unit 17, and the first pull-up circuit and its control unit 11 are connected in parallel on V. CCB Between port B and port A, one end of the first rising edge detection logic module 4 is connected to the first level conversion module 1 of port A, and the other end of the first rising edge detection logic module 4 is connected to the first pull-up drive unit 9. One end of the second rising edge detection logic module 14 is connected to the first level conversion module 1 of port A, and the other end of the second rising edge detection logic module 14 is connected to the second pull-up drive unit 17.
[0020] The second pull-up one-shot acceleration circuit includes a third pull-up one-shot path, a fourth pull-up one-shot path, and a second pull-up resistor and its control unit 10. The third pull-up one-shot path includes a third rising edge detection logic module 5 and a third pull-up drive unit 8. The fourth pull-up one-shot path includes a fourth rising edge detection logic module 15 and a fourth pull-up drive unit 16. The third pull-up drive unit 8, the fourth pull-up drive unit 16, and the second pull-up circuit and its control unit 10 are connected in parallel at V. CCABetween port A and port B, one end of the third rising edge detection logic module 5 is connected to the first-stage level conversion module 2 of port B, and the other end of the third rising edge detection logic module 5 is connected to the third pull-up drive unit 8. One end of the fourth rising edge detection logic module 15 is connected to the first-stage level conversion module 2 of port B, and the other end of the fourth rising edge detection logic module 15 is connected to the fourth pull-up drive unit 16.
[0021] The first pull-down one-shot acceleration circuit includes a first pull-down one-shot path and a second pull-down one-shot path. The first pull-down one-shot path includes a first falling edge detection logic module 6 and a first pull-down driver unit 13. The second pull-down one-shot path includes a second falling edge detection logic module 18 and a second pull-down driver unit 21. The first pull-down driver unit 13 and the second pull-down driver unit 21 are connected in parallel between port B and ground. One end of the first falling edge detection logic module 6 is connected to the first-stage level conversion module 1 at port A, and the other end of the first falling edge detection logic module 6 is connected to the first pull-down driver unit 13. One end of the second falling edge detection logic module 18 is connected to the first-stage level conversion module 1 at port A, and the other end of the second falling edge detection logic module 18 is connected to the second pull-down driver unit 21.
[0022] The second pull-down one-shot acceleration circuit includes a third pull-down one-shot path and a fourth pull-down one-shot path. The third pull-down one-shot path includes a third falling edge detection logic module 7 and a third pull-down driver unit 12. The fourth pull-down one-shot path includes a fourth falling edge detection logic module 19 and a fourth pull-down driver unit 20. The third pull-down driver unit 12 and the fourth pull-down driver unit 20 are connected in parallel between port A and ground. One end of the third falling edge detection logic module 7 is connected to the first-stage level conversion module 2 at port B, and the other end of the third falling edge detection logic module 7 is connected to the third pull-down driver unit 12. One end of the fourth falling edge detection logic module 19 is connected to the first-stage level conversion module 2 at port B, and the other end of the fourth falling edge detection logic module 19 is connected to the fourth pull-down driver unit 20.
[0023] Compared to conventional solutions, this invention improves the single one-shot acceleration circuit in conventional solutions into two specially designed one-shot acceleration circuits capable of supporting wide capacitive loads. By using two relatively independent one-shot acceleration circuits connected in parallel to drive the output load, the driving transistors (i.e., pull-up and pull-down driving units) in the fast-response one-shot path are small, the one-shot logic units (i.e., rising edge detection logic modules and falling edge detection logic modules) have fast response times, high on-resistance of the driving transistors, and weak driving capability. Conversely, the driving transistors in the slow-response path are large, the one-shot logic units have fast response times, and low on-resistance of the driving transistors.
[0024] When the level shifter chip drives a small capacitive load, the propagation delay is mainly limited by the one-shot response time, in which case the fast-response one-shot path plays a major role. When the level shifter chip drives a large capacitive load, both the fast-response one-shot path and the slow-response one-shot path work simultaneously. Since the output port voltage does not start from 0 when the slow-response one-shot path starts working, the propagation delay also decreases, and the overshoot is also reduced.
[0025] A control method for a segmented-drive level conversion circuit includes the following steps: like Figure 2 As shown, when driving the small capacitor, the state relies on the channel switch to be on during times t1 to t2. At this time, since the one-shot acceleration in the traditional circuit architecture has not yet started, the rising edge rises slowly. Because the channel switch usually uses NMOS, the rise stops when the voltage rises to near the NMOS cutoff state. The traditional circuit's one-shot acceleration circuit starts from t3. After the one-shot acceleration circuit starts, the output is quickly pulled up to V during the t3 to t5 stages. CCB In this invention, the fast response acceleration path starts at time t2. Due to the small output load capacitance, the fast response acceleration path directly pulls the output to V during times t2 to t5. CCB .
[0026] like Figure 3 As shown, in a conventional one-shot acceleration circuit, when driving a large capacitor, the state relies on the channel switch being on during times t1 to t2. At this time, since one-shot acceleration has not yet started, the rising edge rises slowly. Because the channel switch typically uses an NMOS transistor, the rise stops when the voltage approaches the NMOS's cutoff state. The traditional one-shot acceleration circuit starts from t4. After the one-shot acceleration circuit starts, the output is quickly pulled up to V during the t4 to t6 stages.CCB In this invention, the fast response acceleration path starts at time t2. Due to the large output load capacitance, the fast response acceleration path can only drive the output to V1 voltage before the slow response acceleration path starts. After time t3, the slow response acceleration path starts. At this time, the fast response acceleration path and the slow response acceleration path work together, but the slow response acceleration path plays a major role. The one-shot acceleration circuit directly pulls the output to V1 voltage between times t3 and t5. CCB .
[0027] Figure 2 and Figure 3 In the diagram, the solid line represents the input waveform, the discontinuous line represents the output waveform of the present invention, and the dashed line represents the output waveform of the conventional technical solution. It can be seen that the transmission delay is significantly reduced after using the solution of the present invention.
[0028] Meanwhile, in traditional circuits, to cover a large capacitive load range, the driving capabilities of one-shot pull-up and pull-down drive units are usually set to be quite strong. This directly leads to output overshoot, which can severely affect communication functionality. This invention can optimize overshoot; its principle is as follows: When the capacitive load is small, the system is primarily driven by a fast-response one-shot acceleration circuit. The pull-up and pull-down drive units in this circuit typically have weak driving capabilities, thus preventing overshoot during low capacitive load conditions. When the capacitive load is large, due to the presence of the fast-response one-shot acceleration circuit, it first raises the voltage to V1, while the slow-response one-shot acceleration circuit only needs to raise the output voltage from V1 to V... CCB The slow-response one-shot acceleration circuit has a lower step response step, and the overshoot is also reduced, thus avoiding overshoot when the capacitive load is large.
[0029] This invention provides a segmented driving level conversion circuit and its control method. By using a segmented driving method, the output load is driven in parallel by two relatively independent one-shot acceleration circuits, which solves the overshoot problem in the prior art when the output capacitor load is small. This reduces transmission delay and rise / fall time, while also having the advantages of low hardware overhead and high reliability.
[0030] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.
Claims
1. A segmented driving level conversion circuit, characterized in that: It includes a first-stage level conversion module for port A, a first-stage level conversion module for port B, a channel switch, a first pull-up one-shot acceleration circuit, a second pull-up one-shot acceleration circuit, a first pull-down one-shot acceleration circuit, and a second pull-down one-shot acceleration circuit. The two outputs of the first-stage level conversion module for port A are connected to the first pull-up one-shot acceleration circuit and the first pull-down one-shot acceleration circuit, respectively. The two outputs of the first-stage level conversion module for port B are connected to the second pull-up one-shot acceleration circuit and the second pull-down one-shot acceleration circuit, respectively. The input terminal of the first-stage level conversion module for port A is connected to one end of the channel switch and to port A. The input terminal of the first-stage level conversion module for port B is connected to the other end of the channel switch and to port B. The first pull-up one-shot acceleration circuit, the second pull-up one-shot acceleration circuit, the first pull-down one-shot acceleration circuit, and the second pull-down one-shot acceleration circuit are respectively composed of a fast response acceleration path and a slow response acceleration path.
2. The segmented driving level conversion circuit according to claim 1, characterized in that: The first pull-up one-shot acceleration circuit includes a first pull-up one-shot path, a second pull-up one-shot path, a first pull-up resistor, and its control unit. The first pull-up one-shot path includes a first rising edge detection logic module and a first pull-up drive unit. The second pull-up one-shot path includes a second rising edge detection logic module and a second pull-up drive unit. The first pull-up drive unit, the second pull-up drive unit, and the first pull-up circuit and its control unit are connected in parallel on V. CCB Between port B and port A, one end of the first rising edge detection logic module is connected to the first level conversion module of port A, and the other end of the first rising edge detection logic module is connected to the first pull-up drive unit. One end of the second rising edge detection logic module is connected to the first level conversion module of port A, and the other end of the second rising edge detection logic module is connected to the second pull-up drive unit.
3. The segmented driving level conversion circuit according to claim 1, characterized in that: The second pull-up one-shot acceleration circuit includes a third pull-up one-shot path, a fourth pull-up one-shot path, and a second pull-up resistor and its control unit. The third pull-up one-shot path includes a third rising edge detection logic module and a third pull-up drive unit. The fourth pull-up one-shot path includes a fourth rising edge detection logic module and a fourth pull-up drive unit. The third pull-up drive unit, the fourth pull-up drive unit, and the second pull-up circuit and its control unit are connected in parallel at V. CCA Between port A and port B, one end of the third rising edge detection logic module is connected to the first-stage level conversion module of port B, and the other end of the third rising edge detection logic module is connected to the third pull-up drive unit. One end of the fourth rising edge detection logic module is connected to the first-stage level conversion module of port B, and the other end of the fourth rising edge detection logic module is connected to the fourth pull-up drive unit.
4. The segmented driving level conversion circuit according to claim 1, characterized in that: The first pull-down one-shot acceleration circuit includes a first pull-down one-shot path and a second pull-down one-shot path. The first pull-down one-shot path includes a first falling edge detection logic module and a first pull-down driver unit. The second pull-down one-shot path includes a second falling edge detection logic module and a second pull-down driver unit. The first pull-down driver unit and the second pull-down driver unit are connected in parallel between port B and ground. One end of the first falling edge detection logic module is connected to the first-stage level conversion module of port A, and the other end of the first falling edge detection logic module is connected to the first pull-down driver unit. One end of the second falling edge detection logic module is connected to the first-stage level conversion module of port A, and the other end of the second falling edge detection logic module is connected to the second pull-down driver unit.
5. The segmented driving level conversion circuit according to claim 1, characterized in that: The second pull-down one-shot acceleration circuit includes a third pull-down one-shot path and a fourth pull-down one-shot path. The third pull-down one-shot path includes a third falling edge detection logic module and a third pull-down driver unit. The fourth pull-down one-shot path includes a fourth falling edge detection logic module and a fourth pull-down driver unit. The third and fourth pull-down driver units are connected in parallel between port A and ground. One end of the third falling edge detection logic module is connected to the first-stage level conversion module of port B, and the other end of the third falling edge detection logic module is connected to the third pull-down driver unit. One end of the fourth falling edge detection logic module is connected to the first-stage level conversion module of port B, and the other end of the fourth falling edge detection logic module is connected to the fourth pull-down driver unit.
6. A control method for a segmented driving level conversion circuit according to any one of claims 1-5, characterized in that... Includes the following steps: When driving a small capacitor, the state relies on the channel switch to be on during times t1 to t2. The fast response acceleration path starts to activate at time t2. Due to the small output load capacitance, the fast response acceleration path directly pulls the output to V during times t2 to t4. CCB ; When driving a large capacitor, the state relies on the channel switch to be on during times t1 to t2. The fast response acceleration path starts to activate at time t2. Due to the large output load capacitance, the fast response acceleration path can only drive the output to V1 voltage before the slow response acceleration path starts. After time t3, the slow response acceleration path starts, and the one-shot acceleration circuit directly pulls the output to V1 during times t3 to t5. CCB .