Vector processing unit for wireless communication

Abstract

The invention relates to the technical field of wireless communication signal processing, in particular to a vector processing unit for wireless communication. Comprising a vector processing controller used for receiving and decoding an external instruction and generating a mode configuration signal corresponding to the external instruction according to a decoding result; the vector arithmetic unit is connected to the vector processing controller and is used for executing 16-bit, 32-bit or 64-bit precision arithmetic operation according to the mode configuration signal; a vector bit operation unit connected to the vector processing controller for performing a bit-level operation according to the mode configuration signal; and the vector operation unit is connected to the vector processing controller and is used for processing movement, filling and storage of vector register data according to the mode configuration signal. The vector processing unit provided by the invention can flexibly adapt to various baseband processing algorithms in wireless communication, and overcomes the defects of fixed function and poor scene adaptability of a traditional special accelerator.

Description

Technical Field

[0001] This application relates to the field of wireless communication signal processing technology, and in particular to a vector processing unit for wireless communication. Background Technology

[0002] With the development of wireless communication technology, the computing demands in machine learning and artificial intelligence applications are growing exponentially. Next-generation mobile communications place higher demands on the coordinated optimization of throughput, latency, and power consumption, and must adapt to processing flows of varying specifications and complexities across different application scenarios.

[0003] A Vector Processing Unit (VPU) is hardware specifically designed for batch data processing. Its instructions operate not on a single data point, but on an entire group of data, also known as a vector. Currently, traditional general-purpose processing units, in order to better accommodate more application scenarios, typically retain only basic computational processing functions. Therefore, they suffer from limited efficiency when implementing complex algorithms, poor performance in application scenarios with varying requirements, and insufficient scalability. Summary of the Invention

[0004] In view of the above-mentioned shortcomings and deficiencies of the prior art, this application provides a vector processing unit for wireless communication, the main purpose of which is to solve the problems that current general-purpose processing units are limited in efficiency when implementing complex algorithms and perform poorly in application scenarios with different requirements.

[0005] To achieve the above objectives, the main technical solutions adopted in this application include: In a first aspect, embodiments of this application provide a vector processing unit for wireless communication, comprising: A vector processing controller is used to receive external instructions, decode them, and generate a mode configuration signal corresponding to the external instructions based on the decoding results. Three arithmetic units, including: A vector arithmetic unit, connected to the vector processing controller, is used to perform arithmetic operations with 16-bit, 32-bit, or 64-bit precision according to the mode configuration signal; A vector bit manipulation unit, connected to the vector processing controller, is used to perform bit-level operations according to the mode configuration signal; A vector operation unit, connected to the vector processing controller, is used to move, fill, and store signal processing vector register data according to the mode configuration; The vector arithmetic unit, vector bit operation unit, and vector operation unit all include physically implemented configuration registers for directly receiving and storing mode configuration signals from the vector processing controller.

[0006] Optionally, the vector processing controller includes a state machine circuit for characterizing the working state of the vector processing controller; wherein the working state includes at least an idle state (IDLE), a computation state (COMPUTE), and a completion state (DONE); the state machine circuit jumps from the IDLE state to the COMPUTE state when it receives a start signal in the decoding result, jumps to the DONE state in the next cycle, and returns to the IDLE state after any computation unit outputs a valid signal.

[0007] Optionally, the vector processing controller further includes a decoder circuit, wherein the input of the decoder circuit is the vector calculation opcode in the decoding result, and the decoder circuit outputs a mode configuration signal for controlling each arithmetic unit according to the state output by the state machine circuit.

[0008] Optionally, the vector processing controller further includes: an output control circuit, including a multi-input OR gate and a multiplexer; the input terminal of the multi-input OR gate is connected to the result validity signal of each arithmetic unit to generate an overall arithmetic completion flag; the selection terminal of the multiplexer receives a signal identifying the type of arithmetic unit, and its data input terminal is connected to the output terminal of each arithmetic unit to write back the currently valid arithmetic result.

[0009] Optionally, the arithmetic operations performed by the vector arithmetic unit include: multiplication and addition, division, exponentiation, taking absolute value, and taking conjugate operations; the vector arithmetic unit includes a multiplication and addition unit, which is constructed as a three-stage pipelined structure, wherein: the first stage deploys a combinational logic multiplier; the second stage deploys an adder and a data selector, used to select to perform addition or accumulation operations according to the mode configuration signal registered in the configuration register; and the third stage deploys a second-stage adder.

[0010] Optionally, the vector arithmetic unit further includes: a division unit, which uses single-cycle combinational logic to implement integer division operations; an absolute value unit, which consists of two parallel absolute value subunits, each subunit being 16 bits; an exponent unit, which integrates two lookup tables, a multiplier, and an adder; and a conjugate unit, which includes parallel real and imaginary part paths. The real part path directly outputs the high 16 bits of the input 32-bit complex data, and the imaginary part path includes an inverting circuit that inverts the low 16 bits of the input 32-bit complex data and outputs the inverted result. The multiply-add unit, the conjugate unit, and the adder in the vector arithmetic unit work together to implement complex multiplication and complex multiplication-accumulation operations.

[0011] Optionally, the vector bit operation unit includes a displacement unit, which includes a barrel displacement unit and two independent displacement paths; wherein, the mode configuration signal stored in the displacement unit configuration register controls the multiplexer to output the spliced ​​result after independently displacing the real and imaginary parts of the complex number, or the result after displacing the overall data.

[0012] Optionally, the vector operation unit includes an access control unit, which includes a state machine or counter for controlling the transmission of 256-bit data and 32-bit registers in sequences of eight 32-bit data units.

[0013] Optionally, the vector operation unit includes a padding unit, which adopts a dual-path structure, wherein the first path includes a comparator for data saturation truncation, and the second path includes logic circuitry for sign bit extension; a mode configuration signal registered in the padding unit configuration register controls a top-level multiplexer to select either the clipping result or the sign extension result as the output.

[0014] Optionally, before the dual-path structure of the filling unit, an input data splitting circuit is provided to split the input 32-bit data into two 16-bit half-words, and send them to the comparator for saturation truncation and the logic circuit for sign bit extension for parallel processing, respectively.

[0015] By employing the above technical solution, this application provides a vector processing unit for wireless communication, including a vector processing controller for receiving and decoding external instructions, and generating a mode configuration signal corresponding to the external instructions based on the decoding result; and three arithmetic units, including: a vector arithmetic unit connected to the vector processing controller for performing 16-bit, 32-bit, or 64-bit precision arithmetic operations according to the mode configuration signal; a vector bit manipulation unit connected to the vector processing controller for performing bit-level operations according to the mode configuration signal; and a vector manipulation unit connected to the vector processing controller for processing the movement, filling, and storage of vector register data according to the mode configuration signal; wherein the vector arithmetic unit, the vector bit manipulation unit, and the vector manipulation unit all include physically implemented configuration registers for directly receiving and storing the mode configuration signal from the vector processing controller. Compared with related technologies, by setting configuration registers and directly storing the mode configuration signal from the vector processing controller, the vector processing unit can dynamically change the internal data paths and arithmetic functions of the vector arithmetic unit, the vector bit manipulation unit, and the vector manipulation unit according to different external instructions. This allows a single hardware platform to flexibly adapt to a variety of baseband processing algorithms in wireless communication, overcoming the shortcomings of traditional dedicated accelerators, such as fixed functions and poor scenario adaptability. Attached Figure Description

[0016] Figure 1 A schematic diagram of a vector processing unit for wireless communication provided in an embodiment of this application; Figure 2 The state transition diagram of the internal state machine of the vector processing controller provided in this application embodiment.

[0017] Figure 3 This is a schematic diagram illustrating the implementation of the decoder circuit provided in an embodiment of this application.

[0018] Figure 4 This is a schematic diagram illustrating the implementation of the output control circuit provided in an embodiment of this application.

[0019] Figure 5 A schematic diagram of the data format for writing the operation result back to the register provided in the embodiments of this application.

[0020] Figure 6 This is a schematic diagram of the structure of the multiply-accumulate unit provided in an embodiment of this application.

[0021] Figure 7 The circuit structure diagram of the adder unit ADD_U0 provided in the embodiments of this application is shown.

[0022] Figure 8 The circuit structure diagram of the adder unit ADD_U1 provided in the embodiment of this application is shown.

[0023] Figure 9 The basic circuit implementation diagram of the single-cycle adder provided in the embodiments of this application is shown.

[0024] Figure 10 The timing diagrams for the operation of 8-bit and 16-bit adders provided in the embodiments of this application are shown.

[0025] Figure 11 The timing diagram of the operation of a 32-bit adder provided in the embodiments of this application is shown.

[0026] Figure 12 The timing diagram of the operation of a 64-bit adder provided in the embodiments of this application is shown.

[0027] Figure 13 The circuit structure diagram of the multiplication unit provided in the embodiments of this application is shown.

[0028] Figure 14 The circuit structure diagram of the absolute value unit provided in the embodiments of this application is shown.

[0029] Figure 15 The circuit structure diagram of the conjugate unit provided in the embodiments of this application is shown.

[0030] Figure 16 The circuit structure diagram of the exponent unit provided in the embodiments of this application is shown.

[0031] Figure 17 The circuit structure diagram of the displacement unit provided in the embodiment of this application is shown.

[0032] Figure 18 The circuit structure diagram of the comparison unit provided in the embodiments of this application is shown.

[0033] Figure 19 The circuit structure diagram of the packaging unit provided in the embodiment of this application is shown.

[0034] Figure 20 The circuit structure diagram of the logic unit provided in the embodiments of this application is shown.

[0035] Figure 21 This is a circuit diagram of the access control unit provided in an embodiment of this application.

[0036] Figure 22 This is an operation timing diagram of the access control unit provided in an embodiment of this application.

[0037] Figure 23 The circuit structure diagram of the filling unit provided in the embodiment of this application is shown.

[0038] Figure 24 The circuit structure diagram of the moving unit provided in the embodiment of this application is shown.

[0039] Figure 25 This is an operation timing diagram of the mobile unit provided in an embodiment of this application. Detailed Implementation

[0040] To better understand the above technical solutions, exemplary embodiments of this application will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this application can be understood more clearly and thoroughly, and that the scope of this application can be fully conveyed to those skilled in the art.

[0041] As mentioned in the background, traditional general-purpose processors are inefficient at executing complex baseband algorithms under stringent real-time and energy efficiency constraints; fixed-function acceleration solutions (dedicated accelerators with fixed functions) lack scalability and have high upgrade costs when standards are iterated and scenarios change. To improve this problem, this application proposes a vector processing unit for wireless communication, which can be efficiently used in reconfigurable vector processors to meet the computational needs of wireless communication algorithms. Figure 1 As shown, the vector processing unit includes: Vector processing controller, i.e. Figure 1The vector processing unit controller in the middle is used to receive external instructions and decode them, and generate mode configuration signals corresponding to the external instructions based on the decoding results.

[0042] External instructions refer to vector operation instructions issued by the upper-level processing control unit (Program Control Unit, PCU). The decoding results may include vector computation opcodes, data bit width identifiers, operation types, and operand addresses. Mode configuration signals are used to directly configure the data path selection, operation mode, and pipeline control within each arithmetic unit. The vector processing controller controls the entire vector processing unit by handling decoding, data control, and computation state transitions. The decoder allows for precise scheduling of each arithmetic unit, and input / output control accurately controls the data bit width and format, ensuring the correctness of data read and write operations. This unit can fulfill the complete functions of a front-end arithmetic unit.

[0043] Three arithmetic units, including: The vector arithmetic unit, connected to the vector processing controller, performs 16-bit, 32-bit, or 64-bit precision arithmetic operations according to mode configuration signals. The vector bit manipulation unit, connected to the vector processing controller, performs bit-level operations according to mode configuration signals. The vector manipulation unit, also connected to the vector processing controller, processes the movement, filling, and storage of vector register data according to mode configuration signals.

[0044] Specifically, the vector arithmetic unit is responsible for performing multiplication-addition, division, exponentiation, absolute value, and conjugate operations. Furthermore, through the coordinated configuration of the multiplication-addition unit, conjugate unit, and addition unit, it can efficiently perform native complex number operations such as complex multiplication and complex multiplication-accumulation. The vector bit manipulation unit supports operations including bit shifting, logical operations, comparison, and packing. The vector manipulation unit handles register shifting, data bit width padding, and load / store control type operations.

[0045] The vector arithmetic unit, vector bit operation unit, and vector operation unit all contain physically implemented configuration registers, which are used to directly receive and store mode configuration signals from the vector processing controller.

[0046] In this embodiment, by setting a configuration register and directly storing the mode configuration signal of the vector processing controller, the vector processing unit can dynamically change the internal data paths and computational functions of the vector arithmetic unit, vector bit manipulation unit, and vector operation unit according to different external instructions. This enables a single hardware platform to flexibly adapt to a variety of baseband processing algorithms in wireless communication, overcoming the shortcomings of traditional dedicated accelerators that have fixed functions and poor scenario adaptability.

[0047] Optionally, such as Figure 1As shown, the vector processing controller includes a state machine circuit for characterizing the working states of the vector processing controller; wherein the working states include at least an idle state (IDLE), a computation state (COMPUTE), and a completion state (DONE). When the state machine circuit receives the start signal in the decoding result, it jumps from the IDLE state to the COMPUTE state, jumps to the DONE state in the next cycle, and returns to the IDLE state after any computation unit outputs a valid signal.

[0048] In this embodiment, a state machine is provided to ensure the correct storage and retrieval of internal registers and control signals of the vector processor control unit module, such as... Figure 2 As shown, a simple state machine is used only as a flag for the current computational state, facilitating signal registration and control in sequential logic. In other words, the design of this state machine circuit ensures clear controller timing and efficient state switching, providing a stable and reliable control timing foundation for each arithmetic unit.

[0049] Specifically, the state machine has three states: IDLE (idle state), COMPUTE (decoding and computation state), and DONE (complete state). Upon receiving the start (vcu_comp_en) signal, indicating the need for decoding instructions, the machine transitions from the IDLE state to the COMPUTE state, outputting the arithmetic unit enable signal and the computation mode. In the next cycle after the start signal, the machine transitions from the COMPUTE state to the DONE state, loading the computation mode configuration register. When the arithmetic unit output is valid, the machine transitions from the DONE state to the IDLE state, resetting the computation mode configuration register.

[0050] Optionally, the vector processing controller further includes a decoder circuit, the input of which is the vector calculation opcode in the decoding result, and outputs a mode configuration signal for controlling each arithmetic unit according to the state output by the state machine circuit.

[0051] Figure 3 A schematic diagram of a decoder circuit is shown. In this embodiment, the decoder decodes external instructions and then forwards them to various computing or operational units based on the type of computation or operation. For example... Figure 3 The vector computation opcode matches the corresponding path and, based on the state machine circuit, outputs mode configuration signals to control each arithmetic unit. By combining the state machine with a decoder, a precise mapping between instruction parsing and hardware configuration is achieved, significantly improving the response speed and execution accuracy of the vector processing unit for complex instruction sets.

[0052] Optionally, the vector processing controller further includes: an output control circuit, including a multi-input OR gate and a multiplexer; the input terminals of the multi-input OR gate are connected to the result validity signals of each arithmetic unit to generate an overall operation completion flag; the selection terminal of the multiplexer receives a signal identifying the type of arithmetic unit, and its data input terminals are respectively connected to the output terminals of each arithmetic unit to write back the currently valid operation result.

[0053] Output control circuit such as Figure 4 As shown, in Figure 4 In this context, the MSB is the most significant bit. The valid output signal from the arithmetic unit passes through a multi-input OR gate, and the result, after little-endian alignment, is used as a selection signal to select the final unit output result to write back to the register. For example, when the arithmetic unit result is valid, the output is padded with 176 leading zeros before being written back. See [link to relevant documentation]. Figure 5 This output control mechanism effectively solves the problems of result arbitration and data synchronization when multiple computing units execute in parallel, ensuring that the correct computing results can be written back to the destination in the standard format at any time, thereby improving the reliability of data output and the overall efficiency of the system.

[0054] Optionally, the arithmetic operations performed by the vector arithmetic unit include: multiplication and addition, division, exponentiation, absolute value taking, and conjugate taking; the vector arithmetic unit includes a multiplication and addition unit, which is constructed as a three-stage pipeline structure, wherein: the first stage deploys a combinational logic multiplier; the second stage deploys an adder and a data selector, used to select to perform addition or accumulation operation according to the mode configuration signal registered in the configuration register; and the third stage deploys a second-stage adder.

[0055] Furthermore, the vector arithmetic unit also includes: a division unit, which uses single-cycle combinational logic to implement integer division operations; an absolute value unit, which consists of two parallel absolute value sub-units, each sub-unit being 16 bits; an exponent unit, which integrates two lookup tables, a multiplier, and an adder; and a conjugate unit, which includes parallel real and imaginary part paths. The real part path directly outputs the high 16 bits of the input 32-bit complex data, while the imaginary part path includes an inverting circuit that inverts the low 16 bits of the input 32-bit complex data and outputs the inverted result. The multiply-add unit, the conjugate unit, and the adder in the vector arithmetic unit work together to implement complex multiplication and complex multiplication-accumulation operations.

[0056] In this embodiment, the vector arithmetic unit comprises five sub-modules: a multiplication-addition unit, a division unit, an exponentiation unit, an absolute value unit, and a conjugate unit. The conjugate unit, when combined with other units, can also perform complex number operations. The specific circuit configuration of each unit will be described below.

[0057] The structure of the multiply-accumulate unit is as follows: Figure 6 As shown, it supports 16 or 64-bit input and outputs 32 or 64-bit multiply-accumulate results in different cycles depending on the operation type. Figure 6 The diagram shows the size of each unit and the number of cycles required for processing; the right side shows the longest number of cycles. For example, processing a multiply-add operation requires going through all processing steps, taking a maximum of 2 cycles to output the result. The multiply-add unit can be reused for addition, multiplication, and multiply-add; multiply-add requires two cycles to output the calculation result. To reflect the high reuse design concept, the multiply-add unit is divided into three stages, namely the three-stage pipeline structure mentioned above: Whether to perform a 64-bit addition operation can be determined by selecting either a 16-bit summation result or 64-bit data input via the input-stage adder. Before inputting the 16-bit multiplication result in the second stage, a 64-to-16 bit sign bit truncation operation is performed. In the third stage, whether to perform a 32-bit or 64-bit accumulation operation depends on whether the configuration register requires accumulation; the input-stage adder selects whether to input the summation result from the previous stage or 64-bit data from the accumulation destination register. The final stage outputs the result of the multiply-accumulate instruction. Figure 6 The input signals can be compared with those in Table 1.

[0058] Table 1 Input / output ports of the multiply-accumulate unit

[0059] Furthermore, to configure the relevant arithmetic units, the register loading configurations in Tables 2 and 3 are set. Each 16-bit and 32-bit physical unit adder has this configuration register. Output behavior control allows large-bit-width adders to output smaller-bit-width calculation results. The final calculation result output width of ADD_U0 is 64 bits, and the output width of ADD_U1 is 32 bits. After configuring the calculation mode, the output behavior must also be controlled accordingly. For example, in add16 mode, the output period is the current period, so the 64-bit final output port needs to be connected to the 16-bit adder output that produces the result in the current period. In add32 mode, the output period is 1, so it needs to be connected to the 32-bit output that produces the result one period later.

[0060] Table 2 Configure Enable Register

[0061] Table 3 Multiplier Module Enable Configuration Register

[0062] Addition Unit: Due to unit design optimization and the special nature of the instructions, two sets of addition units are required. For example... Figure 7 and Figure 8 As shown, to avoid wasting hardware resources, these two groups are not actually symmetrically designed based on the different maximum data bit widths of the executed instructions. ADD_U0 performs a maximum of 64-bit addition, and the ADD_U0 unit can be configured as 16-bit, 32-bit, or 64-bit addition depending on the computational requirements. ADD_U1 performs a maximum of 32-bit addition, and the ADD_U1 unit can be configured as 16-bit or 32-bit addition depending on the computational requirements. The 16-bit adder in the adder unit is an independent unit, while the 32-bit and 64-bit adders are implemented by splicing together physical adder units. A single-cycle adder circuit is implemented as follows: Figure 9 As shown.

[0063] The timing diagrams for adders are categorized into 8-bit, 16-bit, 32-bit, and 64-bit adders. For 8-bit adders, combinational logic implements a single-cycle 8-bit addition process. For 16-bit adders, after receiving the mode configuration and input data, the adder outputs the calculation result and an enable signal in the current cycle. The timing diagrams for 8-bit and 16-bit adders are shown below. Figure 10 As shown in the diagram. For 32-bit addition, two parallel 16-bit adders in ADD_U0 are used. The high and low 16 bits are concatenated in the current cycle to produce the 32-bit addition result, and the carry bit of the high 16 bits is taken as the carry output. The timing diagram is shown in the diagram. Figure 11 As shown in the diagram. For 64-bit addition, a parallel 32-bit adder is used. The current cycle calculates a 16-bit result, which is then stored. Simultaneously, another 32-bit result is calculated in the next cycle. After one cycle, the 64-bit addition result is output. The timing diagram is shown below. Figure 12 As shown.

[0064] Multiplication unit: such as Figure 13 As shown, the multiplication unit uses 16-bit combinational logic symbolic multipliers, outputting a 32-bit result after combinational logic processing. The multipliers in the multiply-accumulate unit (MAC Unit) are reused; after mode configuration, the multipliers begin operation. Finally, output behavior control is used to directly connect the multiplier output to the MAC unit output.

[0065] The structure of the absolute value unit is as follows Figure 14 As shown, this is used to perform operations such as taking the absolute value of 32-bit signed data or taking the absolute value of the difference between 32-bit signed numbers. It uses two 32-bit inputs and has a 32-bit output port with a result validity signal. Its structure consists of two 16-bit units within the absolute value unit, forming a 32-bit unit. Each unit has a configuration register (config0, config1). See Tables 4 and 5 for specific port signals.

[0066] Table 4 Absolute Value Unit Input / Output Ports

[0067] Table 5. Absolute Value Unit Internal Register Settings

[0068] The division unit can reuse existing divider circuits to perform integer or half-precision floating-point division operations. The module uses 32-bit input and 32-bit output, with a 1-bit valid signal for the result. Table 6 lists the input and output ports of the division unit, along with a description of the direction bit width.

[0069] Table 6. List of ports for the division unit

[0070] For integer division, the module directly uses the symbol library (standard cell library) for synthesis, and the calculation part adopts single-cycle combinational logic. The output is the reciprocal of the input value after one cycle. For floating-point division, it uses half-precision (16-bit) floating-point arithmetic conforming to the IEEE 754 standard, with 16-bit input and output.

[0071] The circuit structure of the conjugate unit is as follows Figure 15 As shown, this is used for complex number conjugation operations. When the current stage decoder decodes the current instruction as a conjugation operation, the input 32-bit complex number (the high 16 bits are the real part, and the low 16 bits are the imaginary part) is processed. The output real part remains unchanged, and the imaginary part is inverted to form the conjugation result (conj_rslt). The output result valid (conj_valid) indicates whether the current conjugation operation result is valid; it is high when valid. The conjugation unit is designed with an enable port and a 1-bit signal to indicate that the result is valid. Table 7 lists the input and output ports of the conjugation unit, along with a description of the direction bit width. Table 8 shows the internal register settings and descriptions of this unit.

[0072] Table 7. List of conjugate unit ports

[0073] Table 8 Internal Registers of Conjugate Units

[0074] The circuit structure of the exponent unit is as follows: Figure 16 As shown, to implement the exponential function The calculation employs a piecewise linear approximation method. To achieve transcendental function calculations by approximating the curve with a straight line, a similar approach is also needed. The function first requires a lookup table consisting of two RAMs to store the data. The value also requires a 40-bit multiplier and a 40-bit adder. During computation, the input data is used... The value is searched for in the lookup table. The values ​​are then multiplied and added according to the linear function formula to obtain the calculation result. The entire module's computation section is implemented using combinational logic, and finally, the result from the arithmetic unit is output. Figure 16 The system has two lookup tables (u_ram0 and u_ram1) to store coefficients a and b, and subsequent operations are performed using a multiplier. Finally, perform floating-point addition. .

[0075] Optionally, the vector bit operation unit includes a shift unit, which includes a barrel shifter and two independent shift paths; wherein, the mode configuration signal registered in the shift unit configuration register controls the multiplexer output to perform the splicing of the complex real part and imaginary part independently shifted, or to perform the shift of the overall data.

[0076] In this embodiment, the vector bit operation unit is mainly used to accelerate the execution of various bit operation instructions, combined with Figure 1 It has four sub-modules: displacement unit, logic unit, comparison unit, and packing unit.

[0077] The shift unit provides both logical and arithmetic shifts, and supports separate shifts of the real and imaginary parts of complex numbers. After receiving the operation mode, the arithmetic unit needs to configure its internal registers, including the shift direction, extension mode, and word length mode. Shift operations support both arithmetic and logical shifts. When the word length is configured to 0, it supports shifting and outputting the MSB16 and LSB16 bits respectively; otherwise, it shifts the entire 32 bits. The circuit structure of the shift unit is as follows: Figure 17 As shown, a barrel shifter is used to achieve a shift operation of any specified number of bits within a single clock cycle, unlike ordinary cascaded multiplexers which can only shift a fixed number of bits. The barrel shifter achieves arbitrary shifting in a single cycle, greatly improving the throughput and efficiency of the shift operation and meeting the low latency requirements of real-time signal processing. Secondly, by configuring the word length mode, this unit can flexibly support the shifting of 32-bit whole data, or the independent and parallel shifting of the real part (MSB16) and imaginary part (LSB16) of a complex number. This hardware-level independent shifting capability of complex components eliminates the need for cumbersome data splitting and merging operations in software when processing complex data commonly used in communication algorithms; a single instruction can complete the task, greatly simplifying the programming model and improving the processing speed of complex data shifting.

[0078] The circuit structure of the comparator unit is as follows: Figure 18 As shown, comparison operations are performed according to different operation modes (compare_mode). The output value is based on the maximum value corresponding to the calculation mode register (boolean) and the Boolean judgment result. If the output configuration register (word) is true, the output result is the concatenated result of the comparison operation return registers MSB16 and LSB16; otherwise, the return register value is output. The comparison unit, through hardware parallel comparison, can quickly generate comparison results within one cycle, providing key signals for conditional execution and data selection, and accelerating the decision-making process in the algorithm. The configurable output mode (controlled by the word register) is also crucial. When configured to output Boolean judgment, it directly generates a vector bitmask for masking operations, which is the core of implementing vector conditional execution. When configured to output concatenated comparison results, it can package multiple comparison results (such as the comparison results of each element in a 16-bit vector) into a single word, facilitating subsequent centralized processing and reducing data movement overhead. This flexibility enables it to efficiently support various comparison application scenarios, from data-level parallel conditional processing to result reduction.

[0079] The packet unit, also known as the bit packet unit, has the following circuit structure: Figure 19 As shown, this module handles bit packing, bit extraction, and compression operations. Internally, it uses bit concatenation, masking, and shifting operations to extract specific segments, allowing the bit packing unit to perform more precise bit operations on the vector. Figure 19 For the input / output ports, please refer to Table 9.

[0080] The packing unit can efficiently adjust the data bit width dynamically, optimizing memory bandwidth utilization and adapting to data interfaces with different bit widths. Its "compression" operation can filter out the effective elements in the vector based on the mask and arrange them tightly, effectively removing invalid elements in sparse data and reducing the amount of data and transmission overhead required for subsequent processing. These fine-grained bit-level operations are crucial for tasks such as bit descrambling, protocol field extraction, and data compression and packing in wireless communication. Integrating these complex operations, which originally required multiple basic instructions, into a single hardware unit achieves hardware acceleration and significantly reduces processing latency and power consumption.

[0081] Table 9 Packaging Unit Input / Output Ports

[0082] A logic unit, also known as a logic operation unit, has the following circuit structure: Figure 20 As shown, it supports AND, OR, NOT, NOR NOT and XOR logical operations and outputs to a general vector register.

[0083] Optionally, the vector operation unit includes an access control unit, which includes a state machine or counter for controlling the transfer of 256-bit data and 32-bit registers in sequences of eight 32-bit data units.

[0084] In this embodiment, the vector operation unit includes a move unit, a fill unit, and a storage control unit, mainly used to accelerate the execution of various vector operation instructions. The structure of each unit will be described below.

[0085] The storage control unit (SCU), also known as the access control unit, is used to control the loading of data from memory to registers and the storage of data from registers to memory. It supports batch transfers of 256-bit wide data. The data source and destination addresses are determined by the data memory index (dmsp) and the vector register index (vsp), respectively. Data is transferred one at a time, in units of 32 bits, for a total of *n* 32-bit data units, thus completing the batch processing of 256-bit data. The circuit structure of the SCU is as follows: Figure 21 As shown, the input / output ports are listed in Table 10, and the internal registers are listed in Table 11.

[0086] The specific access control flow includes: In the load direction (from memory to register), the 256-bit data in the memory index is sequentially split into eight 32-bit fields and written to num consecutive registers starting from the vector register index. In the storage direction (from register to memory), the contents of num registers starting from the vector register index are written back to the 256-bit memory region corresponding to the memory index. The access control flow timing diagram can be combined with... Figure 22 As shown, this design is suitable for scenarios involving bulk data exchange between memory and registers in vector processors.

[0087] Table 10 List of Access Control Unit Ports

[0088] Table 11 Access Control Unit Internal Registers

[0089] Optionally, the vector operation unit includes a padding unit, which adopts a dual-path structure, wherein the first path contains a comparator for data saturation truncation, and the second path contains logic circuitry for sign bit extension; a mode configuration signal registered in the padding unit configuration register controls a top-level multiplexer to select either the clipping result or the sign extension result as the output.

[0090] Furthermore, before the dual-path structure of the filling unit, there is an input data splitting circuit, which splits the input 32-bit data into two 16-bit half-words and sends them to a comparator for saturation truncation and a logic circuit for sign bit extension for parallel processing.

[0091] In this embodiment, the FillUnit executes amplitude limiting (vlim) and register filling (vfill, etc.) instructions. This provides assurance for controlling the range of signed data and loading signed constants into vector registers, and is commonly used in scenarios involving large-scale register initialization or signed number operations. It supports limiting vector amplitude; this embodiment implements a vector data processing function with saturation truncation. For each vector, its numerical range is determined. If it is greater than the maximum value of a 32-bit signed integer, the source register value is saturated and truncated to that maximum value; if it is less than the minimum value of a 32-bit signed integer, it is truncated to that minimum value; otherwise, the input is directly used as the output result. This module is commonly used to ensure data is within a valid range and is suitable for data precision control in vector processors. It also supports filling registers with signed numbers. The module can perform signed number expansion on the data, determining whether to perform half-word (16-bit) or full-word (32-bit) signed number expansion on the input immediate value based on the word enable register configuration, and outputting the processed MSB20 and LSB20 or the processed 40-bit result. The circuit structure of the FillUnit is as follows: Figure 23 As shown, the input and output ports are listed in Table 12.

[0092] Table 12 List of Filler Unit Ports

[0093] Finally, it also includes the moving unit, the circuit structure of which is as follows: Figure 24 As shown, different computation paths are achieved through a two-stage dual-path selector. Figure 25 The timing diagram of the moving unit is shown below, serving as a test case, combined with... Figure 25 As can be seen, the test stimulus consists of four inputs. The first input is copied, and the input is directly output. The second stimulus swaps the high 16 bits with the low 16 bits, thus swapping the real and imaginary parts of the complex number. The third stimulus only outputs the low 2 bits, so the result is 3. The fourth stimulus is similarly 1. All results are validly output in the next cycle after the input is valid.

[0094] The vector processing unit for wireless communication proposed in any of the above embodiments supports addition, multiplication, division, multiplication-addition, logical operations, complex arithmetic, and transcendental function operations; it also supports shift, comparison, packing, and padding operations, and allows the vector unit to interact with on-chip memory. Furthermore, it possesses at least the following technical advantages: (1) Optimized conditional execution mechanism: In order to improve processing efficiency, instruction execution efficiency was optimized. Pipelined reusable arithmetic units were designed to ensure mixed operations of different data types.

[0095] (2) Multi-granularity computing architecture: In response to the wide variation in data bit width and precision in wireless communication algorithms (e.g., from bit-level descrambling to word-level FFT calculation), this processor is designed and implemented with a multi-granularity computing architecture. This architecture can flexibly support data types and vector operations with different precisions of 16-bit, 32-bit, and 64-bit, thereby efficiently matching the ever-changing computing scenarios and maximizing resource utilization and energy efficiency while ensuring accuracy.

[0096] (3) Hardware acceleration of critical operations: To further improve the algorithm's execution efficiency and reduce latency, this design has been deeply optimized for the computational characteristics of wireless communication. A dedicated data path and hardware acceleration unit were designed for multiply-accumulate operations. This design enables critical operations to be completed in a very small number of cycles, significantly improving the overall processing throughput.

[0097] (4) Native support for complex number operations: Given the core role of complex number operations in communication processing, this processor natively supports complex number arithmetic operations at the hardware level. Through a specially designed complex multiplier and accumulator, this unit can efficiently execute instructions such as complex multiplication, complex accumulation, and complex multiply-accumulate, which greatly improves the execution efficiency of the core algorithms of the communication physical layer (PHY).

[0098] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented using software plus necessary general-purpose hardware platforms, or it can be implemented in hardware. By applying the scheme of this embodiment, compared with related technologies, by setting configuration registers and directly storing the mode configuration signals of the vector processing controller, the vector processing unit can dynamically change the internal data paths and computational functions of the vector arithmetic unit, vector bit manipulation unit, and vector operation unit according to different external instructions. This allows a single hardware platform to flexibly adapt to a variety of baseband processing algorithms in wireless communication, overcoming the shortcomings of traditional dedicated accelerators with fixed functions and poor scenario adaptability.

[0099] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0100] In the description of this specification, the terms "one embodiment," "some embodiments," "embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0101] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make modifications, alterations, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A vector processing unit for wireless communication, characterized in that, include: A vector processing controller is used to receive external instructions, decode them, and generate a mode configuration signal corresponding to the external instructions based on the decoding results. Three arithmetic units, including: A vector arithmetic unit, connected to the vector processing controller, is used to perform arithmetic operations with 16-bit, 32-bit, or 64-bit precision according to the mode configuration signal; A vector bit manipulation unit, connected to the vector processing controller, is used to perform bit-level operations according to the mode configuration signal; A vector operation unit, connected to the vector processing controller, is used to move, fill, and store signal processing vector register data according to the mode configuration; The vector arithmetic unit, vector bit operation unit, and vector operation unit all include physically implemented configuration registers for directly receiving and storing mode configuration signals from the vector processing controller.

2. The vector processing unit for wireless communication according to claim 1, characterized in that, The vector processing controller includes: A state machine circuit is used to characterize the working state of the vector processing controller; wherein the working state includes at least an idle state (IDLE), a computation state (COMPUTE), and a completion state (DONE). When the state machine circuit receives the start signal in the decoding result, it jumps from the IDLE state to the COMPUTE state, jumps to the DONE state in the next cycle, and returns to the IDLE state after any computation unit outputs a valid signal.

3. The vector processing unit for wireless communication according to claim 2, characterized in that, The vector processing controller further includes: The decoder circuit has the vector calculation opcode in the decoding result as its input and outputs mode configuration signals for controlling each arithmetic unit based on the state output of the state machine circuit.

4. The vector processing unit for wireless communication according to claim 3, characterized in that, The vector processing controller further includes: The output control circuit includes a multi-input OR gate and a multiplexer; the input terminal of the multi-input OR gate is connected to the result validity signal of each arithmetic unit to generate an overall arithmetic completion flag; the selection terminal of the multiplexer receives a signal identifying the type of arithmetic unit, and its data input terminal is connected to the output terminal of each arithmetic unit to write back the currently valid arithmetic result.

5. The vector processing unit for wireless communication according to claim 1, characterized in that, The arithmetic operations performed by the vector arithmetic unit include: multiplication and addition, division, exponentiation, taking the absolute value, and taking the conjugate; the vector arithmetic unit includes a multiplication and addition unit, which is constructed as a three-stage pipeline structure, wherein: The first level is equipped with combinational logic multipliers; The second stage is equipped with adders and data selectors, which are used to select whether to perform addition or accumulation operations based on the mode configuration signal registered in the configuration register. The third-level deployment includes a second-level adder.

6. The vector processing unit for wireless communication according to claim 5, characterized in that, The vector arithmetic unit further includes: A division unit, wherein the division unit uses single-cycle combinational logic to implement integer division operations; An absolute value unit, which consists of two parallel absolute value sub-units, each sub-unit being 16 bits; An exponent unit, which integrates two lookup tables, a multiplier, and an adder; The conjugate unit includes parallel real part paths and imaginary part paths. The real part path directly outputs the high 16 bits of the input 32-bit complex data, and the imaginary part path includes an inverting circuit that inverts the low 16 bits of the input 32-bit complex data and outputs the inverted result. The multiply-add unit, the conjugate unit, and the adder in the vector arithmetic unit work together to implement complex multiplication and complex multiplication-accumulation operations.

7. The vector processing unit for wireless communication according to claim 1, characterized in that, The vector bit operation unit includes a shift unit, which includes a shifter and two independent shift paths. The mode configuration signal stored in the displacement unit configuration register controls the multiplexer to output the splicing result after independently displacing the real and imaginary parts of the complex number, or the result after displacing the overall data.

8. The vector processing unit for wireless communication according to claim 1, characterized in that, The vector operation unit includes an access control unit, which includes a counter for controlling the transmission of 256-bit data and 32-bit registers in sequences of eight 32-bit data units.

9. The vector processing unit for wireless communication according to claim 1, characterized in that, The vector operation unit includes a padding unit with a dual-path structure. The first path contains a comparator for data saturation truncation, and the second path contains logic circuitry for sign bit extension. A mode configuration signal stored in the padding unit configuration register controls a top-level multiplexer to select either the clipping result or the sign extension result as the output.

10. The vector processing unit for wireless communication according to claim 9, characterized in that, Before the dual-path structure of the filling unit, there is an input data splitting circuit, which splits the input 32-bit data into two 16-bit half-words and sends them to the comparator for saturation truncation and the logic circuit for sign bit extension for parallel processing.

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