Micro-nano protection array device and preparation method thereof

Abstract

The invention relates to a micro-nano protection array device and a preparation method thereof, and belongs to the field of electromagnetic field protection. The electromagnetic interference protection device solves at least one problem that an existing electromagnetic interference protection device is difficult to meet the protection requirement of a high-density integrated and / or miniaturized electronic system for strong electromagnetic interference and is difficult to meet the protection requirement for narrow-band high-frequency electromagnetic interference. The invention discloses a preparation method of a micro-nano protection array device, the micro-nano protection array device comprises a graphical array structure formed by metal grids, and the preparation method comprises the following steps: S1, providing a sapphire substrate; s2, drawing a layout, and manufacturing a mask plate; s3, coating photoresist, forming a photoresist pattern through photoetching and developing, and depositing a metal strip line on the sapphire substrate; and S4, removing the photoresist to form the metal grid. According to the invention, high-density miniaturization and large-area integration of the electromagnetic protection device are realized, the electromagnetic interference protection capability of a unit area is improved, and the working frequency upper limit of electromagnetic interference protection is improved.

Description

Technical Field

[0001] This invention relates to the field of electromagnetic field protection technology, and in particular to a micro / nano protection array device and its fabrication method. Background Technology

[0002] Electromagnetic field protection is widely used in wireless communication systems, typically to protect sensitive components such as front-end amplifiers in radio frequency links. In recent years, with the rapid increase in 5G massive MIMO infrastructure globally, the demand for electromagnetic interference protection has also gradually increased.

[0003] Currently, energy selective surfaces (ESS) are an emerging electromagnetic interference (EMI) protection method that can automatically adjust their transmission or reflection state based on the energy of electromagnetic waves. Common ESS implementations use PCBs, with the electromagnetic induction structure achieved through copper traces on the PCB. To improve the operating bandwidth of EMI protection, PIN diodes are further connected to the PCB via soldering. However, due to limitations in PCB manufacturing precision, implementing EMI structures using copper traces suffers from long dimensions and large parasitic characteristics. Furthermore, the miniaturization and high integration requirements of modern electronic systems limit the number of EMI structures (e.g., copper traces, PIN diodes) that can be arranged on ESSs obtained using existing methods. This makes it difficult to meet the protection requirements of high-density integrated and / or miniaturized electronic systems against strong electromagnetic interference, especially for narrowband high-frequency electromagnetic interference. Summary of the Invention

[0004] In view of the above analysis, the present invention aims to provide a micro-nano protection array device and its fabrication method to solve at least one of the following problems of existing electromagnetic interference protection devices based on energy selective surfaces: (1) it is difficult to meet the protection requirements of high-density integrated and / or miniaturized electronic systems for strong electromagnetic interference; (2) it is difficult to meet the protection requirements of electronic systems for narrowband high-frequency electromagnetic interference.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] This invention provides a method for fabricating a micro / nano protective array device. Based on the principle of energy selective surfaces, the micro / nano protective array device comprises a patterned array structure formed by a metal grid. The fabrication method includes the following steps:

[0007] S1. Provides a sapphire substrate;

[0008] S2. Draw the layout according to the parameters of the patterned array structure, and fabricate a mask for photolithography to form the patterned array structure according to the layout.

[0009] S3. Coat a photoresist onto a sapphire substrate, form a photoresist pattern through photolithography and development, and deposit a multi-layer structure of metal strips on the sapphire substrate according to the photoresist pattern.

[0010] S4. After the deposition and patterning of the metal strip is completed, the photoresist is removed, leaving the metal strip on the sapphire substrate to form a metal grid, thereby obtaining the micro-nano protective array device; the thickness H of the metal grid is ≤10μm.

[0011] Further, in step S3, the multilayer structure of the metal strip consists of an adhesion layer, a seed layer, and an electroplating layer from the sapphire substrate upwards; wherein, the material of the adhesion layer is one or more of Au, Ti, Ni, Pt, and TiN; the material of the seed layer is one or a combination of Au and Ti; and the material of the electroplating layer is one or a combination of Au and Cu.

[0012] Furthermore, the thickness H1 of the adhesion layer satisfies: 10nm≤H1≤3μm; and / or, the thickness H2 of the seed layer is 50nm~800nm; and / or, the thickness H3 of the electroplating layer is 1μm~6μm.

[0013] Furthermore, the metal grid is formed by multiple intersecting strip metal structures, with the width W of each strip metal structure ≤ 100 μm; and / or, the spacing Z between two adjacent strip metal structures ≤ 900 μm.

[0014] Furthermore, W and Z also satisfy: Z = k × W, where the value of k ranges from 1.5 to 8.

[0015] Furthermore, in step S3, the photolithography process mainly includes:

[0016] (c) Photoresist coating: A 1-15 μm thick photoresist is coated on the sapphire substrate by spin coating;

[0017] (d) Photolithography: Align the photomask with the sapphire substrate coated with photoresist and expose it, wherein the light source for exposure is ultraviolet light.

[0018] Further, in (a), the photoresist includes, but is not limited to, one or more combinations of PMGI series photoresist, SPR series photoresist, PMMA series photoresist, Krf series photoresist, and AZ5214 photoresist, and the spin coating speed is 2000-4000 rpm; in (b), the wavelength of the ultraviolet light is ≤365 nm, and the exposure light intensity is 4-6 mW / cm². 2 .

[0019] Furthermore, the photoresist comprises two layers, wherein the first photoresist layer closest to the sapphire substrate is a PMGI series photoresist with a thickness of 400-500 nm, and the second photoresist layer is an SPR series photoresist with a thickness of 0.6 μm-1.3 μm; or,

[0020] The first layer of photoresist close to the sapphire substrate is a PMGI series photoresist with a thickness of 400-500nm, and the second layer of photoresist is an SPR series photoresist with a thickness of 1.5μm-3.2μm.

[0021] Furthermore, the photoresist comprises two layers, wherein the first photoresist layer near the sapphire substrate is a PMMA series photoresist with a thickness of 250-350nm, and the second photoresist layer is a Krf series photoresist with a thickness of 2.8μm-3.2μm.

[0022] The present invention also provides a micro / nano protective array device, which is prepared by the method described above.

[0023] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0024] (1) This invention innovatively applies photolithography technology to the fabrication of energy selective surfaces, achieving high-density miniaturization and large-area integration of electromagnetic interference (EMI) protection devices. Traditional energy selective surfaces are typically formed on PCBs through processes such as soldering to create EMI induction structures, with the resulting EMI induction structures (e.g., copper traces) usually exceeding the millimeter scale in size. In contrast, this invention utilizes photolithography to fabricate micro- and nano-scale energy selective surfaces (e.g., high-density integrated metal grid array structures), reducing the size of each metal array structure unit from the existing millimeter scale to the micro- and nano-scale. This allows for the integration of more EMI induction structures per unit area, thereby improving the EMI protection capability provided per unit area of ​​the protection array device and better meeting the protection requirements of high-density integrated and / or miniaturized electronic systems for strong electromagnetic interference.

[0025] (2) This invention innovatively improves the integration density of the protection array by using photolithography to manufacture the energy selective surface, enabling the integration of more electromagnetic induction structures, such as metal grid arrays, within a unit area of ​​the protection device. Compared with existing energy selective surfaces (such as copper traces on PCBs), this invention significantly improves the upper limit of the operating frequency for electromagnetic interference protection. Specifically, this invention can effectively cope with higher frequency pulse electromagnetic interference above 10 GHz, and exhibits excellent electromagnetic protection performance when facing narrowband ultra-high frequency pulse electromagnetic interference of 30 GHz and above. In contrast, existing energy selective surfaces can usually only handle electromagnetic interference below 10 GHz, and their protection effect against higher frequency (>10 GHz) narrowband electromagnetic interference is poor.

[0026] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0027] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0028] Figure 1 This is a partial schematic diagram of the metal lattice structure in the preparation method provided in the embodiment of the present invention;

[0029] Figure 2 This is a cross-sectional schematic diagram of a photoresist pattern formed on a substrate in the preparation method provided in an embodiment of the present invention.

[0030] Figure 3 This is a cross-sectional schematic diagram of a metal lattice formed on a substrate in the fabrication method provided in an embodiment of the present invention.

[0031] Figure 4 This is a schematic diagram of the inductor and capacitor in the metal grid unit of the present invention;

[0032] Figure label:

[0033] 1-Photoresist; 2-Substrate; 3-Strip metal structure; L-Inductor with metal grid unit structure; C-Capacitor with metal grid unit structure. Detailed Implementation

[0034] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0035] When high-power microwave energy is concentrated within the operating frequency band of a device, the protection of electronic systems against strong electromagnetic attack signals and the compatibility of normal signal transmission and reception become a challenge in front-door protection design. To resolve this contradiction, an electromagnetic shielding surface with energy selectivity has been proposed, exhibiting low-pass characteristics in the energy domain for electromagnetic waves. This surface allows the transmission and reception of normal signals while blocking the passage of high-power electromagnetic pulses. Subsequently, researchers have conducted a series of studies on the working mechanism, structural design, performance design, and experimental methods of energy selective surfaces, demonstrating their effective protection against electromagnetic attack threats. However, the energy selective surface structures obtained by existing fabrication methods are limited by the precision of PCB manufacturing processes. The electromagnetic induction structures on these energy selective surfaces are often large (millimeter-level and above), accompanied by significant parasitic effects. This makes it difficult for existing methods and the resulting energy selective surface structures to meet the ever-increasing demands of modern electronic systems for electromagnetic interference protection, especially in areas requiring higher operating frequency limits and stronger electromagnetic interference protection per unit area.

[0036] Based on this, the present invention provides a method for fabricating a micro / nano protective array device. Based on the principle of energy selective surfaces, the micro / nano protective array device comprises a patterned array structure formed by a metal grid. The fabrication method includes the following steps:

[0037] S1. Provides a sapphire substrate;

[0038] S2. Draw the layout according to the parameters of the patterned array structure, and fabricate a mask for photolithography to form the patterned array structure according to the layout.

[0039] S3. Coat a photoresist onto a sapphire substrate, form a photoresist pattern through photolithography and development, and deposit a multi-layer structure of metal strips on the sapphire substrate according to the photoresist pattern.

[0040] S4. After the deposition and patterning of the metal strip is completed, the photoresist is removed, leaving the metal strip on the sapphire substrate to form a metal grid, thereby obtaining the micro-nano protective array device; the thickness H of the metal grid is ≤10μm.

[0041] Compared to existing technologies, this invention innovatively applies photolithography to the fabrication of energy-selective surfaces, achieving high-density miniaturization and large-area integration of electromagnetic interference (EMI) protection devices. Traditional energy-selective surfaces are typically formed on PCBs using processes such as soldering to create EMI induction structures, with the resulting structures (e.g., copper traces) usually exceeding millimeter dimensions. In contrast, this invention utilizes photolithography to fabricate micro- and nano-scale energy-selective surfaces (e.g., high-density integrated metal grid array structures), reducing the size of each metal array unit from the millimeter level to the micro- and nano-scale. This allows for the integration of more EMI induction structures per unit area, thereby improving the EMI protection capability per unit area of ​​the protection array device and better meeting the protection requirements of high-density integrated and / or miniaturized electronic systems for strong electromagnetic interference.

[0042] It is understood that the metal grid mentioned in this invention refers to a metal mesh or grid structure formed by arranging multiple strip metals in a periodic repeating pattern. This structure can be divided into multiple metal grid units, each of which has a specific size and arrangement to achieve specific electromagnetic protection performance.

[0043] Existing electromagnetic interference (EMI) protection devices, when applied to high-density integrated and / or miniaturized electronic systems, suffer from limited electromagnetic induction structures per unit area due to the relatively large size of the EMI induction functional elements / structures themselves, making it difficult to meet the protection requirements against strong electromagnetic interference. This invention significantly reduces the size of the EMI induction functional elements / structures (e.g., metal grid units) on the protection array device through photolithography, thereby significantly improving the integration density of the EMI induction functional elements / structures and the EMI protection capability per unit area of ​​the protection device. By applying photolithography to the fabrication of energy selective surfaces, this invention not only achieves miniaturization and high-density integration of EMI protection devices but also significantly improves the EMI protection capability per unit area. With a fixed device size, the protection array device fabricated by this invention exhibits stronger EMI protection capabilities than array devices fabricated by existing methods. This invention provides a more effective electromagnetic field protection solution for high-density integrated and / or miniaturized electronic systems.

[0044] Compared to existing technologies, this invention innovatively improves the integration density of the protection array by employing photolithography to fabricate the energy selective surface. This allows for the integration of more electromagnetic induction structures, such as metal grid arrays, within a unit area of ​​the protection device. Compared to existing energy selective surfaces (such as copper traces on PCBs), this invention significantly increases the upper limit of the operating frequency for electromagnetic interference protection. Specifically, this invention can effectively cope with higher frequency pulse electromagnetic interference above 10 GHz, exhibiting excellent electromagnetic protection performance against narrowband ultra-high frequency pulse electromagnetic interference of 30 GHz and above. In contrast, existing energy selective surfaces typically only handle electromagnetic interference below 10 GHz, and their protection effect against higher frequency (>10 GHz) narrowband electromagnetic interference is poor.

[0045] It is understood that the term "narrowband" mentioned in this invention refers to the bandwidth of pulse electromagnetic interference being 1±0.5GHz.

[0046] In addition, see Figure 4 Furthermore, in conjunction with the following formula (1), the effect of the present invention in significantly improving the upper limit of the operating frequency for electromagnetic interference protection is further explained from a theoretical perspective: the L (inductance) and C (capacitance) in a metal grid unit determine the operating frequency f of the unit structure. c Existing methods typically involve forming electromagnetic induction structures on a PCB board through processes such as soldering. The resulting electromagnetic induction structures (e.g., copper traces) are usually on the order of millimeters or larger, resulting in very high inductance values ​​(L) and low operating frequencies, typically below 10 GHz. This invention utilizes photolithography to fabricate electromagnetic induction structures (such as metal grids) at the micro- and nano-scale. The L (inductance) and C (capacitance) of the metal grid units can reach the micrometer level or even lower, thus enabling operating frequencies of at least 10 GHz or even higher, such as above 30 GHz.

[0047]

[0048] In some embodiments, in step S4, the thickness H of the metal grid is ≤ 6 μm. Further, the thickness H of the metal grid is ≤ 2 μm.

[0049] In some preferred embodiments, in step S3, the multilayer structure of the metal strip consists of an adhesion layer, a seed layer, and an electroplating layer, sequentially arranged from the sapphire substrate upwards. The adhesion layer is made of one or more of Au, Ti, Ni, Pt, and TiN; the seed layer is made of one or a combination of Au and Ti; and the electroplating layer is made of one or a combination of Au and Cu. By thickening the metal strip as a whole, i.e., adopting a multilayer structure of "adhesion layer + seed layer + electroplating layer," parasitic series resistance can be further reduced, conductivity improved, and the mechanical strength of the metal strip enhanced. This multilayer metal strip design helps avoid metal loss during the interconnection process between the protective array device and external circuits, improving the electromagnetic protection performance, high-temperature resistance, and reliability of the entire protective array device.

[0050] It is understandable that a multilayer structure of metal strips is fabricated on a sapphire substrate, in which an adhesion layer, a seed layer, and an electroplating layer each play a role. The main function of the adhesion layer is to ensure that the subsequently deposited metal layer can firmly adhere to the sapphire substrate. As an intermediary layer, it can improve the adhesion between the metal strip and the substrate, preventing the metal strip from falling off during subsequent assembly or use. The adhesion layer is composed of materials that can form good adhesion with the sapphire substrate and the seed layer, such as one or more of Au, Ti, Ni, Pt, and TiN. The function of the seed layer is to promote the uniform growth of the electroplating layer and provide nuclei for grain growth, helping the electroplating layer to form a uniform and dense structure. The seed layer is composed of materials with good affinity to the adhesion layer and the electroplating layer, such as Au and Ti, to better promote the deposition of the electroplating layer and improve the surface flatness of the metal strip. The electroplating layer is the main part of the metal strip structure, providing the required conductivity and mechanical strength for the metal strip.

[0051] In some embodiments, the thickness H1 of the adhesion layer satisfies: 10nm ≤ H1 ≤ 3μm. Further, 200nm ≤ H1 ≤ 1.5μm.

[0052] In some embodiments, the thickness H2 of the seed layer is 50 nm to 800 nm. Further, the thickness H2 of the seed layer is 200 nm to 300 nm.

[0053] In some embodiments, the thickness H3 of the electroplated layer is 1 μm to 6 μm; further, the thickness H3 of the electroplated layer is 2 μm to 4 μm.

[0054] It should be noted that by controlling the thickness of each layer at the micro-nano scale, the protective array device can be further thinned. This allows for the integration of more protective array devices within a limited space, better meeting the protection requirements of modern electronic devices with high-density integration and / or miniaturization for strong electromagnetic interference. Furthermore, at the micro-nano scale, by rationally allocating the thickness of each layer, it is possible to ensure the strength and high-temperature resistance of the metal interconnects while effectively reducing series resistance and parasitic problems. This ensures that the protective array device can still operate normally and stably in high-temperature environments or under strong external vibrations, fully exerting its protection function against strong electromagnetic interference.

[0055] In one embodiment, the adhesion layer comprises two layers: a first adhesion layer near the sapphire substrate is a 100-300 nm thick Ti layer, and a second adhesion layer is a 100-300 nm thick Au layer. For example, the first adhesion layer is a 200 nm thick Ti layer, and the second adhesion layer is a 200 nm thick Au layer.

[0056] In one embodiment, the adhesion layer comprises two layers: a first adhesion layer near the sapphire substrate is 200-400 nm thick Ti, and a second adhesion layer is 5-15 nm thick TiN. For example, the first adhesion layer is 300 nm thick Ti, and the second adhesion layer is 10 nm thick TiN.

[0057] In one embodiment, the adhesion layer comprises three layers: a first adhesion layer close to the sapphire substrate is Ti with a thickness of 300-500 nm, a second adhesion layer is Ni with a thickness of 300-500 nm, and a third adhesion layer is Au with a thickness of 300-500 nm. For example, the first adhesion layer is Ti with a thickness of 500 nm, the second adhesion layer is Ni with a thickness of 500 nm, and the third adhesion layer is Au with a thickness of 500 nm.

[0058] In one embodiment, the adhesion layer comprises three layers: a first adhesion layer close to the sapphire substrate is Ti with a thickness of 200-400 nm, a second adhesion layer is Pt with a thickness of 200-400 nm, and a third adhesion layer is Au with a thickness of 200-400 nm. For example, the first adhesion layer is Ti with a thickness of 300 nm, the second adhesion layer is Pt with a thickness of 300 nm, and the third adhesion layer is Au with a thickness of 300 nm.

[0059] In some embodiments, the metal grid is formed by a plurality of intersecting strip metal structures, each strip metal structure having a width W ≤ 100 μm; and / or, the spacing Z between two adjacent strip metal structures ≤ 900 μm.

[0060] Furthermore, the spacing Z between two adjacent strip metal structures is ≤500μm.

[0061] Furthermore, W and Z also satisfy: Z = k × W, where the value of k ranges from 1.5 to 8; preferably, the value of k ranges from 4 to 8; for example: 5 ≤ k ≤ 7.

[0062] For example, the width W of each strip metal structure is 1μm-80μm.

[0063] For example, the spacing Z between two adjacent strip metal structures is 1.5 μm to 480 μm.

[0064] It can be understood that Z can be the distance between two adjacent vertically arranged strip metal structures, or the distance between two adjacent horizontally arranged strip metal structures.

[0065] This invention utilizes photolithography to significantly reduce the width of each strip-shaped metal structure and the distance between them, allowing for the arrangement of more metal grid structures within a limited space, thereby improving the integration of the electromagnetic shielding array structure. This high-density electromagnetic structure arrangement helps achieve stronger electromagnetic protection capabilities in a smaller area, which is crucial for the increasing integration requirements of modern electronic devices. The micro- and nano-scale metal grid structures provide a larger surface area, facilitating heat dissipation and conduction, thus improving the thermal management of the device, which is essential for preventing overheating and ensuring long-term reliability. By further optimizing the size and spacing of the metal structures, enhanced electromagnetic protection performance, improved mechanical strength, and optimized temperature resistance can be achieved, thus maintaining a high level of integration while achieving an optimal balance among these three aspects.

[0066] Specifically, in step S3, the photolithography process mainly includes:

[0067] (a) Photoresist coating: A 1-15 μm thick photoresist is coated on a sapphire substrate by spin coating;

[0068] (b) Photolithography: The photomask fabricated in S2 is aligned with the sapphire substrate coated with photoresist and exposed to ultraviolet light.

[0069] Optionally, in (b), the contact method between the mask and the sapphire substrate coated with photoresist is at least one of contact lithography, proximity lithography, and projection lithography. Preferably, proximity lithography or projection lithography is used. Proximity lithography refers to maintaining a tiny gap α between the mask and the photoresist layer, where 0 μm < α ≤ 200 μm.

[0070] It is understandable that coating with 1-15 μm thick photoresist is a key step in micro-nano fabrication, providing a foundation for the subsequent fabrication of micro- and nano-scale metal lattice structures.

[0071] In some embodiments, a photoresist with a thickness of 1-6 μm is coated.

[0072] In some embodiments, the photoresist comprises two layers, the first photoresist layer having a thickness h1 of 200-600 nm and the second photoresist layer having a thickness h2 of 0.5-3.5 μm, and 1 μm ≤ h1 + h2 ≤ 4 μm.

[0073] For example, in (a), the photoresist includes, but is not limited to, one or more combinations of PMGI series photoresist, SPR series photoresist, PMMA series photoresist, Krf series photoresist, and AZ5214 photoresist, and the spin coating speed is 2000-4000 rpm; in (b), the wavelength of the ultraviolet light is ≤365 nm, and the exposure light intensity is 4-6 mW / cm². 2 .

[0074] It is understandable that using high-resolution photoresists, such as the PMGI series, SPR series, PMMA series, KrF series, and AZ5214 photoresists, allows for the transfer of finer patterns onto sapphire substrates. By controlling the spin-coating speed and exposure intensity, a more uniform photoresist layer can be obtained, and the uniformity of the photoresist layer is crucial to the final pattern transfer quality. The exposure light source is ultraviolet light with a wavelength ≤365nm and an exposure intensity of 4-6mW / cm². 2 The synergistic effect of these parameters helps to achieve better adhesive layer uniformity and pattern transfer. For example, the wavelengths of ultraviolet light are 248 nm, 193 nm, and 13.5 nm.

[0075] In some embodiments, the photoresist comprises two layers. For example, in the following two cases:

[0076] (1) The first photoresist layer near the sapphire substrate is a PMGI series photoresist with a thickness of 400-500 nm, and the second photoresist layer is an SPR series photoresist with a thickness of 0.6 μm-1.3 μm; or,

[0077] (2) The first photoresist layer near the sapphire substrate is a PMGI series photoresist with a thickness of 400-500 nm, and the second photoresist layer is an SPR series photoresist with a thickness of 1.5 μm-3.2 μm; or,

[0078] (3) The first layer of photoresist close to the sapphire substrate is a PMMA series photoresist with a thickness of 250-350nm, and the second layer of photoresist is a Krf series photoresist with a thickness of 2.8μm-3.2μm.

[0079] For cases (1) or (2), the photolithography process specifically includes: after coating the photoresist, pre-baking the sapphire substrate coated with photoresist for 80-100 seconds using a vacuum hot plate at 90-110℃, followed by exposure with an exposure light intensity of 4-6 mW / cm². 2 The exposure time for case (1) is 5-7 seconds, and the exposure time for case (2) is 10-14 seconds; then development is carried out using a developing solution.

[0080] For example, in case (1), the first photoresist layer near the sapphire substrate is a PMGI series photoresist with a thickness of 450 nm, and the second photoresist layer is an SPR series photoresist with a thickness of 0.9 μm; the photolithography process specifically includes: after coating the photoresist, pre-baking the sapphire substrate coated with photoresist for 90 seconds using a 100°C vacuum hot plate, and then exposing it to light with an intensity of 5 mW / cm². 2 The exposure time is 6 seconds; then development is performed using CD26 developer.

[0081] For case (3), the photolithography process specifically includes: after coating the photoresist, exposure is performed, and the light intensity of the exposure is 4-6 mW / cm. 2 The exposure time is 10-14 seconds; then development is carried out using a developing solution.

[0082] For example, in case (3), the first photoresist layer near the sapphire substrate is a PMMA series photoresist with a thickness of 300 nm, and the second photoresist layer is a Krf series photoresist with a thickness of 3.0 μm; the photolithography process specifically includes: after coating the photoresist, exposure is performed, and the light intensity of the exposure is 5 mW / cm. 2 The exposure time is 12 seconds; then development is performed using CD26 developer.

[0083] Optionally, in cases (1)-(3), the developer includes, but is not limited to, CD26 developer.

[0084] Specifically, the full name of CD26 developer is Microposit MF-CD-26 Developer, manufactured by Rohm and Haas Electronic Materials LLC. Its main components include 95.0–99.0% water and 1.0–5.0% tetramethylammonium hydroxide, making it a liquid developer.

[0085] In one embodiment, the photoresist is a single layer with a thickness of 1.0-4.0 μm. For example, in the following case (4): the photoresist is a single layer of AZ5214 photoresist with a thickness of 1.0-3.6 μm; for case (4), the photolithography process specifically includes: after coating the photoresist, performing pre-exposure, the light intensity of the pre-exposure being 4-6 mW / cm 2 The exposure time is 4-6 seconds; then, the sapphire substrate after the previous exposure is reverse-baked for 60-90 seconds using a vacuum hot plate at 110-120℃; further, the mask is removed and a generalized exposure is performed, with the light intensity of the generalized exposure being 4-6 mW / cm². 2 The exposure time is 60-70 seconds; then development is performed using a developing solution.

[0086] For example, in case (4): the photoresist is a 1.4μm thick layer of AZ5214 photoresist; the photolithography process specifically includes: after coating the photoresist, performing pre-exposure, the light intensity of the pre-exposure is 5mW / cm. 2 The exposure time is 5 seconds; then, the sapphire substrate after the previous exposure is reverse-baked for 75 seconds using a 115°C vacuum hot plate; further, the mask is removed and a generalized exposure is performed, with a light intensity of 5 mW / cm². 2 The exposure time is 65 seconds; then development is performed using AZ developer.

[0087] Optionally, in case (4), the developer includes, but is not limited to, AZ developer.

[0088] Specifically, AZ developer refers to a series of photoresist-compatible developer solutions produced by Merck.

[0089] It should be noted that the PMGI series photoresist, SPR series photoresist, PMMA series photoresist, Krf series photoresist, AZ5214 photoresist, CD26 developer, and AZ developer mentioned in this invention can be obtained commercially.

[0090] Preferably, in step S1, the thickness of the sapphire substrate is 200-600 μm. This thickness ensures that the sapphire substrate provides sufficient support while minimizing the size of the resulting protective array device, thereby better meeting the requirements for strong electromagnetic field protection in high-density integrated and / or miniaturized electronic systems, especially suitable for strong electromagnetic interference protection requirements in narrowband high-frequency applications. Before coating with photoresist, the sapphire substrate is cleaned to remove substances not belonging to the substrate, improving the adhesion between the photoresist and the substrate.

[0091] Optionally, in S3, the deposition method includes physical vapor deposition and chemical vapor deposition.

[0092] For example, the physical vapor deposition methods include, but are not limited to, vacuum evaporation, sputtering, and ion plating. The chemical vapor deposition methods include, but are not limited to, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, and organometallic chemical vapor deposition.

[0093] The present invention also provides a micro / nano protective array device, which is prepared by the method described above.

[0094] The micro / nano protective array device includes a sapphire substrate and a metal grid disposed on the sapphire substrate; the thickness H of the metal grid is ≤10μm.

[0095] In some embodiments, the metal grid is formed by a plurality of intersecting strip metal structures, each strip metal structure having a width W ≤ 100 μm and a spacing Z ≤ 900 μm between two adjacent strip metal structures.

[0096] The technical solution of the present invention will be further described in detail below with reference to specific embodiments.

[0097] Example 1

[0098] This embodiment provides a method for fabricating a micro / nano protective array device, which includes a patterned array structure formed by a metal grid. The metal grid is formed by multiple strip metal structures arranged in a cross shape, with each strip metal structure having a width W = 100 μm and the spacing Z between two adjacent strip metal structures being the same, i.e., Z1 = Z2 = 900 μm. Figure 1 This is a partial schematic diagram of a metal grid structure. Z1 represents the distance between two adjacent vertically arranged strip metal structures, and Z2 represents the distance between two adjacent horizontally arranged strip metal structures.

[0099] The preparation method includes the following steps:

[0100] S1. Provides a 400μm thick C-plane sapphire substrate;

[0101] S2, according to... Figure 1 The parameters W and Z of the patterned array structure formed by the metal grid shown are used to draw the layout. Based on the layout, a mask is made for photolithography to form the patterned array structure.

[0102] S3. Coat a photoresist layer on a sapphire substrate, form a photoresist pattern through photolithography and development, and deposit a multilayer structure of metal strips on the sapphire substrate according to the photoresist pattern; specifically including:

[0103] S31. First, spin coat a first layer of PMGI-SF3 photoresist with a thickness of 400nm onto the C-side sapphire substrate described in S1 at a speed of 4000rpm. Then, spin coat a second layer of SPR955-CM photoresist with a thickness of 3.2μm onto the PMGI-SF3 photoresist at a speed of 4000rpm.

[0104] S32. After spin-coating the photoresist, pre-bake the C-side sapphire substrate coated with photoresist for 90 seconds using a 100°C vacuum hot plate.

[0105] S33. After pre-baking, align the mask fabricated in S2 with the C-side sapphire substrate coated with photoresist, with a gap α = 50 μm between the mask and the photoresist. Expose the C-side sapphire substrate coated with photoresist using ultraviolet light with a wavelength of 365 nm and an exposure intensity of 5 mW / cm². 2 The exposure time is 12 seconds;

[0106] S34. After exposure, develop the photoresist using CD26 developer to form a photoresist pattern, such as... Figure 2 As shown;

[0107] S35. According to the photoresist pattern in S34, firstly, a Ti layer with a thickness of 300nm (first adhesion layer) is deposited on the C-side sapphire substrate using electron beam physical vapor deposition, and then a TiN layer with a thickness of 10nm (second adhesion layer) is deposited on the first adhesion layer using magnetron sputtering.

[0108] S36. A Ti layer (seed layer) with a thickness of 250 nm is deposited on the second adhesion layer using electron beam physical vapor deposition; then a Cu layer (electroplating layer) with a thickness of 3 μm is deposited on the seed layer using magnetron sputtering.

[0109] Based on S35-S36, a multilayer structure of metal strips is deposited on a C-plane sapphire substrate;

[0110] S4. After completing the deposition and patterning of the metal strip, the photoresist is stripped off, such as... Figure 3 This allows the metal strip to remain on the sapphire substrate, forming a metal grid, thereby obtaining a micro / nano protective array device. The thickness of the metal grid is H = 3.56 μm.

[0111] Furthermore, the electromagnetic interference protection performance of the above-described Embodiment 1 is explained as follows:

[0112] (a) Electromagnetic interference protection performance per unit area:

[0113] Each metal grid cell (e.g., in the protective array device prepared in Example 1) Figure 1The average size (shown by the red dashed line in the middle) is 1000μm × 1000μm = 10 6 μm 2 Therefore, it is possible to integrate 200 metal grid units within a 2cm × 1cm area. In contrast, the electromagnetic induction structures on the energy selection surface in existing technologies are often quite large. Theoretically, within the same 2cm × 1cm area, existing technologies can only allow a maximum of 10,000 structural units, but in practical applications, due to limitations in PCB manufacturing precision, this is typically less than 50 or even fewer. In comparison, the array protection device obtained in Embodiment 1 of this invention improves electromagnetic protection performance by at least 4 times compared to electromagnetic protection devices obtained by existing methods of the same area, and in most cases, by more than 10 times.

[0114] It is understood that as the width (W) and spacing (Z) of the strip metal structure are set smaller in the preparation steps of the embodiments of the present invention, the number of metal grid units integrated per unit area will also increase accordingly, and the electromagnetic interference protection capability will be further improved compared with Embodiment 1; for example, when W = 20 μm and Z = 30 μm, each metal grid unit (e.g. Figure 1 The average size (shown by the red dashed line) is 50μm × 50μm = 2500μm. 2 Therefore, it is possible to integrate 80,000 metal grid units within a 2cm × 1cm area. As can be seen, the micro / nano shielding array device prepared by the method provided in this invention significantly improves the electromagnetic interference protection capability per unit area, better meeting the protection requirements of high-density integrated and / or miniaturized electronic systems for strong electromagnetic field interference.

[0115] (b) Upper limit of operating frequency

[0116] Based on the micro-nano protective array device obtained in Example 1, experiments (e.g., terahertz detection technology) show that the upper limit of the operating frequency of a metal grid cell in Example 1 can reach 14 GHz, while the upper limit of the operating frequency of a metal grid cell in the energy selective surface device made by the prior art can only reach 10 GHz.

[0117] It is understood that as the fabrication steps of this embodiment of the invention incorporate smaller widths (W) and spacings (Z) of the strip-shaped metal structures, the upper limit of the operating frequency will be further increased compared to Embodiment 1. For example, experimental measurements show that the upper limit of the operating frequency of a single metal grid cell can reach 100 GHz when W = 20 μm and Z = 30 μm.

[0118] Therefore, the micro-nano protective array device obtained by the preparation method described in this invention has the ability to effectively resist high-frequency pulse electromagnetic interference above 10 GHz. In contrast, the electromagnetic protection performance of energy selective surfaces manufactured by existing technologies is significantly insufficient in the high-frequency range above 10 GHz, making it difficult to meet the protection requirements of high-frequency electromagnetic environments.

[0119] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a micro / nano protective array device, characterized in that, Based on the principle of energy-selective surfaces, the micro / nano protective array device comprises a patterned array structure formed by a metal grid; the fabrication method includes the following steps: S1. Provides a sapphire substrate; S2. Draw the layout according to the parameters of the patterned array structure, and fabricate a mask for photolithography to form the patterned array structure according to the layout. S3. Coat a photoresist onto a sapphire substrate, form a photoresist pattern through photolithography and development, and deposit a multi-layer structure of metal strips on the sapphire substrate according to the photoresist pattern. S4. After the deposition and patterning of the metal strip is completed, the photoresist is removed, leaving the metal strip on the sapphire substrate to form a metal grid, thereby obtaining the micro-nano protective array device; the thickness H of the metal grid is ≤10μm.

2. The preparation method according to claim 1, characterized in that, In step S3, the multilayer structure of the metal strip consists of an adhesion layer, a seed layer, and an electroplating layer, arranged sequentially from the sapphire substrate upwards; wherein the material of the adhesion layer is one or more of Au, Ti, Ni, Pt, and TiN; the material of the seed layer is one or a combination of Au and Ti; and the material of the electroplating layer is one or a combination of Au and Cu.

3. The preparation method according to claim 2, characterized in that, The thickness H1 of the adhesion layer satisfies: 10nm≤H1≤3μm; and / or, the thickness H2 of the seed layer is 50nm~800nm; and / or, the thickness H3 of the electroplating layer is 1μm~6μm.

4. The preparation method according to claim 1, characterized in that, The metal grid is formed by multiple intersecting strip metal structures, each strip metal structure having a width W ≤ 100 μm; and / or, the spacing Z between two adjacent strip metal structures ≤ 900 μm.

5. The preparation method according to claim 4, characterized in that, The W and Z also satisfy: Z = k × W, where the value of k ranges from 1.5 to 8.

6. The preparation method according to claim 1, characterized in that, In step S3, the photolithography process mainly includes: (a) Photoresist coating: A 1-15 μm thick photoresist is coated on a sapphire substrate by spin coating; (b) Photolithography: Align the photomask with the sapphire substrate coated with photoresist and expose it to ultraviolet light.

7. The preparation method according to claim 6, characterized in that, In (a), the photoresist includes, but is not limited to, one or more combinations of PMGI series photoresist, SPR series photoresist, PMMA series photoresist, Krf series photoresist, and AZ5214 photoresist, and the spin coating speed is 2000-4000 rpm; in (b), the wavelength of the ultraviolet light is ≤365nm, and the exposure light intensity is 4-6mW / cm². 2 .

8. The preparation method according to claim 1, characterized in that, The photoresist comprises two layers: a first layer of photoresist near the sapphire substrate, consisting of a PMGI series photoresist with a thickness of 400-500 nm, and a second layer of photoresist, consisting of an SPR series photoresist with a thickness of 0.6 μm-1.3 μm; or... The first layer of photoresist close to the sapphire substrate is a PMGI series photoresist with a thickness of 400-500nm, and the second layer of photoresist is an SPR series photoresist with a thickness of 1.5μm-3.2μm.

9. The preparation method according to claim 1, characterized in that, The photoresist comprises two layers. The first photoresist layer, which is close to the sapphire substrate, is a PMMA series photoresist with a thickness of 250-350 nm, and the second photoresist layer is a Krf series photoresist with a thickness of 2.8 μm-3.2 μm.

10. A micro / nano protective array device, characterized in that, It is obtained by the preparation method described in any one of claims 1-9.

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