Method for processing impedance of inner electroplated layer of PCB, electronic equipment and product

Abstract

The embodiment of the invention provides a PCB inner electroplated layer impedance processing method, electronic equipment and a product. The method comprises the following steps: on the basis of determining a target impedance range of an inner electroplated layer according to design parameters of the inner electroplated layer of a printed circuit board (PCB) and impedance design parameters of a finished product of the PCB, carrying out impedance test on the inner electroplated layer to obtain an impedance test value; according to the target impedance range and the impedance test value, generating an impedance test result of the inner electroplated layer; the impedance test result is used for indicating whether to adjust the line width of the inner electroplated layer or the thickness of the dielectric layer; the staged impedance control of the PCB is realized, and the problem that the impedance test of the inner electroplated layer usually needs to wait to the finished product stage after the outer pattern is transferred to cause test lag in the impedance test of the inner electroplated layer is avoided, namely, the time difference between PCB test and adjustment is shortened, and the test efficiency is improved. And the problem that the whole board is scrapped due to test lag is avoided.

Description

Methods for handling the impedance of the inner electroplated layer of PCB, electronic equipment and products Technical Field

[0001] This application relates to the field of PCB technology, and in particular to a method for processing the impedance of the inner electroplated layer of a PCB, electronic equipment, and products. Background Technology

[0002] In the fields of high-speed communication, high-performance computing, and advanced electronic devices, the signal transmission quality of printed circuit boards (PCBs) directly affects the performance of end products. With technological advancements, PCB design is gradually evolving towards high-density interconnect (HDI) and N+N multilayer stack-up structures. These structures require multiple lamination processes to integrate multiple sub-boards into the final motherboard.

[0003] In PCBs with multiple lamination processes, the inner electroplated layer, as a critical structural layer, must meet stringent impedance requirements (such as...). (Within 5%) to ensure signal integrity and reduce electromagnetic interference. In existing technologies, impedance testing of the inner electroplated layer usually has to wait until the finished product stage after the outer layer pattern transfer is completed.

[0004] However, existing solutions suffer from a testing lag when testing the impedance of the inner electroplated layer. Summary of the Invention

[0005] The PCB inner layer electroplating impedance processing method, electronic device and product provided in this application are used to solve the problem of test lag in the impedance test of the inner layer electroplating.

[0006] In a first aspect, embodiments of this application provide a method for processing the impedance of an inner layer plating layer in a PCB, comprising: determining a target impedance range for the inner layer plating layer based on design parameters of the inner layer plating layer of the printed circuit board (PCB) and finished impedance design parameters of the PCB; performing an impedance test on the inner layer plating layer to obtain an impedance test value; generating an impedance test result for the inner layer plating layer based on the target impedance range and the impedance test value; the impedance test result being used to indicate whether to adjust the linewidth or dielectric layer thickness of the inner layer plating layer.

[0007] In one possible implementation, the impedance test of the inner electroplated layer to obtain an impedance test value includes: testing the single-line impedance of the inner electroplated layer based on the impedance test structure to obtain a single-line impedance test value; and / or testing the differential impedance of the inner electroplated layer to obtain a differential impedance test value; and determining the single-line impedance test value and / or the differential impedance test value as the impedance test value.

[0008] In one possible implementation, the impedance test structure includes a ground test path and a ground test pad; wherein the ground test path includes mechanical vias and laser-etched blind vias.

[0009] In one possible implementation, determining the target impedance range of the inner electroplated layer based on the design parameters of the inner electroplated layer of the printed circuit board (PCB) and the finished impedance design parameters of the PCB includes: determining the finished impedance tolerance based on the finished impedance design parameters of the PCB; determining the electroplated layer impedance tolerance of the inner electroplated layer based on the finished impedance tolerance; determining the predicted electroplated layer impedance of the inner electroplated layer based on the design parameters of the inner electroplated layer; and determining the target impedance range based on the electroplated layer impedance tolerance and the predicted electroplated layer impedance.

[0010] In one possible implementation, determining the predicted electroplating impedance of the inner electroplating layer based on its design parameters includes: determining a preset linewidth, a preset copper plating thickness, and a preset dielectric layer thickness based on the design parameters of the inner electroplating layer; dividing the inner electroplating layer into multiple functional regions; calculating the residual copper rate for each functional region; increasing or decreasing the preset linewidth, preset copper plating thickness, and preset dielectric layer thickness for each functional region based on the residual copper rate for each functional region to obtain the predicted linewidth, predicted copper plating thickness, and predicted dielectric layer thickness for each functional region; determining the predicted electroplating impedance for each functional region based on the predicted linewidth, predicted copper plating thickness, and predicted dielectric layer thickness; and determining the predicted electroplating impedance of the inner electroplating layer based on the predicted electroplating impedance of each functional region.

[0011] In one possible implementation, after generating the impedance test result of the inner electroplated layer based on the target impedance range and the impedance test value, the method further includes: maintaining, increasing, or decreasing the electroplating solution concentration or etching rate based on the impedance test result.

[0012] Secondly, embodiments of this application provide a processing apparatus for the impedance of an inner layer plating layer of a PCB, comprising: a determining module, configured to determine a target impedance range of the inner layer plating layer based on the design parameters of the inner layer plating layer of the printed circuit board (PCB) and the finished impedance design parameters of the PCB; a processing module, configured to perform an impedance test on the inner layer plating layer to obtain an impedance test value; and a generating module, configured to generate an impedance test result of the inner layer plating layer based on the target impedance range and the impedance test value; wherein the impedance test result is used to indicate whether to adjust the linewidth or dielectric layer thickness of the inner layer plating layer.

[0013] In one possible implementation, when the processing module performs an impedance test on the inner electroplated layer to obtain an impedance test value, it is specifically used to: test the single-line impedance of the inner electroplated layer based on the impedance test structure to obtain a single-line impedance test value; and / or test the differential impedance of the inner electroplated layer to obtain a differential impedance test value; and determine the single-line impedance test value and / or the differential impedance test value as the impedance test value.

[0014] In one possible implementation, the impedance test structure includes a ground test path and a ground test pad; wherein the ground test path includes mechanical vias and laser-etched blind vias.

[0015] In one possible implementation, when determining the target impedance range of the inner electroplated layer based on the design parameters of the inner electroplated layer of the printed circuit board (PCB) and the finished impedance design parameters of the PCB, the determining module is specifically used for: determining the finished impedance tolerance based on the finished impedance design parameters of the PCB; determining the electroplated layer impedance tolerance of the inner electroplated layer based on the finished impedance tolerance; determining the predicted electroplated layer impedance of the inner electroplated layer based on the design parameters of the inner electroplated layer; and determining the target impedance range based on the electroplated layer impedance tolerance and the predicted electroplated layer impedance.

[0016] In one possible implementation, when determining the predicted electroplating impedance of the inner electroplating layer based on the design parameters of the inner electroplating layer, the determining module is specifically configured to: determine a preset linewidth, a preset copper plating thickness, and a preset dielectric layer thickness based on the design parameters of the inner electroplating layer; divide the inner electroplating layer into multiple functional regions; calculate the residual copper rate corresponding to each functional region; increase or decrease the preset linewidth, preset copper plating thickness, and preset dielectric layer thickness of each functional region based on the residual copper rate of each functional region to obtain the predicted linewidth, predicted copper plating thickness, and predicted dielectric layer thickness of each functional region; determine the predicted electroplating impedance of each functional region based on the predicted linewidth, predicted copper plating thickness, and predicted dielectric layer thickness of each functional region; and determine the predicted electroplating impedance of the inner electroplating layer based on the predicted electroplating impedance of each functional region.

[0017] In one possible implementation, after generating the impedance test result of the inner layer electroplating layer based on the target impedance range and the impedance test value, the PCB inner layer electroplating layer impedance processing device is further configured to: maintain, increase, or decrease the electroplating solution concentration or etching rate based on the impedance test result.

[0018] Thirdly, embodiments of this application provide an electronic device, including: a memory and a processor;

[0019] The memory stores computer-executed instructions;

[0020] The processor executes computer execution instructions stored in the memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0021] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.

[0022] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.

[0023] The PCB inner layer electroplating impedance processing method, electronic device, and product provided in this application, based on the design parameters of the inner layer electroplating layer and the finished impedance design parameters of the PCB, determine the target impedance range of the inner layer electroplating layer. Then, impedance testing is performed on the inner layer electroplating layer to obtain impedance test values. Finally, based on the target impedance range and the impedance test values, impedance test results of the inner layer electroplating layer are generated. The impedance test results are used to indicate whether to adjust the linewidth or dielectric layer thickness of the inner layer electroplating layer. This achieves phased impedance control of the PCB, avoiding the problem of test lag caused by the usual requirement that impedance testing of the inner layer electroplating layer must wait until the finished product stage after the outer layer pattern transfer is completed. In other words, it shortens the time difference between PCB testing and adjustment, avoiding the problem of entire board scrapping due to test lag. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0025] Figure 1 is a schematic diagram of a scenario for the method of handling the impedance of the inner layer of PCB plating provided in this application;

[0026] Figure 2 is a flowchart of a method for processing the impedance of the inner layer plating layer of a PCB according to an embodiment of this application;

[0027] Figure 3 is a schematic diagram of a single-wire impedance test provided in an embodiment of this application;

[0028] Figure 4 is a schematic diagram of the single-wire impedance test provided in the embodiment of this application.

[0029] Figure 5 is a flowchart of a method for processing the impedance of the inner layer plating layer of a PCB according to another embodiment of this application;

[0030] Figure 6 is a schematic diagram of the structure of a PCB inner layer electroplating impedance processing device provided in an embodiment of this application;

[0031] Figure 7 is a schematic diagram of the structure of the electronic device provided in this application.

[0032] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0033] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0034] The technical solution of this application involves the collection, storage, use, processing, transmission, provision and disclosure of user personal information and data, which comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0035] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0036] In high-speed communication, high-performance computing, and advanced electronic devices, the signal transmission quality of printed circuit boards (PCBs) directly affects the performance of end products. With technological advancements, PCB design is evolving towards high-density interconnect (HDI) and N+N multilayer stack-up structures. These structures require multiple lamination processes to integrate multiple sub-boards into a final motherboard. In multi-laminated PCBs, the inner plating layer, as a critical structural layer, must meet stringent impedance requirements (such as...). To ensure signal integrity and reduce electromagnetic interference, impedance testing of the inner electroplated layer must be performed within 5% of the outer layer's impedance (indicated by a delay in testing). In existing technologies, impedance testing of the inner electroplated layer typically requires waiting until the finished product stage after the outer layer pattern transfer is complete. However, existing solutions suffer from a testing lag in the impedance testing of the inner electroplated layer.

[0037] The application scenarios of the embodiments of this application are explained below:

[0038] Figure 1 is a schematic diagram of a scenario illustrating the method for processing the impedance of the inner layer plating of a PCB provided in this application. As shown in Figure 1, the execution subject of the method provided in this application embodiment can be any form of electronic device. Taking a computer device as the execution subject, the computer device 101 determines the target impedance range of the inner layer plating based on the design parameters of the inner layer plating of the printed circuit board PCB and the finished impedance design parameters of the PCB; then, it performs an impedance test on the inner layer plating of the printed circuit board PCB 102 to obtain the impedance test value; based on the target impedance range and the impedance test value, it generates the impedance test result of the inner layer plating; the impedance test result is used to adjust the linewidth or dielectric layer thickness of the inner layer plating.

[0039] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0040] Figure 2 is a flowchart of a method for processing the impedance of the inner plating layer of a PCB according to an embodiment of this application. As shown in Figure 2, the execution subject of the method for processing the impedance of the inner plating layer of a PCB provided in this embodiment can be any form of electronic device. For example, this embodiment uses a computer device as the execution subject of the method. The method for processing the impedance of the inner plating layer of a PCB provided in this embodiment includes the following steps:

[0041] Step S201: Determine the target impedance range of the inner electroplating layer based on the design parameters of the inner electroplating layer of the printed circuit board (PCB) and the finished impedance design parameters of the PCB.

[0042] Specifically, the specific implementation steps of step S201 include:

[0043] Step S2011: Determine the impedance tolerance of the finished product based on the finished impedance design parameters of the PCB.

[0044] For example, based on the finished impedance design parameters of the PCB, the finished impedance design requirement is 100. If the impedance is 10Ω, then the impedance tolerance of the finished product is... 10%.

[0045] Step S2012: Determine the impedance tolerance of the inner electroplating layer based on the impedance tolerance of the finished product.

[0046] For example, the impedance tolerance of the finished product is reduced linearly or non-linearly to obtain the impedance tolerance of the inner electroplated layer. Specifically, for example, the impedance tolerance of the finished product is... 10%, linearly reduced by 2%, meaning the impedance tolerance of the inner electroplated layer is... 8%.

[0047] Step S2013: Determine the predicted electroplating impedance of the inner electroplating layer based on the design parameters of the inner electroplating layer.

[0048] For example, the design parameters of the inner electroplated layer include a preset linewidth, a preset copper plating thickness, and a preset dielectric layer thickness. Based on electromagnetic field theory calculations or a pre-trained impedance prediction model, the predicted electroplated layer impedance of the inner electroplated layer can be determined according to the preset linewidth, preset copper plating thickness, and preset dielectric layer thickness. For example, based on a preset linewidth of 50 μm, a preset copper plating thickness of 18 μm, and a preset dielectric layer thickness of 100 μm, the predicted electroplated layer impedance is calculated to be 50 Ω.

[0049] Furthermore, in one possible implementation, the pre-trained impedance prediction model is a prediction model established by training based on line width, copper plating thickness, dielectric layer thickness, and measured impedance value. The pre-trained impedance prediction model can determine the nonlinear relationship between line width, copper plating thickness, dielectric layer thickness, and measured impedance value. By dynamically adjusting the line width and / or copper plating thickness and / or dielectric layer thickness through a machine learning model, the problem of bias in the predicted electroplated layer impedance caused by fixed formula assumptions is solved.

[0050] Step S2014: Determine the target impedance range based on the electroplating layer impedance tolerance and the predicted electroplating layer impedance.

[0051] For example, the calculation formula for determining the target impedance range based on the electroplating layer impedance tolerance and the predicted electroplating layer impedance is shown in Equation (1).

[0052] (1)

[0053] in, The target impedance range; To predict the impedance of the electroplated layer; This refers to the impedance tolerance of the electroplated layer. For example, It is 50Ω. If it is 8%, then 50 4Ω.

[0054] Step S202: Perform impedance testing on the inner electroplated layer to obtain the impedance test value.

[0055] For example, based on the design parameters of the inner plating layer of the PCB, it is determined to perform single-line impedance testing and / or differential impedance testing on the inner plating layer, thereby obtaining the corresponding impedance test values.

[0056] Specifically, the specific implementation steps of step S202 include:

[0057] Step S2021: Based on the impedance test structure, the single-line impedance of the inner electroplated layer is tested to obtain the single-line impedance test value.

[0058] Specifically, the impedance test structure includes a grounding test path and a grounding test pad; the grounding test path includes mechanical vias and laser-drilled blind vias. In one possible implementation, after the first lamination of the PCB sub-board, mechanical vias are drilled into the PCB sub-board to serve as pilot holes for the grounding test path. Subsequently, with each subsequent stacking of sub-boards, a first laser-drilled blind via, a second laser-drilled blind via, and so on, up to the Nth laser-drilled blind via, are added based on this via. When single-wire impedance testing is required, a grounding test pad is added to the corresponding PCB sub-board for testing.

[0059] For example, Figure 3 is a schematic diagram of a single-line impedance test provided in an embodiment of this application. Figure 3 shows a single-line impedance test performed after the second laser blind via is fabricated. The view shown in Figure 3 is a cross-sectional schematic diagram of the PCB sub-board. As shown in Figure 3, it includes mechanical through-holes, first laser blind vias, second laser blind vias, copper dielectric and shielding layers of the PCB sub-board, grounding test pads, single-line impedance test pads of the first inner layer electroplating layer, and single-line impedance test pads of the second inner layer electroplating layer.

[0060] Furthermore, based on this, Figure 4 is a second schematic diagram of the single-line impedance test provided in the embodiment of this application. Based on the implementation shown in Figure 3, the view shown in Figure 4 is a top view of the PCB sub-board. As shown in Figure 4(a), according to the test requirements of the single-line impedance test of the second inner layer electroplating layer, it includes the single-line impedance of the inner layer electroplating layer, the single-line impedance test pad of the second inner layer electroplating layer, and the ground test pad. If the test requirements of the single-line impedance test of the second inner layer electroplating layer also include testing other specifications of single-line impedance, then other specifications of single-line impedance and corresponding other single-line impedance test pads can be further added to the second inner layer electroplating layer, as shown in Figure 4(b).

[0061] It is understood that the method provided in this application is also applicable to PCBs with more than two laminations and multiple specifications of single-line impedance. The single-line impedance of the second outermost layer of each PCB sub-board can be tested when the outer layer pattern is transferred after the previous lamination. At the same time, for any specification of single-line impedance, the PCB design test requirements can be met by increasing the length, width and shape of the impedance strip.

[0062] Step S2022, and / or, test the differential impedance of the inner electroplated layer to obtain the differential impedance test value.

[0063] For differential impedance, due to the mutual coupling of the two impedance lines, grounding is not required to perform differential impedance testing and obtain the differential impedance test value.

[0064] Step S2023: Determine the single-line impedance test value and / or differential impedance test value as the impedance test value.

[0065] Step S203: Based on the target impedance range and impedance test value, generate the impedance test result of the inner electroplated layer; the impedance test result is used to indicate whether to adjust the line width of the inner electroplated layer or the thickness of the dielectric layer.

[0066] Specifically, if the impedance test value is a single-line impedance test value, then it is determined whether the single-line impedance test value is within the target impedance range; if the single-line impedance test value is within the target impedance range, then the generated impedance test result is that the line width of the inner plating layer or the thickness of the dielectric layer is not adjusted; if the single-line impedance test value is not within the target impedance range, then the generated impedance test result is that the line width of the inner plating layer or the thickness of the dielectric layer is adjusted.

[0067] If the impedance test value is a differential impedance test value, then determine whether the differential impedance test value is within the target impedance range; if the differential impedance test value is within the target impedance range, then the generated impedance test result is that the line width of the inner plating layer or the thickness of the dielectric layer is not adjusted; if the differential impedance test value is not within the target impedance range, then the generated impedance test result is that the line width of the inner plating layer or the thickness of the dielectric layer is adjusted.

[0068] If the impedance test value includes single-line impedance test value and differential impedance test value, then determine whether the single-line impedance test value is within the target impedance range and whether the differential impedance test value is within the target impedance range respectively; the determination process and the corresponding impedance test results generated are as described above, and will not be repeated here.

[0069] Specifically, taking the single-line impedance test value as an example, if the single-line impedance test value is greater than the upper limit of the target impedance range, the impedance is reduced by increasing the line width or decreasing the dielectric layer thickness; if the single-line impedance test value is less than the lower limit of the target impedance range, the impedance is increased by decreasing the line width or increasing the dielectric layer thickness, thereby ensuring that the single-line impedance test value is within the target impedance range, that is, ensuring that the impedance of the inner layer plating layer of the PCB meets the design requirements of the finished PCB impedance design parameters in the semi-finished product stage.

[0070] In this embodiment, based on the design parameters of the inner electroplated layer of the printed circuit board (PCB) and the finished impedance design parameters of the PCB, the target impedance range of the inner electroplated layer is determined. Impedance testing is then performed on the inner electroplated layer to obtain impedance test values. Furthermore, based on the target impedance range and the impedance test values, the impedance test results of the inner electroplated layer are generated. These impedance test results indicate whether to adjust the linewidth or dielectric layer thickness of the inner electroplated layer. This achieves phased impedance control of the PCB, avoiding the test lag problem caused by the usual requirement that impedance testing of the inner electroplated layer must wait until the finished product stage after the outer layer pattern transfer. In other words, it shortens the time difference between PCB testing and adjustment, avoiding the problem of entire board scrapping due to test lag.

[0071] Furthermore, the method provided in this application embodiment also includes: maintaining, increasing, or decreasing the concentration of the electroplating solution or the etching rate based on the impedance test results.

[0072] Specifically, taking the single-line impedance test value as an example, if the single-line impedance test value is greater than the upper limit of the target impedance range, then the single-line impedance test value is reduced to the target impedance range by decreasing the etching rate to increase the linewidth; and / or, the concentration of the electroplating solution (copper ions) is increased. The concentration of copper salts can be increased to improve the thickness of the copper plating, thereby reducing the single-line impedance test value to the target impedance range.

[0073] Based on the steps of this embodiment, the response time for adjusting the deviation between the impedance test value and the target impedance range is shortened, avoiding the problem of the entire board being scrapped due to test lag.

[0074] Figure 5 is a flowchart of a method for processing the impedance of the inner plating layer of a PCB according to another embodiment of this application. As shown in Figure 5, the method for processing the impedance of the inner plating layer of a PCB provided in this embodiment is further refined based on the method for processing the impedance of the inner plating layer of a PCB provided in the embodiment shown in Figure 2. The method for processing the impedance of the inner plating layer of a PCB provided in this embodiment includes the following steps:

[0075] Step S301: Determine the impedance tolerance of the finished product based on the finished impedance design parameters of the PCB.

[0076] Step S302: Determine the impedance tolerance of the inner electroplating layer based on the impedance tolerance of the finished product.

[0077] Step S303: Based on the design parameters of the inner electroplating layer, determine the preset line width, preset electroplated copper thickness, and preset dielectric layer thickness, and divide the inner electroplating layer into multiple functional areas.

[0078] For example, the design parameters of the inner electroplating layer include a preset line width, a preset copper plating thickness, and a preset dielectric layer thickness; based on the design parameters of the inner electroplating layer, the functional areas of the inner electroplating layer (e.g., signal area, power area, BGA area, process edge) are determined, wherein the line density of different functional areas is different, and the corresponding residual copper rate is different.

[0079] Step S304: Calculate the residual copper rate of each functional area.

[0080] For example, the residual copper rate of each functional area is calculated separately. The calculation formula is shown in equation (2).

[0081] (2)

[0082] in, The total area of ​​conductive copper foil within the functional area (including the area of ​​the circuit, the area of ​​the pad, and the area of ​​the copper foil, but excluding the copper foil in the solder mask coverage area). This refers to the area of ​​the functional zone.

[0083] Step S305: Based on the residual copper rate of each functional area, increase or decrease the preset line width, preset electroplated copper thickness and preset dielectric layer thickness of each functional area to obtain the predicted line width, predicted electroplated copper thickness and predicted dielectric layer thickness of each functional area.

[0084] Specifically, for example, in sparsely populated areas, the residual copper content is lower, and the corresponding dielectric layer thickness is thicker. Therefore, the linewidth needs to be reduced to lower the predicted electroplated layer impedance. Conversely, in densely populated areas, the residual copper content is higher, and the corresponding dielectric layer thickness is thinner. Therefore, the linewidth needs to be increased to improve the predicted electroplated layer impedance. That is, based on the residual copper content of each functional area, the preset linewidth, preset electroplated copper thickness, and preset dielectric layer thickness for each functional area are increased or decreased to obtain the corresponding predicted linewidth, predicted electroplated copper thickness, and predicted dielectric layer thickness.

[0085] Step S306: Determine the predicted plating impedance of each functional area based on the predicted linewidth, predicted copper plating thickness, and predicted dielectric layer thickness of each functional area.

[0086] Step S307: Determine the predicted electroplating impedance of the inner electroplating layer based on the predicted electroplating impedance of each functional area.

[0087] Step S308: Determine the target impedance range based on the electroplating layer impedance tolerance and the predicted electroplating layer impedance.

[0088] Specifically, the target impedance range of each functional area is determined based on the electroplating layer impedance tolerance and the predicted electroplating layer impedance of each functional area.

[0089] Step S309: Perform impedance testing on the inner electroplated layer to obtain the impedance test value.

[0090] Specifically, based on each functional area, impedance tests are performed on the inner electroplated layer to obtain the impedance test values ​​corresponding to each functional area.

[0091] Step S310: Based on the target impedance range and impedance test value, generate the impedance test result of the inner electroplated layer; the impedance test result is used to indicate whether to adjust the linewidth of the inner electroplated layer or the thickness of the dielectric layer.

[0092] Specifically, for each functional area, impedance test results are generated based on the target impedance range and impedance test values ​​of each functional area. These impedance test results are then summarized to obtain the impedance test results of the inner electroplated layer. The impedance test results of each functional area are used to indicate whether to adjust the linewidth or dielectric layer thickness of the corresponding functional area.

[0093] In this embodiment, by dividing different functional areas and calculating the corresponding residual copper rate, the problem of inaccurate predicted electroplating impedance determined by calculating the overall residual copper rate is solved, thereby improving the accuracy of the determined target impedance range and avoiding the problem of scrapping the entire board due to inaccurate testing.

[0094] In this embodiment, the implementation of steps S301-S302 is the same as that of steps S2011-S2012 in the embodiment shown in FIG2 of this application, and the implementation of steps S309-S310 is the same as that of steps S202-S203 in the embodiment shown in FIG2 of this application. They will not be described in detail here.

[0095] Figure 6 is a schematic diagram of the structure of a PCB inner layer electroplating impedance processing device provided in an embodiment of this application. As shown in Figure 6, the PCB inner layer electroplating impedance processing device 60 provided in this embodiment includes: a determining module 601, used to determine the target impedance range of the inner layer electroplating layer according to the design parameters of the inner layer electroplating layer of the printed circuit board PCB and the finished impedance design parameters of the PCB; a processing module 602, used to perform impedance testing on the inner layer electroplating layer to obtain impedance test values; and a generating module 603, used to generate the impedance test results of the inner layer electroplating layer according to the target impedance range and the impedance test values; the impedance test results are used to indicate whether to adjust the line width or dielectric layer thickness of the inner layer electroplating layer.

[0096] In one possible implementation, when the processing module 602 performs an impedance test on the inner electroplated layer to obtain an impedance test value, it is specifically used to: test the single-line impedance of the inner electroplated layer based on the impedance test structure to obtain a single-line impedance test value; and / or test the differential impedance of the inner electroplated layer to obtain a differential impedance test value; and determine the single-line impedance test value and / or the differential impedance test value as the impedance test value.

[0097] In one possible implementation, the impedance test structure includes a ground test path and a ground test pad; wherein the ground test path includes mechanical vias and laser-drilled blind vias.

[0098] In one possible implementation, when determining the target impedance range of the inner electroplated layer based on the design parameters of the inner electroplated layer of the printed circuit board (PCB) and the finished impedance design parameters of the PCB, the determining module 601 is specifically used for: determining the finished impedance tolerance based on the finished impedance design parameters of the PCB; determining the electroplated layer impedance tolerance of the inner electroplated layer based on the finished impedance tolerance; determining the predicted electroplated layer impedance of the inner electroplated layer based on the design parameters of the inner electroplated layer; and determining the target impedance range based on the electroplated layer impedance tolerance and the predicted electroplated layer impedance.

[0099] In one possible implementation, when determining the predicted electroplating impedance of the inner electroplating layer based on the design parameters of the inner electroplating layer, the determining module 601 is specifically used for: determining a preset linewidth, a preset copper plating thickness, and a preset dielectric layer thickness based on the design parameters of the inner electroplating layer, and dividing the inner electroplating layer into multiple functional regions; calculating the residual copper rate of each functional region; increasing or decreasing the preset linewidth, preset copper plating thickness, and preset dielectric layer thickness of each functional region based on the residual copper rate of each functional region, to obtain the predicted linewidth, predicted copper plating thickness, and predicted dielectric layer thickness of each functional region; determining the predicted electroplating impedance of each functional region based on the predicted linewidth, predicted copper plating thickness, and predicted dielectric layer thickness of each functional region; and determining the predicted electroplating impedance of the inner electroplating layer based on the predicted electroplating impedance of each functional region.

[0100] In one possible implementation, after generating the impedance test results of the inner layer electroplating layer based on the target impedance range and the impedance test value, the PCB inner layer electroplating layer impedance processing device 60 is further used to: maintain, increase, or decrease the electroplating solution concentration or etching rate based on the impedance test results.

[0101] The PCB inner layer electroplating impedance processing device 60 provided in this embodiment can execute the technical solution of any of the method embodiments shown in Figures 2-5. Its implementation principle and technical effect are similar, and will not be described again here.

[0102] Figure 7 is a schematic diagram of the structure of the electronic device provided in this application. As shown in Figure 7, the electronic device 70 provided in this embodiment includes at least one processor 701 and a memory 702. Optionally, the device 70 further includes a communication component 703. The processor 701, the memory 702, and the communication component 703 are connected via a bus.

[0103] In a specific implementation, at least one processor 701 executes computer execution instructions stored in memory 702, causing at least one processor 701 to perform the above-described method.

[0104] The specific implementation process of processor 701 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0105] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0106] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0107] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0108] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0109] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0110] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0111] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0112] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0113] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0114] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0115] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0116] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0117] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A method for processing the impedance of an inner electroplated layer on a PCB, characterized in that, The method includes: determining the target impedance range of the inner electroplated layer based on the design parameters of the inner electroplated layer of the printed circuit board (PCB) and the finished impedance design parameters of the PCB; performing an impedance test on the inner electroplated layer to obtain an impedance test value; generating an impedance test result of the inner electroplated layer based on the target impedance range and the impedance test value; and using the impedance test result to indicate whether to adjust the linewidth or dielectric layer thickness of the inner electroplated layer.

2. The method according to claim 1, characterized in that, The step of performing an impedance test on the inner electroplated layer to obtain an impedance test value includes: testing the single-line impedance of the inner electroplated layer based on the impedance test structure to obtain a single-line impedance test value; and / or testing the differential impedance of the inner electroplated layer to obtain a differential impedance test value; and determining the single-line impedance test value and / or the differential impedance test value as the impedance test value.

3. The method according to claim 2, characterized in that, The impedance test structure includes a grounding test path and a grounding test pad; wherein, the grounding test path includes mechanical through holes and laser blind holes.

4. The method according to claim 1, characterized in that, The step of determining the target impedance range of the inner electroplated layer based on the design parameters of the inner electroplated layer of the printed circuit board (PCB) and the finished impedance design parameters of the PCB includes: determining the finished impedance tolerance based on the finished impedance design parameters of the PCB; determining the electroplated layer impedance tolerance of the inner electroplated layer based on the finished impedance tolerance; determining the predicted electroplated layer impedance of the inner electroplated layer based on the design parameters of the inner electroplated layer; and determining the target impedance range based on the electroplated layer impedance tolerance and the predicted electroplated layer impedance.

5. The method according to claim 4, characterized in that, The step of determining the predicted electroplating impedance of the inner electroplating layer based on the design parameters of the inner electroplating layer includes: determining a preset linewidth, a preset copper plating thickness, and a preset dielectric layer thickness based on the design parameters of the inner electroplating layer; dividing the inner electroplating layer into multiple functional regions; calculating the residual copper rate of each functional region; increasing or decreasing the preset linewidth, preset copper plating thickness, and preset dielectric layer thickness of each functional region based on the residual copper rate of each functional region to obtain the predicted linewidth, predicted copper plating thickness, and predicted dielectric layer thickness of each functional region; determining the predicted electroplating impedance of each functional region based on the predicted linewidth, predicted copper plating thickness, and predicted dielectric layer thickness; and determining the predicted electroplating impedance of the inner electroplating layer based on the predicted electroplating impedance of each functional region.

6. The method according to any one of claims 1-5, characterized in that, After generating the impedance test result of the inner electroplated layer based on the target impedance range and the impedance test value, the method further includes: maintaining, increasing, or decreasing the electroplating solution concentration or etching rate based on the impedance test result.

7. A device for processing the impedance of an inner electroplated layer on a PCB, characterized in that, include: The determination module is used to determine the target impedance range of the inner electroplated layer based on the design parameters of the inner electroplated layer of the printed circuit board (PCB) and the finished impedance design parameters of the PCB. The processing module is used to perform impedance testing on the inner electroplated layer and obtain the impedance test value; The generation module is used to generate the impedance test result of the inner electroplated layer based on the target impedance range and the impedance test value; the impedance test result is used to indicate whether to adjust the linewidth or dielectric layer thickness of the inner electroplated layer.

8. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1 to 6.

10. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method of any one of claims 1 to 6.

Images