Semiconductor structure, preparation method of semiconductor structure and electronic equipment

Abstract

The invention provides a semiconductor structure, a preparation method of the semiconductor structure and electronic equipment, the semiconductor structure comprises a substrate, multiple layers of storage arrays, multiple word lines and multiple bit lines, and the multiple layers of storage arrays are stacked in the direction perpendicular to the substrate; each layer of storage array comprises a plurality of storage units, and the storage units are arranged in an array mode in the row direction and the column direction; each storage unit comprises a transistor; the first electrodes of the transistors corresponding to the row of storage units arranged in the direction perpendicular to the substrate are connected to the same bit line; channels of the transistors of the storage units located on the same layer and in the same column are all connected to the same word line; in the word lines, the width of a part of the word lines corresponding to the channels of the transistors is greater than that of the rest of the word lines; in the channel of the transistor, the width of a part of the channel corresponding to the word line is greater than the width of the rest part of the channel. The preparation difficulty and cost of the semiconductor structure are reduced.

Description

Semiconductor structure, semiconductor structure fabrication method and electronic device Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for preparing the semiconductor structure, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] In view of the above problems, this application provides a semiconductor structure, a method for fabricating the semiconductor structure, and an electronic device to improve the integration of the semiconductor structure and reduce the fabrication difficulty and cost.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0006] The first aspect of this application provides a semiconductor structure, including:

[0007] Substrate;

[0008] A multilayer memory array, wherein multiple memory arrays are stacked along a direction perpendicular to the substrate; each layer of the memory array includes multiple memory cells, which are arranged in an array along row and column directions; each memory cell includes a transistor;

[0009] Multiple word lines, wherein the multiple word lines are stacked at intervals along a direction perpendicular to the substrate, and all extend along the column direction;

[0010] Multiple bit lines are arranged in an array along the row direction and the column direction, and all extend in a direction perpendicular to the substrate.

[0011] The first electrode of each transistor corresponding to a row of memory cells arranged in a direction perpendicular to the substrate is connected to the same bit line; the channels of the transistors of memory cells located in the same layer and the same column are all connected to the same word line.

[0012] In the word lines, the width of the portion of the word lines corresponding to the channel of the transistor is greater than the width of the remaining portion of the word lines;

[0013] In the channel of the transistor, the width of the portion of the channel corresponding to the word line is greater than the width of the remaining portion of the channel;

[0014] The row direction and the column direction are both parallel to the substrate and intersect each other.

[0015] In some embodiments, the character line includes a first character line portion and a second character line portion that are connected to each other;

[0016] In the same character line, the first character line portion is spaced apart along the column direction, and the second character line portion is connected between adjacent first character line portions;

[0017] The first word line portion is opposite to the channel of the transistor; the second word line portion is offset from the channel of the transistor.

[0018] The width of the first character line is greater than the width of the second character line.

[0019] In some embodiments, both sides of the second character line portion along the width direction are arc-shaped edges, and the arc-shaped edges of the second character line portion are recessed toward the center side of the second character line portion along the width direction.

[0020] In some embodiments, the word line includes two sub-word lines;

[0021] Two sub-word lines are spaced apart along a direction perpendicular to the substrate and are located on opposite sides of the transistor connected to the word lines.

[0022] In some embodiments, the channel of the transistor extends along the row direction and includes a first semiconductor portion and two second semiconductor portions;

[0023] In the same transistor, two second semiconductor portions are connected to both sides of the first semiconductor portion along the row direction;

[0024] The first semiconductor portion is opposite to the first word line portion, forming the channel of the transistor;

[0025] The width of the first semiconductor portion is greater than the width of the second semiconductor portion.

[0026] In some embodiments, the channel width of the transistor gradually decreases along the direction from the first semiconductor portion to the second semiconductor portion;

[0027] The first semiconductor portion is located near both sides of the two second semiconductor portions, and both sides of its edge along the width direction of the transistor channel are arc-shaped edges. The arc-shaped edges of the first semiconductor portion are recessed toward the center side of the transistor channel along the width direction.

[0028] In some embodiments, each of the memory cells includes a capacitor;

[0029] The second terminal of the transistor in each of the memory cells is connected to the capacitor.

[0030] In some embodiments, the capacitor includes a plurality of first capacitor electrodes and second capacitor electrodes, wherein the second capacitor electrode includes a first sub-electrode;

[0031] The semiconductor structure further includes a capacitor hole penetrating through multiple layers of the memory cells, with multiple first capacitor electrodes opposite to multiple memory cells disposed on different layers and arranged in a direction perpendicular to the substrate; the multiple first capacitor electrodes are disposed on the sidewall of the capacitor hole and are spaced apart in a direction perpendicular to the substrate.

[0032] The first sub-electrode fills the capacitor hole, and a plurality of the first capacitor electrodes surround the first sub-electrode through a first dielectric layer.

[0033] In some embodiments, the first capacitor electrode includes a first portion extending in a direction perpendicular to the substrate and a second portion extending from both ends of the first portion toward the first sub-electrode.

[0034] The first portion of each of the first capacitor electrodes is connected to the second electrode of each of the transistors in the plurality of memory cells in a one-to-one correspondence.

[0035] In some embodiments, the second capacitor electrode further includes a second sub-electrode, which surrounds the first capacitor electrode via a second dielectric layer portion.

[0036] In some embodiments, each of the capacitors has a projection on the surface of the substrate, and the projection extends along the row direction by a length greater than the projection extends along the column direction.

[0037] A second aspect of this application provides a method for fabricating a semiconductor structure, comprising:

[0038] A stacked structure is formed on a substrate, and the stacked structure includes a plurality of alternating semiconductor structure layers and sacrificial layers along a direction perpendicular to the substrate;

[0039] Along a direction perpendicular to the substrate, a plurality of first deep holes, a plurality of second deep holes, a plurality of third deep holes, a plurality of fourth deep holes, and a plurality of first trenches are formed through the stacked structure; the plurality of first deep holes, the plurality of second deep holes, the plurality of third deep holes, and the plurality of fourth deep holes are distributed at intervals along the column direction, and the first trenches extend along the column;

[0040] Multiple word lines are formed through the fourth deep hole and the first trench. The multiple word lines are stacked at intervals along a direction perpendicular to the substrate and all extend along the column direction.

[0041] Multiple bit lines are formed through the second deep hole and the fourth deep hole. The multiple bit lines are arranged in an array along the row direction and the column direction, and all extend in a direction perpendicular to the substrate.

[0042] The semiconductor structure layer is laterally etched based on the second and third deep holes, such that the second and third deep holes are connected, to cut the semiconductor structure layer into channels of a plurality of transistors extending along the row direction and spaced apart along the column direction; the width of the word line corresponding to the channel of the transistor is greater than the width of the remaining word line; the width of the channel of the transistor corresponding to the word line is greater than the width of the remaining channel of the transistor; wherein the row direction and the column direction are both parallel to the substrate and intersect.

[0043] In some embodiments, multiple letter lines are formed through the fourth deep hole and the first trench, specifically including:

[0044] The sacrificial layer is etched laterally along the sidewall of the fourth deep hole to form a first lateral trench between two adjacent semiconductor structure layers;

[0045] Based on the first lateral trench, the thickness of the semiconductor structure layer in the direction perpendicular to the substrate is reduced, and the thinned semiconductor structure layer is oxidized to form a gate insulating layer;

[0046] An initial character line is formed that covers the inner wall of the first transverse groove, and the initial character line has an initial character line groove.

[0047] An isolation layer is formed in the initial word line groove;

[0048] Based on the fourth deep hole and the first trench, the initial word line is laterally etched at both ends along the row direction to form a plurality of first sub-word lines and second sub-word lines spaced apart along the direction perpendicular to the substrate. Along the direction perpendicular to the substrate, the plurality of first sub-word lines and the plurality of second sub-word lines are alternately spaced apart and together form a plurality of word lines spaced apart along the direction perpendicular to the substrate. The first sub-word lines and second sub-word lines located on adjacent sides of the channel of each transistor together form a word line extending along the column direction.

[0049] In some embodiments, the semiconductor structure layer is laterally etched based on the second deep hole and the third deep hole, such that the second deep hole and the third deep hole are connected, so as to cut the semiconductor structure layer into channels of a plurality of transistors extending along the row direction and spaced apart along the column direction, specifically including:

[0050] The stacked structure is etched along the first deep hole and the fourth deep hole to form an initial semiconductor layer in the semiconductor structure layer;

[0051] Based on the fourth deep hole, a transistor contact terminal is formed at the end of the initial semiconductor layer;

[0052] The initial semiconductor layer is etched laterally along the second and third deep holes to form a first semiconductor portion and a second semiconductor portion.

[0053] Along the column direction, the first semiconductor portion is offset from the second deep hole and the third deep hole, and the second semiconductor portion corresponds to the second deep hole and the third deep hole respectively; the first semiconductor portion forms the channel of the transistor.

[0054] In some embodiments, the semiconductor structure layer includes silicon, and based on the fourth deep hole, a transistor contact is formed at the end of the initial semiconductor layer, specifically including:

[0055] A metal layer is formed on the exposed end face of the initial semiconductor layer based on the fourth deep hole;

[0056] A high-temperature annealing process is used to form a metal silicide, and a wet etching process is used to remove excess metal layers. The metal silicide forms the contact terminals of the transistor.

[0057] In some embodiments, multiple bit lines are formed through the second deep hole and the fourth deep hole, specifically including:

[0058] An initial bit line is formed in the fourth deep hole to cover the interior of the fourth deep hole;

[0059] A filling layer is formed that covers the initial bit line and fills the fourth deep hole;

[0060] The initial bit lines are partially removed by the second deep hole etching to form multiple bit lines.

[0061] In some embodiments, after forming the word line and before forming the transistor, the method further includes:

[0062] Based on the sidewall of the first deep hole, the semiconductor structure layer is laterally etched to form a plurality of capacitor electrode trenches spaced apart along a direction perpendicular to the substrate;

[0063] A plurality of first capacitor electrodes are formed in the capacitor electrode trench, and the plurality of first capacitor electrodes are located on the sidewalls of the plurality of capacitor electrode trenches;

[0064] Based on the sidewall of the first deep hole, the sacrificial layer is etched laterally to form a plurality of second lateral trenches spaced apart along a direction perpendicular to the substrate;

[0065] A first dielectric layer is formed covering the inner wall of the first deep hole, the first capacitor electrode, and the inner wall of the second lateral groove; a first sub-electrode is formed covering the first dielectric layer and filling the first deep hole, the capacitor electrode trench, and the second lateral groove.

[0066] Based on the first trench etching, the semiconductor structure layer is laterally removed to form a third lateral trench;

[0067] A second dielectric layer and a second sub-electrode are sequentially formed in the third transverse trench;

[0068] The first sub-electrode and the second sub-electrode form the second capacitor electrode, and the first capacitor electrode, the second capacitor electrode, the first dielectric layer and the second dielectric layer form the capacitor.

[0069] A third aspect of this application also provides an electronic device, comprising: a semiconductor structure fabricated by the semiconductor structure fabrication method provided in the above embodiments; or, a semiconductor structure provided in the above embodiments.

[0070] In the semiconductor structure fabrication method provided in this application embodiment, the first deep hole, second deep hole, third deep hole, fourth deep hole, and first trench are first etched into the stacked structure using three dry etching processes. Then, multiple word lines are formed by lateral etching along the first trench and fourth deep hole. These word lines are stacked at intervals along a direction perpendicular to the substrate and extend along the column direction. Multiple bit lines are formed through the second and fourth deep holes. These bit lines are arranged in an array along the row and column directions and extend along a direction perpendicular to the substrate. The semiconductor structure layer is laterally etched based on the second and third deep holes, such that the second deep hole and the third deep hole... The vias are interconnected to cut the semiconductor structure layer into channels of multiple transistors extending in the row direction and spaced apart in the column direction; the width of the word line corresponding to the channel of the transistor is greater than the width of the remaining word line; the width of the channel of the transistor corresponding to the word line is greater than the width of the remaining channel of the transistor; thus, in subsequent fabrication processes, there is no need to fabricate deep vias. This avoids the difficulty of fabricating deep vias in subsequent fabrication processes and also avoids the problem of low alignment accuracy during deep via fabrication, thereby reducing the fabrication difficulty and cost of three-dimensional memory.

[0071] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure, the method for preparing the semiconductor structure, and the electronic device provided by the embodiments of this application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific embodiments. Attached Figure Description

[0072] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0073] Figure 1 is a schematic diagram of a semiconductor structure after the silicon oxide layer is hidden in an embodiment of this application;

[0074] Figure 2 is a cross-sectional view along CC in Figure 1;

[0075] Figure 3 is a schematic cross-sectional view along point AA in Figure 1;

[0076] Figure 4 is a schematic flowchart of the semiconductor structure fabrication method provided in the embodiments of this application;

[0077] Figure 5 is a schematic diagram of the structure in which the first deep hole and the second deep hole are formed in the stacked structure in an embodiment of this application;

[0078] Figure 5a is a cross-sectional view of section BB in Figure 5;

[0079] Figure 5b is a cross-sectional view of point CC in Figure 5;

[0080] Figure 6 is a schematic diagram of the structure in which the third and fourth deep holes are formed in the stacked structure in an embodiment of this application;

[0081] Figure 6a is a cross-sectional view of section BB in Figure 6;

[0082] Figure 6b is a cross-sectional view of CC in Figure 6;

[0083] Figure 7 is a schematic diagram of the structure in which the first trench is formed in the stacked structure in an embodiment of this application;

[0084] Figure 7a is a cross-sectional view of section BB in Figure 7;

[0085] Figure 7b is a cross-sectional view of point CC in Figure 7;

[0086] Figure 8 is a schematic diagram of the structure in which the initial bit line hole is formed in the stacked structure in an embodiment of this application;

[0087] Figure 8a is a cross-sectional view of section AA in Figure 8;

[0088] Figure 8b is a cross-sectional view of CC in Figure 8;

[0089] Figure 9 is a schematic diagram of the structure in which the initial double-word line is formed in the stacked structure in an embodiment of this application;

[0090] Figure 9a is a cross-sectional view of section BB in Figure 9;

[0091] Figure 9b is a cross-sectional view of point CC in Figure 9;

[0092] Figure 10 is a schematic diagram of the structure in which the initial bit line is formed in the stacked structure in an embodiment of this application;

[0093] Figure 10a is a cross-sectional view of section BB in Figure 10;

[0094] Figure 10b is a cross-sectional view of CC in Figure 10;

[0095] Figure 11 is a schematic diagram of the structure in which double-line characters are formed in the stacked structure in an embodiment of this application;

[0096] Figure 11a is a cross-sectional view of section BB in Figure 11;

[0097] Figure 11b is a cross-sectional view of CC in Figure 11;

[0098] Figure 12 is a schematic diagram of the internal structure of the capacitor in the stacked structure in an embodiment of this application;

[0099] Figure 12a is a cross-sectional view of section BB in Figure 12;

[0100] Figure 12b is a cross-sectional view of point CC in Figure 12;

[0101] Figure 13 is a schematic diagram of the external structure of the capacitor formed in the stacked structure in an embodiment of this application;

[0102] Figure 13a is a cross-sectional view of section AA in Figure 13;

[0103] Figure 13b is a cross-sectional view of section BB in Figure 13;

[0104] Figure 13c is a cross-sectional view of CC in Figure 13;

[0105] Figure 14 is a schematic diagram of the sub-line and channel structure in the stacked structure in an embodiment of this application;

[0106] Figure 14a is a cross-sectional view of section BB in Figure 14;

[0107] Figure 14b is a cross-sectional view of CC in Figure 14;

[0108] Figure 15 is a schematic diagram of the structure filled with silicon oxide in an embodiment of this application;

[0109] Figure 15a is a cross-sectional view of BB in Figure 15;

[0110] Figure 15b is a cross-sectional view of point CC in Figure 15.

[0111] Explanation of reference numerals in the attached figures:

[0112] 10-Semiconductor structure;

[0113] 100 - Substrate; 110 - Stacked structure; 111 - Semiconductor structure layer; 111a - Initial semiconductor layer;

[0114] 112 - Sacrificial layer; 113 - First sacrificial structure;

[0115] 114 - Second sacrificial structure; 115 - Third sacrificial structure; 116 - Fourth sacrificial structure; 117 - Fifth sacrificial structure;

[0116] 118-silicon nitride layer;

[0117] 120 - Word line; 120a - Initial word line; 121 - First sub-word line; 122 - Second sub-word line;

[0118] 123 - First character line; 124 - Second character line;

[0119] 130 - Bit line; 130a - Initial bit line;

[0120] 140 - Capacitor; 141 - First capacitor electrode; 1411 - First part; 1412 - Second part;

[0121] 142 - Second capacitor electrode; 1421 - First sub-electrode; 1422 - Second sub-electrode; 143 - First dielectric layer; 144 - Second dielectric layer;

[0122] 150 - First transverse trench; 151 - Isolation layer;

[0123] 160 - Transistor; 161 - Channel; 1611 - First semiconductor section; 1612 - Second semiconductor section; 162 - First electrode; 163 - Second electrode;

[0124] 170 - Dielectric layer; 171 - Initial bit line via;

[0125] 190 - Gate insulation layer;

[0126] 200 - First deep hole; 210 - Second deep hole; 220 - Third deep hole; 230 - Fourth deep hole;

[0127] 240 - First trench;

[0128] 250 - Filler layer. Detailed Implementation

[0129] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0130] Where there is no conflict, the embodiments of this application and the features in the embodiments can be combined arbitrarily with each other.

[0131] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning as understood by a person of ordinary skill in the art to which this application pertains.

[0132] The embodiments described in this application are not necessarily limited to the dimensions shown in the accompanying drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments described in this application are not limited to the shapes or values ​​shown in the drawings.

[0133] In this application, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° to 10°, therefore also including angles of -5° to 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° to 100°, therefore also including angles of 85° to 95°. Figure 1 is a schematic diagram of a semiconductor structure with a hidden isolation layer provided in an embodiment of this application; referring to Figure 1, this application provides a semiconductor structure 10, which can be a three-dimensional dynamic random access memory (DRAM); the DRAM includes a substrate 100 and a multilayer memory array, the multilayer memory array being stacked along a direction perpendicular to the substrate 100; in Figure 1, the direction perpendicular to the substrate 100 is, for example, a third direction. The substrate 100 can provide a supporting foundation for the multilayer memory array located thereon.

[0134] Each layer of the memory array includes multiple memory cells, which are arranged in an array along the row and column directions. The row and column directions are parallel to the substrate 100 and intersect each other. Each memory cell includes a transistor 160. In Figure 1, the row direction is, for example, a first direction, and the column direction is, for example, a second direction.

[0135] In addition, the semiconductor structure 10 also includes multiple word lines 120 and multiple bit lines 130. The multiple word lines 120 are stacked at intervals along a direction perpendicular to the substrate 100 (third direction) and all extend along the column direction (second direction). The multiple bit lines 130 are arranged in an array along the row direction and the column direction and all extend along a direction perpendicular to the substrate 100. That is, each bit line 130 extends along the third direction and there are multiple bit lines 130 in the first direction and the second direction, respectively.

[0136] As shown in Figure 1, in each layer of memory cells, the first electrode 162 of each transistor 160 corresponding to a row of memory cells arranged in a direction perpendicular to the substrate 100 is connected to the same bit line 130; the channels 161 of the transistors 160 of memory cells located in the same layer and the same column are all connected to the same word line 120. In this way, the number of word lines 120 can be reduced, the cost can be reduced, the space utilization can be improved, and the integration of the semiconductor structure 10 can be improved.

[0137] It should be noted that, in this embodiment of the application, by extending the bit line 130 in a direction perpendicular to the substrate 100, the load on the bit line 130 can be reduced, and the control accuracy of the bit line 130 can be improved, thereby improving the overall performance of the semiconductor structure 10.

[0138] In addition, each memory cell also includes a capacitor 140, and the second terminal 163 of the transistor 160 of each memory cell is connected to the capacitor 140. The first terminal 162 of the transistor 160 is one of the source and drain of the transistor 160, and the second terminal 163 of the transistor 160 is the other of the source and drain of the transistor 160. The positions of the source and drain of the transistor 160 can be interchanged according to specific requirements.

[0139] In this embodiment, the width of the portion of word line 120 corresponding to the channel 161 of transistor 160 is greater than the width of the remaining portion of word line 120; the width of the portion of channel 161 corresponding to word line 120 in transistor 160 is greater than the width of the remaining portion of channel 161. This increases the relative area between the channel and the gate (the area corresponding to the word line and the channel is used as the gate of the transistor), improves gate control, and thus improves the performance of semiconductor structure 10 while also increasing the integration density of semiconductor structure 10.

[0140] Referring to Figure 1, each word line 120 includes a first word line portion 123 and a second word line portion 124 that are interconnected. In the same word line 120, the first word line portions 123 are spaced apart along the column direction, and the second word line portions 124 are connected between adjacent first word line portions 123. The first word line portions 123 are opposite to the channel 161 of the transistor 160. The second word line portions 124 are offset from the channel 161 of the transistor 160. The width of the first word line portion 123 is greater than the width of the second word line portion 124.

[0141] For example, as shown in FIG1, both sides of the second character line portion 124 along the width direction of the character line 120 are curved edges, and the curved edges of the second character line portion 124 are recessed toward the center side of the second character line portion 124 along the width direction. Here, the width direction of the character line 120 is, for example, along a first direction, and the curved edges of the second character line portion 124 include, but are not limited to, curved edges that are rounded, without specific limitation here.

[0142] Alternatively, word line 120 can be a double word line 120 structure; for example, as shown in FIG2, each word line 120 includes two sub-word lines 120; along the direction perpendicular to the substrate 100 (i.e., the third direction), the two sub-word lines 120 are spaced apart and located on opposite sides of the transistor 160 connected to the word line 120.

[0143] For ease of description, the two sub-word lines 120 in each word line 120 can be represented by the first sub-word line 121 and the second sub-word line 122, respectively. The first sub-word line 121 is located on the upper side of the transistor 160 connected to the word line 120, and the second sub-word line 122 is located on the lower side of the transistor 160 connected to the word line 120.

[0144] In this embodiment, by setting the word line 120 as a double word line 120 structure, the relative area between the word line 120 and the transistor 160 can be increased, thereby improving the gate control capability and enhancing the reliability of the working performance of the semiconductor structure 10.

[0145] In some embodiments, as shown in FIG3, the channel 161 of the transistor 160 extends along the row direction and includes a first semiconductor portion 1611 and two second semiconductor portions 1612; in the same transistor 160, the two second semiconductor portions 1612 are connected to both sides of the first semiconductor portion 1611 along the row direction; the first semiconductor portion 1611 is opposite to the first word line portion 123 to form the channel 161 of the transistor 160; the width of the first semiconductor portion 1611 is greater than the width of the second semiconductor portion 1612, which can increase the width and area of ​​the channel, thereby improving the working performance of the transistor 160 and increasing the integration density of the semiconductor structure 10.

[0146] For example, along the direction from the first semiconductor portion 1611 to the second semiconductor portion 1612, the width of the channel 161 of the transistor 160 gradually decreases; the first semiconductor portion 1611 is close to both sides of the two second semiconductor portions 1612, and both sides of the channel 161 of the transistor 160 are arc-shaped edges. The arc-shaped edges of the first semiconductor portion 1611 are all recessed toward the center side of the channel 161 of the transistor 160 along the width direction. The arc-shaped edges of the first semiconductor portion 1611 include, but are not limited to, arc-shaped edges.

[0147] In some embodiments, capacitor 140 includes a plurality of first capacitor electrodes 141 and second capacitor electrodes 142, the second capacitor electrode 142 including a first sub-electrode 1421; semiconductor structure 10 also includes a capacitor hole penetrating through multiple layers of memory cells, the plurality of first capacitor electrodes 141 being opposite to a plurality of memory cells disposed on different layers and in a direction perpendicular to substrate 100; the plurality of first capacitor electrodes 141 are disposed on the sidewall of the capacitor hole and are spaced apart in a direction perpendicular to substrate 100; the first sub-electrode 1421 fills the capacitor hole, and the plurality of first capacitor electrodes 141 surround the first sub-electrode 1421 through a first dielectric layer 143; exemplary, as shown in FIG2, the plurality of first capacitor electrodes 141 surround the outer periphery of the first sub-electrode 1421 through the first dielectric layer 143, and the second electrode 163 of transistor 160 is connected to the first capacitor electrode 141 on the same layer opposite to it.

[0148] In some embodiments, the first capacitor electrode 141 includes a first portion 1411 extending along a direction perpendicular to the substrate 100 and a second portion 1412 extending from both ends of the first portion 1411 toward the first sub-electrode 1421, respectively; the first portions 1411 of the plurality of first capacitor electrodes 141 are connected one-to-one with the second poles 163 of the transistors 160 of the plurality of memory cells (a portion of the first capacitor electrode 141 can be reused as the second pole 163).

[0149] In addition, the second capacitor electrode 142 also includes a second sub-electrode 1422, which is partially surrounded by the first capacitor electrode 141 through the second dielectric layer 144. In this way, the relative area of ​​the first capacitor electrode 141 and the second capacitor electrode 142 can be increased, thereby increasing the storage capacity of the capacitor 140.

[0150] In order to further improve the integration and space utilization of the semiconductor structure 10, in this embodiment, each capacitor 140 has a projection on the surface of the substrate 100, and the extension length of the projection along the row direction is greater than the extension length of the projection along the column direction. In this way, the arrangement density of the capacitors 140 in the second direction can be increased, thereby improving the space utilization.

[0151] This application provides a method for preparing a semiconductor structure, which can prepare a semiconductor structure as provided in the above embodiments.

[0152] Please refer to Figure 4. The preparation method includes:

[0153] S1: A stacked structure is formed on a substrate. Along the direction perpendicular to the substrate, the stacked structure includes multiple alternating semiconductor structural layers and sacrificial layers.

[0154] S2: Along the direction perpendicular to the substrate, a plurality of first deep holes, a plurality of second deep holes, a plurality of third deep holes, a plurality of fourth deep holes and a plurality of first trenches are formed through the stacked structure; the plurality of first deep holes, a plurality of second deep holes, a plurality of third deep holes and a plurality of fourth deep holes are distributed at intervals along the column direction, and the first trenches extend along the column.

[0155] S3: Multiple word lines are formed through the fourth deep hole and the first trench. The multiple word lines are stacked at intervals along the direction perpendicular to the substrate 100 and all extend along the column direction.

[0156] S4: Multiple bit lines are formed through the second and fourth deep holes. The multiple bit lines are arranged in an array along the row and column directions and all extend in a direction perpendicular to the substrate.

[0157] S5: Laterally etch the semiconductor structure layer based on the second and third deep holes, so that the second and third deep holes are connected, so as to cut the semiconductor structure layer into channels of multiple transistors extending in the row direction and spaced apart in the column direction; the width of the word line corresponding to the channel of the transistor is greater than the width of the remaining word line; the width of the channel of the transistor corresponding to the word line is greater than the width of the remaining channel of the transistor; wherein, the row direction and the column direction are parallel to the substrate and intersect each other.

[0158] In a specific implementation, referring to Figure 5, multiple semiconductor structure layers 111 and sacrificial layers 112 can be formed sequentially on the substrate 100 along a direction perpendicular to the substrate 100 (i.e., the third direction) using chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes. In this way, the semiconductor structure layers 111 and sacrificial layers 112 sequentially stacked on the substrate 100 along the third direction together form a stacked structure 110.

[0159] Understandably, substrate 100 can provide a supporting foundation for stacked structure 110.

[0160] Wherein, the semiconductor structure layer 111 includes, but is not limited to, a single crystal silicon layer, and the sacrificial layer 112 includes, but is not limited to, a germanium silicon layer. In the stacked structure 110, both the semiconductor structure layer 111 and the sacrificial layer 112 are at least two layers. The at least two semiconductor structure layers 111 and the at least two sacrificial layers 112 are sequentially overlapped along the direction perpendicular to the substrate 100, that is, the sacrificial layer 112 is located between two adjacent semiconductor structure layers 111.

[0161] Referring to Figures 5 and 5b, after forming a stacked structure 110 on the substrate 100, silicon oxide material is deposited on the stacked structure 110 to form a dielectric layer 170. A first photoresist layer is formed on the dielectric layer 170 and patterned. Using the patterned first photoresist layer as a mask, the stacked structure 110 is etched to form a plurality of first deep holes 200 and a plurality of second deep holes 210 penetrating the stacked structure 110 along a third direction.

[0162] The plurality of first deep holes 200 form at least two first deep hole groups, the at least two first deep hole groups are arranged at intervals along a first direction, each first deep hole group includes at least two first deep holes 200, and the at least two first deep holes 200 in each first deep hole group are arranged at intervals along a second direction; the plurality of second deep holes 210 form at least one second deep hole group, the second deep hole group includes at least two second deep holes 210, and the at least two second deep holes 210 in each second deep hole group are arranged at intervals along a second direction.

[0163] For example, as shown in Figures 5 to 5a, two first deep hole groups and a second deep hole group are formed in the stacked structure 110, with a second deep hole group located between the two first deep hole groups.

[0164] In addition, multiple first deep holes 200 and multiple second deep holes 210 are formed simultaneously in a single etching process, which reduces the number of fabrication processes and thus lowers the fabrication cost.

[0165] After forming multiple first deep holes 200 and multiple second deep holes 210, silicon oxide material can be deposited on the hole walls of each first deep hole 200 and each second deep hole 210 by CVD process, ALD process or physical vapor deposition (PVD) process, so as to form a first silicon oxide layer on the hole wall of each first deep hole 200 and a second silicon oxide layer on the hole wall of each second deep hole 210.

[0166] Next, referring to Figures 5a and 5b, sacrificial materials are deposited on the first silicon oxide layer and the second silicon oxide layer, respectively, to fill the first deep hole 200 and the second deep hole 210 with the sacrificial materials, so as to form a first sacrificial structure 113 in the first deep hole 200 and a second sacrificial structure 114 in the second deep hole 210; wherein, the sacrificial material includes, but is not limited to, polycrystalline silicon material.

[0167] After forming the first sacrificial structure 113 and the second sacrificial structure 114 in the first deep hole 200 and the second deep hole 210 respectively, the top surfaces of the first sacrificial structure 113 and the second sacrificial structure 114 are planarized by chemical mechanical polishing.

[0168] It is understandable that after forming the first deep hole 200 and the second deep hole 210, a first sacrificial structure 113 is formed in the first deep hole 200 and a second sacrificial material is formed in the second deep hole 210, so as to improve the strength of the stacked structure 110 and avoid the problem of insufficient strength of the stacked structure 110 leading to collapse when preparing subsequent deep holes.

[0169] After planarizing the top surfaces of the first sacrificial structure 113 and the second sacrificial structure 114 using a chemical mechanical polishing process, as shown in Figures 6, 6a and 6b, a first mask layer is formed on the dielectric layer 170, and a second photoresist layer is coated on the first mask layer. The second photoresist layer is exposed, and the first mask layer is patterned using the exposed second photoresist layer. Using the patterned first mask layer as a mask, the stacked structure 110 is etched using a dry etching process to form a third deep hole 220 and a fourth deep hole 230 on the stacked structure 110.

[0170] The third deep hole 220 is multiple, and the multiple third deep holes 220 are formed into at least two third deep hole groups. The at least two third deep hole groups are spaced apart along a first direction. For example, there are two third deep hole groups, one third deep hole group is located between a first deep hole group and a second deep hole group, and the other third deep hole group is located between another first deep hole group and a second deep hole group. The third deep hole group 220 includes at least two third deep holes 220, and the at least two third deep holes 220 in each third deep hole group are spaced apart along a second direction. The fourth deep hole 230 is also multiple, and the multiple fourth deep holes 230 and the multiple second deep holes 210 are alternately spaced apart in the second direction (as shown in Figure 7a).

[0171] After forming the third deep hole 220 and the fourth deep hole 230 on the stacked structure 110, silicon oxide material can be deposited on the hole walls of the third deep hole 220 and the fourth deep hole 230 respectively by CVD process, ALD process or PVD process, so as to form a third silicon oxide layer on the hole wall of the third deep hole 220 and a fourth silicon oxide layer on the hole wall of the fourth deep hole 230.

[0172] Next, referring to Figures 6a and 6b, sacrificial materials are deposited on the third silicon oxide layer and the fourth silicon oxide layer, respectively, to fill the third deep hole 220 and the fourth deep hole 230 with the sacrificial materials, so as to form a third sacrificial structure 115 in the third deep hole 220 and a fourth sacrificial structure 116 in the fourth deep hole 230; wherein, the sacrificial material includes, but is not limited to, polycrystalline silicon material.

[0173] After forming the third sacrificial structure 115 and the fourth sacrificial structure 116 in the third deep hole 220 and the fourth deep hole 230 respectively, the top surfaces of the third sacrificial structure 115 and the fourth sacrificial structure 116 are planarized by chemical mechanical polishing.

[0174] Referring to Figures 7, 7a, and 7b, after planarizing the top surfaces of the third sacrificial structure 115 and the fourth sacrificial structure 116 using a chemical mechanical polishing process, a second mask layer is formed on the dielectric layer 170, and a third photoresist layer is coated on the second mask layer. The third photoresist layer is then exposed, and the exposed third photoresist layer is used to pattern the second mask layer. Using the patterned second mask layer as a mask, a dry etching process is employed to etch the stacked structure 110 to form two first trenches on opposite sides of the substrate 100 along the second direction.

[0175] After the first trench 240 is formed, the sacrificial layer 112 is etched laterally along the sidewall of the first trench 240 using a wet etching process. The etching is stopped at the position corresponding to the center of the third deep hole 220. This position serves as the connection point between the subsequently formed transistor 160 and capacitor 140. In this way, a third lateral trench is formed between adjacent semiconductor structure layers 111.

[0176] Subsequently, an isolation material, such as silicon nitride, can be deposited on the wall of the first trench 240 using CVD, ALD, or PVD processes. This allows the silicon nitride to fill the third lateral trench and cover the wall of the first trench 240, forming a silicon nitride layer 118 on the wall of the first trench 240. A sacrificial material is then deposited on the silicon nitride layer 118 to fill the first trench 240, forming a fifth sacrificial structure 117 in the first trench 240. Afterward, a chemical mechanical polishing process is used to planarize the surface of the fifth sacrificial structure 117.

[0177] Subsequently, word lines 120, bit lines 130, transistors 160, and capacitors 140 are fabricated in the stacked structure 110 based on the first deep hole 200, the second deep hole 210, the third deep hole 220, the fourth deep hole 230, and the first trench 240.

[0178] In the above embodiment, firstly, the first deep hole 200, the second deep hole 210, the third deep hole 220, the fourth deep hole 230 and the first trench 240 are all etched on the stacked structure 110 by three dry etching processes. Then, based on the first deep hole 200, the second deep hole 210, the third deep hole 220, the fourth deep hole 230 and the first trench 240, word lines 120, bit lines 130, transistors 160 and capacitors 140 are formed in the stacked structure 110. In this way, in the subsequent fabrication process, there is no need to fabricate deep holes again, which can avoid the difficulty of fabricating deep holes in the subsequent fabrication process and the problem of low alignment accuracy during the deep hole fabrication process. This can reduce the fabrication difficulty and cost of the three-dimensional memory.

[0179] After the first deep hole 200, the second deep hole 210, the third deep hole 220, the fourth deep hole 230 and the first trench 240 are all etched, based on Figure 7, a third mask layer is formed on the dielectric layer 170, a fourth photoresist layer is formed on the third mask layer, and the fourth photoresist layer is exposed to pattern the third mask layer. The patterned third mask layer exposes the position corresponding to the fourth deep hole 230, and the dielectric layer 170 is etched with the patterned fourth mask layer to form an initial bit line hole 171 on the dielectric layer 170 (as shown in Figure 8). The initial bit line hole 171 exposes the fourth sacrificial structure 116. It should be noted that the initial bit line hole 171 is not a deep hole etching, but only the dielectric layer 170 on the top of the stacked structure 110 is etched.

[0180] Referring to Figures 8a and 8b, after forming the initial bit line via 171, a wet etching process is used to etch the fourth sacrificial structure 116, exposing the fourth silicon oxide layer on the sidewall of the fourth deep via 230. The fourth silicon oxide layer is then etched using a wet etching process to expose the semiconductor structure layer 111 and the sacrificial layer 112, which are sequentially overlapped along the first direction. Subsequently, the sacrificial layer 112 is etched laterally in the fourth deep via 230 using a wet etching process to expose the silicon nitride layer 118 between adjacent semiconductor structure layers 111, forming a first lateral trench 150 between two adjacent semiconductor structure layers 111. At this time, each semiconductor structure layer 111 near the fourth deep via 230 is in a suspended state (as shown in Figure 8b).

[0181] Subsequently, based on the first lateral trench 150, the semiconductor structure layer 111 is further etched using a wet etching process to reduce the thickness of the semiconductor structure layer 111 in the direction perpendicular to the substrate 100, thereby increasing the width of each first lateral trench 150 in the direction perpendicular to the substrate 100. The thinned semiconductor structure layer 111 forms part of the initial semiconductor layer 111a of the transistor 160.

[0182] Referring to Figures 9, 9a, and 9b, after thinning the semiconductor structure layer 111, a high-temperature thermal oxidation process is used to thermally oxidize the semiconductor structure layer 111 (i.e., high-temperature thermal oxidation of single-crystal silicon) to form a gate insulating layer 190 on the surface of the semiconductor structure layer 111. The gate insulating layer 190 is a silicon oxide gate oxide layer. Then, a metal material, such as titanium nitride, is deposited to form a titanium nitride layer (TiN) on the surface of the gate insulating layer 190. The titanium nitride layer forms an initial layer covering the inner wall of the first lateral trench 150. The initial word line 120a has an initial word line trench. An isolation material, such as silicon oxide, is deposited in the initial word line trench to fill the initial word line trench and form an isolation layer 151. Then, the initial word line 120a is laterally etched along the row direction of the fourth deep hole 230 near one end of the fourth deep hole 230 to expose the isolation layer 151, such that there are gaps between the isolation layer 151 and the adjacent semiconductor structure layer 111 on both sides along the direction perpendicular to the substrate 100 (as shown in FIG. 9b).

[0183] Based on the structure shown in Figure 9b, and referring to Figures 10, 10a, and 10b, silicon oxide material is deposited in the fourth deep hole 230 to fill the gap between the isolation layer 151 and the adjacent semiconductor structure layer. Then, a wet etching process is used to etch the silicon oxide to expose the end face of each semiconductor structure layer 111 along the row direction, and a metal material such as titanium is deposited on the end face to form a metal layer. Since the semiconductor structure layer includes silicon, a high-temperature annealing process is used to form metal silicide, that is, to form a titanium silicide layer. Then, a wet etching process is used to remove excess titanium. The titanium silicide layer is used as the contact terminal of the transistor 160, which can reduce the contact resistance.

[0184] After forming the contact terminal of transistor 160, a metal material, such as titanium nitride, is deposited along the fourth deep hole 230 to form an initial bit line 130a covering the inner wall of the fourth deep hole 230. Then, the titanium nitride at the bottom of the fourth deep hole 230 is removed by a dry etching process, leaving only the titanium nitride layer on the sidewall of the fourth deep hole 230. Then, silicon oxide is deposited along the fourth deep hole 230 to form a filling layer 250 (shown in FIG. 10b) filling the fourth deep hole 230. Finally, the upper surface of the filling layer 250 is planarized by a chemical mechanical polishing process.

[0185] Based on the structure shown in Figure 10b, and referring to Figures 11, 11a, and 11b, a wet etching process is used to remove the fifth sacrificial structure 117 in the first trenches 240 on both sides. The wet etching process is then used to remove the silicon nitride layer 118 on the trench walls of the first trenches 240, and to remove the silicon nitride layer 118 in the third lateral trench (i.e., between adjacent semiconductor structure layers 111) via lateral etching. The silicon oxide layer is then removed via lateral etching to expose the initial word line 120a. Finally, a portion of the initial word line is removed via lateral etching. Line 120a forms multiple first sub-word lines 121 and second sub-word lines 122 spaced apart along a direction perpendicular to the substrate 100. Along a direction perpendicular to the substrate 100, the multiple first sub-word lines 121 and multiple second sub-word lines 122 are alternately spaced apart to jointly form multiple word lines 120 spaced apart along a direction perpendicular to the substrate 100. The first sub-word lines 121 and second sub-word lines 122 located on adjacent sides of the thinned initial semiconductor layer 111a respectively jointly form a word line 120 extending along the column direction (as shown in FIG11b).

[0186] Referring to Figures 12, 12a, and 12b, after forming the word line 120, silicon oxide material is deposited at one end of the word line 120 near the first trench 240, such that the silicon oxide material fills the gap between adjacent semiconductor structure layers 111 and covers the trench wall of the first trench 240. Then, sacrificial material is deposited in the first trench 240 to fill the first trench 240. Finally, chemical mechanical polishing is used to planarize the upper surface of the sacrificial material.

[0187] Subsequently, a fourth mask layer is formed on the dielectric layer 170, and a fifth photoresist layer is coated on the fourth mask layer. The fifth photoresist layer is exposed to pattern the fourth mask layer. Using the fourth mask layer as a mask, the dielectric layer 170 is etched along the position of the first deep hole 200 to form an initial capacitor hole that exposes the first sacrificial structure 113 in the first deep hole 200.

[0188] Understandably, the initial capacitor via is not a deep via etching; the etching thickness is only the thickness of the dielectric layer 170. Subsequently, a wet etching process is used to sequentially remove the first sacrificial structure 113 inside the deep via and the first silicon oxide layer on the sidewall of the first deep via 200, exposing the semiconductor structure layer 111 inside the first deep via 200. Then, a wet etching process is used to laterally etch the semiconductor structure layer 111. The retained semiconductor structure layer 111 and the thinned semiconductor structure layer 111 in the same layer together form the initial semiconductor layer 111a. That is, the stacked structure 110 is etched along the first deep via 200 and the fourth deep via 230 so that the semiconductor structure layer 111 forms the initial semiconductor layer 111a.

[0189] Referring to Figures 12, 12a, and 12b, the semiconductor structure layer 111 is etched along the sidewall of the first deep hole 200 to form multiple capacitor electrode trenches. The capacitor electrode trenches expose the end face of the initial semiconductor layer 111a. Along the first deep hole 200, metallic titanium material is deposited on the exposed end face of the initial semiconductor layer 111a, and the metallic titanium is subjected to high-temperature annealing to form a titanium silicide layer. Excess metallic titanium material and part of the titanium silicide layer are removed by wet etching, leaving only the titanium silicide layer on the end face of the initial semiconductor layer 111a. The retained titanium silicide layer forms the contact terminal of the transistor 160, which can reduce the contact resistance.

[0190] Subsequently, titanium nitride and sacrificial materials are deposited sequentially along the first deep hole 200. Then, a wet etching process is used to remove the sacrificial material and part of the titanium nitride material, while retaining the titanium nitride material on the sidewalls of the capacitor electrode trenches. This results in the formation of multiple first capacitor electrodes 141 in the first deep hole 200 along the direction perpendicular to the substrate 100. The multiple first capacitor electrodes 141 are located on the sidewalls of the multiple capacitor electrode trenches. Among them, one first capacitor electrode 141 is located on the sidewall of the capacitor electrode trench in the same layer.

[0191] After forming the first capacitor electrode 141, the silicon oxide layer in the sacrificial layer is etched along the first deep hole 200 to form a plurality of second lateral grooves spaced apart along the direction perpendicular to the substrate. A first dielectric layer 143 is formed covering the first capacitor electrode 141, the sidewall of the first deep hole 200, and the inner wall of the second lateral grooves. A first sub-electrode 1421 is formed covering the first dielectric layer 143 and filling the first deep hole 200, the capacitor electrode trench, and the second lateral grooves. The plurality of first capacitor electrodes 141 surround the first sub-electrode 1421 through the first dielectric layer 143. The first capacitor electrode 141 surrounds the side of the first dielectric layer 143 away from the first sub-electrode 1421. The first dielectric layer 143 includes, but is not limited to, a high-k material. Finally, the upper surface of the first sub-electrode 1421 is chemically and mechanically polished.

[0192] Based on Figures 12, 12a, and 12b, and referring to Figures 13 to 13c, the semiconductor structure layer 111 is etched away based on the first trench 240 to form a third lateral trench; a second dielectric layer 144 and a second sub-electrode 1422 are sequentially formed in the third lateral trench; the first sub-electrode 1421 and the second sub-electrode 1422 form a second capacitor electrode 142, and the first capacitor electrode 141, the second capacitor electrode 142, the first dielectric layer 143, and the second dielectric layer 144 form a capacitor 140.

[0193] The material of the second dielectric layer 144 includes, but is not limited to, a high-K material, and the material of the second sub-electrode 1422 includes, but is not limited to, titanium nitride, tungsten, etc.

[0194] Referring to Figures 14 to 14b, after forming the capacitor 140, a fifth mask layer is formed on the dielectric layer 170, and a sixth photoresist layer is formed on the fifth mask layer. The sixth photoresist layer is exposed to pattern the fifth mask layer. Using the patterned fifth mask layer as a mask, a portion of the initial bit line 130a is etched away based on the second deep hole 210 to form multiple bit lines 130.

[0195] Referring to Figures 14 to 14b, using the fifth mask layer as a mask, the dielectric layer 170 is etched to retain the third sacrificial structure 115 in the third deep hole 220. Wet etching is then used to sequentially remove the third sacrificial structure 115 in the third deep hole 220. Wet etching is performed along the third deep hole 220 and the second deep hole 210 to make the second deep hole and the third deep hole connected, so that the initial semiconductor layer 111a forms the first semiconductor portion 1611 and the second semiconductor portion 1612. Along the column direction, the first semiconductor portion 1611 is offset from the second deep hole 210 and the third deep hole 220, and the second semiconductor portion 1612 corresponds to the second deep hole 210 and the third deep hole 220, respectively. The first semiconductor portion 1611 forms the channel 161 of the transistor 160.

[0196] In this transistor 160, each channel 161 passes through its corresponding word line 120, that is, it is located between the first sub-word line 121 and the second sub-word line 122 of its corresponding word line 120.

[0197] Next, referring to Figures 15 to 15b, silicon oxide material is deposited in the second deep hole 210 and the third deep hole 220 by a deposition process to fill the second deep hole 210 and the third deep hole 220, and the upper surface of the dielectric layer 170 is planarized by a chemical mechanical polishing process.

[0198] Therefore, in this embodiment, firstly, the first deep hole, second deep hole, third deep hole, fourth deep hole, and first trench are all etched in the stacked structure using three dry etching processes. Then, multiple word lines are formed by lateral etching along the first trench and fourth deep hole. These word lines are stacked at intervals along a direction perpendicular to the substrate and all extend along the column direction. Multiple bit lines are formed through the second and fourth deep holes. These bit lines are arranged in an array along the row and column directions and all extend along a direction perpendicular to the substrate. The semiconductor structure layer is laterally etched based on the second and third deep holes, connecting the second and third deep holes. The semiconductor structure layer is cut into channels of multiple transistors extending in the row direction and spaced apart in the column direction. The width of the word line corresponding to the channel of the transistor is greater than the width of the remaining word line. The width of the channel of the transistor corresponding to the word line is greater than the width of the remaining channel of the transistor. Therefore, in subsequent fabrication processes, there is no need to fabricate deep holes. This avoids the difficulty of fabricating deep holes in subsequent fabrication processes and also avoids the problem of low alignment accuracy during deep hole fabrication, thereby reducing the fabrication difficulty and cost of three-dimensional memory.

[0199] This application also provides an electronic device, which includes the semiconductor structure provided in the above embodiments; or includes a semiconductor structure prepared by the preparation method provided in the above embodiments.

[0200] In some embodiments, electronic devices include, but are not limited to, storage devices, smartphones, computers, tablets, artificial intelligence devices, wearable devices, or power banks, etc. Storage devices include, but are not limited to, memory in a computer, etc., and are not specifically limited herein.

[0201] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0202] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0203] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A multilayer memory array, wherein multiple memory arrays are stacked along a direction perpendicular to the substrate; Each layer of the memory array includes multiple memory cells, which are arranged in an array along the row and column directions; each memory cell includes a transistor; multiple word lines are stacked at intervals along a direction perpendicular to the substrate and extend along the column direction. Multiple bit lines are arranged in an array along the row direction and the column direction, and all extend in a direction perpendicular to the substrate; the first electrode of each transistor corresponding to a row of memory cells arranged in a direction perpendicular to the substrate is connected to the same bit line. The channels of the transistors in the memory cells located on the same layer and in the same column are all connected to the same word line; In the word lines, the width of the portion of the word lines corresponding to the channel of the transistor is greater than the width of the remaining portion of the word lines; in the channel of the transistor, the width of the portion of the channel corresponding to the word lines is greater than the width of the remaining portion of the channel; the row direction and the column direction are both parallel to the substrate and intersect each other.

2. The semiconductor structure according to claim 1, characterized in that, The word line includes a first word line portion and a second word line portion that are connected to each other; in the same word line, the first word line portions are spaced apart along the column direction, and the second word line portions are connected between adjacent first word line portions; the first word line portions are opposite to the channel of the transistor; the second word line portions are offset from the channel of the transistor; the width of the first word line portion is greater than the width of the second word line portion.

3. The semiconductor structure according to claim 2, characterized in that, Both sides of the second character line portion along the width direction of the character line are curved edges, and the curved edges of the second character line portion are concave towards the center side of the second character line portion along the width direction.

4. The semiconductor structure according to claim 1, characterized in that, The word line includes two sub-word lines; the two sub-word lines are spaced apart along a direction perpendicular to the substrate and are located on opposite sides of the transistor connected to the word line.

5. The semiconductor structure according to claim 2, characterized in that, The channel of the transistor extends along the row direction and includes a first semiconductor portion and two second semiconductor portions; in the same transistor, the two second semiconductor portions are connected to both sides of the first semiconductor portion along the row direction; the first semiconductor portion is opposite to the first word line portion to form the channel of the transistor; the width of the first semiconductor portion is greater than the width of the second semiconductor portion.

6. The semiconductor structure according to claim 5, characterized in that, Along the direction from the first semiconductor portion to the second semiconductor portion, the channel width of the transistor gradually decreases; the first semiconductor portion is close to both sides of the two second semiconductor portions, and both sides of the first semiconductor portion are arc-shaped edges along the channel width direction of the transistor, and the arc-shaped edges of the first semiconductor portion are recessed toward the center side of the channel of the transistor along the width direction.

7. The semiconductor structure according to any one of claims 1-6, characterized in that, Each of the memory cells includes a capacitor; the second terminal of the transistor in each of the memory cells is connected to the capacitor.

8. The semiconductor structure according to claim 7, characterized in that, The capacitor includes a plurality of first capacitor electrodes and second capacitor electrodes, the second capacitor electrodes including a first sub-electrode; the semiconductor structure also includes a capacitor hole penetrating through multiple layers of the memory cells, the plurality of first capacitor electrodes being opposite to a plurality of memory cells disposed on different layers and in a direction perpendicular to the substrate; the plurality of first capacitor electrodes are disposed on the sidewalls of the capacitor hole and are spaced apart in a direction perpendicular to the substrate; the first sub-electrode fills the capacitor hole, and the plurality of first capacitor electrodes surround the first sub-electrode through a first dielectric layer.

9. The semiconductor structure according to claim 8, characterized in that, The first capacitor electrode includes a first portion extending in a direction perpendicular to the substrate and a second portion extending from both ends of the first portion toward the first sub-electrode; the first portions of the plurality of first capacitor electrodes are connected one-to-one with the second electrodes of the transistors of the plurality of memory cells.

10. The semiconductor structure according to claim 9, characterized in that, The second capacitor electrode further includes a second sub-electrode, which surrounds the first capacitor electrode via a second dielectric layer portion.

11. The semiconductor structure according to claim 7, characterized in that, Each of the capacitors has a projection on the surface of the substrate, and the extension length of the projection along the row direction is greater than the extension length of the projection along the column direction.

12. A method for fabricating a semiconductor structure, characterized in that, include: A stacked structure is formed on a substrate, and the stacked structure includes a plurality of alternating semiconductor structure layers and sacrificial layers along a direction perpendicular to the substrate; Along a direction perpendicular to the substrate, a plurality of first deep holes, a plurality of second deep holes, a plurality of third deep holes, a plurality of fourth deep holes, and a plurality of first trenches are formed through the stacked structure; A plurality of first deep vias, a plurality of second deep vias, a plurality of third deep vias, and a plurality of fourth deep vias are distributed at intervals along the column direction, and a first trench extends along the column direction; a plurality of word lines are formed through the fourth deep vias and the first trench, and the plurality of word lines are stacked at intervals along a direction perpendicular to the substrate and all extend along the column direction; a plurality of bit lines are formed through the second deep vias and the fourth deep vias, and the plurality of bit lines are arrayed along the row direction and the column direction and all extend along a direction perpendicular to the substrate; the semiconductor structure layer is laterally etched based on the second deep vias and the third deep vias, so that the second deep vias and the third deep vias are connected, so as to cut the semiconductor structure layer into channels of a plurality of transistors extending along the row direction and spaced apart along the column direction; The width of the word line corresponding to the channel of the transistor is greater than the width of the remaining portion of the word line; The width of the channel in the transistor portion corresponding to the word line is greater than the width of the channel in the remaining portion of the transistor; wherein the row direction and the column direction are both parallel to the substrate and intersect.

13. The preparation method according to claim 12, characterized in that, The formation of multiple word lines through the fourth deep hole and the first trench specifically includes: laterally etching the sacrificial layer along the sidewall of the fourth deep hole to form a first lateral trench between two adjacent semiconductor structure layers; thinning the semiconductor structure layer in the direction perpendicular to the substrate based on the first lateral trench, and oxidizing the thinned semiconductor structure layer to form a gate insulating layer; forming an initial word line covering the inner wall of the first lateral trench, the initial word line having an initial word line trench; forming an isolation layer in the initial word line trench; laterally etching both ends of the initial word line along the row direction based on the fourth deep hole and the first trench to form multiple first sub-word lines and second sub-word lines spaced apart along the direction perpendicular to the substrate, the multiple first sub-word lines and multiple second sub-word lines being alternately spaced apart along the direction perpendicular to the substrate, and together forming multiple word lines spaced apart along the direction perpendicular to the substrate, and the first sub-word lines and second sub-word lines located on adjacent sides of the channel of each transistor together forming a word line extending along the column direction.

14. The preparation method according to claim 12, characterized in that, Laterally etching the semiconductor structure layer based on the second and third deep holes, such that the second and third deep holes are connected, to cut the semiconductor structure layer into channels for a plurality of transistors extending along the row direction and spaced apart along the column direction, specifically includes: etching the stacked structure along the first and fourth deep holes to form an initial semiconductor layer in the semiconductor structure layer; forming transistor contacts at the ends of the initial semiconductor layer based on the fourth deep hole; laterally etching the initial semiconductor layer along the second and third deep holes to form a first semiconductor portion and a second semiconductor portion; the first semiconductor portion is offset from the second and third deep holes along the column direction, and the second semiconductor portion corresponds to the second and third deep holes respectively; the first semiconductor portion forms the channel of the transistor.

15. The preparation method according to claim 14, characterized in that, The semiconductor structure layer includes silicon. Based on the fourth deep hole, a transistor contact is formed at the end of the initial semiconductor layer. Specifically, this includes: forming a metal layer on the exposed end face of the initial semiconductor layer based on the fourth deep hole; forming a metal silicide using a high-temperature annealing process; and removing the excess metal layer using a wet etching process. The metal silicide forms the contact of the transistor.

16. The preparation method according to claim 13, characterized in that, The formation of multiple bit lines through the second deep hole and the fourth deep hole specifically includes: forming an initial bit line in the fourth deep hole that covers the inner wall of the fourth deep hole; forming a filling layer that covers the initial bit line and fills the fourth deep hole; and etching away a portion of the initial bit line based on the second deep hole to form multiple bit lines.

17. The preparation method according to claim 13, characterized in that, After forming the word line and before forming the transistor, the method further includes: laterally etching the semiconductor structure layer based on the sidewall of the first deep hole to form a plurality of capacitor electrode trenches spaced apart along a direction perpendicular to the substrate; forming a plurality of first capacitor electrodes in the capacitor electrode trenches, the plurality of first capacitor electrodes being located on the sidewalls of the plurality of capacitor electrode trenches; laterally etching the sacrificial layer based on the sidewall of the first deep hole to form a plurality of second lateral trenches spaced apart along a direction perpendicular to the substrate; forming a first dielectric layer covering the inner wall of the first deep hole, the first capacitor electrodes, and the inner wall of the second lateral trenches; forming a first sub-electrode covering the first dielectric layer and filling the first deep hole, the capacitor electrode trenches, and the second lateral trenches; laterally removing the semiconductor structure layer based on the first trenches to form a third lateral trench; sequentially forming a second dielectric layer and a second sub-electrode in the third lateral trench; the first sub-electrode and the second sub-electrode forming a second capacitor electrode; and the first capacitor electrode, the second capacitor electrode, the first dielectric layer, and the second dielectric layer forming a capacitor.

18. An electronic device, characterized in that, It includes the semiconductor structure as described in any one of claims 1-11, or the semiconductor structure formed by the method of preparing the semiconductor structure according to any one of claims 12-17.

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