Germanium-silicon heterojunction npn type bipolar transistor and preparation method thereof
By using a p-type in-situ doped germanium-silicon-carbon selective epitaxial growth method, the problem of high base region parasitic resistance in germanium-silicon heterojunction npn bipolar transistors was solved, achieving a comprehensive improvement in high-frequency performance and low noise.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SEMICON TECH INNOVATION CENT(BEIJING) CORP
- Filing Date
- 2025-12-17
- Publication Date
- 2026-05-01
AI Technical Summary
Existing germanium-silicon heterojunction npn bipolar transistors have a contradiction in the doping and diffusion of the germanium-silicon-carbon interconnect base region, resulting in high base region parasitic resistance, which affects the high-frequency performance and radio frequency noise performance of the device.
A p-type in-situ doped germanium-silicon-carbon selective epitaxial growth method is adopted. By simultaneously growing the germanium-silicon-carbon epitaxial inner base region and the silicon connecting base region, the diffusion of boron impurities during the growth and thermal process is avoided, ensuring the uniformity of boron impurity concentration in the connecting base region and reducing parasitic resistance.
This achieves the goal of reducing base region parasitic resistance, increasing maximum oscillation frequency, and reducing RF noise while maintaining a high cutoff frequency, thereby improving the RF power and noise performance of the device.
Smart Images
Figure CN121968607A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor device and integrated circuit process design and manufacturing, specifically to a germanium-silicon heterojunction npn bipolar transistor and its fabrication method. Background Technology
[0002] A key process step of a germanium-silicon heterojunction npn bipolar transistor is to simultaneously grow an intrinsic inner base region located below the region surrounded by the inner sidewall of silicon nitride and a germanium-silicon-carbon connection base region located below the polysilicon layer cantilever and the inner sidewall of silicon nitride in the outer base region by using a p-type in-situ doped germanium-silicon-carbon selective epitaxial growth method.
[0003] The epitaxial base region, which is the core intrinsic region of the device obtained by selective epitaxial growth, actually includes a silicon buffer layer, a germanium-silicon-carbon layer and a silicon capping layer in the order of growth. The buffer layer and the capping layer are undoped. Even the germanium-silicon-carbon layer includes several epitaxial layers, of which only the middle layer is boron doped. Since the germanium-silicon-carbon (GSiC) interconnect base region is grown simultaneously with the inner base region, its doping situation during growth is largely similar to that of the inner base region. Specifically, only the innermost layer is boron-doped, while the other layers are undoped. Although some boron impurities can diffuse from the heavily doped outer polysilicon layer during growth and subsequent thermal processes, to ensure an ultra-thin inner base region, it is crucial to minimize boron impurity diffusion during growth and subsequent thermal processes. In particular, carbon doping is necessary to effectively suppress the diffusion of simultaneously in-situ doped boron impurities during growth and subsequent thermal processes. Furthermore, the diffusion coefficient of boron in germanium is smaller than that in silicon. Therefore, the final inner base region can be thin enough to achieve a sufficiently short carrier base region transition time, thereby ensuring a sufficiently high cutoff frequency f for the device. T In other words, there are conflicting requirements for boron doping and diffusion in the germanium-silicon-carbon intrinsic base region and the germanium-silicon-carbon connecting base region. Therefore, while ensuring the requirements of the intrinsic germanium-silicon-carbon intrinsic base region, the germanium-silicon-carbon connecting base region grown at the same time cannot be fully optimized in terms of boron doping and diffusion on its own. This inevitably results in a considerable portion of the final germanium-silicon-carbon connecting base region having relatively low doping concentrations, i.e., high resistance. The high resistance of the germanium-silicon-carbon connecting base region will inevitably prevent the parasitic base region resistance of the entire device from being sufficiently reduced.
[0004] As a representative of high-performance silicon-based radio frequency semiconductor devices, the germanium-silicon heterojunction bipolar transistor, even with structural and process optimizations including the intrinsic region of the inner base region, achieves a very high cutoff frequency fo. T However, if the base region parasitic resistance, one of the most important parasitic parameters, cannot be sufficiently reduced, the final device performance will be significantly compromised, not only in terms of its relationship with the cutoff frequency f.T Another performance metric that is equally or even more important is the highest oscillation frequency f. max The base region parasitic resistance is not small enough, so it cannot be fully improved, thus failing to ensure that the device obtains a sufficiently high RF power gain under high frequency operating conditions. Moreover, a high base region parasitic resistance will directly cause the deterioration of RF noise performance.
[0005] This section is intended to provide background or context for the embodiments of this application set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section. Summary of the Invention
[0006] In order to solve at least one of the above-mentioned problems in the prior art, embodiments of this application provide a germanium-silicon heterojunction npn bipolar transistor and a method for fabricating the same.
[0007] This application provides a germanium-silicon heterojunction npn bipolar transistor, including:
[0008] p-type lightly doped silicon substrate;
[0009] An n-type heavily doped silicon buried collector region is formed on the substrate;
[0010] An n-type lightly doped silicon epitaxial collector region is formed on the buried layer collector region;
[0011] The SiC region is formed in the silicon epitaxial collector region by SiC ion implantation process;
[0012] A field region silicon oxide layer is formed on the buried layer current collector region and located on the side of the silicon epitaxial current collector region;
[0013] p-type in-situ boron-doped germanium-silicon-carbon epitaxial base region is formed on the SiC region;
[0014] p-type in-situ boron-doped silicon interconnect base regions are formed on the SiC region and the silicon epitaxial collector region;
[0015] A base-collector region isolation silicon oxide layer is formed on the silicon epitaxial collector region and the field region silicon oxide layer;
[0016] L-shaped silicon oxide inner walls are formed on the germanium-silicon-carbon epitaxial inner base region and the silicon connection base region, and the bottom of the L-shaped silicon oxide inner walls encloses a window region.
[0017] A single-crystal emitter region is formed on the inner base region of the germanium-silicon-carbon epitaxial layer and located below the window region;
[0018] p-type heavily doped polycrystalline silicon outer base region is formed on the base region-collector region isolation silicon oxide layer and the silicon interconnect base region and is located on the side of the L-shaped silicon oxide inner wall;
[0019] An emitter-base isolation silicon oxide layer is formed on the outer base region of the polycrystalline silicon and located on the side of the inner sidewall of the L-shaped silicon oxide.
[0020] The n-type heavily doped polycrystalline silicon emitter region is formed inside and above the inner wall of the L-shaped silicon oxide and extends outward to the emitter-base isolation silicon oxide layer.
[0021] In some embodiments, the germanium-silicon-carbon epitaxial inner base region and the silicon-connecting base region are simultaneously grown using a p-type in-situ boron-doped germanium-silicon-carbon selective epitaxial growth method.
[0022] In some embodiments, it also includes:
[0023] A silicon oxide outer wall is formed on the outer side of the base-collector region isolation silicon oxide layer, the polysilicon outer base region, the emitter region-base region isolation silicon oxide layer, and the polysilicon emitter region.
[0024] In some embodiments, the upper surfaces of the field region silicon oxide layer and the silicon epitaxial collector region are flush;
[0025] The upper surfaces of the silicon interconnect base region, the germanium-silicon-carbon epitaxial inner base region, and the base region-collector region isolation silicon oxide layer are flush.
[0026] In some embodiments, it also includes:
[0027] The emitter is connected to the polycrystalline silicon emitter region;
[0028] The base is connected to the outer base region of the polycrystalline silicon.
[0029] The collector electrode is electrically connected to the buried layer current collection region;
[0030] The substrate electrode is electrically connected to the substrate.
[0031] In some embodiments, the emitter includes an emitter silicide electrode formed on the polysilicon emitter region;
[0032] The base includes a base silicide electrode formed on the exposed upper surface of the polycrystalline silicon outer base region.
[0033] In some embodiments, heavy doping refers to impurity concentrations of 10. 19 cm -3 The above refers to light doping, which means an impurity concentration of 10. 16 cm -3 the following.
[0034] This application also provides a method for fabricating a germanium-silicon heterojunction npn bipolar transistor, including:
[0035] An npn bipolar transistor basic structure is provided, the npn bipolar transistor basic structure includes a p-type lightly doped silicon substrate, an n-type heavily doped silicon buried collector region formed on the substrate, and an n-type lightly doped silicon epitaxial collector region and a field region silicon oxide layer formed on the buried collector region, wherein the field region silicon oxide layer is located on the side of the silicon epitaxial collector region;
[0036] A base-collector region isolation silicon oxide layer, a p-type heavily doped outer base region polycrystalline silicon layer, an emitter-base region isolation silicon oxide layer, and a first silicon nitride layer are deposited sequentially.
[0037] Photolithography is performed on the collector region window. The first silicon nitride layer, the emitter-base region isolation silicon oxide layer and the outer base region polysilicon layer are sequentially etched using photoresist as a mask until the base region-collector region isolation silicon oxide layer is exposed, forming the collector region window.
[0038] SiC ion implantation is performed through the collector region window to form a SiC region in the area of the silicon epitaxial collector region opposite the collector region window, and then the photoresist is removed.
[0039] First, a second silicon nitride layer is deposited, and then the silicon nitride is etched anisotropically to form an inner wall of silicon nitride inside the window of the collector region.
[0040] Using the remaining silicon nitride layer and the inner wall of the silicon nitride as a mask, the exposed base-collector region isolation silicon oxide layer is wet-etched away, and the base-collector region isolation silicon oxide layer is further etched laterally, so that a part of the silicon epitaxial collector region is exposed.
[0041] By using a p-type in-situ boron-doped germanium-silicon-carbon selective epitaxial growth method, a p-type in-situ boron-doped germanium-silicon-carbon epitaxial inner base region located below the region surrounded by the inner sidewall of the silicon nitride, a cantilever of the polycrystalline silicon layer in the outer base region, and a p-type in-situ boron-doped silicon connection base region located below the inner sidewall of the silicon nitride are simultaneously grown.
[0042] The remaining silicon nitride layer and the inner wall of the silicon nitride are removed by wet etching;
[0043] Deposit silicon oxide isolation layer;
[0044] First, an n-type heavily doped first polysilicon layer is deposited, and then the first polysilicon layer is anisotropically dry etched to form the inner sidewall of the emitter region polysilicon.
[0045] The exposed silicon oxide isolation layer is removed by wet etching using the polycrystalline silicon inner wall as a mask to form an L-shaped silicon oxide inner wall, wherein the bottom of the L-shaped silicon oxide inner wall forms a window area.
[0046] A second polysilicon layer heavily doped with n-type is deposited, and the second polysilicon layer is combined with the inner sidewall of the emitter polysilicon layer to form an n-type heavily doped emitter polysilicon layer.
[0047] Photolithography is performed on the polycrystalline silicon emitter region, and the n-type heavily doped emitter region polycrystalline silicon layer and the emitter region-base region isolation silicon oxide layer are sequentially etched using photoresist as a mask to form the n-type heavily doped polycrystalline silicon emitter region. Then the photoresist is removed.
[0048] Photolithography is performed on the polysilicon outer base region, and the polysilicon layer of the outer base region and the base-collector isolation silicon oxide layer are etched using photoresist as a mask to form a p-type heavily doped polysilicon outer base region. Then the photoresist is removed.
[0049] Rapid thermal annealing is performed to allow impurities in the polycrystalline silicon emitter region to diffuse into the germanium-silicon-carbon epitaxial inner base region, forming an n-type heavily doped single-crystal emitter region.
[0050] In some embodiments, the selective epitaxial growth method of germanium-silicon-carbon with p-type in-situ boron doped silica simultaneously grows a p-type in-situ boron doped silica epitaxial inner base region located below the region surrounded by the inner sidewalls of the silicon nitride, and a cantilever of the polycrystalline silicon layer in the outer base region and a p-type in-situ boron doped silicon connection base region located below the inner sidewalls of the silicon nitride, including:
[0051] By selective epitaxy and deposition processes, on the one hand, silicon and boron precursors can be diffusely distributed throughout the entire cavity formed by wet etching of the base-collector region isolation silicon oxide layer, and can penetrate deep into the cantilever of the outer base region polycrystalline silicon layer and the cavity region below the inner sidewall of the silicon nitride before being adsorbed at the reaction interface; on the other hand, germanium and carbon precursors can only reach the reaction interface in the region directly below the window enclosed by the inner sidewall of the silicon nitride, and are thus adsorbed by the reaction interface and react to participate in the epitaxial growth of the inner base region; finally, p-type in-situ boron-doped germanium-silicon-carbon epitaxial inner base region and p-type in-situ boron-doped silicon connecting base region are grown or deposited simultaneously.
[0052] In some embodiments, after forming the p-type heavily doped polysilicon substrate region and then removing the photoresist, and before performing rapid thermal annealing, the method further includes:
[0053] Deposit a silicon oxide layer on the outer wall;
[0054] After the rapid thermal annealing, the method further includes:
[0055] The outer wall silicon oxide layer is etched using anisotropic dry etching to form a silicon oxide outer wall.
[0056] In some embodiments, the method further includes:
[0057] An emitter, a base, a collector, and a substrate are formed, such that the emitter is connected to the polysilicon emitter region, the base is connected to the polysilicon outer base region, the collector is electrically connected to the buried layer collector region, and the substrate is electrically connected to the substrate.
[0058] In some embodiments, forming the emitter and base includes:
[0059] Emitter silicide electrodes and base silicide electrodes are formed by silicide reaction between refractory metal and the exposed polycrystalline silicon emitter region and polycrystalline silicon base region, which are self-aligned and isolated by the outer wall of the silicon oxide.
[0060] The germanium-silicon heterojunction npn bipolar transistor and its fabrication method provided in this application embodiment, through a p-type in-situ doped germanium-silicon-carbon selective epitaxial growth method, can simultaneously grow a p-type in-situ boron-doped germanium-silicon-carbon epitaxial inner base region located below the region surrounded by the silicon nitride inner sidewall, and a p-type in-situ boron-doped silicon connection base region located on the cantilever of the polycrystalline silicon layer in the outer base region and below the silicon nitride inner sidewall. This avoids the problems caused by doping germanium and carbon into the connection base region, which would affect boron as an in-situ dopant during growth and subsequent thermal processes. Diffusion suppression allows boron impurities to diffuse sufficiently during growth and subsequent thermal processes. This includes diffusion from the pre-formed p-type heavily doped polysilicon outer base region into the connection base region and diffusion of in-situ doped boron within the connection base region. This ensures the highest possible and most uniform boron impurity concentration within the final connection base region, resulting in a low-resistance current path for the base current flowing from the outer base region to the inner base region during device operation, free from high-resistance "dead zones." In other words, it minimizes the parasitic resistance of the connection base region. The technical solution proposed in this application simultaneously addresses the different, even contradictory, needs of the inner and connection base regions in dual-polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistors, achieving a sufficiently high cutoff frequency f. T The germanium-silicon-carbon epitaxial inner base region and the silicon interconnect base region ensure minimal parasitic resistance. Reducing the parasitic resistance of the interconnect base region can reduce the parasitic base resistance of the dual polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistor, which can increase the maximum oscillation frequency f under a given cutoff frequency. max Moreover, it can effectively reduce the radio frequency noise figure, ultimately achieving the goal of improving the overall device performance of the dual polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistor as a radio frequency device, such as radio frequency power and noise. Attached Figure Description
[0061] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:
[0062] Figure 1 This is a schematic flowchart illustrating a method for fabricating a germanium-silicon heterojunction npn bipolar transistor according to an embodiment of this application.
[0063] Figures 2 to 16 This is a schematic diagram of the semiconductor structure obtained by each key process step in the fabrication method of a germanium-silicon heterojunction npn bipolar transistor provided in the embodiments of this application.
[0064] [Attached image labels]
[0065] A. Current collection area window;
[0066] 1. Substrate;
[0067] 2. Buried layer current collection area;
[0068] 3. Silicon epitaxial collector region;
[0069] 4. Silica layer in the field area;
[0070] 5. Base-collector region isolation silicon oxide layer;
[0071] 5a. Cavity;
[0072] 6. Polycrystalline silicon layer in the outer base region;
[0073] 6a. Polycrystalline silicon outer base region;
[0074] 7. Emitter-base isolation silicon oxide layer;
[0075] 8. First silicon nitride layer;
[0076] 9. Photoresist;
[0077] 9a. Window area;
[0078] 10. SIC Zone;
[0079] 11. Germanium-silicon-carbon epitaxial inner base region;
[0080] 12. Silicon interconnect base region;
[0081] 13. Silicon oxide insulating layer;
[0082] 13a. L-shaped silica inner wall;
[0083] 14. Emitter region polycrystalline silicon layer;
[0084] 14a. Inner wall of polysilicon emitter region;
[0085] 14b. Polycrystalline silicon emitter region;
[0086] 15. Single-crystal emitter region;
[0087] 16. Emitter silicide electrode;
[0088] 17. Base silicide electrode;
[0089] 18. Silicon oxide layer on the outer wall;
[0090] 18a. Silica outer wall;
[0091] 19. Silicon nitride inner wall;
[0092] 20. The remaining silicon nitride layer. Detailed Implementation
[0093] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0094] Specific embodiments of this application are disclosed in detail with reference to the following description and accompanying drawings, indicating how the principles of this application can be adopted. It should be understood that the embodiments of this application are not limited in scope. Within the spirit and scope of the appended claims, embodiments of this application include many changes, modifications, and equivalents.
[0095] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.
[0096] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.
[0097] In order to solve at least one of the above-mentioned problems in the prior art, embodiments of this application provide a germanium-silicon heterojunction npn bipolar transistor and a method for fabricating the same.
[0098] Figure 1This is a schematic flowchart illustrating a method for fabricating a germanium-silicon heterojunction npn bipolar transistor according to an embodiment of this application. Figure 1 As shown in the embodiment of this application, a method for fabricating a germanium-silicon heterojunction npn bipolar transistor includes:
[0099] S1. Provide an npn bipolar transistor basic structure, the npn bipolar transistor basic structure including a p-type lightly doped silicon substrate 1, an n-type heavily doped silicon buried collector region 2 formed on the substrate 1, and an n-type lightly doped silicon epitaxial collector region 3 and a field region silicon oxide layer 4 formed on the buried collector region 2, wherein the field region silicon oxide layer 4 is located on the side of the silicon epitaxial collector region 3;
[0100] In step S1, the basic structure of the npn bipolar transistor is as follows: Figure 2 As shown.
[0101] S2, sequentially deposit the base region-collector region isolation silicon oxide layer 5, the p-type heavily doped outer base region polycrystalline silicon layer 6, the emitter region-base region isolation silicon oxide layer 7, and the first silicon nitride layer 8;
[0102] In step S2, see Figure 3 On the basic structure of the npn bipolar transistor, a base-collector isolation silicon oxide layer 5, a p-type heavily doped outer base region polycrystalline silicon layer 6, an emitter-base isolation silicon oxide layer 7, and a first silicon nitride layer 8 are deposited sequentially. Specifically, the p-type heavily doped outer base region polycrystalline silicon layer 6 can be a p-type in-situ boron heavily doped outer base region polycrystalline silicon layer 6.
[0103] S3. Perform photolithography on the collector region window. Using photoresist 9 as a mask, sequentially etch the first silicon nitride layer 8, the emitter-base region isolation silicon oxide layer 7, and the outer base region polysilicon layer 6 until the base region-collector region isolation silicon oxide layer 5 is exposed, forming the collector region window A.
[0104] In step S3, see Figure 4 Photolithography is performed on the collector region window to form photoresist 9 on the first silicon nitride layer 8, and a window region 9a is formed on the photoresist 9; see also Figure 5 Using photoresist 9 as a mask, the first silicon nitride layer 8, the emitter-base region isolation silicon oxide layer 7, and the outer base region polysilicon layer 6 are etched sequentially to expose the base region-collector region isolation silicon oxide layer 5, forming the collector region window A.
[0105] S4. Perform SIC ion implantation through the collector region window A to form an SIC region 10 in the area of the silicon epitaxial collector region 3 opposite to the collector region window A, and then remove the photoresist 9.
[0106] In step S4, see Figure 5Before removing the photoresist 9 after etching, selective implantation of the collector region (SIC) is performed on the exposed base-collector region isolation silicon oxide layer 5, thereby forming a selectively implanted collector region, i.e., the SIC region 10, in the area of the lightly doped silicon epitaxial collector region 3 opposite the collector region window A. Then, the photoresist 9 is removed.
[0107] S5. First, deposit the second silicon nitride layer, then anisotropically dry etch the silicon nitride to form a silicon nitride inner wall 19 inside the collector region window A.
[0108] In step S5, see Figure 6 First, a second silicon nitride layer is deposited, and then silicon nitride is anisotropically etched to form an inner sidewall 19 of silicon nitride at the edge of the collector window A.
[0109] S6. Using the remaining silicon nitride layer 20 and the inner wall 19 of the silicon nitride as a mask, wet etching is used to remove the exposed base-collector region isolation silicon oxide layer 5, and the base-collector region isolation silicon oxide layer 5 is further etched laterally, so that a part of the silicon epitaxial collector region 3 is exposed.
[0110] In step S6, see Figure 7 Using the remaining silicon nitride layer 20 and the silicon nitride inner sidewall 19 as a mask, the exposed base-collector region isolation silicon oxide layer 5 is wet-etched away, and the base-collector region isolation silicon oxide layer 5 is further etched laterally, so that a part of the silicon epitaxial collector region 3 is exposed.
[0111] S7. Using a p-type in-situ doped germanium-silicon-carbon selective epitaxial growth method, a p-type in-situ boron-doped germanium-silicon-carbon epitaxial inner base region 11 located below the region surrounded by the silicon nitride inner sidewall 19, and a p-type in-situ boron-doped silicon connection base region 12 located below the cantilever of the polycrystalline silicon layer 6 in the outer base region and the silicon nitride inner sidewall 19 are simultaneously grown.
[0112] In step S7, see Figure 8 By using a p-type in-situ boron-doped germanium-silicon-carbon selective epitaxial growth method, a germanium-silicon-carbon epitaxial inner base region 11 (intrinsic inner base region) and an outer base region polycrystalline silicon layer 6 cantilever and a silicon connection base region 12 under the silicon nitride inner sidewall 19 are simultaneously grown.
[0113] S8. Wet etching removes the remaining silicon nitride layer 20 and the silicon nitride inner wall 19;
[0114] In step S8, see Figures 8 to 9 The remaining silicon nitride layer 20 and the silicon nitride inner wall 19 are removed by wet etching.
[0115] S9, Deposited silicon oxide isolation layer 13;
[0116] In step S9, see Figure 10 A thin silicon oxide isolation layer 13 is deposited.
[0117] S10. First, deposit an n-type heavily doped first polysilicon layer, and then anisotropically dry etch the first polysilicon layer to form the emitter region polysilicon inner sidewall 14a.
[0118] In step S10, see Figure 10 First, an n-type in-situ heavily doped inner sidewall emitter polysilicon layer (first polysilicon layer) is deposited, and then anisotropic dry etching is used to form the emitter polysilicon inner sidewall 14a.
[0119] S11. Using the inner sidewall 14a of the emitter region as a mask, wet etching is used to remove the exposed silicon oxide isolation layer 13 to form an L-shaped silicon oxide inner sidewall 13a, wherein the bottom of the L-shaped silicon oxide inner sidewall 13a forms a window area.
[0120] In step S11, see Figures 10 to 11 The exposed silicon oxide isolation layer 13 is removed by wet etching using the inner sidewall 14a of the emitter region as a mask, forming an L-shaped silicon oxide inner sidewall 13a (also called an L-shaped silicon oxide isolation layer). The bottom of the L-shaped silicon oxide inner sidewall 13a forms a window area.
[0121] S12. Deposit an n-type heavily doped second polysilicon layer. The second polysilicon layer and the inner sidewall 14a of the emitter region polysilicon layer are combined to form an n-type heavily doped emitter region polysilicon layer 14.
[0122] In step S12, see Figure 11 An in-situ heavily doped n-type polysilicon layer is deposited, and the second polysilicon layer is combined with the inner sidewall 14a of the emitter region polysilicon to form an n-type heavily doped emitter region polysilicon layer 14.
[0123] S13. Perform polysilicon emitter region photolithography, and sequentially etch the n-type heavily doped emitter region polysilicon layer 14 and the emitter region-base region isolation silicon oxide layer 7 using photoresist as a mask to form the n-type heavily doped polysilicon emitter region 14b, and then remove the photoresist.
[0124] In step S13, see Figure 12 Photolithography of the polysilicon emitter region is performed, and the exposed n-type in-situ heavily doped emitter region polysilicon layer 14 and the underlying emitter-base isolation silicon oxide layer 7 are sequentially etched away using photoresist as a mask to form the n-type heavily doped polysilicon emitter region 14b. Then the photoresist is removed.
[0125] S14. Perform photolithography on the polysilicon outer base region, and use photoresist as a mask to etch the polysilicon layer 6 of the outer base region and the base region-collector region isolation silicon oxide layer 5 to form a p-type heavily doped polysilicon outer base region 6a, and then remove the photoresist.
[0126] In step S14, see Figure 13 Photolithography is performed on the polysilicon outer substrate, and the exposed polysilicon outer substrate layer 6 and the underlying base-collector isolation silicon oxide layer 5 are sequentially etched away using photoresist as a mask to form a p-type heavily doped polysilicon outer substrate region 6a. Then the photoresist is removed.
[0127] S15. Rapid thermal annealing is performed to allow impurities in the polycrystalline silicon emitter region 14b to diffuse into the germanium-silicon-carbon epitaxial inner base region 11 to form an n-type heavily doped single crystal emitter region 15.
[0128] In step S15, see Figure 14 Rapid thermal annealing (RTA) is performed, which on the one hand allows impurities in the polycrystalline silicon emitter region 14b to diffuse into the germanium-silicon-carbon epitaxial inner base region 11 to form an n-type heavily doped single crystal emitter region 15, and on the other hand achieves impurity activation.
[0129] The method for fabricating a germanium-silicon heterojunction npn bipolar transistor provided in this application embodiment utilizes a p-type in-situ doped germanium-silicon-carbon selective epitaxial growth method. This method simultaneously grows a p-type in-situ boron-doped germanium-silicon-carbon epitaxial inner base region 11 located below the region surrounded by the silicon nitride inner sidewall 19, and a p-type in-situ boron-doped silicon connection base region 12 located on the cantilever of the polysilicon layer 6 in the outer base region and below the silicon nitride inner sidewall 19. This avoids the problems caused by doping germanium and carbon into the connection base region, which would affect the boron as an in-situ dopant during growth and subsequent thermal processes. Diffusion suppression during the process allows boron impurities to diffuse sufficiently during growth and subsequent thermal processes. This includes diffusion from the pre-formed p-type heavily doped outer polycrystalline silicon layer 6 into the connection base region and diffusion of in-situ doped boron within the connection base region. This ensures the highest possible and most uniform boron impurity concentration within the final connection base region, resulting in a low-resistance current path for the base current flowing from the outer base region to the inner base region during device operation, free from high-resistance "dead zones." In other words, it minimizes the parasitic resistance of the connection base region. The technical solution proposed in this application simultaneously addresses the different, even contradictory, needs of the inner and connection base regions in dual-polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistors, achieving a sufficiently high cutoff frequency f. T The germanium-silicon-carbon epitaxial inner base region and the silicon interconnect base region ensure minimal parasitic resistance. Reducing the parasitic resistance of the interconnect base region can reduce the parasitic base region resistance of the dual polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistor, which can not only reduce the parasitic base region resistance at a given cutoff frequency f T Under the condition of increasing the highest oscillation frequency fmax Moreover, it can effectively reduce the radio frequency noise figure, ultimately achieving the goal of improving the overall device performance of the dual polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistor as a radio frequency device, such as radio frequency power and noise.
[0130] In some embodiments, step S7 specifically includes: through selective epitaxy and deposition processes, on the one hand, the silicon and boron precursors are diffusely distributed throughout the entire cavity 5a formed by wet etching of the base region-collector region isolation silicon oxide layer 5, and are able to penetrate into the cantilever of the outer base region polycrystalline silicon layer 6 and the cavity region below the silicon nitride inner sidewall 19 before being adsorbed at the reaction interface; on the other hand, the germanium and carbon precursors are simultaneously allowed to reach the reaction interface in the region directly below the window enclosed by the silicon nitride inner sidewall 19, thereby being adsorbed by the reaction interface and reacting to participate in the epitaxial growth of the inner base region; finally, p-type in-situ boron-doped germanium-silicon-carbon epitaxial inner base region 11 and p-type in-situ boron-doped silicon connection base region 12 are grown or deposited simultaneously.
[0131] Specifically, the inner base region needs to incorporate germanium to realize the structure and function of a germanium-silicon heterojunction bipolar transistor based on silicon-based bandgap engineering. Carbon doping is also required to effectively suppress the diffusion of boron impurities, which are simultaneously doped in situ, during growth and subsequent thermal processes. Furthermore, the diffusion coefficient of boron in germanium is smaller than that in silicon, thus ensuring that the final inner base region is thin enough to achieve a sufficiently short carrier base region transition time, thereby ensuring a sufficiently high cutoff frequency f. T .
[0132] The interconnect base region, as a transitional connection between the pre-formed outer base region and the inner base region, does not functionally require germanium to achieve the bandgap engineering of the germanium-silicon heterojunction. Instead, it is necessary to avoid introducing germanium, and especially carbon, to prevent the diffusion of boron, an in-situ doped impurity, during growth and subsequent thermal processes. Conversely, by obtaining a silicon interconnect base region that is undoped of germanium and carbon but only in-situ doped with boron, the boron impurities can diffuse sufficiently during growth and subsequent thermal processes. This includes diffusion from the pre-formed p-type heavily doped polysilicon layer 6 of the outer base region into the interconnect base region and diffusion of in-situ doped boron within the interconnect base region. This ensures that the final interconnect base region achieves the highest and most uniform boron impurity concentration possible. Consequently, the base current flowing from the outer base region to the inner base region during device operation can obtain a low-resistance current path without high-resistance "dead zones," meaning that the parasitic resistance of the interconnect base region can be minimized.
[0133] By employing appropriate selective epitaxy and deposition techniques, precursors of silicon, boron, germanium, and carbon, corresponding to, but not limited to, silane, diborane, germanane, and methylsilane, can exhibit different molecular dynamic behaviors during the reaction growth process. Specifically, silicon and boron precursors can have relatively small mean free paths, allowing them to be diffusely and uniformly distributed throughout the entire cavity 5a to be grown or deposited. Before reaching the reaction interface and being adsorbed, they can penetrate into the corner under the "eaves" formed by the cantilever of the polycrystalline silicon layer 6 and the inner sidewall of silicon nitride 19 in the outer base region. On the other hand, germanium and carbon precursors can simultaneously have relatively large mean free paths, ensuring that they can only reach the reaction interface directly below the window formed by the remaining silicon nitride layer 20 and the inner sidewall of silicon nitride 19, where they are adsorbed and participate in the epitaxial growth of the inner base region. Ultimately, p-type in-situ boron-doped germanium-silicon-carbon epitaxial inner base region 11 and p-type in-situ boron-doped silicon connecting base region 12 are simultaneously grown or deposited.
[0134] In some embodiments, after step S14 and before step S15, the method further includes:
[0135] S15-0, deposited outer wall silicon oxide layer 18.
[0136] In step S15-0, see Figure 14 , depositing a silicon oxide layer 18 on the outer wall.
[0137] In some embodiments, after depositing the outer wall silicon oxide layer 18 and performing rapid thermal annealing, the method further includes:
[0138] S16. The outer wall silicon oxide layer 18 is etched using anisotropic dry etching to form a silicon oxide outer wall 18a.
[0139] In step S16, see Figure 15 Anisotropic dry etching is used to etch the outer wall silicon oxide layer 18 to form the silicon oxide outer wall 18a.
[0140] In some embodiments, after step S16 described above, the method further includes:
[0141] S17. An emitter, a base, a collector, and a substrate are formed, such that the emitter is connected to the polysilicon emitter region 14b, the base is connected to the polysilicon outer base region 6a, the collector is electrically connected to the buried layer collector region 2, and the substrate is electrically connected to the substrate 1.
[0142] In some embodiments, the formation of the emitter and base includes: forming an emitter silicide electrode 16 and a base silicide electrode 17 by silicide reaction of a refractory metal with the exposed polycrystalline silicon emitter region 14b and the polycrystalline silicon base region 6a, which are self-aligned and isolated by the silicon oxide outer wall 18a.
[0143] For details, see Figure 16 By utilizing the silicide reaction between refractory metal and exposed monocrystalline and polycrystalline silicon, a low-resistance metal silicide layer is formed through self-alignment, thereby forming an emitter silicide electrode 16 and a base silicide electrode 17, respectively.
[0144] Finally, the germanium-silicon heterojunction npn bipolar transistor can also be fabricated using back-end metallization processes in this field. It should be noted that, considering that this application does not impose any restrictions on the collector and substrate lead-out methods, or the number and relative positions of the emitter, base, collector, and substrate electrodes of the germanium-silicon heterojunction npn bipolar transistor, the electrode lead-out methods of the collector and substrate regions and all electrode configurations are not fully illustrated in the specification and related process flow diagrams of this application. However, all of these can be implemented using common techniques in this field.
[0145] Based on the same inventive concept, this application also provides a germanium-silicon heterojunction npn bipolar transistor.
[0146] Figure 16 This is a schematic diagram of the structure of a germanium-silicon heterojunction npn bipolar transistor provided in an embodiment of this application. Figure 16 As shown in the embodiment of this application, a germanium-silicon heterojunction npn bipolar transistor 001 includes:
[0147] p-type lightly doped silicon substrate 1;
[0148] n-type heavily doped silicon buried layer collector region 2 is formed on the substrate 1;
[0149] n-type lightly doped silicon epitaxial collector region 3 is formed on the buried layer collector region 2;
[0150] The SIC region 10 is formed in the silicon epitaxial collector region 3 by the SIC ion implantation process;
[0151] A field region silicon oxide layer 4 is formed on the buried layer current collector region 2 and located on the side of the silicon epitaxial current collector region 3;
[0152] p-type in-situ boron-doped germanium silicon-carbon epitaxial base region 11 is formed on the SiC region 10;
[0153] p-type in-situ boron-doped silicon interconnect base region 12 is formed on the SiC region 10 and the silicon epitaxial collector region 3;
[0154] A base-collector isolation silicon oxide layer 5 is formed on the silicon epitaxial collector region 3 and the field region silicon oxide layer 4. The base-collector isolation silicon oxide layer 5 reduces positive charge through process means, and negative charge is introduced at the interface between the base-collector isolation silicon oxide layer 5 and the silicon epitaxial collector region 3 through process means.
[0155] L-shaped silicon oxide inner sidewalls 13a are formed on the germanium-silicon-carbon epitaxial inner base region 11 and the silicon connection base region 12. The bottom of the L-shaped silicon oxide inner sidewalls 13a forms a window region. The positive charge of the L-shaped silicon oxide inner sidewalls 13a is reduced by process means, and negative charge is introduced at the interface between the bottom of the L-shaped silicon oxide inner sidewalls 13a and the germanium-silicon-carbon epitaxial inner base region 11 and the silicon connection base region 12 by process means.
[0156] A single-crystal emitter region 15 is formed on the germanium-silicon-carbon epitaxial inner base region 11 and located below the window region;
[0157] p-type heavily doped polycrystalline silicon outer base region 6a is formed on the base region-collector region isolation silicon oxide layer 5 and the silicon connection base region 12 and is located on the side of the L-shaped silicon oxide inner sidewall 13a;
[0158] An emitter-base isolation silicon oxide layer 7 is formed on the outer base region 6a of the polysilicon and is located on the side of the inner sidewall 13a of the L-shaped silicon oxide.
[0159] An n-type heavily doped polycrystalline silicon emitter region 14b is formed inside and above the L-shaped silicon oxide inner sidewall 13a and extends outward to the emitter-base isolation silicon oxide layer 7.
[0160] The germanium-silicon heterojunction npn bipolar transistor provided in this application embodiment has a p-type in-situ boron-doped germanium-silicon-carbon epitaxial inner base region 11 located below the region surrounded by the silicon nitride inner sidewall 19, and a p-type in-situ boron-doped silicon connection base region 12 located below the cantilever of the polysilicon layer 6 of the outer base region and the silicon nitride inner sidewall 19. This avoids the diffusion suppression of boron as an in-situ dopant impurity during growth and subsequent thermal processes caused by the doping of germanium and carbon in the connection base region. It allows the boron impurity to diffuse sufficiently during growth and subsequent thermal processes, including diffusion from the pre-formed p-type heavily doped polysilicon layer of the outer base region into the connection base region and diffusion of in-situ doped boron inside the connection base region. This ensures that the final connection base region can obtain the highest and most uniform boron impurity concentration possible, so that the base current flowing from the outer base region to the inner base region during device operation can obtain the lowest possible current path without high-resistance "dead zones", that is, it can obtain the lowest possible parasitic resistance of the connection base region. The technical solution proposed in this application simultaneously addresses the different, even contradictory, requirements of the inner base region and the connection base region in dual polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistors. This allows for the simultaneous achievement of a sufficiently high cutoff frequency f. T The germanium-silicon-carbon epitaxial inner base region and the silicon interconnect base region ensure minimal parasitic resistance. Reducing the parasitic resistance of the interconnect base region can reduce the parasitic base region resistance of the dual polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistor, which can not only reduce the parasitic base region resistance at a given cutoff frequency f T Under the condition of increasing the highest oscillation frequency f max Moreover, it can effectively reduce the radio frequency noise figure, ultimately achieving the goal of improving the overall device performance of the dual polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistor as a radio frequency device, such as radio frequency power and noise.
[0161] In some embodiments, the germanium-silicon-carbon epitaxial inner base region 11 and the silicon-connected base region 12 are simultaneously grown by a p-type in-situ boron-doped germanium-silicon-carbon selective epitaxial growth method.
[0162] In some embodiments, at least one of the field region silicon oxide layer 4, the base region-collector region isolation silicon oxide layer 5, and the L-shaped silicon oxide inner sidewall 13a reduces positive charge through processes such as annealing; negative charge is introduced at the interface between the field region silicon oxide layer 4 and the buried layer collector region 2 and the silicon epitaxial collector region 3 through processes such as electron or ion implantation; negative charge is introduced at the interface between the base region-collector region isolation silicon oxide layer 5 and the silicon epitaxial collector region 3 through processes such as electron or ion implantation; negative charge is introduced at the interface between the bottom of the L-shaped silicon oxide inner sidewall 13a and the germanium-silicon-carbon epitaxial inner base region 11 and the silicon connecting base region 12 through processes such as electron or ion implantation.
[0163] In some embodiments, it also includes:
[0164] The silicon oxide outer wall 18a is formed on the outer side of the base region-collector region isolation silicon oxide layer 5, the polysilicon outer base region 6a, the emitter region-base region isolation silicon oxide layer 7, and the polysilicon emitter region 14b.
[0165] In some embodiments, the upper surfaces of the field region silicon oxide layer 4 and the silicon epitaxial collector region 3 are flush; the upper surfaces of the silicon interconnect base region 12, the germanium-silicon-carbon epitaxial inner base region 11, and the base region-collector region isolation silicon oxide layer 5 are flush.
[0166] In some embodiments, it also includes:
[0167] The emitter is connected to the polycrystalline silicon emitter region 14b;
[0168] The base is connected to the polycrystalline silicon outer base region 6a;
[0169] The collector electrode is electrically connected to the buried layer collector region 2.
[0170] The substrate electrode is electrically connected to the substrate 1.
[0171] In some embodiments, the emitter includes an emitter silicide electrode 16, which is formed on the polysilicon emitter region 14b;
[0172] The base includes a base silicide electrode 17, which is formed on the exposed upper surface of the polysilicon outer base region 6a.
[0173] In some embodiments, heavy doping refers to impurity concentrations of 10. 19 cm -3 The above refers to light doping, which means an impurity concentration of 10. 16 cm -3 the following.
[0174] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The terms "upper," "lower," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and for simplification, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0175] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In the description of this specification, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments in this specification. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0176] This application uses specific embodiments to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A germanium-silicon heterojunction npn-type bipolar transistor, characterized in that, include: p-type lightly doped silicon substrate; An n-type heavily doped silicon buried collector region is formed on the substrate; An n-type lightly doped silicon epitaxial collector region is formed on the buried layer collector region; The SiC region is formed in the silicon epitaxial collector region by SiC ion implantation process; A field region silicon oxide layer is formed on the buried layer current collector region and located on the side of the silicon epitaxial current collector region; p-type in-situ boron-doped germanium-silicon-carbon epitaxial base region is formed on the SiC region; p-type in-situ boron-doped silicon interconnect base regions are formed on the SiC region and the silicon epitaxial collector region; A base-collector region isolation silicon oxide layer is formed on the silicon epitaxial collector region and the field region silicon oxide layer; L-shaped silicon oxide inner walls are formed on the germanium-silicon-carbon epitaxial inner base region and the silicon connection base region, and the bottom of the L-shaped silicon oxide inner walls encloses a window region. A single-crystal emitter region is formed on the inner base region of the germanium-silicon-carbon epitaxial layer and located below the window region; p-type heavily doped polycrystalline silicon outer base region is formed on the base region-collector region isolation silicon oxide layer and the silicon interconnect base region and is located on the side of the L-shaped silicon oxide inner wall; An emitter-base isolation silicon oxide layer is formed on the outer base region of the polycrystalline silicon and located on the side of the inner sidewall of the L-shaped silicon oxide. The n-type heavily doped polycrystalline silicon emitter region is formed inside and above the inner wall of the L-shaped silicon oxide and extends outward to the emitter-base isolation silicon oxide layer.
2. The germanium-silicon heterojunction npn bipolar transistor according to claim 1, characterized in that, The germanium-silicon-carbon epitaxial inner base region and the silicon-connecting base region are simultaneously grown using a p-type in-situ boron-doped germanium-silicon-carbon selective epitaxial growth method.
3. The germanium-silicon heterojunction npn bipolar transistor according to claim 2, characterized in that, Also includes: A silicon oxide outer wall is formed on the outer side of the base-collector region isolation silicon oxide layer, the polysilicon outer base region, the emitter region-base region isolation silicon oxide layer, and the polysilicon emitter region.
4. The germanium-silicon heterojunction npn bipolar transistor according to claim 3, characterized in that, The upper surfaces of the silicon oxide layer in the field region and the silicon epitaxial current collector region are flush; The upper surfaces of the silicon interconnect base region, the germanium-silicon-carbon epitaxial inner base region, and the base region-collector region isolation silicon oxide layer are flush.
5. The germanium-silicon heterojunction npn bipolar transistor according to claim 1, characterized in that, Also includes: The emitter is connected to the polycrystalline silicon emitter region; The base is connected to the outer base region of the polycrystalline silicon. The collector electrode is electrically connected to the buried layer current collection region; The substrate electrode is electrically connected to the substrate.
6. The germanium-silicon heterojunction npn bipolar transistor according to claim 5, characterized in that, The emitter includes an emitter silicide electrode, which is formed on the polycrystalline silicon emitter region; The base includes a base silicide electrode formed on the exposed upper surface of the polycrystalline silicon outer base region.
7. The germanium-silicon heterojunction npn bipolar transistor according to claim 1, characterized in that, The term "heavy doping" refers to an impurity concentration of 10. 19 cm -3 The above refers to light doping, which means an impurity concentration of 10. 16 cm -3 the following.
8. A method for fabricating a germanium-silicon heterojunction npn-type bipolar transistor, characterized in that, include: An npn bipolar transistor basic structure is provided, the npn bipolar transistor basic structure includes a p-type lightly doped silicon substrate, an n-type heavily doped silicon buried collector region formed on the substrate, and an n-type lightly doped silicon epitaxial collector region and a field region silicon oxide layer formed on the buried collector region, wherein the field region silicon oxide layer is located on the side of the silicon epitaxial collector region; A base-collector region isolation silicon oxide layer, a p-type heavily doped outer base region polycrystalline silicon layer, an emitter-base region isolation silicon oxide layer, and a first silicon nitride layer are deposited sequentially. Photolithography is performed on the collector region window. The first silicon nitride layer, the emitter-base region isolation silicon oxide layer and the outer base region polysilicon layer are sequentially etched using photoresist as a mask until the base region-collector region isolation silicon oxide layer is exposed, forming the collector region window. SiC ion implantation is performed through the collector region window to form a SiC region in the area of the silicon epitaxial collector region opposite the collector region window, and then the photoresist is removed. First, a second silicon nitride layer is deposited, and then the silicon nitride is etched anisotropically to form an inner wall of silicon nitride inside the window of the collector region. Using the remaining silicon nitride layer and the inner wall of the silicon nitride as a mask, the exposed base-collector region isolation silicon oxide layer is wet-etched away, and the base-collector region isolation silicon oxide layer is further etched laterally, so that a part of the silicon epitaxial collector region is exposed. By using a p-type in-situ boron-doped germanium-silicon-carbon selective epitaxial growth method, a p-type in-situ boron-doped germanium-silicon-carbon epitaxial inner base region located below the region surrounded by the inner sidewall of the silicon nitride, a cantilever of the polycrystalline silicon layer in the outer base region, and a p-type in-situ boron-doped silicon connection base region located below the inner sidewall of the silicon nitride are simultaneously grown. The remaining silicon nitride layer and the inner wall of the silicon nitride are removed by wet etching; Deposit silicon oxide isolation layer; First, an n-type heavily doped first polysilicon layer is deposited, and then the first polysilicon layer is anisotropically dry etched to form the inner sidewall of the emitter region polysilicon. The exposed silicon oxide isolation layer is removed by wet etching using the polycrystalline silicon inner wall as a mask to form an L-shaped silicon oxide inner wall, wherein the bottom of the L-shaped silicon oxide inner wall forms a window area. A second polysilicon layer heavily doped with n-type is deposited, and the second polysilicon layer is combined with the inner sidewall of the emitter polysilicon layer to form an n-type heavily doped emitter polysilicon layer. Photolithography is performed on the polycrystalline silicon emitter region, and the n-type heavily doped emitter region polycrystalline silicon layer and the emitter region-base region isolation silicon oxide layer are sequentially etched using photoresist as a mask to form the n-type heavily doped polycrystalline silicon emitter region. Then the photoresist is removed. Photolithography is performed on the polysilicon outer base region, and the polysilicon layer of the outer base region and the base-collector isolation silicon oxide layer are etched using photoresist as a mask to form a p-type heavily doped polysilicon outer base region. Then the photoresist is removed. Rapid thermal annealing is performed to allow impurities in the polycrystalline silicon emitter region to diffuse into the germanium-silicon-carbon epitaxial inner base region, forming an n-type heavily doped single-crystal emitter region.
9. The method according to claim 8, characterized in that, The selective epitaxial growth method of germanium-silicon-carbon with p-type in-situ boron doping simultaneously grows a p-type in-situ boron doped germanium-silicon-carbon epitaxial inner base region located below the region surrounded by the inner sidewalls of the silicon nitride, and a cantilever of the polycrystalline silicon layer in the outer base region and a p-type in-situ boron doped silicon connection base region located below the inner sidewalls of the silicon nitride, including: By selective epitaxy and deposition processes, on the one hand, silicon and boron precursors can be diffusely distributed throughout the entire cavity formed by wet etching of the base-collector region isolation silicon oxide layer, and can penetrate deep into the cantilever of the outer base region polycrystalline silicon layer and the cavity region below the inner sidewall of the silicon nitride before being adsorbed at the reaction interface; on the other hand, germanium and carbon precursors can only reach the reaction interface in the region directly below the window enclosed by the inner sidewall of the silicon nitride, and are thus adsorbed by the reaction interface and react to participate in the epitaxial growth of the inner base region; finally, p-type in-situ boron-doped germanium-silicon-carbon epitaxial inner base region and p-type in-situ boron-doped silicon connecting base region are grown or deposited simultaneously.
10. The method according to claim 9, characterized in that, After forming the p-type heavily doped polycrystalline silicon substrate region and then removing the photoresist, and before performing rapid thermal annealing, the method further includes: Deposit a silicon oxide layer on the outer wall; After the rapid thermal annealing, the method further includes: The outer wall silicon oxide layer is etched using anisotropic dry etching to form a silicon oxide outer wall.
11. The method according to claim 10, characterized in that, The method further includes: An emitter, a base, a collector, and a substrate are formed, such that the emitter is connected to the polysilicon emitter region, the base is connected to the polysilicon outer base region, the collector is electrically connected to the buried layer collector region, and the substrate is electrically connected to the substrate.
12. The method according to claim 11, characterized in that, The formation of the emitter and base includes: Emitter silicide electrodes and base silicide electrodes are formed by silicide reaction between refractory metal and the exposed polycrystalline silicon emitter region and polycrystalline silicon base region, which are self-aligned and isolated by the outer wall of the silicon oxide.