Segmented polycrystalline silicon deep groove silicon carbide MOSFET

Abstract

The invention discloses a segmented polycrystalline silicon deep groove silicon carbide MOSFET, and belongs to the technical field of semiconductor power devices. According to the device, a P + polycrystalline silicon section connected with a source electrode, a lightly doped Npolycrystalline silicon section and an N + polycrystalline silicon section connected with a grid electrode are sequentially arranged in a deep groove in the depth direction, and the P + polycrystalline silicon section, the lightly doped Npolycrystalline silicon section and the N + polycrystalline silicon section jointly form a polycrystalline silicon diode structure similar to a PIN. The P + polycrystalline silicon section at the bottom of the groove is used for shielding an electric field, the gate-drain coupling capacitance (Cgd) is effectively reduced, and the switching characteristic of the device is improved; meanwhile, by utilizing the characteristic that the reverse leakage current of the PIN structure is obviously increased under the short-circuit temperature rise, the self-adaptive reduction of the gate-source voltage (Vgs) is realized through gate loop resistance voltage division, so that the short-circuit current is inhibited. While voltage resistance and conduction performance of the device are ensured, short-circuit endurance capability and safe turn-off reliability of the device are remarkably improved.

Description

A segmented polysilicon deep trench silicon carbide MOSFET Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a segmented polycrystalline silicon deep trench silicon carbide MOSFET. Background Technology

[0002] With the continuous development of power electronics technology, applications such as electric vehicles (EVs / HEVs), photovoltaics and energy storage, electric drives, rail transportation, and high-power-density server power supplies are placing higher demands on power semiconductor devices, particularly in terms of higher conversion efficiency, higher switching frequency, higher power density, and wider operating temperature range. Traditional silicon (Si) power devices have long dominated the industry, but due to the intrinsic properties of the material, silicon devices struggle to balance low conduction losses and low switching losses under high voltage, high temperature, and high frequency conditions. In particular, at high voltage ratings, the drift region resistance increases significantly, leading to higher on-resistance and thus limiting further improvements in system efficiency and power density.

[0003] Wide bandgap semiconductor materials (such as silicon carbide (SiC) and gallium nitride (GaN)) exhibit significant advantages in high-voltage, low-loss, high-temperature, and high-frequency applications due to their wider bandgap, higher critical breakdown electric field, higher thermal conductivity, and higher saturated electron drift velocity. Among them, SiC MOSFETs (metal-oxide-semiconductor field-effect transistors) combine high breakdown voltage, low specific on-resistance, and excellent thermal stability, making them an important device choice for achieving high efficiency and miniaturization in medium- and high-voltage power converters.

[0004] Existing SiC MOSFET device structures mainly include two types: planar gate and trench gate. Compared to planar structures, trench gate SiC MOSFETs can increase channel density and reduce channel resistance components by using vertical channels, thereby achieving lower specific on-resistance under the same voltage withstand conditions. However, while pursuing low on-resistance, trench gate structures also introduce new technical challenges: on the one hand, the device's on-resistance consists of multiple components, including channel resistance, JFET region resistance, and drift region / current spread layer resistance. Among these, the potential distribution and carrier concentration near the current spread layer (such as the current spread layer / CSL) below the channel have a significant impact on conduction losses. On the other hand, the gate-drain coupling capacitance Cgd of trench gate structures is relatively large, leading to a significant Miller plateau effect during switching, increasing switching losses and exacerbating electromagnetic interference. Furthermore, under extreme conditions such as short circuits, SiC MOSFETs are prone to problems such as large short-circuit current, high power dissipation density, and rapid junction temperature rise, which in turn leads to gate oxide reliability degradation and an increased risk of device failure. Short-circuit tolerance has become one of the key bottlenecks restricting its widespread application in high-reliability applications.

[0005] To address the aforementioned technical challenges, this invention proposes a segmented polysilicon deep trench silicon carbide MOSFET device structure. Through the synergistic design of the segmented polysilicon trench gate and source shielding structure, combined with the potential modulation effect of the lightly doped layer, the on-resistance is kept at an acceptable level while maintaining breakdown voltage and improving short-circuit robustness. Simultaneously, the gate-drain coupling capacitance Cgd is reduced, and the gate-source voltage is adaptively reduced under short-circuit conditions, thereby improving the overall performance of the device in high-frequency, high-efficiency, and high-reliability applications. Summary of the Invention

[0006] In view of this, the present invention aims to provide a segmented polysilicon deep trench silicon carbide MOSFET. This device introduces segmented polysilicon electrodes into a deep trench structure, with an N+ gate polysilicon segment, a lightly doped N− polysilicon segment, and a P+ source polysilicon segment connected to the source sequentially arranged along the trench depth direction, thereby forming an approximately PIN polysilicon diode structure. During normal conduction, the polysilicon diode is reverse biased. The lightly doped N− polysilicon segment conducts the gate control potential downwards along the trench direction, extending the gate control effect to the current spread layer region below the trench, reducing the potential barrier in this region and inducing electron accumulation. While maintaining voltage withstand capability and improving short-circuit robustness, the on-resistance remains at an acceptable level. Simultaneously, the P+ source polysilicon segment at the bottom of the trench shields the bottom electric field, weakening the gate-drain coupling to reduce the gate-drain coupling capacitance Cgd and improve switching characteristics. Under extreme conditions such as short circuits, the temperature rise of the device increases the reverse leakage current of the polysilicon diode. The gate-source voltage Vgs is adaptively reduced by the voltage division of the equivalent gate resistor Rg in the gate drive circuit, thereby suppressing the short circuit current and improving the device's short circuit withstand capability and safe turn-off reliability. To achieve the above objectives, the present invention provides the following technical solution: a segmented polysilicon deep trench silicon carbide MOSFET device: the device comprises a drain (1), an N+SUB (2), an N-drift region (3), an N-CSL current extension layer (4), a P-base / channel region (5), an N+ source region (6), a P-well (7), a P+ body contact region (8), a lower polysilicon oxide layer (9), a gate polysilicon oxide layer (10), a P+ source polysilicon segment (11), a lightly doped N− polysilicon segment (12), an N+ gate polysilicon segment (13), and a source metal (14); the drain (1) is located on the lower surface of the N+SUB (2); the N+SUB (2) is located on the lower surface of the N-drift region (3) and the drain (1) The N-drift region (3) is located between the upper surface of the N+SUB (2) and the lower surface of the N-CSL current extension layer (4); the N-CSL current extension layer (4) is located between the upper surface of the N-drift region (3) and the lower surface of the P-well (7) / P-base (5); the P-well (7) is formed on the upper surface of the N-CSL current extension layer (4), and the P-base / channel region (5) is located on the surface area of ​​the P-well (7); the N+ source region (6) is located on the surface of the P-base / channel region (5) and is electrically connected to the source metal (14); the P+ body contact region (8) is located on the surface of the P-well (7) and is electrically connected to the source metal (14).The device has a deep trench structure, within which segmented polysilicon electrodes and corresponding oxide layer structures are arranged: the P+ source polysilicon segment (11), the lightly doped N− polysilicon segment (12), and the N+ gate polysilicon segment (13) are sequentially arranged within the deep trench along the trench depth direction, forming a structure similar to a PIN diode; the P+ source polysilicon segment (11) is located in the bottom region of the trench and is electrically connected to the source metal layer; the N+ gate polysilicon segment (13) is located in the trench... The upper region of the trench is electrically connected to the gate metal layer; the lightly doped N− polysilicon segment (12) is located between the P+ source polysilicon segment (11) and the N+ gate polysilicon segment (13); the lower polysilicon oxide layer (9) covers the P+ source polysilicon segment (11) and the lightly doped N− polysilicon segment (12); the gate polysilicon segment oxide layer (10) covers the N+ gate polysilicon segment (13); the lightly doped N− polysilicon segment (12) A near-PIN polysilicon diode structure is formed between the P+ source polysilicon segment (11) and the P+ source polysilicon segment (12). Further, an N+ gate polysilicon segment (13), a lightly doped N− polysilicon segment (12), and a P+ source polysilicon segment (11) are sequentially arranged along the trench depth direction in the deep trench. The P+ source polysilicon segment (11) is electrically connected to the source metal layer, the N+ gate polysilicon segment (13) is electrically connected to the gate, and the lightly doped N− polysilicon segment (12) is located between the two, forming a near-PIN polysilicon diode structure. During normal forward conduction, the polysilicon diode is reverse biased. The lightly doped N− polysilicon segment (12) conducts the gate control potential downward along the deep trench direction, so that the gate control effect extends to the area adjacent to the N-type current extension layer (CSL) (4) below the channel, reducing the potential barrier in this area and inducing the formation of electron accumulation. Under the premise of maintaining the withstand voltage and improving the short-circuit robustness, the on-resistance is kept at an acceptable level. Meanwhile, the P+ source polysilicon segment (11) at the bottom of the deep trench acts as a shield for the electric field at the bottom of the trench, weakening the capacitive coupling between the gate and drain sides, thereby reducing the gate-drain coupling capacitance Cgd and improving the device switching characteristics.

[0007] Furthermore, under extreme conditions such as short circuits, the transient temperature rise caused by the large current inside the device significantly increases the reverse leakage current of the polysilicon diode structure, which is composed of an N+ gate polysilicon segment (13), a lightly doped N− polysilicon segment (12), and a P+ source polysilicon segment (11), forming an approximate PIN. This leads to an increase in the gate current and enhances the voltage division effect on the equivalent gate resistance Rg in the gate drive circuit, causing the gate-source voltage Vgs to decrease adaptively or be clamped. Accompanied by a decrease in short-circuit current, this improves the device's short-circuit tolerance and safe turn-off capability.

[0008] The beneficial effects of this invention are as follows: The device of this invention introduces segmented polysilicon electrodes into a deep trench structure. The upper N+ gate polysilicon segment, the middle lightly doped N− polysilicon segment, and the lower P+ source polysilicon segment together constitute an approximately PIN polysilicon diode structure. During forward conduction, the polysilicon diode remains reverse biased. The lightly doped N− polysilicon segment extends the gate control potential downwards to the current spread layer region below the channel, reducing the potential barrier and inducing electron accumulation, thereby reducing the resistance component of the conduction path and further reducing the on-resistance without sacrificing the breakdown voltage. Simultaneously, the P+ source polysilicon segment at the bottom of the trench shields the electric field, weakening the gate-drain coupling to reduce Cgd and improve switching characteristics. Under abnormal operating conditions such as short circuits, the reverse leakage current of the polysilicon diode adaptively increases with temperature rise. Through voltage division in the gate drive circuit, Vgs adaptively decreases, thereby suppressing the short-circuit current and improving the device's short-circuit tolerance and safe turn-off reliability. In summary, this invention achieves comprehensive optimization of conduction loss, switching loss, and short-circuit reliability through the synergistic design of segmented polysilicon deep trench electrode structures. Other advantages, objectives, and features of this invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of this invention can be realized and obtained through the following description. Attached Figure Description

[0009] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be described in detail below with reference to the accompanying drawings, in which: Figure 1 is a schematic diagram of the overall structure of the SiC MOSFET of the present invention; Figure 2 is a comparison curve of the output characteristics of the device of the present invention and the conventional double-trench SiC MOSFET under a gate voltage of 15 V, and a schematic diagram of the current path of the device of the present invention when it is turned on in the first quadrant; Figure 3 is a comparison curve of the breakdown characteristics of the device of the present invention and the conventional double-trench SiC MOSFET, and shows the leakage current change under the breakdown state; Figure 4 is a comparison curve of the short-circuit transient characteristics of the device of the present invention and the conventional device under a short-circuit duration of 3 μs, and shows a schematic diagram of the current path after the short circuit ends; Figure 5 is a schematic diagram of the potential distribution and lattice temperature distribution of the device of the present invention at t=1 μs and t=2 μs under short-circuit conditions, used to illustrate the process of increasing reverse leakage current of the PIN-like structure and triggering a decrease in gate-source voltage as the temperature rises; Figure 6 is a comparison curve of the capacitance characteristics of the device of the present invention and the conventional double-trench SiC MOSFET, showing the capacitance change as the voltage rises... DSThe relationship between the changing input capacitance Ciss, output capacitance Coss, and feedback capacitance Crss; Figure 7 shows the comparison curves of the gate charge characteristics of the device of the present invention and the traditional dual-trench SiC MOSFET, and the corresponding test circuit schematic diagram; Figure 8 shows the comparison diagram of the turn-on and turn-off transient waveforms of the device of the present invention and the traditional dual-trench SiC MOSFET, used to compare the switching speed and Miller plateau characteristics of the two devices; Figure labels: 1-drain, 2-N+SUB, 3-N-drift region, 4-N-CSL current extension layer, 5-P-base / channel region, 6-N+ source region, 7-P-well, 8-P+ body contact region, 9-lower polysilicon oxide layer, 10-gate polysilicon oxide layer, 11-P+ source polysilicon segment, 12-lightly doped N-polysilicon segment, 13-N+ gate polysilicon segment, 14-source metal. Detailed Implementation

[0010] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0011] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0012] In the accompanying drawings of this invention, the same or similar reference numerals correspond to the same or similar components. In the description of this invention, it should be understood that terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this invention and simplifying the description, not to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms describing positional relationships in the drawings are for illustrative purposes only and should not be construed as limiting this invention. Those skilled in the art can understand the specific meaning of the above terms according to the specific circumstances. Example 1

[0013] As shown in Figure 1, a segmented polysilicon deep trench silicon carbide MOSFET is composed of a drain (1), an N+SUB (2), an N-drift region (3), an N-CSL current extension layer (4), a P-base / channel region (5), an N+ source region (6), a P-well (7), a P+ body contact region (8), a lower polysilicon oxide layer (9), a gate polysilicon oxide layer (10), a P+ source polysilicon segment (11), a lightly doped N− polysilicon segment (12), an N+ gate polysilicon segment (13), and a source metal (14).

[0014] The drain (1) is located on the lower surface of the device and is electrically connected to N+SUB (2).

[0015] The N+SUB (2) is located below the N-drift region (3), with a lateral width of 4.0 μm and a longitudinal thickness of 3.0 μm; the material is SiC, doped with N-type impurity nitrogen (N), with a doping concentration of 2×10^19 cm⁻³.

[0016] The N-drift region (3) is located above the N+SUB (2) and below the N-CSL current extension layer (4), with a lateral width of 4.0 μm and a longitudinal thickness of 10.0 μm. The material is SiC, doped with N-type impurity nitrogen (N), with a doping concentration of 8×10^15 cm⁻³.

[0017] The N-CSL current extension layer (4) is located in the upper region above the drift region, with a lateral width of 4.0 μm and a longitudinal thickness of 3.5 μm; the material is SiC, doped with N-type impurity nitrogen (N), and the doping concentration is 4×10^16 cm⁻³.

[0018] The P-base / channel region (5) is located on the surface of the N-CSL current extension layer (4), with a lateral width of 4.0 μm and a longitudinal thickness of 0.3 μm. The material is SiC, doped with P-type impurity aluminum (Al), with a doping concentration of 2×10^17 cm⁻³.

[0019] The N+ source region (6) is located on the surface of the P-base / channel region (5), with a lateral width of 4.0 μm and a longitudinal thickness of 0.3 μm; the material is SiC, doped with N-type impurity nitrogen (N), with a doping concentration of 1×10^19 cm⁻³.

[0020] The source metal (14) is disposed on the device surface and electrically connected to the N+ source region (6) and the P+ body contact region (8) to form the source terminal.

[0021] The P-well (7) is located on the left and right sides of the device in this embodiment and is used to realize the body region / shielding function: its left and right sides are respectively formed on the left side: lateral width 0.9 μm, vertical height 2.6 μm; right side: lateral width 0.9 μm, vertical height 2.6 μm; the material is SiC, doped with P-type impurity aluminum (Al), and the doping concentration is 2×10^18 cm⁻³.

[0022] The P+ body contact regions (8) are located on the upper part of the left and right P-wells (7) respectively, and are used to form low-resistance body contacts with the source metal (14): left P+ body contact region: lateral width 0.2 μm, longitudinal thickness 0.3 μm; right P+ body contact region: lateral width 0.2 μm, longitudinal thickness 0.3 μm; the material is SiC, doped with P-type impurity aluminum (Al), and the doping concentration is 1×10^19 cm⁻³.

[0023] Furthermore, source contact openings / trench regions are provided on the left and right source sides of the device to form contact windows between the source metal (14) and the source / body region; the opening depth is 2.0 μm and the opening width on one side is 0.5 μm.

[0024] The device has a deep trench gate structure in the center of the device. In this embodiment, the trench opening is located at x=1.45~2.55 μm, the opening width is 1.10 μm, and the trench depth is 2.20 μm. An oxide layer (9, 10) and segmented polysilicon electrodes (11–13) are disposed in the trench: the lower segment polysilicon oxide layer (9) and the gate polysilicon segment oxide layer (10) are both SiO2, which are used to electrically insulate and isolate the polysilicon in the trench from the surrounding SiC.

[0025] In this embodiment, the trench oxide layer has different sidewall thicknesses at different heights: the upper region (y=0~1.0 μm) of the N+ gate polysilicon segment (13) has a lateral range of x=1.50~2.50 μm, and the oxide layer thickness on both sides is about 0.05 μm (corresponding to the gate polysilicon segment oxide layer (10)); the lower region (y=1.0~2.0 μm) of the lightly doped N− polysilicon segment (12) and P+ source polysilicon segment (11) has a lateral range of x=1.60~2.40 μm, and the oxide layer thickness on both sides is about 0.15 μm. The bottom of the trench retains an oxide layer extending to y=2.20 μm, and the bottom oxide layer thickness is about 0.20 μm (used for top insulation and electric field mitigation, (corresponding to the lower polysilicon oxide layer (9))).

[0026] The N+ gate polysilicon segment (13) is located in the upper region of the trench, with a lateral width of 1.0 μm (x=1.50~2.50 μm) and a vertical height of 1.0 μm (y=0~1.0 μm). The material is polysilicon, doped with N-type impurity phosphorus (P) at a doping concentration of 1×10^19 cm⁻³, and electrically connected to the gate.

[0027] The lightly doped N− polysilicon segment (12) is located below the N+ gate polysilicon segment (13), with a lateral width of 0.8 μm (x = 1.60~2.40 μm) and a vertical height of 0.8 μm; the material is polysilicon, doped with N-type impurity phosphorus (P), with a doping concentration of 1×10^16 cm⁻³.

[0028] The P+ source polycrystalline silicon segment (11) is located below the lightly doped N− polycrystalline silicon segment (12) and in the bottom region of the trench. Its lateral width is 0.8 μm (x=1.60~2.40 μm) and its vertical height is 0.2 μm (y=1.8~2.0 μm). The material is polycrystalline silicon, doped with P-type impurity boron (B) at a doping concentration of 1×10^19 cm⁻³, and electrically connected to the source.

[0029] The lightly doped N− polysilicon segment (12) and the P+ source polysilicon segment (11) form an approximately PIN polysilicon PN junction (diode) structure, which puts it in a reverse bias state under normal gate drive and has temperature-dependent reverse leakage current regulation capability under extreme conditions (such as short-circuit temperature rise).

[0030] Figure 2 shows a comparison of the output characteristic curves of the device of the present invention and the conventional dual-trench SiC MOSFET when the gate voltage is 15V and the current path diagram of the SiC MOSFET of the present invention in the first quadrant. When Vds = 1V, the on-resistances are 2.58mΩ·cm2 and 2.31mΩ·cm2, respectively. The on-resistance of the device of the present invention is slightly larger than that of the conventional asymmetric trench SiC MOSFET. However, because the deeper trench leads to a larger JFET resistance, the gate potential is conducted downward along the trench direction through the lightly doped N− polysilicon segment, so that the gate control potential can act on the current extension layer region below the channel, reducing the potential barrier in this region and inducing electron accumulation, which can optimize the on-resistance to a certain extent. As shown in Figure 3, this figure is a comparison of the breakdown characteristic curves of the two devices. The two devices exhibit similar BV characteristics. The figure also shows the leakage current of the two devices under breakdown. As can be seen from the curves, the device of the present invention, due to the sacrifice of drift region length by the deep trench, has a lower breakdown voltage, but still far meets the withstand voltage requirement of 1200V. Figure 4 shows a comparison of the short-circuit transient characteristics of the device of the present invention and a conventional device under a short-circuit duration of 3 μs, and also provides a schematic diagram of the current path after the short circuit ends. The comparison curves show that after a brief rise in current at the beginning of the short circuit, the gate-source voltage Vgs of the device of the present invention begins to decrease significantly around 1.3 μs, and the short-circuit current is effectively suppressed and gradually decreases. After the short-circuit pulse ends, the device can achieve normal turn-off and restore its blocking capability, exhibiting good withstand voltage retention characteristics. In contrast, the conventional device experiences a rapid rise in short-circuit current during the short circuit and is difficult to self-limit. After the short circuit ends, the rise in body region potential triggers the conduction of parasitic NPN transistors, forming a continuous current path, leading to ineffective turn-off and eventual failure. These results demonstrate that the structure of the present invention can achieve adaptive modulation of Vgs and short-circuit current under short-circuit conditions, improving short-circuit robustness and safe turn-off reliability.

[0031] Figure 5 shows the potential and lattice temperature distributions of the device under short-circuit conditions at t = 1 μs and t = 2 μs. As can be seen from the figure, near t = 1 μs, the lattice temperature has not yet risen to trigger a significant leakage current, and the gate voltage can still rise to approximately 12 V under external driving. At this time, the PIN-like structure formed by the segmented polysilicon in the trench is in a reverse bias state, with a small reverse leakage current, and no significant discharge path has yet formed between G and S. As the short-circuit current continues, the device's self-heating intensifies, and the lattice temperature rises significantly at t = 2 μs. The reverse leakage current of the PIN-like structure increases significantly with the temperature rise, thus forming an effective discharge path between G and S, accelerating the release of gate charge and causing Vgs to decrease adaptively. With the decrease in Vgs, the short-circuit current of the device is suppressed, thereby reducing transient power consumption and temperature rise rate, improving short-circuit withstand capability, and enhancing safe turn-off reliability.

[0032] Figure 6 shows a comparison of the capacitance characteristics (Ciss, Coss, and Crss as a function of VDS) of the device of the present invention and a conventional dual-trench SiC MOSFET. As can be seen from the figure, compared with the conventional device, the input capacitance Ciss of the device of the present invention is increased by approximately 20.8%, while the feedback capacitance Crss (also known as Miller capacitance Cgd) is significantly reduced across the entire voltage range, which is beneficial for reducing the Miller plateau effect and switching losses, and improving switching speed. The present invention introduces a P+ source polysilicon segment connected to the source in the deep trench, effectively shielding the drain-side potential change at the bottom of the trench by the source potential, thereby weakening the electric field coupling between the gate and drain, significantly reducing Cgd, and consequently significantly reducing Crss. Simultaneously, a stronger gate-source coupling is formed between this source shielding electrode and the upper gate polysilicon segment, causing Ciss = Cgs + Cgd to show an overall upward trend. Figure 7 shows a comparison of the gate charge characteristics of the device of the present invention and a conventional dual-trench SiC MOSFET, along with a test circuit diagram. The gate charge (Q) of the device of the present invention... gd The value is 88.5 nC / cm. 2 The traditional dual-trench SiC MOSFET has a voltage rating of 270.2 nC / cm. 2This is because the P+ source polysilicon segment connected to the source effectively shields the drain-side potential change at the bottom of the trench from the source potential, thereby weakening the electric field coupling between the gate and drain, significantly reducing Cgd, and consequently significantly reducing Crss. As shown in Figure 8, this figure compares the transient waveforms of the turn-off and turn-on of the device of the present invention with those of a conventional dual-trench SiC MOSFET. It can be seen that during the turn-off process, the turn-off speed and key waveforms of the two devices are not significantly different, and their overall performance is basically equivalent. The reason is that although the reduction of Crss in the device of the present invention helps to shorten the Miller plateau, the increase in its input capacitance Ciss increases the gate charge required for turn-off, and the two cancel each other out during the turn-off process. In addition, the turn-off transient is also limited by factors such as external circuit parasitic inductance, load conditions, and drive pull-down capability, so the difference in the turn-off process is small. During the turn-on process, the drain-source voltage of the device of the present invention drops faster and the Miller plateau duration is shorter, and the overall turn-on speed is better than that of the conventional device. The reason is that the source shielding introduced in this invention significantly weakens the gate-drain coupling, reduces the feedback capacitance Crss, and thus reduces the Miller charge Qgd, making it easier to complete the V under the same driving conditions. DS The rapid pull-down.

[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A segmented polysilicon deep trench silicon carbide MOSFET device: the device comprises a drain (1), an N+SUB (2), an N-drift region (3), an N-CSL current extension layer (4), a P-base / channel region (5), an N+ source region (6), a P-well (7), a P+ body contact region (8), a lower polysilicon oxide layer (9), a gate polysilicon oxide layer (10), a P+ source polysilicon segment (11), a lightly doped N− polysilicon segment (12), an N+ gate polysilicon segment (13), and a source metal (14); the drain (1) is located on the lower surface of the N+SUB (2); the N+ source polysilicon segment (11) is located on the lower surface of the N+SUB (2); the N+ source polysilicon segment (12) is located on the lower surface of the N+SUB (2); the N+ source polysilicon segment (13) is located on the lower surface of the N+SUB (2); the N+ source polysilicon segment (14) is located on the lower surface of the N+SUB (2); the N+ source polysilicon segment (15) is located on the lower surface of the N+SUB (2); the N+ source polysilicon segment (16) is located on the lower surface of the N+SUB (2); the N+ source polysilicon segment (17) is located on the lower surface of the N+SUB (2); the N+ source polysilicon segment (18) is located on the lower surface of the N+SUB (2); the N+ source polysilicon segment (19) is located on the lower surface of the N+SUB (2); the N+ source polysilicon segment (10) is located on the lower surface of the N+SUB (2); the N+ source polysilicon segment (11) is located on the lower surface of the N+SUB (2); the N+ source polysilicon segment (12) is located on the lower surface of the N+SUB (2); the N+ source polysilicon segment (1 +SUB (2) is located between the lower surface of the N-drift region (3) and the upper surface of the drain (1); the N-drift region (3) is located between the upper surface of N+SUB (2) and the lower surface of the N-CSL current extension layer (4); the N-CSL current extension layer (4) is located between the upper surface of the N-drift region (3) and the lower surface of the P-well (7) / P-base (5); the P-well (7) is formed on the upper surface of the N-CSL current extension layer (4), and the P-base / channel region (5) is located on the surface area of ​​the P-well (7); The N+ source region (6) is located on the surface of the P-base / channel region (5) and is electrically connected to the source metal (14); the P+ body contact region (8) is located on the surface of the P-well (7) and is electrically connected to the source metal (14); the device has a deep trench structure, and segmented polysilicon electrodes and corresponding oxide layer structures are set in the deep trench: the P+ source polysilicon segment (11), the lightly doped N− polysilicon segment (12) and the N+ gate polysilicon segment (13) are sequentially arranged in the deep trench along the trench depth direction to form a PIN diode-like structure; the P+ source polysilicon segment (11) is located in the bottom region of the trench and is electrically connected to the source metal. The gate polysilicon segment (13) is located in the upper region of the trench and is electrically connected to the gate metal layer; the lightly doped N− polysilicon segment (12) is located between the P+ source polysilicon segment (11) and the N+ gate polysilicon segment (13); the lower polysilicon oxide layer (9) covers the P+ source polysilicon segment (11) and the lightly doped N− polysilicon segment (12); the gate polysilicon segment oxide layer (10) covers the N+ gate polysilicon segment (13); an approximately PIN polysilicon diode structure is formed between the lightly doped N− polysilicon segment (12) and the P+ source polysilicon segment (11).

2. The segmented polycrystalline silicon deep trench silicon carbide MOSFET device according to claim 1, characterized in that: The P+ source polysilicon segment (11) is located at the bottom of the trench and electrically connected to the source metal layer to shield the electric field at the bottom of the trench and weaken the capacitive coupling between the gate and the drain side, thereby reducing the gate-drain coupling capacitance Cgd.

3. The segmented polycrystalline silicon deep trench silicon carbide MOSFET device according to claim 1, characterized in that: Under extreme conditions such as short circuits, the transient temperature rise caused by the large current inside the device significantly increases the reverse leakage current of the PIN diode-like structure composed of the P+ source polysilicon segment (11), the lightly doped N− polysilicon segment (12), and the N+ gate polysilicon segment (13). This leads to an increase in the gate current and enhances the voltage division effect on the equivalent gate resistance Rg in the gate drive circuit, causing the gate-source voltage Vgs to decrease or clamp adaptively. Accompanied by a decrease in short-circuit current, this improves the device's short-circuit tolerance and safe turn-off capability.

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