Semiconductor device

Abstract

A semiconductor device includes: a substrate including a first surface and a second surface facing each other, and including a first device region and a second device region provided with devices of different conductivity types; a first channel pattern and a second channel pattern disposed over the first surface of the substrate at the first device region and the second device region, respectively; an insulating structure extending in a first direction between the first device region and the second device region; a gate structure surrounding the first channel pattern and the second channel pattern and extending in a second direction intersecting the first direction; a source / drain pattern connected to both sides of each of the first channel pattern and the second channel pattern; a lower conductive line disposed on the second surface of the substrate and connected to at least some of the source / drain patterns and a gate structure disposed at one edge of the first device region; and a device separation film penetrating the gate structure disposed at the other edge of the first device region.

Description

Semiconductor devices

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0150023, filed on October 29, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor devices. Background Technology

[0004] Standard cells are a widely used design method in integrated circuit (IC) design, referring to small, reusable blocks of transistors arranged in a predetermined manner. Using standard cells reduces design complexity, improves productivity, and ensures a certain level of performance and power efficiency. However, as semiconductor processes become increasingly sophisticated, problems such as interference between transistors and inefficient power consumption may arise, and leakage current issues in diffusion regions negatively impact IC performance.

[0005] Diffusion break is a technique used to address leakage current issues. It separates the diffusion region to block unwanted current flow, reducing power consumption and mitigating electrical interference between transistors. The diffusion break is placed at the boundary between the P-type and N-type regions of the transistor to prevent continuous connection of the diffusion layer. Therefore, it prevents device performance degradation and improves power efficiency.

[0006] Diffusion interruption is critical in high-density integrated circuits, where the spacing between transistors becomes increasingly narrow as process nodes shrink. This reduced spacing increases the risk of current leakage, making diffusion interruption necessary to maintain device isolation and performance. Therefore, diffusion interruption technology is a fundamental element in state-of-the-art process technologies and is considered an important component in the design of high-performance and low-power semiconductors. Summary of the Invention

[0007] The embodiments are designed to effectively prevent current leakage by mixing and using various diffusion interruptions, depending on the characteristics of the device.

[0008] The semiconductor device according to embodiments of this disclosure includes: a substrate including a first surface and a second surface facing each other, and including a first device region and a second device region having devices of different conductivity types; a first channel pattern and a second channel pattern, each disposed above the first surface of the substrate at the first device region and the second device region; an insulating structure extending in a first direction between the first device region and the second device region; a gate structure surrounding the first channel pattern and the second channel pattern and extending in a second direction intersecting the first direction; a source / drain pattern connected to both sides of each of the first channel pattern and the second channel pattern; a lower conductor disposed on the second surface of the substrate and connected to at least some of the source / drain patterns and the gate structure disposed at one edge of the first device region; and a device separation film penetrating the gate structure disposed at another edge of the first device region.

[0009] A semiconductor device according to another embodiment includes: a substrate including a first surface and a second surface facing each other, and including a first device region and a second device region having devices of different conductivity types; a first channel pattern and a second channel pattern, each disposed above the first surface of the substrate at the first device region and the second device region; an insulating structure extending in a first direction with the first channel pattern and the second channel pattern interposed therebetween, and facing each other in a second direction intersecting the first direction; a gate structure surrounding the first channel pattern and the second channel pattern, and extending in the second direction; a source / drain pattern connected to both sides of each of the first channel pattern and the second channel pattern; a lower conductor disposed on the second surface of the substrate and connected to at least some of the source / drain patterns and a gate structure disposed at one edge of the first device region; and a device separation film penetrating the gate structure disposed at another edge of the first device region.

[0010] A semiconductor device according to another embodiment includes: a substrate including a first surface and a second surface facing each other, and including a first device region and a second device region having devices of different conductivity types; a first channel pattern and a second channel pattern, the first channel pattern and the second channel pattern being disposed above the first surface of the substrate at the first device region and the second device region, respectively; at least one insulating structure extending in a first direction and disposed adjacent to at least one of the first channel pattern and the second channel pattern in a second direction intersecting the first direction; a gate structure surrounding the first channel pattern and the second channel pattern and extending in the second direction; a source / drain pattern connected to both sides of each of the first channel pattern and the second channel pattern; and a lower conductor disposed on the second surface of the substrate, connected to at least some of the source / drain patterns, and connected to the gate structure disposed at two edges of the first device region and the second device region.

[0011] According to embodiments, current leakage can be effectively prevented by mixing and using various diffusion interruptions, depending on the characteristics of the device. Attached Figure Description

[0012] Each of Figures 1 and 2 is a layout diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 3 is a cross-sectional view of the semiconductor device along line A-A' of each of Figures 1 and 2.

[0014] Figure 4 is a cross-sectional view of the semiconductor device along line B-B' of each of Figures 1 and 2.

[0015] Figure 5 is a cross-sectional view of the semiconductor device along line C-C' of each of Figures 1 and 2.

[0016] Figure 6 is a cross-sectional view of the semiconductor device along line D-D' of each of Figures 1 and 2.

[0017] Each of Figures 7 and 8 is a layout diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0018] Figure 9 is a cross-sectional view of the semiconductor device along line E-E' of each of Figures 7 and 8.

[0019] Figure 10 is a cross-sectional view of the semiconductor device along line F-F' of each of Figures 7 and 8.

[0020] Each of Figures 11 and 12 is a layout diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0021] Figure 13 is a cross-sectional view of the semiconductor device along line G-G' of each of Figures 11 and 12.

[0022] Figure 14 is a cross-sectional view of the semiconductor device along line H-H' of each of Figures 11 and 12.

[0023] Each of Figures 15 and 16 is a layout diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0024] Figure 17 is a cross-sectional view of the semiconductor device along line I-I' of each of Figures 15 and 16.

[0025] Figure 18 is a cross-sectional view of the semiconductor device along line J-J' of each of Figures 15 and 16.

[0026] Each of Figures 19 and 20 is a layout diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0027] Figure 21 is a cross-sectional view of the semiconductor device along line A-A' of each of Figures 19 and 20.

[0028] Figure 22 is a cross-sectional view of the semiconductor device along line B-B' of each of Figures 19 and 20.

[0029] Figure 23 is a cross-sectional view of the semiconductor device along line C-C' of each of Figures 19 and 20.

[0030] Figure 24 is a cross-sectional view of the semiconductor device along line D-D' of each of Figures 19 and 20.

[0031] Each of Figures 25 and 26 is a layout diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0032] Figure 27 is a cross-sectional view of the semiconductor device along line E-E' of each of Figures 25 and 26.

[0033] Figure 28 is a cross-sectional view of the semiconductor device along line F-F' of each of Figures 25 and 26.

[0034] Each of Figures 29 and 30 is a layout diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0035] Figure 31 is a cross-sectional view of the semiconductor device along line G-G' of each of Figures 29 and 30.

[0036] Figure 32 is a cross-sectional view of the semiconductor device along line H-H' of each of Figures 29 and 30.

[0037] Each of Figures 33 and 34 is a layout diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0038] Figure 35 is a cross-sectional view of the semiconductor device along line I-I' of each of Figures 33 and 34.

[0039] Figure 36 is a cross-sectional view of the semiconductor device along line J-J' of each of Figures 33 and 34. Detailed Implementation

[0040] Embodiments of this disclosure will be described more fully below with reference to the accompanying drawings, enabling those skilled in the art to readily implement the embodiments. This disclosure may be modified in various ways without departing from its spirit or scope.

[0041] For clarity of description, parts or components not related to the description are omitted, and identical or similar constituent elements are indicated by the same reference numerals throughout the specification.

[0042] In the accompanying drawings, for ease of description, the dimensions and thicknesses of each element are shown arbitrarily, and this disclosure is not necessarily limited to those shown in the drawings. In the accompanying drawings, the thicknesses of some layers and regions are exaggerated for clarity. In the accompanying drawings, the thicknesses of some layers and regions are exaggerated for ease of description.

[0043] It should be understood that when an element such as a layer, film, region, or plate is referred to as being "on" or "above" another element, the element may be directly on said other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly on" another element, there are no intermediate elements present. Furthermore, in this specification, the terms "on" or "above" mean disposed on or below a reference component, and do not necessarily mean disposed on the upper side of the reference component based on the direction of gravity.

[0044] Unless explicitly stated otherwise, the word “including” and variations such as “contains” and “comprising” should be understood to imply the inclusion of the stated element, but not to exclude any other element.

[0045] Throughout the instruction manual, the phrase "in a plan view" or "on a plane" can mean when viewing a portion of an object from above, and the phrase "in a cross-sectional view" or "on a cross-section" can mean when viewing a section taken by vertically cutting a portion of an object from the side.

[0046] Throughout the specification, two directions parallel to and intersecting the upper surface of the substrate are each defined as a first direction D1 and a second direction D2, and a direction perpendicular to the upper surface of the substrate is described as a third direction D3. For example, the first direction D1 and the second direction D2 may be orthogonal to each other.

[0047] Throughout the specification, the upper surface of the substrate may be referred to as the front side, and the lower surface of the substrate may be referred to as the back side.

[0048] Figures 1 to 6 illustrate a structure in which a lower conductor BM1 is electrically connected to a gate structure GS located at one edge of a first active region RX1, while a device separation film SDB extending through the gate structure GS located at the opposite edge of the first active region RX1 is formed to provide electrical isolation. Both the lower conductor BM1 and the device separation film SDB are disposed within the first active region RX1, which forms a portion of a unit cell in a semiconductor device according to an embodiment of the present disclosure. Furthermore, a lower conductor connected to a gate structure formed at the opposite boundary of a second active region RX2 is disposed within the second active region RX2. Hereinafter, for clarity and ease of description, Figures 1 and 2 will be described first, followed by Figures 3 to 6. Throughout this specification, the device separation film SDB and the lower gate pattern BCB connecting the gate structure GS to the lower conductor BM1 may be referred to as a diffusion interruption.

[0049] Each of Figures 1 and 2 is a layout diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 1 is a layout diagram illustrating a first surface (e.g., front side) of a semiconductor device according to an embodiment of the present disclosure. Figure 2 is a layout diagram illustrating a second surface (e.g., back side) of a semiconductor device according to an embodiment of the present disclosure.

[0050] Referring to Figures 1 and 2, a semiconductor device according to an embodiment may include a gate structure GS disposed at a first device region RX1 and a second device region RX2 on a substrate, an insulating structure DW and a gate separation structure CT separating the gate structure GS, a device separation film SDB disposed at the edge of the first device region RX1, an upper conductor M1 disposed above or on the upper surface of the substrate, and a lower conductor BM1 disposed above or on the lower surface of the substrate. The semiconductor device according to an embodiment may further include a contact pattern CA connected to the upper conductor M1, a contact via CAV, a gate via CBV, a lower contact pattern BCA, a lower gate pattern BCB, and a lower via BVA connected to the lower conductor BM1.

[0051] According to an embodiment, the gate structure GS, contact pattern CA, gate pattern CB, upper conductor M1, lower conductor BM1, lower via BVA, lower contact pattern BCA, and lower gate pattern BCB disposed at the first device region RX1 and the second device region RX2 can form a standard cell. The first device region RX1 and the second device region RX2 can be disposed within a standard cell.

[0052] For ease of description, Figure 1 shows only a portion of the standard cells included in the semiconductor device, and the standard cells may be designed to include other components. In this disclosure, the semiconductor device may be referred to as an integrated circuit or a semiconductor device.

[0053] According to embodiments, a semiconductor device may include a plurality of standard cells. A standard cell may be a unit of layout included in an integrated circuit chip and may be simply referred to as a cell or unit cell. An integrated circuit chip may include a plurality of various standard cells, and the standard cells may have a structure conforming to predetermined rules based on semiconductor processes used to manufacture the integrated circuit chip. A standard cell may refer to a cell of a chip whose layout dimensions meet predetermined rules and have predetermined functions. According to embodiments, a standard cell may include input pins and output pins, and may output signals through output pins by processing signals received via input pins. For example, a standard cell may correspond to basic cells (such as AND elements, OR elements, NOR elements, and inverters), complex cells (such as OAI (OR / AND / INVERTER) and AOI (AND / OR / INVERTER)), or memory elements (such as simple master-slave flip-flops and latches). According to embodiments, a standard cell may have a quadrilateral shape, but is not limited to this shape.

[0054] The semiconductor device according to the embodiment may include an upper conductor M1 and a lower conductor BM1, and a power distribution network may be implemented using the upper conductor M1 and the lower conductor BM1. Therefore, some of the signals and / or power applied to the source / drain pattern 150 (e.g., the source / drain pattern 150 of FIG. 5 and FIG. 6) and / or the gate structure GS of the first device region RX1 and the second device region RX2 may be transmitted through the upper conductor M1, and the remainder may be transmitted through the lower conductor BM1.

[0055] According to an embodiment, each of the plurality of unit cells may include a device region RX having a predetermined width in the second direction D2 and extending along the first direction D1. A transistor (or device) including a gate electrode, a channel pattern having a plurality of sub-channel patterns stacked on the third direction D3, and a source / drain pattern, as described subsequently, may be disposed at the device region RX. According to an embodiment, the device region RX may include a first device region RX1 and a second device region RX2, the second device region RX2 being disposed adjacent to the first device region RX1, having a predetermined width in the second direction D2, and extending along the first direction D1. According to an embodiment, the widths of the first device region RX1 and the second device region RX2 (e.g., the width along the second direction D2) may be similar or substantially the same.

[0056] According to embodiments, devices of different types (i.e., conductivity types) can be disposed in a first device region RX1 and a second device region RX2. According to embodiments, a first type of transistor can be disposed in the first device region RX1, and a second type of transistor, different from the first type of transistor, can be disposed in the second device region RX2. For example, the source / drain pattern included in the first type of transistor may include one of P-type dopant and N-type dopant, or may be doped with one of P-type dopant and N-type dopant, and the source / drain pattern included in the second type of transistor may include another of P-type dopant and N-type dopant, or may be doped with another of P-type dopant and N-type dopant. For ease of description, in the following embodiments, the source / drain pattern disposed in the first device region RX1 will be described as including P-type dopant or being doped with P-type dopant, and the source / drain pattern disposed in the second device region RX2 will be including N-type dopant or being doped with N-type dopant. In other words, in the following embodiments, the first device region RX1 may be a PMOS transistor region, and the second device region RX2 may be an NMOS transistor region. In an embodiment, each of the first device region RX1 and the second device region RX2 can be used as an active region in which a transistor is formed. In an embodiment, the first device region RX1 and the second device region RX2 can be planar active regions or finned active regions.

[0057] Although not clearly shown in the accompanying drawings, each of the plurality of unit cells may include a first device region RX1 and a second device region RX2, and the first device region RX1 and the second device region RX2 may be alternately arranged adjacent to each other along a second direction D2. However, this disclosure is not limited thereto, and each of the plurality of unit cells may include a first device region RX1 and a second device region RX2, the first device region RX1 being arranged adjacent to each other along the second direction D2, and the second device region RX2 being arranged adjacent to each other along the second direction D2. According to an embodiment, the first device region RX1 and the second device region RX2 may be formed above or on a substrate. For example, the substrate may be made of an insulating material.

[0058] According to an embodiment, a first device region RX1 and a second device region RX2, having a plurality of channel patterns to be described subsequently, and an insulating structure DW separating the first device region RX1 and the second device region RX2, can be disposed above or on a substrate. Each of the first device region RX1, the insulating structure DW, and the second device region RX2 can extend along a first direction D1. The first device region RX1, the insulating structure DW, and the second device region RX2 can be disposed along a second direction D2. In other words, the insulating structure DW can extend in the first direction D1 between the first device region RX1 and the second device region RX2.

[0059] According to an embodiment, the insulating structure DW may contact the first channel pattern CP1 and the second channel pattern CP2, which will be described subsequently, in the second direction D2. In other words, the insulating structure DW may not be spaced apart from the first channel pattern CP1 and the second channel pattern CP2 in the second direction D2. However, this disclosure is not limited thereto, and the gate insulating film 130, described subsequently, may be interposed between the insulating structure DW and the first channel pattern CP1 and the second channel pattern CP2. At least a portion of the gate electrode 120, described below, may be interposed between the insulating structure DW and the first channel pattern CP1 and the second channel pattern CP2.

[0060] As described above, since the insulating structure DW of the semiconductor device according to this disclosure is not spaced apart from the first channel pattern CP1 and the second channel pattern CP2 in the second direction D2, the first device region RX1 and the second device region RX2 can be physically and / or electrically separated while improving the integration of the device.

[0061] As described below, multiple channel patterns can be disposed above or on the upper surface of the substrate. The multiple channel patterns can be disposed along a second direction D2. The multiple channel patterns may include a first channel pattern CP1 formed at a first device region RX1 and a second channel pattern CP2 formed at a second device region RX2. According to an embodiment, the multiple channel patterns may be surrounded by a gate structure GS and an insulating structure DW.

[0062] According to an embodiment, the semiconductor device may include a plurality of gate structures GS, which surround a plurality of channel patterns and extend along a second direction D2. According to an embodiment, the gate structures GS may have a shape extending along the second direction D2 within a standard cell. According to an embodiment, the gate structures GS may have a shape separated along the second direction D2 by an insulating structure DW. According to an embodiment, at least some of the plurality of gate structures GS may be disposed at an edge of a first device region RX1 and / or a second device region RX2.

[0063] According to an embodiment, the pitch between multiple gate structures GS can be referred to as 1-contacted poly pitch (CPP). For example, 1CPP is the minimum distance in the same direction from the center of one gate structure (the gate of a transistor having contacts thereon) to the center of the next gate structure. The number of gate structures GS in this specification is merely an example, and it is obvious that it is possible to configure cells to have a different number of gate structures GS.

[0064] According to an embodiment, the semiconductor device may further include a gate separation structure CT that separates and spaces a gate structure GS extending along a second direction D2. According to an embodiment, the gate separation structure CT may be disposed along the second direction D2 between adjacent channel patterns CP1 or CP2, as described subsequently.

[0065] According to an embodiment, the gate separation structure CT can be disposed adjacent to the edges of one side (e.g., the upper side) and the other side (e.g., the lower side) of a standard cell. Some of the gate separation structures CT can have a shape that overlaps with the upper conductor M1 and extends along the first direction D1.

[0066] According to an embodiment, some of the gate-separated structures CT can be configured to face the insulating structure DW with a first device region RX1 inserted therebetween. According to an embodiment, some of the gate-separated structures CT can be configured to face the insulating structure DW with a second device region RX2 located therebetween.

[0067] According to an embodiment, the gate separation structure CT may be spaced apart from the first channel pattern CP1 disposed at the first device region RX1 in the second direction D2. According to an embodiment, the gate separation structure CT may be spaced apart from the second channel pattern CP2 disposed at the second device region RX2 in the second direction D2.

[0068] According to an embodiment, the contact pattern CA may be disposed above or on at least one source / drain pattern 150 of the first device region RX1 and / or the second device region RX2. According to an embodiment, the contact pattern CA may be disposed above or on the source / drain pattern 150 to be electrically connected to the source / drain pattern 150.

[0069] According to an embodiment, the contact pattern CA can be connected to the upper conductor M1 via a contact via CAV. For example, the contact via CAV may include aluminum, copper, tungsten, molybdenum, cobalt, or a combination thereof.

[0070] According to an embodiment, the gate pattern CB may be disposed above or on at least one gate structure GS of the first device region RX1 and / or the second device region RX2. For example, the gate pattern CB may be disposed on at least one gate electrode 120, which will be described later. In this way, the gate pattern CB may be disposed on the gate electrode for electrical connection to the gate electrode.

[0071] According to an embodiment, the gate pattern CB can be connected to the upper conductor M1 via a gate via CBV. For example, the gate via CBV may include aluminum, copper, tungsten, molybdenum, cobalt, or a combination thereof.

[0072] According to an embodiment, the upper conductor M1 may include a plurality of conductive patterns or a plurality of patterns made of conductive material. In this specification, a pattern may refer to an electrical pattern. For example, the upper conductor M1 may include each of an upper conductor pattern extending along a first direction D1. In this case, a pattern extending in one direction may be referred to as a line, such that the upper conductor pattern is referred to as an upper conductor. According to an embodiment, the gate electrode 120, described subsequently, may be connected to the upper conductor M1 via a gate pattern CB.

[0073] According to an embodiment, a semiconductor device may include a device separation film (SDB) that physically separates adjacent cells. According to an embodiment, the channel pattern of the cells can be terminated using the device separation film (SDB). The SDB can be inserted to reduce the influence between adjacent cells (e.g., local layout effect (LLE)) and to separate impurity-doped regions between adjacent cells. According to an embodiment, the SDB may be made of an insulating material.

[0074] According to an embodiment, the device separation membrane SDB may be disposed adjacent to the edge (or boundary) of the cell. In this disclosure, the device separation membrane SDB is shown as a single diffusion interruption, but this disclosure is not limited thereto, and the device separation membrane SDB may be a double diffusion interruption.

[0075] According to an embodiment, the device separation film SDB can penetrate the gate structure GS disposed at one edge (e.g., left or right) of the cell in the third direction D3. The width of the device separation film SDB (e.g., its length along the first direction D1) can be less than or substantially the same as the width of the gate structure GS. For example, if the width of the device separation film SDB (or its length along the first direction D1) is less than the width of the gate structure GS, the gate structure GS that has not been removed can be disposed around the device separation film SDB. For example, a material identical to the material of the gate structure GS can be disposed in contact with the exterior of the device separation film SDB. For example, if the width of the device separation film SDB (or its length along the first direction D1) is substantially the same as the width of the gate structure GS, the device separation film SDB can be in direct contact with the first interlayer insulating layer (e.g., the first interlayer insulating layer 160 of Figures 5 and 6) described below.

[0076] Referring to Figures 1 and 2, in an embodiment, a device separation membrane SDB disposed adjacent to one edge of the cell may be disposed at the first device region RX1. In Figures 1 and 2, the device separation membrane SDB is shown disposed adjacent to the right edge of the cell, but this disclosure is not limited thereto, and the device separation membrane SDB may be disposed adjacent to the left edge of the cell.

[0077] According to an embodiment, the device separation film SDB can physically separate one side of the first device region RX1 from the adjacent area of ​​another unit on the same side of the first device region RX1. In this case, the first channel pattern CP1 can be removed at the portion intersecting with the device separation film SDB. For example, the device separation film SDB can be designed not to overlap with the first channel pattern CP1 on the third direction D3.

[0078] According to an embodiment, one of the plurality of gate structures GS located at one edge (e.g., left or right) of the first device region RX1 can be replaced with a device separation film SDB. For example, the device separation film SDB can be formed by removing the gate structure GS and filling the removed location with an insulating material. Therefore, it can be configured such that substantially no current flows between the components located on both sides (i.e., opposite sides) of the device separation film SDB.

[0079] According to an embodiment, the semiconductor device may be disposed above or on the lower surface of the substrate, and may include a lower conductor BM1 connected to at least some of the source / drain patterns 150 described below. According to an embodiment, at least some of the source / drain patterns 150 may be electrically connected to the lower conductor BM1 via a lower contact pattern BCA.

[0080] According to an embodiment, the lower contact pattern BCA may extend along the second direction D2 between the gate structures GS. For example, the lower contact pattern BCA may be connected to the source / drain pattern 150 of the first device region RX1 and the source / drain pattern 150 of the second device region RX2.

[0081] According to an embodiment, the lower via BVA can be disposed between the lower contact pattern BCA and the lower conductor BM1. In other words, the lower contact pattern BCA can be electrically connected to the lower conductor BM1 through the lower via BVA. For example, the lower via BVA may include aluminum, copper, tungsten, molybdenum, cobalt, or combinations thereof.

[0082] According to an embodiment, the lower conductor BM1 may overlap with the first channel pattern CP1 and the second channel pattern CP2 on a third direction D3, and may extend along the first direction D1. However, this disclosure is not limited thereto, and the arrangement and / or extension direction of the lower conductor BM1 may be changed differently according to the embodiment.

[0083] According to an embodiment, the lower conductor BM1 may include a first lower conductor BM1(VDD) to which a first voltage (e.g., VDD) is applied and a second lower conductor BM1(VSS) to which a second voltage (e.g., VSS) lower than the first voltage is applied. According to an embodiment, the first voltage may be a positive voltage, and the second voltage may be a negative voltage or ground voltage. According to an embodiment, the first lower conductor BM1(VDD) may be located at a first device region RX1, and the second lower conductor BM1(VSS) may be located at a second device region RX2.

[0084] According to an embodiment, the lower conductor BM1 can be connected to a gate structure GS disposed at one edge of the first device region RX1 and / or the second device region RX2. Referring to Figures 1 and 2, the lower conductor BM1 can be connected to a gate structure GS disposed at one edge of the first device region RX1. The lower conductor BM1 can be connected to gate structures GS disposed at both edges (i.e., opposite edges) of the second device region RX2.

[0085] According to an embodiment, the lower gate pattern BCB can be disposed between the lower conductor BM1 and the gate structure GS. According to an embodiment, the first device region RX1 may include the lower gate pattern BCB, which connects the gate structure GS disposed at one edge of the first device region RX1 and a first lower conductor (e.g., a VDD conductor) to which a first voltage is applied. According to an embodiment, the second device region RX2 may include the lower gate pattern BCB, which connects the gate structure GS disposed at both edges of the second device region RX2 and a second lower conductor (e.g., a VSS conductor) to which a second voltage lower than the first voltage is applied.

[0086] Figure 3 is a cross-sectional view of the semiconductor device along line A-A' of each of Figures 1 and 2. Figure 4 is a cross-sectional view of the semiconductor device along line B-B' of each of Figures 1 and 2. Figure 5 is a cross-sectional view of the semiconductor device along line CC of each of Figures 1 and 2. Figure 6 is a cross-sectional view of the semiconductor device along line D-D' of each of Figures 1 and 2.

[0087] Referring to Figures 3 to 6, the semiconductor device according to the embodiment may include a substrate 110, a first channel pattern CP1 and a second channel pattern CP2, a gate structure GS, an insulating structure DW, a source / drain pattern 150, a gate separation structure CT, a device separation film SDB, an upper lead wire M1, and a lower lead wire BM1.

[0088] According to an embodiment, substrate 110 may include an insulating material. Substrate 110 may include oxides, nitrides, oxide-oxygen nitrides, or combinations thereof. For example, substrate 110 may include silicon nitride (SiN). xAlthough substrate 110 is shown as a single film in the accompanying drawings, this is only for ease of description and the present disclosure is not limited thereto.

[0089] The first and second surfaces of substrate 110 can be formed as planes parallel to a first direction D1 and a second direction D2 intersecting the first direction D1. For example, the first surface of substrate 110 can be the upper surface, and the second surface of substrate 110 can be the lower surface. The upper surface of substrate 110 can be a surface opposite to the lower surface of substrate 110 in a third direction D3. The third direction D3 can be a direction perpendicular to the first direction D1 and the second direction D2. The upper surface of substrate 110 can be referred to as the front side of substrate 110, and the lower surface of substrate 110 can be referred to as the back side of substrate 110. In some embodiments, the logic circuitry of the cell region can be implemented above or on the upper surface of substrate 110. In some embodiments, the lower wiring structure can be disposed above or on the lower surface of substrate 110.

[0090] According to an embodiment, the substrate 110 may include a first device region RX1 and a second device region RX2. The first device region RX1 and the second device region RX2 may be defined by a first channel pattern CP1 and a second channel pattern CP2 and a source / drain pattern 150 disposed above or on the substrate 110. In other words, the first channel pattern CP1 and the source / drain pattern 150, doped with a first impurity (e.g., a P-type impurity), may be disposed at the first device region RX1, and the second channel pattern CP2 and the source / drain pattern 150, doped with a second impurity (e.g., an N-type impurity), may be disposed at the second device region RX2. As described above, in this embodiment, the first device region RX1 may be a PMOS transistor region, and the second device region RX2 may be an NMOS transistor region.

[0091] According to an embodiment, a first channel pattern CP1 may be disposed at a first device region RX1. According to an embodiment, the first channel pattern CP1 may be configured to be spaced apart in a first direction D1 above the upper surface of the substrate 110. According to an embodiment, a plurality of sub-channel patterns of the first channel pattern CP1 may be configured to be spaced apart from each other in a third direction D3. For example, each of the plurality of sub-channel patterns of the first channel pattern CP1 may have a sheet shape. Each sub-channel pattern of the first channel pattern CP1 may be a nanosheet having a thickness of several nanometers along the third direction D3.

[0092] According to an embodiment, the first channel pattern CP1 can provide a path for current to flow between the source / drain patterns 150 described below. For example, the first channel pattern CP1 can be disposed between the source / drain patterns 150 to connect two adjacent source / drain patterns 150 to each other.

[0093] According to an embodiment, the first channel pattern CP1 can penetrate a portion of the gate structure GS in a direction intersecting the direction of the gate structure GS (e.g., a first direction D1). Although Figures 3 to 6 show that the three sub-channel patterns of the first channel pattern CP1 are spaced apart from each other in a third direction D3, this disclosure is not limited thereto, and the number of stacked sub-channel patterns of the first channel pattern CP1 can be varied.

[0094] According to an embodiment, a second channel pattern CP2 may be disposed at the second device region RX2. According to an embodiment, the second channel pattern CP2 may be configured to be spaced apart in a first direction D1 above the upper surface of the substrate 110. According to an embodiment, a plurality of sub-channel patterns of the second channel pattern CP2 may be configured to be spaced apart from each other in a third direction D3. For example, each of the plurality of sub-channel patterns of the second channel pattern CP2 may have a sheet shape. Each sub-channel pattern of the second channel pattern CP2 may be a nanosheet having a thickness of several nanometers along the third direction D3.

[0095] According to an embodiment, the second channel pattern CP2 can provide a path for current to flow between the source / drain patterns 150 described below. For example, the second channel pattern CP2 can be disposed between the source / drain patterns 150 to connect two adjacent source / drain patterns 150 to each other.

[0096] According to an embodiment, the second channel pattern CP2 can penetrate a portion of the gate structure GS in a direction intersecting the direction in which the gate structure GS extends (e.g., a first direction D1). Although Figures 3 to 6 show that the three sub-channel patterns of the second channel pattern CP2 are spaced apart from each other in a third direction D3, this disclosure is not limited thereto, and the number of stacked sub-channel patterns of the second channel pattern CP2 can be varied.

[0097] According to an embodiment, each of the first channel pattern CP1 and the second channel pattern CP2 may include a semiconductor material. For example, each of the first channel pattern CP1 and the second channel pattern CP2 may include a group IV semiconductor (such as Si and Ge), a group III-V compound semiconductor, or a group II-VI compound semiconductor.

[0098] According to an embodiment, a gate structure GS can be disposed on a substrate 110. According to an embodiment, the gate structure GS can extend on the substrate 110 in a second direction D2. The gate structures GS can be spaced apart from each other in a first direction D1. The gate structure GS may include a plurality of sub-gate structures S_GS and a main gate structure M_GS. The sub-gate structures S_GS can be disposed on the substrate 110, and the main gate structure M_GS can be disposed above the sub-gate structures S_GS.

[0099] Each of the sub-gate structures S_GS can be formed from several layers. For example, each of the sub-gate structures S_GS may include a sub-gate electrode 120S and a sub-gate insulating film 130S. In the first device region RX1, the sub-gate structures S_GS and multiple sub-channel patterns of the first channel pattern CP1 can be alternately stacked on the third direction D3. In the second device region RX2, the sub-gate structures S_GS and multiple sub-channel patterns of the second channel pattern CP2 can be alternately stacked on the third direction D3.

[0100] In Figures 3 through 6, the three sub-gate structures S_GS are configured to be spaced apart from each other on the third direction D3, but the number of sub-gate structures S_GS that are spaced apart is not limited to this. For example, the gate structure GS may include four sub-gate structures S_GS.

[0101] Referring to Figures 3 and 4, the sub-gate electrode 120S may enclose at least some of the multiple sub-channel patterns of the first channel pattern CP1 and / or the second channel pattern CP2. For example, in the first device region RX1, the sub-gate electrode 120S may enclose at least some of the multiple sub-channel patterns of the first channel pattern CP1. For example, the sub-gate electrode 120S and the insulating structure DW described later may enclose multiple sub-channel patterns of the first channel pattern CP1. Furthermore, for example, in the second device region RX2, the sub-gate electrode 120S may enclose at least some of the multiple sub-channel patterns of the second channel pattern CP2. For example, the sub-gate electrode 120S and the insulating structure DW described later may enclose multiple sub-channel patterns of the second channel pattern CP2.

[0102] The sub-gate electrode 120S may include at least one of the following: metal, metal alloy, conductive metal nitride, metal silicide, doped semiconductor material, conductive metal oxide, and conductive metal oxide nitride. For example, the sub-gate electrode 120S may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), and tungsten (W). The present disclosure includes at least one of the following: aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof, but is not limited thereto. Conductive metal oxides and conductive metal nitrides may include the oxidized forms of the above-mentioned materials, but are not limited thereto.

[0103] The sub-gate insulating film 130S may extend along the upper surface of the substrate 110. The sub-gate insulating film 130S may be disposed along the outer periphery of a plurality of sub-gate electrodes 120S. The sub-gate insulating film 130S may be in direct contact with the upper surface of the substrate 110 and a plurality of sub-channel patterns of each of the first channel pattern CP1 and the second channel pattern CP2. The sub-gate insulating film 130S may be interposed between the plurality of sub-channel patterns of each of the first channel pattern CP1 and the second channel pattern CP2 and the plurality of sub-gate electrodes 120S. The sub-gate insulating film 130S may comprise various insulating materials. Although not shown in Figures 3 to 6, the semiconductor device according to the embodiment may further include an internal gate spacer disposed between the sub-gate insulating film 130S and the source / drain pattern 150 described below.

[0104] In this embodiment, the sub-gate insulating film 130S is shown as a single film in the drawings, but this disclosure is not limited thereto. For example, the sub-gate insulating film 130S may be formed from multiple films comprising silicon oxide (SiO2) and a high-dielectric-constant material. In this case, the high-dielectric-constant material may comprise a material having a dielectric constant greater than that of silicon oxide (SiO2). For example, the high-dielectric-constant material may comprise hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO).

[0105] According to an embodiment, the main gate structure M_GS can be disposed above the sub-gate structure S_GS and multiple sub-channel patterns of the first channel pattern CP1 and the second channel pattern CP2, or on the sub-gate structure S_GS and multiple sub-channel patterns of the first channel pattern CP1 and the second channel pattern CP2. The main gate structure M_GS can be disposed on the upper surface of the uppermost sub-channel pattern among the multiple sub-channel patterns of the first channel pattern CP1 and the second channel pattern CP2.

[0106] Referring to Figures 3 and 4, at least a portion of the gate electrode 120 may be disposed on a structure in which the sub-gate electrode 120S and a plurality of sub-channel patterns of the first channel pattern CP1 and the second channel pattern CP2 are alternately stacked. Another portion of the gate electrode 120 may be formed to cover a side surface of the structure in which the sub-gate electrode 120S and a plurality of sub-channel patterns of the first channel pattern CP1 and the second channel pattern CP2 are alternately stacked. According to an embodiment, a gate insulating film 130 may be interposed between the gate electrode 120 and the plurality of sub-channel patterns of the first channel pattern CP1 and the second channel pattern CP2. In this case, three surfaces of each of the plurality of sub-channel patterns of the first channel pattern CP1 and the second channel pattern CP2 may be surrounded by the gate electrode 120, and one surface of each of the plurality of sub-channel patterns of the first channel pattern CP1 and the second channel pattern CP2 may be surrounded by the insulating structure DW, which will be described later.

[0107] According to an embodiment, the main gate structure M_GS may include a main gate electrode 120M and a main gate insulating film 130M.

[0108] According to an embodiment, the main gate electrode 120M can be disposed above or on the sub-gate structure S_GS and the multiple sub-channel patterns of the first channel pattern CP1 and the second channel pattern CP2. The main gate electrode 120M can include the same material as the sub-gate electrode 120S. For example, the main gate electrode 120M can include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

[0109] According to an embodiment, the main gate insulating film 130M may extend along the side and bottom surfaces of the main gate electrode 120M. The main gate insulating film 130M may extend along the side surface of the gate spacer 140 described below. The main gate insulating film 130M may include various insulating materials.

[0110] In this embodiment, the main gate insulating film 130M is shown as a single film in the drawings, but this disclosure is not limited thereto. For example, the main gate insulating film 130M may be formed from multiple films comprising silicon oxide (SiO2) and a high dielectric constant material. In this case, the high dielectric constant material may include a material having a dielectric constant greater than that of silicon oxide (SiO2). For example, the high dielectric constant material may include hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO).

[0111] According to an embodiment, the insulating structure DW can be disposed on the substrate 110 between the first device region RX1 and the second device region RX2. According to an embodiment, the insulating structure DW can extend in a first direction D1.

[0112] According to an embodiment, the upper surface of the insulating structure DW can be disposed at a level higher than the level of the upper surfaces of the first channel pattern CP1 and the second channel pattern CP2 disposed at the uppermost portion. In other words, the upper surface of the insulating structure DW can be disposed further away from the upper surface of the substrate 110 than the upper surfaces of the uppermost first channel pattern CP1 and the second channel pattern CP2. According to an embodiment, the upper surface of the insulating structure DW can be disposed at a level higher than the level of the upper surface of the gate structure GS. In other words, the upper surface of the insulating structure DW can be disposed further away from the upper surface of the substrate 110 than the upper surface of the uppermost gate structure GS.

[0113] As shown in Figure 3, the insulating structure DW can be disposed between the side surface of the first channel pattern CP1 and the side surface of the second channel pattern CP2. According to an embodiment, the insulating structure DW can contact the first channel pattern CP1 and the second channel pattern CP2 in the second direction D2. In other words, the insulating structure DW can be not spaced apart from the first channel pattern CP1 and the second channel pattern CP2 in the second direction D2. For example, one side of the insulating structure DW can contact the first channel pattern CP1, and the other side of the insulating structure DW can contact the second channel pattern CP2. However, unlike the illustration in the figures, the gate insulating film 130 can be interposed between the insulating structure DW and the first channel pattern CP1 and the second channel pattern CP2.

[0114] Additionally, as shown in Figure 3, the insulating structure DW can contact the side surface of the gate structure GS disposed between first channel patterns CP1 adjacent to each other in the third direction D3. The side surface of the insulating structure DW can also contact the side surface of a stacked structure in which the gate structures GS and the first channel patterns CP1 are alternately stacked. In other words, the side surface of the insulating structure DW can be unspaced from the side surface of a stacked structure in the second direction D2 where the gate structures GS and the first channel patterns CP1 are alternately stacked.

[0115] According to an embodiment, the insulating structure DW can contact the side surface of the gate structure GS disposed between multiple sub-channel patterns of the second channel pattern CP2 that are adjacent to each other on the third direction D3. The side surface of the insulating structure DW can contact the side surface of a stacked structure in which the gate structure GS and the multiple sub-channel patterns of the second channel pattern CP2 are alternately stacked. In other words, the side surface of the insulating structure DW can be unspaced from the side surface of the stacked structure on the second direction D2. In the stacked structure, the gate structure GS and the multiple sub-channel patterns of the second channel pattern CP2 are alternately stacked on the third direction D3.

[0116] As shown in Figure 4, the insulating structure DW can be disposed between the side surface of the second channel pattern CP2 and the device separation film SDB described below. According to an embodiment, the insulating structure DW can contact the second channel pattern CP2 in the second direction D2. According to an embodiment, the insulating structure DW can contact the device separation film SDB in the second direction D2. For example, one side of the insulating structure DW can contact the second channel pattern CP2, and the other side of the insulating structure DW can contact the device separation film SDB.

[0117] The insulating structure DW can function as a gate separation structure that insulates or isolates the gate structures GS from each other. According to an embodiment, the source / drain pattern 150 can be disposed at each of the two sides of the insulating structure DW along the second direction D2.

[0118] The insulating structure DW may include a low dielectric constant material. For example, the insulating structure DW may include at least one of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), and low dielectric constant materials, but this disclosure is not limited thereto.

[0119] As described above, the insulating structure DW of the semiconductor device according to this disclosure can effectively perform electrical isolation between the first device region RX1 and the second device region RX2 by including an insulating material.

[0120] As described above, the insulating structure DW of the semiconductor device according to this disclosure can improve the integration of the device by contacting the first channel pattern CP1 and the second channel pattern CP2.

[0121] The semiconductor device according to the embodiment may further include a gate spacer 140 and a capping layer 145.

[0122] According to an embodiment, the gate spacer 140 may be disposed on both sides of the main gate electrode 120M. Although the gate spacer 140 is shown as a single film in the drawings, this is only for ease of description, and the present disclosure is not limited thereto.

[0123] For example, the gate spacer 140 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonate (SiOC), and combinations thereof. Although the gate spacer 140 is shown as a single film in the figures, this is only for ease of description, and the present disclosure is not limited thereto.

[0124] According to an embodiment, a capping layer 145 may be disposed on the main gate structure M_GS and the gate spacer 140. The upper surface of the capping layer 145 may be disposed on the same plane as the upper surface of the first interlayer insulating layer 160. Unlike the illustration in the figures, the capping layer 145 may be disposed between the gate spacers 140. Alternatively, unlike the illustration in the figures, the capping layer 145 may be omitted.

[0125] For example, capping layer 145 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and combinations thereof. Capping layer 145 may include a material having etch selectivity relative to the first interlayer insulating layer 160.

[0126] Referring to Figures 5 and 6, the first device region RX1 and the second device region RX2 may include source / drain patterns 150 disposed on the substrate 110. According to an embodiment, the source / drain patterns 150 may be configured to be spaced apart on the substrate 110 along a first direction D1. Although not clearly shown in the figures, the source / drain patterns 150 may also be disposed in a second direction D2.

[0127] Referring to FIG5, in the first device region RX1, the first channel pattern CP1 and the gate structure GS can be disposed between the source / drain pattern 150. In other words, in the first device region RX1, a plurality of source / drain patterns 150 and a plurality of first channel patterns CP1 can be alternately disposed along the first direction D1.

[0128] According to an embodiment, in the first device region RX1, source / drain patterns 150 may be disposed on both sides of a plurality of sub-channel patterns and / or sub-gate structures S_GS of the first channel pattern CP1. For example, two source / drain patterns 150 may be spaced apart in a direction intersecting the direction of the extension of the gate structure GS (e.g., a first direction D1), and the first channel pattern CP1 and / or the sub-gate structure S_GS may be interposed between these two source / drain patterns 150. The upper surface of the source / drain pattern 150 may be disposed at a level substantially the same as the upper surface of the first channel pattern CP1 disposed at the uppermost portion, but this disclosure is not limited thereto. The source / drain pattern 150 may be in direct contact with the first channel pattern CP1 and the sub-gate structure S_GS.

[0129] Referring to Figure 6, in the second device region RX2, the second channel pattern CP2 and the gate structure GS can be disposed between the source / drain pattern 150. In other words, in the second device region RX2, multiple source / drain patterns 150 and multiple second channel patterns CP2 can be alternately disposed along the first direction D1.

[0130] According to an embodiment, in the second device region RX2, source / drain patterns 150 can be disposed on both sides of a plurality of sub-channel patterns and / or sub-gate structures S_GS of the second channel pattern CP2. For example, two source / drain patterns 150 can be spaced apart in a direction intersecting the direction of the extension of the gate structure GS (e.g., a first direction D1), and the second channel pattern CP2 and / or the sub-gate structure S_GS is interposed between these two source / drain patterns 150. The upper surface of the source / drain pattern 150 can be disposed at a level substantially the same as the upper surface of the second channel pattern CP2 disposed at the uppermost portion, but this disclosure is not limited thereto. The source / drain pattern 150 can be in direct contact with the second channel pattern CP2 and the sub-gate structure S_GS.

[0131] According to an embodiment, the side surface of the source / drain pattern 150 may have an uneven embossed shape. In other words, the side surface of the source / drain pattern 150 may have a wave-like profile. For example, the side surface of the source / drain pattern 150 adjacent to the sub-gate structure S_GS may have a shape that is generally convex toward the sub-gate structure S_GS, and the side surface of the source / drain pattern 150 adjacent to the first channel pattern CP1 may have a shape that is generally concave toward the first channel pattern CP1.

[0132] According to an embodiment, the source / drain pattern 150 may include an epitaxial region of semiconductor material. For example, the source / drain pattern 150 may include a semiconductor element (e.g., Si or SiGe). The source / drain pattern 150 can be used as the source / drain of a transistor using a first channel pattern CP1 and a second channel pattern CP2 as the channel region.

[0133] According to an embodiment, the source / drain pattern 150 may include a first source / drain layer 150a and a second source / drain layer 150b. The first source / drain layer 150a may have a shape surrounding the side surface and the bottom surface of the second source / drain layer 150b.

[0134] The first channel pattern CP1 and the second channel pattern CP2 can be in contact with the first source / drain layer 150a, but can be without contact with the second source / drain layer 150b. Therefore, the first source / drain layer 150a can be disposed between the first channel pattern CP1 and the second channel pattern CP2 and the second source / drain layer 150b.

[0135] According to an embodiment, the lower surface of the first source / drain layer 150a may be disposed at a level similar to or the same as the lower surface of the sub-gate structure S_GS disposed at the lowest part of the sub-gate structure S_GS.

[0136] According to an embodiment, the source / drain pattern 150 may include a P-type impurity (or a P-type dopant) or an N-type impurity (or an N-type dopant), or may be doped with a P-type impurity (or a P-type dopant) or an N-type impurity (or an N-type dopant).

[0137] According to an embodiment, the source / drain pattern 150 disposed at the first device region RX1 may include P-type impurities. For example, the source / drain pattern 150 disposed at the first device region RX1 may include B, V, In, Ga, Al, or combinations thereof.

[0138] According to an embodiment, the source / drain pattern 150 disposed at the second device region RX2 may include N-type impurities. For example, the source / drain pattern 150 disposed at the second device region RX2 may include P, Sb, As, or combinations thereof.

[0139] The semiconductor device according to an embodiment may further include a gate-separated structure CT that penetrates the gate electrode 120. According to an embodiment, the gate-separated structure CT may penetrate the gate electrode 120 on a third-direction D3. As shown in Figures 3 and 4, the lower surface of the gate-separated structure CT may be disposed at a level similar to the level of the lower surface of the insulating structure DW. However, this disclosure is not limited thereto, and the level of the lower surface of the gate-separated structure CT may be varied. According to an embodiment, the upper surface of the gate-separated structure CT may be disposed at a level substantially the same as the level of the upper surface of the insulating structure DW. However, this disclosure is not limited thereto, and the level of the upper surface of the gate-separated structure CT may be varied.

[0140] According to an embodiment, the gate separation structure CT can be cut and separated so that the gate electrodes 120 extending in the second direction D2 are spaced apart from each other relative to the gate separation structure CT. For example, the gate separation structure CT can be made of silicon nitride.

[0141] According to an embodiment, the gate-separated structure CT can be disposed adjacent to one side of the first device region RX1 and / or one side of the second device region RX2. For example, the gate-separated structure CT can be disposed adjacent to one side (e.g., the upper side) of the first device region RX1. For example, the gate-separated structure CT can face the insulating structure DW, and the first channel pattern CP1 is interposed between the gate-separated structure CT and the insulating structure DW.

[0142] For example, the gate-separated structure CT can be disposed adjacent to one side (e.g., the lower side) of the second device region RX2. For example, the gate-separated structure CT can face the insulating structure DW, and the second channel pattern CP2 is interposed between the gate-separated structure CT and the insulating structure DW.

[0143] As shown in FIG5, according to an embodiment, the device separation membrane SDB may be disposed on one side of the first device region RX1. According to an embodiment, the device separation membrane SDB may not be disposed on the other side of the first device region RX1. Although FIG5 shows that the device separation membrane SDB is disposed on the right side of the first device region RX1 and not on the left side of the first device region RX1, the present disclosure is not limited thereto, and the device separation membrane SDB may be disposed on the left side of the first device region RX1 and may not be disposed on the right side of the first device region RX1.

[0144] According to an embodiment, the device separation film SDB can penetrate the gate structure GS disposed at one edge of the first device region RX1. According to an embodiment, the upper surface of the device separation film SDB can be disposed at a level substantially the same as the upper surface of the capping layer 145. According to an embodiment, the device separation film SDB can physically separate the first device region RX1 from the region of another cell adjacent to the first device region RX1.

[0145] For example, the device separation membrane SDB may include at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and a low dielectric constant material.

[0146] The semiconductor device according to the embodiment may further include a first interlayer insulating layer 160 and a second interlayer insulating layer 170. The first interlayer insulating layer 160 may be disposed on the side surface of the gate spacer 140, the side surface of the capping layer 145, and the upper surface of the source / drain pattern 150. The upper surface of the first interlayer insulating layer 160 may be disposed at a level substantially the same as the upper surface of the device separation film SDB.

[0147] According to an embodiment, the second interlayer insulating layer 170 of the cover layer 145 may be disposed on the first interlayer insulating layer 160 and the device separation film SDB. The boundary between the second interlayer insulating layer 170 and the first interlayer insulating layer 160 and / or the device separation film SDB may not be identified.

[0148] For example, the first interlayer insulating layer 160 may include at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and a low dielectric constant material. For example, the low dielectric constant material may include tetraethyl fluorinated orthosilicate (FTEOS), silsesquioxane (HSQ), fluorinated silicate glass (FSG), polyimide nanofoams such as polypropylene oxide, carbon-doped silicon oxide (CDO), organosilicon glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica dry gel, mesoporous silica, or combinations thereof, but this disclosure is not limited thereto.

[0149] According to an embodiment, the second interlayer insulating layer 170 may comprise the same material as the first interlayer insulating layer 160. For example, the second interlayer insulating layer 170 may comprise at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and a low dielectric constant material.

[0150] The semiconductor device according to the embodiment may further include a contact pattern CA disposed on at least one of the source / drain patterns 150, an upper insulating layer 180 disposed on the second interlayer insulating layer 170, and an upper conductor M1.

[0151] According to an embodiment, the contact pattern CA can penetrate the first interlayer insulation layer 160 to connect to at least one of the source / drain patterns 150. According to an embodiment, the contact pattern CA can be disposed adjacent to the main gate electrode 120M in the first direction D1. According to an embodiment, the contact pattern CA can electrically connect the upper conductor M1 to at least one of the source / drain patterns 150 via a contact via CAV. However, this disclosure is not limited thereto, and in some embodiments, the contact via CAV may be omitted.

[0152] For example, the contact pattern CA may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. The metal may include at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and platinum (Pt). The conductive metal nitride may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0153] According to an embodiment, the upper insulating layer 180, the upper conductor M1, and the upper via (not shown) may be disposed above or on the second interlayer insulating layer 170. The upper conductor M1 and the upper via may include metal (e.g., copper). The upper insulating layer 180 may be disposed between the upper conductor M1 and the upper via to insulate the upper conductor M1 and the upper via. The upper insulating layer 180 may cover the second interlayer insulating layer 170. The upper conductor M1 and the upper via may be disposed within the upper insulating layer 180.

[0154] According to an embodiment, the upper insulating layer 180 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x At least one of silicon oxynitride (SiON) and low-k dielectric film.

[0155] According to an embodiment, the upper conductor M1 may be electrically connected to at least one of the main gate electrode 120M and the source / drain pattern 150. According to an embodiment, an externally supplied electrical signal or power supply voltage may be provided to the source / drain pattern 150 through the upper conductor M1 and the contact pattern CA connected to the upper conductor M1.

[0156] The semiconductor device according to the embodiment may further include a lower contact pattern BCA disposed below at least one of the source / drain patterns 150 and a lower conductor BM1 disposed on the lower surface of the substrate 110.

[0157] According to an embodiment, the lower contact pattern BCA can be electrically connected to at least one of the source / drain patterns 150. According to an embodiment, the lower contact pattern BCA can electrically connect the lower conductor BM1 to at least one of the source / drain patterns 150. According to an embodiment, the lower contact pattern BCA can electrically connect the lower conductor BM1 to at least one of the source / drain patterns 150 via the lower via BVA.

[0158] For example, the lower contact pattern BCA may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. The metal may include at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and platinum (Pt). The conductive metal nitride may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0159] According to an embodiment, the lower conductor BM1 and the lower via BVA may be disposed within a substrate 110 formed of an insulating material. The lower conductor BM1 and the lower via BVA may comprise metal (e.g., copper). The substrate 110 comprising the insulating material may be disposed between the lower conductor BM1 and the lower via BVA to insulate the lower conductor BM1 and the lower via BVA.

[0160] According to an embodiment, the lower conductor BM1 may be electrically connected to at least one of the gate electrode 120 and the source / drain pattern 150. According to an embodiment, an externally supplied electrical signal or power supply voltage may be provided to the source / drain pattern 150 through the lower conductor BM1 and the lower contact pattern BCA connected to the lower conductor BM1. According to an embodiment, an externally supplied electrical signal or power supply voltage may be provided to the gate electrode 120 through the lower conductor BM1 and the lower gate pattern BCB connected to the lower conductor BM1.

[0161] According to an embodiment, voltages of the same level can be provided to the source / drain pattern 150 and the sub-gate electrode 120S respectively through the lower contact pattern BCA and the lower gate pattern BCB. Therefore, no potential difference exists between the gate electrode 120 and the source / drain pattern 150, thereby blocking the current flowing between the source and drain. Thus, the source and drain can be electrically isolated. In other words, the lower gate pattern BCB can be used as a boundary to electrically separate the first device region RX1 and / or the second device region RX2 from another cell adjacent to the first device region RX1 and / or the second device region RX2.

[0162] According to an embodiment, the lower conductor BM1 can be connected to a gate structure GS disposed at one edge of the first device region RX1 and / or the second device region RX2. Referring to Figures 3 and 5, in the first device region RX1, the lower conductor BM1 can be connected to a gate structure GS disposed at one edge of the first device region RX1. According to an embodiment, a first lower gate pattern BCB1 disposed at one edge of the first device region RX1 can be used as a boundary to electrically separate the first device region RX1 from the region of another cell adjacent to the first device region RX1. Therefore, the first device region RX1 can be defined by providing a device separation film SDB and including a first lower gate pattern BCB1, which is used to physically separate the first device region RX1 from the region of another cell adjacent to the first device region RX1 at one edge of the first device region RX1, and the first lower gate pattern BCB1 is used to electrically separate the first device region RX1 from the region of another cell adjacent to the first device region RX1 at the other edge of the first device region RX1.

[0163] Referring to Figures 4 and 6, in the second device region RX2, the lower conductor BM1 can be connected to the gate structure GS disposed at the two edges of the second device region RX2. According to an embodiment, a second lower gate pattern BCB2 can be disposed between the lower conductor BM1 and the gate structure GS. According to an embodiment, the second lower gate pattern BCB2 disposed at the two edges of the second device region RX2 can be used as a boundary to electrically separate the second device region RX2 from the region of another cell adjacent to the second device region RX2. Therefore, the second device region RX2 can be defined by including the second lower gate pattern BCB2, which is used to electrically separate the second device region RX2 from the region of another cell adjacent to the second device region RX2 at its two edges.

[0164] Referring to Figures 3 and 4, in the first device region RX1, a gate structure GS disposed at one edge of the first device region RX1 can be connected to a first lower conductor BM1 (VDD) to which a first voltage is applied. For example, in the first device region RX1, the gate structure GS disposed at one edge of the first device region RX1 can be connected to the first lower conductor BM1 (VDD) to which a first voltage is applied via a first lower gate pattern BCB1.

[0165] Referring to Figures 3 and 4, in the second device region RX2, the gate structure GS disposed at the two edges of the second device region RX2 can be connected to the second lower conductor BM1 (VSS) to which a second voltage is applied, which is lower than the first voltage. For example, in the second device region RX2, the gate structure GS disposed at the two edges of the second device region RX2 can be connected to the second lower conductor BM1 (VSS) to which a second voltage is applied through the second lower gate pattern BCB2.

[0166] As described above, the semiconductor device according to this disclosure can effectively prevent current leakage by mixing and using diffusion interruption in at least one device region, based on the characteristics of a first device region RX1 and a second device region RX2 that include or are doped with different types of dopants.

[0167] Each of Figures 7 and 8 is a layout diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 9 is a cross-sectional view of the semiconductor device along line E-E' of each of Figures 7 and 8. Figure 10 is a cross-sectional view of the semiconductor device along line F-F' of each of Figures 7 and 8.

[0168] The semiconductor devices shown in Figures 7 to 10 may include components similar to or the same as those in the semiconductor devices described with reference to Figures 1 to 6. However, unlike the semiconductor devices shown in Figures 1 to 6, the semiconductor device of this embodiment relates to a structure in which a lower conductor BM1 connected to a gate structure GS disposed at both edges of a first device region RX1 is disposed at the first device region RX1 included in a unit cell of the semiconductor device, and both a lower conductor BM1 connected to a gate structure GS disposed at one edge of a second device region RX2 and a device separation film SDB penetrating the gate structure GS disposed at the other edge of the second device region RX2 are provided. Content in this embodiment that is repeated with reference to Figures 1 to 6 will be simplified or omitted, and the differences between this embodiment and the description with reference to Figures 1 to 6 will be primarily described.

[0169] Referring to Figures 7 to 10, a unit cell of a semiconductor device according to an embodiment may include a first device region RX1 in which a first channel pattern CP1 is disposed, a second device region RX2 in which a second channel pattern CP2 is disposed, and an insulating structure DW separating the first device region RX1 and the second device region RX2. According to an embodiment, the insulating structure DW may extend in a first direction D1 between the first device region RX1 and the second device region RX2.

[0170] According to an embodiment, the insulating structure DW may be in contact with the first channel pattern CP1 and the second channel pattern CP2 in the second direction D2. In other words, the insulating structure DW may not be spaced apart from the first channel pattern CP1 and the second channel pattern CP2 in the second direction D2.

[0171] As described above, the insulating structure DW of the semiconductor device according to this disclosure can improve the integration of the device by contacting the first channel pattern CP1 and the second channel pattern CP2.

[0172] According to an embodiment, a unit cell of a semiconductor device may include a device separation film SDB that physically separates adjacent cells and / or a lower gate pattern BCB that electrically separates adjacent cells.

[0173] Referring to Figures 7 and 8, in the first device region RX1, the lower conductor BM1 can be connected to the gate structure GS disposed at the two edges of the first device region RX1. According to an embodiment, the first lower gate pattern BCB1 disposed at the two edges of the first device region RX1 can be used as a boundary to electrically separate the first device region RX1 from the region of another cell adjacent to the first device region RX1.

[0174] Referring to FIG9, the gate structure GS included in the first device region RX1 can be connected to the first lower conductor BM1 (VDD) to which a first voltage is applied. For example, the gate structure GS of the first device region RX1 can be connected to the first lower conductor BM1 (VDD) to which a first voltage is applied via a first lower gate pattern BCB1. The first voltage can be a positive voltage.

[0175] According to an embodiment, the device separation membrane SDB may be disposed on one side of the second device region RX2. According to an embodiment, the device separation membrane SDB may not be disposed on the other side of the second device region RX2. Although Figures 7, 8, and 10 show the device separation membrane SDB disposed on the right side of the second device region RX2 and not disposed on the left side of the second device region RX2, this disclosure is not limited thereto, and the device separation membrane SDB may be disposed on the left side of the second device region RX2 and may not be disposed on the right side of the second device region RX2.

[0176] According to an embodiment, the device separation film SDB can penetrate the gate structure GS disposed at one edge of the second device region RX2. According to an embodiment, the device separation film SDB can physically separate the second device region RX2 from the region of another cell adjacent to the second device region RX2.

[0177] According to an embodiment, in the second device region RX2, the lower conductor BM1 can be connected to the gate structure GS disposed at another edge of the second device region RX2. According to an embodiment, the second lower gate pattern BCB2 disposed at the other edge of the second device region RX2 can be used as a boundary to electrically separate the second device region RX2 from the region of another cell adjacent to the second device region RX2. In other words, one side of the second device region RX2 can be physically terminated by the device separation film SDB as a boundary, and the other side of the second device region RX2 can be electrically terminated by the second lower gate pattern BCB2 as a boundary.

[0178] Although not clearly shown in the accompanying drawings, the gate structure GS located at another edge of the second device region RX2 can be connected to the second lower conductor BM1 (VSS) to which the second voltage is applied. For example, the gate structure GS of the second device region RX2 can be connected to the second lower conductor BM1 (VSS) to which the second voltage is applied via the second lower gate pattern BCB2. The second voltage can be a negative voltage or ground voltage.

[0179] As described above, the semiconductor device of this embodiment may include a first lower gate pattern BCB1 connected to a lower conductor BM1 on both sides of a first device region RX1, a device separation film SDB disposed on one side of a second device region RX2, and a second lower gate pattern BCB2 disposed on the other side of the second device region RX2, thereby effectively preventing current leakage according to the characteristics of the device.

[0180] Each of Figures 11 and 12 is a layout diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 13 is a cross-sectional view of the semiconductor device along line G-G' of each of Figures 11 and 12. Figure 14 is a cross-sectional view of the semiconductor device along line H-H' of each of Figures 11 and 12.

[0181] The semiconductor devices shown in Figures 11 to 14 may include components similar to or the same as those in the semiconductor devices described with reference to Figures 1 to 6. However, unlike the semiconductor devices shown in Figures 1 to 6, the semiconductor device of this embodiment relates to a structure in which a device separation film SDB penetrating the gate structure GS disposed at both edges of the first device region RX1 is disposed in the first device region RX1 included in the unit cell of the semiconductor device, and both a lower conductor BM1 connected to the gate structure GS disposed at one edge of the second device region RX2 and the device separation film SDB penetrating the gate structure GS disposed at the other edge of the second device region RX2 are provided. Content in this embodiment that is repeated with reference to Figures 1 to 6 will be simplified or omitted, and the differences between the content of this embodiment and the content described with reference to Figures 1 to 6 will be mainly described.

[0182] Referring to Figures 11 to 14, a unit cell of a semiconductor device according to an embodiment may include a first device region RX1 in which a first channel pattern CP1 is disposed, a second device region RX2 in which a second channel pattern CP2 is disposed, and an insulating structure DW separating the first device region RX1 and the second device region RX2. According to an embodiment, the insulating structure DW may extend in a first direction D1 between the first device region RX1 and the second device region RX2.

[0183] According to an embodiment, the insulating structure DW may be in contact with the first channel pattern CP1 and the second channel pattern CP2 in the second direction D2. In other words, the insulating structure DW may not be spaced apart from the first channel pattern CP1 and the second channel pattern CP2 in the second direction D2.

[0184] According to an embodiment, a unit cell of a semiconductor device may include a device separation film SDB that physically separates adjacent cells and / or a lower gate pattern BCB that electrically separates adjacent cells.

[0185] Referring to Figures 11 and 12, the first device region RX1 may include a device separation film SDB that penetrates the gate structure GS disposed at both edges of the first device region RX1. According to an embodiment, the device separation film SDB disposed at the two edges of the first device region RX1 can be used as a boundary to physically separate the first device region RX1 from the region of another cell adjacent to the first device region RX1. In other words, the two sides of the first device region RX1 can be physically terminated by the device separation film SDB serving as a boundary.

[0186] According to an embodiment, the device separation membrane SDB may be disposed on one side of the second device region RX2. According to an embodiment, the device separation membrane SDB may not be disposed on the other side of the second device region RX2. Although Figures 11, 12, and 14 show the device separation membrane SDB disposed on the right side of the second device region RX2 and not disposed on the left side of the second device region RX2, this disclosure is not limited thereto, and the device separation membrane SDB may be disposed on the left side of the second device region RX2 and may not be disposed on the right side of the second device region RX2.

[0187] According to an embodiment, the device separation film SDB can penetrate the gate structure GS disposed at one edge of the second device region RX2. According to an embodiment, the device separation film SDB can physically separate the second device region RX2 from the region of another cell adjacent to the second device region RX2.

[0188] According to an embodiment, in the second device region RX2, the lower conductor BM1 can be connected to the gate structure GS disposed at another edge of the second device region RX2. According to an embodiment, the second lower gate pattern BCB2 disposed at the other edge of the second device region RX2 can be used as a boundary to electrically separate the second device region RX2 from the region of another cell adjacent to the second device region RX2. In other words, one side of the second device region RX2 can be physically terminated by the device separation film SDB as a boundary, and the other side of the second device region RX2 can be electrically terminated by the second lower gate pattern BCB2 as a boundary.

[0189] Although not clearly shown in the accompanying drawings, the gate structure GS located at another edge of the second device region RX2 can be connected to the second lower conductor BM1 (VSS) to which the second voltage is applied. For example, the gate structure GS of the second device region RX2 can be connected to the second lower conductor BM1 (VSS) to which the second voltage is applied via the second lower gate pattern BCB2. The second voltage can be a negative voltage or ground voltage.

[0190] As described above, the semiconductor device of this embodiment may include a device separation film SDB located on both sides of the first device region RX1, a device separation film SDB disposed on one side of the second device region RX2, and a second lower gate pattern BCB2 disposed on the other side of the second device region RX2, thereby effectively preventing current leakage according to the characteristics of the device.

[0191] Each of Figures 15 and 16 is a layout diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 17 is a cross-sectional view of the semiconductor device along line I-I' of each of Figures 15 and 16. Figure 18 is a cross-sectional view of the semiconductor device along line J-J' of each of Figures 15 and 16.

[0192] The semiconductor devices shown in Figures 15 to 18 may include components similar to or the same as those in the semiconductor devices described with reference to Figures 1 to 6. However, unlike the semiconductor devices shown in Figures 1 to 6, the semiconductor device of this embodiment relates to a structure in which a lower conductor BM1 of a gate structure GS connected to two edges disposed in each of the first device region RX1 and the second device region RX2 is disposed at each of the first device region RX1 and the second device region RX2 included in a unit cell of the semiconductor device. Content in this embodiment that is repeated with reference to Figures 1 to 6 will be simplified or omitted, and the differences between this embodiment and the description with reference to Figures 1 to 6 will be primarily described.

[0193] Referring to Figures 15 to 18, a unit cell of a semiconductor device according to an embodiment may include a first device region RX1 in which a first channel pattern CP1 is disposed, a second device region RX2 in which a second channel pattern CP2 is disposed, and an insulating structure DW separating the first device region RX1 and the second device region RX2. According to an embodiment, the insulating structure DW may extend in a first direction D1 between the first device region RX1 and the second device region RX2.

[0194] According to an embodiment, the insulating structure DW may be in contact with the first channel pattern CP1 and the second channel pattern CP2 in the second direction D2. In other words, the insulating structure DW may not be spaced apart from the first channel pattern CP1 and the second channel pattern CP2 in the second direction D2.

[0195] According to an embodiment, a unit cell of a semiconductor device may include a lower gate pattern BCB that electrically separates adjacent cells.

[0196] Referring to Figures 15 and 16, in the first device region RX1 and the second device region RX2, the lower conductor BM1 can be connected to the gate structure GS located at the two edges of each of the first device region RX1 and the second device region RX2.

[0197] According to an embodiment, the first lower gate pattern BCB1 disposed at the two edges of the first device region RX1 can be used as a boundary to electrically separate the first device region RX1 from the region of another cell adjacent to the first device region RX1.

[0198] According to an embodiment, the second lower gate pattern BCB2 disposed at the two edges of the second device region RX2 can be used as a boundary to electrically separate the second device region RX2 from the region of another cell adjacent to the second device region RX2.

[0199] Referring to FIG17, the gate structure GS disposed at the edge of the first device region RX1 can be connected to a first lower conductor BM1 (VDD) to which a first voltage is applied. For example, the gate structure GS of the first device region RX1 can be connected to the first lower conductor BM1 (VDD) to which a first voltage is applied via a first lower gate pattern BCB1. The first voltage can be a positive voltage. According to an embodiment, the gate structure GS disposed at the edge of the second device region RX2 can be connected to a second lower conductor BM1 (VSS) to which a second voltage is applied. For example, the gate structure GS of the second device region RX2 can be connected to the second lower conductor BM1 (VSS) to which a second voltage is applied via a second lower gate pattern BCB2. The second voltage can be a negative voltage or ground voltage.

[0200] As described above, the semiconductor device of this embodiment can prevent current leakage by including a lower gate pattern BCB located on both sides of each of the first device region RX1 and the second device region RX2.

[0201] As described above, the semiconductor device of this embodiment may include an insulating structure DW that contacts the first channel pattern CP1 and the second channel pattern CP2 between the first device region RX1 and the second device region RX2, so that the first device region RX1 and the second device region RX2 can be physically and / or electrically separated while improving the integration of the device.

[0202] Each of Figures 19 and 20 is a layout diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 21 is a cross-sectional view of the semiconductor device along line A-A' of each of Figures 19 and 20. Figure 22 is a cross-sectional view of the semiconductor device along line B-B' of each of Figures 19 and 20. Figure 23 is a cross-sectional view of the semiconductor device along line C-C' of each of Figures 19 and 20. Figure 24 is a cross-sectional view of the semiconductor device along line D-D' of each of Figures 19 and 20.

[0203] The semiconductor device shown in Figures 19 to 24 may include components similar to or the same as those in the semiconductor devices described with reference to Figures 1 to 6. However, unlike the semiconductor devices shown in Figures 1 to 6, the semiconductor device of this embodiment relates to a structure in which insulating structures DW face each other in the second direction D2 and a first channel pattern CP1 and a second channel pattern CP2 are interposed between the insulating structures DW. Furthermore, similar to the semiconductor devices shown in Figures 1 to 6, the semiconductor device of this embodiment relates to a structure in which a lower conductor BM1 connected to a gate structure GS disposed at one edge of the first device region RX1 and a device separation film SDB penetrating a gate structure GS disposed at the other edge of the first device region RX1 are both disposed in the first device region RX1, and a lower conductor connected to a gate structure GS disposed at both edges of the second device region RX2 is disposed in the second device region RX2. Content in this embodiment that is repeated with reference to Figures 1 to 6 will be simplified or omitted, and the differences between this embodiment and the description with reference to Figures 1 to 6 will be primarily described.

[0204] Referring to Figures 19 to 24, a unit cell of a semiconductor device according to an embodiment may include a first device region RX1 having a first channel pattern CP1, a second device region RX2 having a second channel pattern CP2, and an insulating structure DW facing each other in a second direction D2 with the first channel pattern CP1 and the second channel pattern CP2 interposed therebetween. According to an embodiment, a unit cell of the semiconductor device may further include a gate separation structure CT separating the first device region RX1 and the second device region RX2.

[0205] Referring to Figures 19 and 20, according to an embodiment, the gate electrode 120 extending in the second direction D2 can be separated from each other relative to the insulating structure DW. For example, the insulating structure DW can be made of silicon nitride.

[0206] According to an embodiment, two insulating structures DW can face each other in the second direction D2, and a first channel pattern CP1 and a second channel pattern CP2 are interposed between the two insulating structures DW. In other words, a first device region RX1 and a second device region RX2 can be disposed between the two insulating structures DW, and the boundaries of the unit (e.g., upper and lower sides) can be defined by the insulating structures DW.

[0207] According to an embodiment, the insulating structure DW may extend along a first direction D1 from one edge of the first device region RX1 and one edge of the second device region RX2. According to an embodiment, the insulating structure DW, the first device region RX1, the second device region RX2, and the insulating structure DW may be arranged along a second direction D2.

[0208] According to an embodiment, the insulating structure DW can be disposed at one edge of the first device region RX1 and one edge of the second device region RX2. According to an embodiment, the insulating structure DW can be disposed at one edge (e.g., the upper edge) of the first device region RX1. For example, the insulating structure DW can face the gate-separated structure CT, and the first channel pattern CP1 is interposed between the insulating structure DW and the gate-separated structure CT. According to an embodiment, the insulating structure DW can be disposed at one edge (e.g., the lower edge) of the second device region RX2. For example, the insulating structure DW can face the gate-separated structure CT, and the second channel pattern CP2 is interposed between the insulating structure DW and the gate-separated structure CT.

[0209] According to an embodiment, the insulating structure DW may be in contact with the first channel pattern CP1 and the second channel pattern CP2 in the second direction D2. In other words, the insulating structure DW may not be spaced apart from the first channel pattern CP1 and the second channel pattern CP2 in the second direction D2.

[0210] According to an embodiment, a unit cell of a semiconductor device may include a device separation film SDB that physically separates adjacent cells and / or a lower gate pattern BCB that electrically separates adjacent cells.

[0211] Referring to Figures 19 and 20, the device separation membrane SDB may be disposed on one side of the first device region RX1. According to an embodiment, the device separation membrane SDB may not be disposed on the other side of the first device region RX1. Although Figures 19, 20, and 23 show the device separation membrane SDB disposed on the right side of the first device region RX1 and not on the left side, this disclosure is not limited thereto, and the device separation membrane SDB may be disposed on the left side of the first device region RX1 and not on the right side.

[0212] According to an embodiment, the device separation film SDB can penetrate the gate structure GS disposed at one edge of the first device region RX1. According to an embodiment, the device separation film SDB can physically separate the first device region RX1 from the region of another cell adjacent to the first device region RX1.

[0213] According to an embodiment, in the first device region RX1, the lower conductor BM1 can be connected to the gate structure GS disposed at the other edge of the first device region RX1. According to an embodiment, the first lower gate pattern BCB1 disposed at the other edge of the first device region RX1 can be used as a boundary to electrically separate the first device region RX1 from the region of another cell adjacent to the first device region RX1. In other words, one side of the first device region RX1 can be physically terminated by the device separation film SDB serving as a boundary, and the other side of the first device region RX1 can be electrically separated from the first channel pattern CP1 by the first lower gate pattern BCB1 serving as a boundary.

[0214] Referring to FIG21, the gate structure GS disposed at another edge of the first device region RX1 can be connected to the first lower conductor BM1 (VDD) to which a first voltage is applied. For example, the gate structure GS of the first device region RX1 can be connected to the first lower conductor BM1 (VDD) to which a first voltage is applied via a first lower gate pattern BCB1. The first voltage can be a positive voltage.

[0215] According to an embodiment, in the second device region RX2, the lower conductor BM1 can be connected to the gate structure GS disposed at the two edges of the second device region RX2. According to an embodiment, the second lower gate pattern BCB2 disposed at the two edges of the second device region RX2 can be used as a boundary to electrically separate the second device region RX2 from the region of another cell adjacent to the second device region RX2.

[0216] Referring to Figures 21 and 22, the gate structure GS included in the second device region RX2 can be connected to a second lower conductor BM1 (VSS) to which a second voltage is applied. For example, the gate structure GS of the second device region RX2 can be connected to the second lower conductor BM1 (VSS) to which a second voltage is applied via a second lower gate pattern BCB2. The second voltage can be a negative voltage or ground voltage.

[0217] As described above, the semiconductor device of this embodiment may include a device separation film SDB disposed on one side of the first device region RX1, a first lower gate pattern BCB1 disposed on the other side of the first device region RX1, and a second lower gate pattern BCB2 connected to the lower conductor BM1 on both sides of the second device region RX2, thereby effectively preventing current leakage according to the characteristics of the device.

[0218] As described above, the semiconductor device of this embodiment can improve the integration of the device because the insulating structure DW disposed outside the first device region RX1 and the second device region RX2 is not spaced apart from the first channel pattern CP1 and the second channel pattern CP2.

[0219] Each of Figures 25 and 26 is a layout diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 27 is a cross-sectional view of the semiconductor device along line E-E' of each of Figures 25 and 26. Figure 28 is a cross-sectional view of the semiconductor device along line F-F' of each of Figures 25 and 26.

[0220] The semiconductor device shown in Figures 25 to 28 may include components similar to or the same as those in the semiconductor devices described with reference to Figures 1 to 6. However, unlike the semiconductor devices shown in Figures 1 to 6, the semiconductor device of this embodiment relates to a structure in which insulating structures DW face each other in the second direction D2, and a first channel pattern CP1 and a second channel pattern CP2 are interposed between the insulating structures DW. Furthermore, unlike the semiconductor devices shown in Figures 1 to 6, the semiconductor device of this embodiment relates to a structure in which a lower conductor connected to a gate structure GS disposed at two edges of a first device region RX1 is disposed at the first device region RX1 included in the unit cell of the semiconductor device, and both a lower conductor BM1 connected to a gate structure GS disposed at one edge of a second device region RX2 and a device separation film SDB penetrating the gate structure GS disposed at the other edge of the second device region RX2 are provided. Content in this embodiment that is repeated with reference to Figures 1 to 6 will be simplified or omitted, and the differences between this embodiment and the content described with reference to Figures 1 to 6 will be primarily described. Content regarding the insulating structure DW that is repeated with reference to Figures 19 to 24 in this embodiment will be simplified or omitted.

[0221] Referring to Figures 25 to 28, a unit cell of a semiconductor device according to an embodiment may include a first device region RX1 having a first channel pattern CP1, a second device region RX2 having a second channel pattern CP2, and an insulating structure DW facing each other in a second direction D2 with the first channel pattern CP1 and the second channel pattern CP2 interposed therebetween. According to an embodiment, a unit cell of the semiconductor device may further include a gate separation structure CT separating the first device region RX1 and the second device region RX2.

[0222] According to an embodiment, a unit cell of a semiconductor device may include a device separation film SDB that physically separates adjacent cells and / or a lower gate pattern BCB that electrically separates adjacent cells.

[0223] Referring to Figures 25 and 26, in the first device region RX1, the lower conductor BM1 can be connected to the gate structure GS disposed at the two edges of the first device region RX1. According to an embodiment, the first lower gate pattern BCB1 disposed at the two edges of the first device region RX1 can be used as a boundary to electrically separate the first device region RX1 from the region of another cell adjacent to the first device region RX1.

[0224] Referring to FIG27, the gate structure GS included in the first device region RX1 can be connected to the first lower conductor BM1 (VDD) to which a first voltage is applied. For example, the gate structure GS of the first device region RX1 can be connected to the first lower conductor BM1 (VDD) to which a first voltage is applied via a first lower gate pattern BCB1. The first voltage can be a positive voltage.

[0225] According to an embodiment, the device separation membrane SDB may be disposed on one side of the second device region RX2. According to an embodiment, the device separation membrane SDB may not be disposed on the other side of the second device region RX2. Although Figures 25, 26, and 28 show the device separation membrane SDB disposed on the right side of the second device region RX2 and not disposed on the left side of the second device region RX2, this disclosure is not limited thereto, and the device separation membrane SDB may be disposed on the left side of the second device region RX2 and may not be disposed on the right side of the second device region RX2.

[0226] According to an embodiment, the device separation film SDB can penetrate the gate structure GS disposed at one edge of the second device region RX2. According to an embodiment, the device separation film SDB can physically separate the second device region RX2 from the region of another cell adjacent to the second device region RX2.

[0227] According to an embodiment, in the second device region RX2, the lower conductor BM1 can be connected to the gate structure GS disposed at another edge of the second device region RX2. According to an embodiment, the second lower gate pattern BCB2 disposed at the other edge of the second device region RX2 can be used as a boundary to electrically separate the second device region RX2 from the region of another cell adjacent to the second device region RX2. In other words, one side of the second device region RX2 can be physically terminated by the device separation film SDB as a boundary, and the other side of the second device region RX2 can be electrically terminated by the second lower gate pattern BCB2 as a boundary.

[0228] Although not clearly shown in the accompanying drawings, the gate structure GS located at another edge of the second device region RX2 can be connected to the second lower conductor BM1 (VSS) to which the second voltage is applied. For example, the gate structure GS of the second device region RX2 can be connected to the second lower conductor BM1 (VSS) to which the second voltage is applied via the second lower gate pattern BCB2. The second voltage can be a negative voltage or ground voltage.

[0229] As described above, the semiconductor device of this embodiment may include a first lower gate pattern BCB1 connected to a lower conductor BM1 on both sides of a first device region RX1, a device separation film SDB disposed on one side of a second device region RX2, and a second lower gate pattern BCB2 disposed on the other side of the second device region RX2, thereby effectively preventing current leakage according to the characteristics of the device.

[0230] As described above, the semiconductor device of this embodiment can improve the integration of the device because the insulating structure DW disposed outside the first device region RX1 and the second device region RX2 is not spaced apart from the first channel pattern CP1 and the second channel pattern CP2.

[0231] Each of Figures 29 and 30 is a layout diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 31 is a cross-sectional view of the semiconductor device along line G-G' of each of Figures 29 and 30. Figure 32 is a cross-sectional view of the semiconductor device along line H-H' of each of Figures 29 and 30.

[0232] The semiconductor device shown in Figures 29 to 32 may include components similar to or the same as those in the semiconductor devices described with reference to Figures 1 to 6. However, unlike the semiconductor devices shown in Figures 1 to 6, the semiconductor device of this embodiment relates to a structure in which insulating structures DW face each other in the second direction D2, and a first channel pattern CP1 and a second channel pattern CP2 are interposed between the insulating structures DW. Furthermore, unlike the semiconductor devices shown in Figures 1 to 6, the semiconductor device of this embodiment relates to a structure in which a device separation film SDB penetrating the gate structure GS disposed at both edges of the first device region RX1 is disposed in the first device region RX1 included in the unit cell of the semiconductor device, and both a lower conductor BM1 connected to the gate structure GS disposed at one edge of the second device region RX2 and the device separation film SDB penetrating the gate structure GS disposed at the other edge of the second device region RX2 are provided. Content in this embodiment that is repeated with reference to Figures 1 to 6 will be simplified or omitted, and the differences between this embodiment and the description with reference to Figures 1 to 6 will be primarily described. The content of the insulation structure DW in this embodiment, which is repeated with the content described with reference to Figures 19 to 24, will be simplified or omitted.

[0233] Referring to Figures 29 to 32, a unit cell of a semiconductor device according to an embodiment may include a first device region RX1 having a first channel pattern CP1, a second device region RX2 having a second channel pattern CP2, and an insulating structure DW facing each other in a second direction D2 with the first channel pattern CP1 and the second channel pattern CP2 interposed therebetween. According to an embodiment, a unit cell of the semiconductor device may further include a gate separation structure CT separating the first device region RX1 and the second device region RX2.

[0234] According to an embodiment, a unit cell of a semiconductor device may include a device separation film SDB that physically separates adjacent cells and / or a lower gate pattern BCB that electrically separates adjacent cells.

[0235] Referring to Figures 29 and 30, the first device region RX1 may include a device separation film SDB that penetrates the gate structure GS disposed at both edges of the first device region RX1. According to an embodiment, the device separation film SDB disposed at the two edges of the first device region RX1 can be used as a boundary to physically separate the first device region RX1 from the region of another cell adjacent to the first device region RX1. In other words, the two sides of the first device region RX1 can be physically terminated by the device separation film SDB serving as a boundary.

[0236] According to an embodiment, the device separation membrane SDB may be disposed on one side of the second device region RX2. According to an embodiment, the device separation membrane SDB may not be disposed on the other side of the second device region RX2. Although Figures 29, 30, and 32 show the device separation membrane SDB disposed on the right side of the second device region RX2 and not disposed on the left side of the second device region RX2, this disclosure is not limited thereto, and the device separation membrane SDB may be disposed on the left side of the second device region RX2 and may not be disposed on the right side of the second device region RX2.

[0237] According to an embodiment, the device separation film SDB can penetrate the gate structure GS disposed at one edge of the second device region RX2. According to an embodiment, the device separation film SDB can physically separate the second device region RX2 from the region of another cell adjacent to the second device region RX2.

[0238] According to an embodiment, in the second device region RX2, the lower conductor BM1 can be connected to the gate structure GS disposed at another edge of the second device region RX2. According to an embodiment, the second lower gate pattern BCB2 disposed at the other edge of the second device region RX2 can be used as a boundary to electrically separate the second device region RX2 from the region of another cell adjacent to the second device region RX2. In other words, one side of the second device region RX2 can be physically terminated by the device separation film SDB as a boundary, and the other side of the second device region RX2 can be electrically terminated by the second lower gate pattern BCB2 as a boundary.

[0239] Although not clearly shown in the accompanying drawings, the gate structure GS located at another edge of the second device region RX2 can be connected to the second lower conductor BM1 (VSS) to which the second voltage is applied. For example, the gate structure GS of the second device region RX2 can be connected to the second lower conductor BM1 (VSS) to which the second voltage is applied via the second lower gate pattern BCB2. The second voltage can be a negative voltage or ground voltage.

[0240] As described above, the semiconductor device of this embodiment may include a device separation film SDB disposed on both sides of the first device region RX1, a device separation film SDB disposed on one side of the second device region RX2, and a second lower gate pattern BCB2 disposed on the other side of the second device region RX2, thereby effectively preventing current leakage according to the characteristics of the device.

[0241] As described above, the semiconductor device of this embodiment can improve the integration of the device because the insulating structure DW disposed outside the first device region RX1 and the second device region RX2 is not spaced apart from the first channel pattern CP1 and the second channel pattern CP2.

[0242] Each of Figures 33 and 34 is a layout diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 35 is a cross-sectional view of the semiconductor device along line I-I' of each of Figures 33 and 34. Figure 36 is a cross-sectional view of the semiconductor device along line J-J' of each of Figures 33 and 34.

[0243] The semiconductor device shown in Figures 33 to 36 may include components similar to or the same as those in the semiconductor devices described with reference to Figures 1 to 6. However, unlike the semiconductor devices shown in Figures 1 to 6, the semiconductor device of this embodiment relates to a structure in which insulating structures DW face each other in a second direction D2, and a first channel pattern CP1 and a second channel pattern CP2 are interposed between the insulating structures DW. Furthermore, unlike the semiconductor devices shown in Figures 1 to 6, the semiconductor device of this embodiment relates to a structure in which a lower conductor BM1 of a gate structure GS connected to two edges of each of the first device region RX1 and the second device region RX2 is provided at each of the first device region RX1 and the second device region RX2 included in a unit cell of the semiconductor device. Content in this embodiment that is repeated with reference to Figures 1 to 6 will be simplified or omitted, and the differences between this embodiment and the content described with reference to Figures 1 to 6 will be primarily described. Content regarding the insulating structure DW that is repeated with reference to Figures 19 to 24 in this embodiment will also be simplified or omitted.

[0244] Referring to Figures 33 to 36, a unit cell of a semiconductor device according to an embodiment may include a first device region RX1 having a first channel pattern CP1, a second device region RX2 having a second channel pattern CP2, and an insulating structure DW facing each other in a second direction D2 with the first channel pattern CP1 and the second channel pattern CP2 interposed therebetween. According to an embodiment, a unit cell of the semiconductor device may further include a gate separation structure CT separating the first device region RX1 and the second device region RX2.

[0245] According to an embodiment, a unit cell of a semiconductor device may include a lower gate pattern BCB that electrically separates adjacent cells.

[0246] Referring to Figures 33 and 34, in the first device region RX1 and the second device region RX2, the lower conductor BM1 can be connected to the gate structure GS located at the two edges of each of the first device region RX1 and the second device region RX2.

[0247] According to an embodiment, the first lower gate pattern BCB1 disposed at the two edges of the first device region RX1 can be used as a boundary to electrically separate the first device region RX1 from the region of another cell adjacent to the first device region RX1.

[0248] According to an embodiment, the second lower gate pattern BCB2 disposed at the two edges of the second device region RX2 can be used as a boundary to electrically separate the second device region RX2 from the region of another cell adjacent to the second device region RX2.

[0249] Referring to FIG35, the gate structure GS disposed at the edge of the first device region RX1 can be connected to a first lower conductor BM1 (VDD) to which a first voltage is applied. For example, the gate structure GS of the first device region RX1 can be connected to the first lower conductor BM1 (VDD) to which a first voltage is applied via a first lower gate pattern BCB1. The first voltage can be a positive voltage. According to an embodiment, the gate structure GS disposed at the edge of the second device region RX2 can be connected to a second lower conductor BM1 (VSS) to which a second voltage is applied. For example, the gate structure GS of the second device region RX2 can be connected to the second lower conductor BM1 (VSS) to which a second voltage is applied via a second lower gate pattern BCB2. The second voltage can be a negative voltage or ground voltage.

[0250] As described above, the semiconductor device of this embodiment can prevent current leakage by using the lower gate pattern BCB as a boundary to electrically separate the first channel pattern CP1 and the second channel pattern CP2.

[0251] As described above, the semiconductor device of this embodiment may include an insulating structure DW that contacts the first channel pattern CP1 and the second channel pattern CP2 between the first device region RX1 and the second device region RX2, thereby improving the integration of the device.

[0252] Although this disclosure has been described in conjunction with embodiments that are now considered practical, it should be understood that this disclosure is not limited to the disclosed embodiments, but rather, this disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: The substrate includes a first surface and a second surface facing each other, and includes a first device region and a second device region provided with devices of different conductivity types. A first channel pattern and a second channel pattern are respectively disposed above a first surface of the substrate in the first device region and the second device region. An insulating structure extending in a first direction between the first device region and the second device region; A gate structure that surrounds the first channel pattern and the second channel pattern and extends in a second direction intersecting the first direction; a source / drain pattern that connects to both sides of each of the first channel pattern and the second channel pattern; A lower conductor is disposed on the second surface of the substrate and connected to at least some of the source / drain patterns and the gate structure disposed at one edge of the first device region; And a device separation membrane that penetrates the gate structure disposed at another edge of the first device region.

2. The semiconductor device according to claim 1, wherein, One side of the insulating structure contacts the first channel pattern in the second direction, and the other side of the insulating structure contacts the second channel pattern in the second direction.

3. The semiconductor device according to claim 1, wherein, The P-type device is located in the first device area, and the N-type device is located in the second device area.

4. The semiconductor device according to claim 3, wherein, The second device region does not include the device separation membrane, and includes a lower gate pattern that connects the gate structure and the lower conductor disposed at the two edges of the second device region.

5. The semiconductor device according to claim 1, wherein, A P-type device is disposed in the first device region, the lower conductor includes a first lower conductor to which a first voltage is applied and a second lower conductor to which a second voltage lower than the first voltage is applied, and the first device region includes a lower gate pattern that connects the gate structure disposed at one edge of the first device region and the first lower conductor.

6. The semiconductor device according to claim 1, wherein, An N-type device is disposed in the first device region, the lower conductor includes a first lower conductor to which a first voltage is applied and a second lower conductor to which a second voltage lower than the first voltage is applied, and the first device region includes a lower gate pattern that connects the gate structure disposed at one edge of the first device region and the second lower conductor.

7. The semiconductor device of claim 1, further comprising a gate separation structure, the gate separation structure being spaced apart from the first channel pattern and the second channel pattern in the second direction, wherein, Some of the gate separation structures face the insulating structure and the first channel pattern is interposed therebetween, and some of the gate separation structures face the insulating structure and the second channel pattern is interposed therebetween.

8. The semiconductor device according to claim 1, wherein, The first device area and the second device area are located within a standard unit.

9. A semiconductor device, comprising: The substrate includes a first surface and a second surface facing each other, and includes a first device region and a second device region provided with devices of different conductivity types. A first channel pattern and a second channel pattern are respectively disposed above a first surface of the substrate in the first device region and the second device region. An insulating structure extending in a first direction, with the first trench pattern and the second trench pattern interposed between the insulating structure and facing each other in a second direction intersecting the first direction; A gate structure that surrounds the first channel pattern and the second channel pattern and extends in the second direction; a source / drain pattern that is connected to both sides of each of the first channel pattern and the second channel pattern; A lower conductor is disposed on the second surface of the substrate and connected to at least some of the source / drain patterns and the gate structure disposed at one edge of the first device region; And a device separation membrane that penetrates the gate structure disposed at another edge of the first device region.

10. The semiconductor device according to claim 9, wherein, Each of the insulating structures contacts the first channel pattern and the second channel pattern in the second direction.

11. The semiconductor device according to claim 9, wherein, The P-type device is located in the first device area, and the N-type device is located in the second device area.

12. The semiconductor device according to claim 11, wherein, The second device region does not include the device separation membrane, and includes a lower gate pattern that connects the gate structure and the lower conductor disposed at the two edges of the second device region.

13. The semiconductor device according to claim 9, wherein, A P-type device is disposed in the first device region, the lower conductor includes a first lower conductor to which a first voltage is applied and a second lower conductor to which a second voltage lower than the first voltage is applied, and the first device region includes a lower gate pattern that connects the gate structure disposed at one edge of the first device region and the first lower conductor.

14. The semiconductor device according to claim 9, wherein, An N-type device is disposed in the first device region, the lower conductor includes a first lower conductor to which a first voltage is applied and a second lower conductor to which a second voltage lower than the first voltage is applied, and the first device region includes a lower gate pattern that connects the gate structure disposed at one edge of the first device region and the second lower conductor.

15. The semiconductor device of claim 9, further comprising a gate separation structure disposed between the first device region and the second device region, wherein, The gate separation structure is spaced apart from the first channel pattern and the second channel pattern in the second direction.

16. The semiconductor device according to claim 9, wherein, The first device area and the second device area are located within a standard unit.

17. A semiconductor device, comprising: The substrate includes a first surface and a second surface facing each other, and includes a first device region and a second device region provided with devices of different conductivity types. A first channel pattern and a second channel pattern are respectively disposed above the first surface of the substrate in the first device region and the second device region. At least one insulating structure extends in a first direction and is disposed adjacent to at least one of the first channel pattern and the second channel pattern in a second direction intersecting the first direction; A gate structure that surrounds the first channel pattern and the second channel pattern and extends in the second direction; a source / drain pattern that is connected to both sides of each of the first channel pattern and the second channel pattern; And a lower conductor disposed on the second surface of the substrate, connected to at least some of the source / drain patterns, and connected to the gate structure disposed at the two edges of the first device region and the second device region.

18. The semiconductor device according to claim 17, wherein, The at least one insulating structure contacts the first channel pattern and the second channel pattern in the second direction and extends in the first direction between the first device region and the second device region.

19. The semiconductor device according to claim 17, wherein, The at least one insulating structure contacts the first channel pattern and the second channel pattern in the second direction and faces the first channel pattern and the second channel pattern inserted therebetween.

20. The semiconductor device according to claim 17, wherein, A P-type device is disposed in the first device region, and an N-type device is disposed in the second device region. The lower conductor includes a first lower conductor to which a first voltage is applied and a second lower conductor to which a second voltage lower than the first voltage is applied. The first device region includes a lower gate pattern connecting the gate structure disposed at one edge of the first device region and the first lower conductor. The second device region includes a lower gate pattern connecting the gate structure disposed at one edge of the second device region and the first lower conductor.

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