Chip-to-wafer bonding structure with chip supporting function and preparation method thereof

Abstract

The invention provides a chip-to-wafer bonding structure with a chip supporting function and a preparation method of the chip-to-wafer bonding structure. According to the method, a polysilazane solution is adopted as a precursor, chip gaps are selectively filled through a spin-coating process, and then the polysilazane solution is converted into a silicon dioxide supporting structure. And the warping problem caused by high temperature and thick film deposition is avoided by utilizing the characteristics of high efficiency and normal-temperature treatment of the spin-coating process. The height of the supporting layer can be accurately controlled by controlling spin-coating parameters, formation of redundant film layers on the top of the chip is avoided, and the subsequent process is simplified. The formed silicon dioxide supporting structure is completely compatible with a standard semiconductor process, chip splitting in the thinning process can be effectively prevented, and the process reliability and economical efficiency are improved. The problems of wafer warping, low process efficiency, high cost and the like caused by filling silicon dioxide through chemical vapor deposition in the prior art are solved.

Description

Chip-to-wafer bonding structure with chip support function and its fabrication method Technical Field

[0001] This invention belongs to the field of advanced semiconductor packaging technology, and particularly relates to a chip-to-wafer bonding structure with chip support function and its preparation method. Background Technology

[0002] As semiconductor process nodes continue to advance, the critical dimensions of integrated circuits (ICs) continue to shrink, and Moore's Law, which traditionally relies on transistor size reduction to improve performance and reduce costs, is gradually facing bottlenecks. On the one hand, the technical difficulty and manufacturing cost of front-end processes such as photolithography, etching, and deposition have increased dramatically after entering the nanometer or even sub-nanometer scale; on the other hand, physical limitations such as power consumption, heat dissipation, and interconnect delays also hinder the improvement of single-chip integration density. Against this backdrop, the industry has begun to seek new technological paths to continue the trend of performance growth and functional integration. Among them, advanced packaging technology, due to its ability to achieve multi-chip integration at the packaging level, effectively improves system performance and functional density, and has become an important means to break through the limitations of Moore's Law.

[0003] Compared to 2.5D packaging, 3D packaging is a more advanced packaging solution. It achieves higher integration and superior performance by vertically stacking chips, representing the future direction of advanced packaging technology. Its core idea is to increase the transistor density per unit volume by vertically stacking chips. However, simply stacking chips vertically, while reducing the area occupied in a two-dimensional plane, does not reduce the overall volume. Therefore, chip thinning is necessary to reduce the vertical height after stacking, thereby truly achieving an increase in transistor density per unit volume. Summary of the Invention

[0004] Therefore, the purpose of this invention is to solve the problems of wafer warpage, low process efficiency, and high cost caused by the previous use of chemical vapor deposition to fill silicon dioxide.

[0005] The present invention provides a chip-to-wafer bonding structure with chip support function, comprising: a substrate; a plurality of chips bonded on the substrate and having gaps between them; and a silicon dioxide support structure filling the gaps between the plurality of chips, wherein the top surface of the silicon dioxide support structure is lower than the top surface of the plurality of chips, wherein the silicon dioxide support structure is formed by spin-coating and conversion of a polysilazane precursor solution.

[0006] Furthermore, the present invention provides a method for fabricating a chip-to-wafer bonding structure with chip support function, comprising the following steps: providing a substrate, bonding a plurality of chips on the substrate, wherein there are gaps between the plurality of chips; spin-coating a polysilazane solution on the substrate, such that the polysilazane solution fills the gaps between the plurality of chips and covers the top of the plurality of chips; removing the polysilazane solution covering the top of the plurality of chips by controlling spin-coating process parameters, and retaining the polysiloxane solution in the gaps between the plurality of chips; and converting the polysilazane solution retained in the gaps into a silicon dioxide layer to form a mechanical support structure between the plurality of chips.

[0007] Preferably, in the method for preparing the chip-to-wafer bonding structure of the present invention, the step of converting polysilazane into silicon dioxide includes: exposing the structure to a water or water vapor environment to cause the polysilazane to undergo a hydrolysis reaction to generate silicon dioxide.

[0008] Preferably, in the method for preparing the chip-to-wafer bonding structure of the present invention, the step of converting polysilazane into silicon dioxide includes: subjecting the structure to plasma treatment to generate hydrophilic dangling bonds on its surface; absorbing moisture from the environment through the hydrophilic dangling bonds, thereby promoting the hydrolysis of polysilazane into silicon dioxide.

[0009] Preferably, in the method for fabricating the chip-to-wafer bonding structure of the present invention, the plasma treatment uses a mixed gas of oxygen and nitrogen, with a treatment power of 100 watts to 200 watts and a treatment time of 30 seconds to 90 seconds.

[0010] Preferably, in the method for preparing the chip-to-wafer bonding structure of the present invention, before spin-coating the polysilazane solution, the method further includes the step of selectively hydrophilicizing the gap region between the chips to make it more hydrophilic relative to the top surface of the chip.

[0011] Preferably, in the method for fabricating the chip-to-wafer bonding structure of the present invention, the selective hydrophilicity treatment is achieved by plasma treatment, and a mask layer is used to protect the top region of the chip during the treatment.

[0012] Preferably, in the method for preparing the chip-to-wafer bonding structure of the present invention, the polysilazane is perhydropolysilazane, the solvent is dibutyl ether, and the solution concentration is 10 wt% to 30 wt%.

[0013] Preferably, in the method for preparing the chip-to-wafer bonding structure of the present invention, after spin-coating the polysilazane solution and before the conversion step, the method further includes a step of heat treatment at 100°C to 150°C for 5 to 10 minutes to remove the solvent.

[0014] Preferably, in the chip-to-wafer bonding structure fabrication method of the present invention, the height of the silicon dioxide support structure formed after conversion is higher than the final target thinning thickness of the chip.

[0015] This invention utilizes the high efficiency and room-temperature processing characteristics of spin coating to avoid warping problems caused by high temperatures and thick film deposition. By controlling the spin coating parameters, the height of the support layer can be precisely controlled, and excess film layers on the top of the chip can be avoided, simplifying subsequent processes. The resulting silicon dioxide support structure is fully compatible with standard semiconductor processes, effectively preventing chip splitting during thinning, improving process reliability and economy, and fundamentally solving the problems of wafer warping, low process efficiency, and high cost caused by previous methods of using chemical vapor deposition to fill silicon dioxide. Attached Figure Description

[0016] Figure 1 is a schematic diagram illustrating the flow of a chip-to-wafer hybrid bonding process in the prior art.

[0017] Figure 2 is a schematic diagram illustrating the chip splitting mechanism and the supporting role of the filling material during the CMP process according to a preferred embodiment of the present invention.

[0018] Figure 3 is a schematic diagram illustrating an isolated chip in grinding and CMP process grinding according to a preferred embodiment of the present invention.

[0019] Figure 4 is a schematic diagram illustrating the process flow of PHPS as a support material between chips according to a preferred embodiment of the present invention.

[0020] Figure 5 is a schematic diagram showing the height of the PHPS spin-coating filling chip gap according to a preferred embodiment of the present invention.

[0021] Figure 6 is a schematic diagram illustrating the plasma treatment PHPS process flow according to a preferred embodiment of the present invention.

[0022] Figure 7 is a schematic diagram illustrating the plasma treatment PHPS process flow according to a preferred embodiment of the present invention.

[0023] Figure 8 is a schematic diagram showing the key dimensions according to a preferred embodiment of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Other embodiments or modifications obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0025] In die-to-die stacking manufacturing processes, wafer-to-wafer and die-to-wafer are two main stacking methods. Wafer-to-wafer stacking requires that the die sizes involved in the stacking be consistent, the wafer sizes be uniform, and that strict alignment and process compatibility requirements be met. However, when the chips to be stacked cannot meet these conditions, die-to-wafer stacking becomes a more suitable choice. Die-to-wafer stacking offers greater flexibility, with no strict restrictions on chip size, wafer size, or material. Furthermore, die-to-wafer processes allow for pre-screening of chips before bonding, using only chips that pass yield tests for stacking, thus significantly improving the overall yield of the final stacked chips. However, in the field of hybrid bonding, die-to-wafer processes are still less mature than wafer-to-wafer processes, presenting numerous technical challenges and room for optimization. In conclusion, wafer-to-wafer and die-to-wafer stacking each have their advantages and limitations, and their selection must be based on a trade-off between specific application scenarios and process requirements. This invention mainly targets the chip-to-wafer stacking process route, focusing on the chip thinning and planarization process, aiming to optimize the technical implementation of chip-to-wafer stacking and improve process maturity.

[0026] In current mainstream chip-to-wafer hybrid bonding processes, the chip and wafer achieve both structural and electrical connections after bonding. To further expose the electrical signals of the stacked chips, it is typically necessary to perform through-silicon via (TSV) formation on one side of the chip, or use backside via reveal (BVR) technology to expose the TSV structure pre-embedded inside the chip from the back side, thereby achieving electrical signal extraction. Based on this, backside metal interconnects can be further constructed to form hybrid bonding vias or pad structures to support subsequent chip-to-wafer hybrid bonding stacking of multiple dies. For example, multi-layer stacking structures in the form of 1+1, 1+2, and 1+3 can be gradually built to achieve a highly integrated three-dimensional packaging architecture, meeting the multiple requirements of heterogeneous integrated systems for performance, bandwidth, and size. A schematic diagram of the existing chip-to-wafer hybrid bonding process flow is shown in Figure 1.

[0027] As we can see from the above process flow diagram, during chip thinning, we don't directly thin the chip. Instead, we fill the bonding gaps with an ultra-thick silicon oxide film, then thin the surface silicon oxide, and finally thin the silicon chip before proceeding with subsequent processes. The purpose of filling the gaps is that CMP (Chip Motion Processing) is typically used during thinning. However, because the CMP polishing pad is soft, it deforms during contact with the chip, generating strong shear forces on the chip's sidewalls. This can cause the chip to break off during CMP polishing, rendering it unusable. This situation is equivalent to a fragment, requiring the replacement of many components in the CMP process, such as the pad, disk, and head, with serious consequences.

[0028] Therefore, the common practice is to fill the gaps between the chips with a certain thickness of material after the chip-to-wafer hybrid bonding. This way, during the subsequent CMP (Chip Motion Processing) thinning process, because the chips are supported by this material, no lateral shearing force is generated. This is equivalent to thinning a whole wafer, not isolated chips, thus preventing the chip splitting phenomenon mentioned above.

[0029] Figure 2 shows a schematic diagram illustrating the principle of chip splitting caused by CMP polishing and the filling material preventing splitting.

[0030] As described above, filling the gaps between chips with support material is a critical operation in semiconductor manufacturing. The filling film must be compatible with subsequent standard fab processes. For example, while depositing a film to fill the gaps between chips, the film inevitably deposits on top of the chip and needs to be removed by chemical mechanical polishing (CMP). Therefore, silicon oxide is commonly used as the deposition material. However, depositing such a thick film also brings a series of challenges, specifically as follows: Stress and Warpage: To ensure complete filling of the gaps between chips and coverage of the chip surface, the thickness of the deposited film must exceed the thickness of the chip. Typically, the thickness of a chip is at least tens of micrometers, while thicker chips can reach hundreds of micrometers. When a dielectric film of this thickness is deposited, the significant difference in the coefficient of thermal expansion (CTE) between the dielectric film and the silicon substrate leads to a sharp deterioration in wafer warpage. Abnormally warped wafers may cause processing anomalies in subsequent processes, affecting manufacturing stability.

[0031] Deposition efficiency and cost issues: In conventional fab processes, PECVD is typically used to deposit dielectric films, which are usually only a few micrometers thick (less than 5 μm). However, the time required to deposit dielectric films that are tens of micrometers thick is significantly increased, resulting in a substantial reduction in wafer throughput per hour (WPH) and a significant increase in production costs.

[0032] The challenges of film removal: After filling the gaps between chips, a dielectric film of equal thickness is also applied to the top of the chip. This top film needs to be removed after gap filling is complete, while ensuring that the dielectric film within the gap is not damaged. Therefore, wet etching cannot be used; only grinding or CMP processes can be employed. As mentioned earlier, grinding processes require removing a dielectric film layer tens of micrometers thick (equivalent to the chip thickness). Since the hardness of the dielectric film is higher than that of silicon, its removal is more difficult, leading to a further reduction in WPH (Weighted Polymerization) and a significant increase in production costs. The above analysis shows that while depositing a thick dielectric film can meet the requirements for filling gaps between chips, the resulting wafer warpage, low process efficiency, and increased costs necessitate optimization to improve the feasibility and economics of the manufacturing process.

[0033] In summary, there is currently a dilemma in the process of realizing the process: if the gaps between the chips are not filled and supported, the isolated chips will split off under shear stress during the subsequent CMP process due to the lack of structural support; on the other hand, if support materials such as SiO2 are filled, it may cause the aforementioned problems such as increased warpage and process compatibility, affecting the overall stability and yield of the process.

[0034] To address the aforementioned issues, the main current solutions and problem descriptions are as follows: Reducing the die thickness can effectively decrease the amount of filler material required, thereby alleviating warpage caused by thick film deposition. It also reduces the burden on subsequent grinding and chemical mechanical polishing (CMP) processes for removing excess film, thus improving the film filling rate and the efficiency of removing excess film from the top. However, this method relies on the ability to reduce die thickness. If chip thickness cannot be reduced due to front-end process limitations, this method is not applicable. Changing the deposited film material is another approach. Currently, attempts are being made to apply organic materials (such as PI, BCB, PBO, etc.) to film deposition. These materials are characterized by their liquid precursors, which can be spin-coated onto the wafer surface using high-speed rotation and centrifugal force for uniform distribution. A stable film is then formed through thermal curing (baking). The advantages of these organic filler materials are their fast filling rate, rapid filling of gaps between dies, and low cost, significantly improving the problems of slow filling rate, low wafer throughput (WPH), and high cost associated with traditional CVD SiO2. However, these organic materials also have significant drawbacks. Their stress difference with silicon is much greater than that between SiO2 and silicon, leading to a significant increase in overall wafer warpage after filling voids. Furthermore, subsequent processes require the removal of excess filler material from the top of the core using common fab processes such as grinding or chemical mechanical polishing (CMP). However, the physicochemical properties of these organic materials differ considerably from those of commonly used dielectric layers (such as SiO2) or silicon in fab processes, making them incompatible with existing fab process flows. Therefore, despite the advantages of organic materials in terms of filling efficiency and cost, their limitations in warpage control and process compatibility restrict their application.

[0035] Note: Optimizing CMP processes with polyimide (PI), benzocyclobutene (BCB), and polybenzoxazole (PBO) can be achieved by using harder CMP polishing pads and reducing the pressure in the process parameters. This method reduces the deformation of the polishing pads during die polishing and decreases the lateral shear force on the die by reducing process pressure, thereby effectively reducing the risk of die splitting. However, the limitation of this method is that the material properties of the polishing pads inevitably result in some degree of deformation. Even with harder polishing pads and reduced pressure, some shear force will still be generated. While this shear force may not be enough to cause die splitting, it can cause some damage to the bonding interface, potentially affecting the reliability and durability of subsequent die stacking; therefore, the effectiveness of this method has certain limitations.

[0036] Grinding is used to thin the die. The grinding wheel, made of a rigid material, deforms almost nothing upon contact with the die, thus significantly reducing lateral shear forces and effectively preventing die splitting. This method can drastically reduce the shear forces on the die, as illustrated in Figure 3. When grinding an isolated die with a rigid grinding wheel, the wheel deforms almost nothing and generates almost no lateral shear force. However, when using a flexible CMP pad, deformation occurs, generating lateral shear force. Therefore, its limitation is that the surface smoothness and roughness of the ground die cannot reach the level of chemical mechanical polishing (CMP), making it difficult to meet the high surface quality requirements of subsequent photolithography, etching, and other processes. Therefore, the applicability of this method is somewhat limited.

[0037] This invention aims to solve the problem of gap filling support material after core-wafer bonding, effectively addressing key issues such as stress and warpage, deposition efficiency and cost, and removal of excess film layer on the top of the core. At the same time, it ensures that splitting and other conditions affecting the bonding interface quality are avoided during the subsequent chemical mechanical polishing (CMP) process to thin and planarize the core.

[0038] The film deposited in this invention is still SiO2, as it is the most common dielectric film in semiconductor manufacturing (Fab), and has good compatibility with subsequent processes such as grinding and chemical mechanical polishing (CMP). Furthermore, the structures prepared from this SiO2 exhibit excellent stability in terms of electrical properties and reliability. However, the SiO2 deposition method used in this invention differs from the traditional chemical vapor deposition (CVD) method.

[0039] Traditional CVD (Chemical Vapor Deposition) processes deposit SiO2 thin films on wafer surfaces via vapor-phase chemical reactions. Common precursors include tetraethoxysilane (TEOS, Si(OC2H5)4) and plasma-enhanced oxide (PEOX, using SiH4). However, CVD processes have the following limitations: First, the deposition rate is slow, typically between 10 nm / min and 200 nm / min. For example, with a 100 μm thick chip, a 30% margin in film thickness is required to ensure complete coverage, resulting in approximately 130 μm of SiO2 film. This process takes approximately 650 to 13,000 minutes, significantly reducing wafer throughput (WPH) and increasing manufacturing costs. Second, CVD inevitably deposits SiO2 on the back side of the chip. For a 100 μm thick chip, approximately 130 μm of SiO2 will also be deposited on the back side. This excess film needs to be removed through grinding and chemical mechanical polishing (CMP). Because CMP is inefficient, the process relies heavily on polishing. For example, if a chip needs to be thinned by 50 μm, 130 μm of SiO2 and 50 μm of silicon (Si) need to be removed, which significantly increases the complexity and cost of the process (as shown in step 2.3 in Figure 1).

[0040] This invention uses PHPS (polysilazane) as a precursor for SiO2 generation. The conversion of polysilazane into silicon dioxide is a unique characteristic, especially perhydropolysilazane (PHPS, chemical formula (SiH2NH)). n When it comes into contact with water, it undergoes a hydrolysis reaction to generate SiO2, while releasing byproducts such as ammonia (NH3) and hydrogen (H2). The reaction formula is: SiH2NH + 2H2O → SiO2 + NH3 + 2H2. This invention utilizes perhydropolysilazane (PHPS) as a filling material for the gaps between chips, which maintains liquid properties in a temperature range of -20°C to 150°C. At room temperature (approximately 25°C), PHPS is filled into the gaps between chips using a spin-coating process. After filling, some PHPS liquid inevitably covers the top of the chip. This invention effectively removes the PHPS on the top of the chip by precisely controlling the spin-coating speed, retaining only the PHPS in the gaps between the chips. Subsequently, by spin-coating water onto the chip and substrate as a whole, the PHPS reacts with water to convert into SiO2, thereby providing mechanical support for the isolated chip and ensuring that the chip does not split or detach during subsequent grinding and chemical mechanical polishing (CMP) processes. Figure 4 shows a schematic diagram of the process flow for using PHPS as the inter-chip support material in this invention.

[0041] The technological advantages of this invention are as follows.

[0042] High throughput (WPH): Utilizing the PHPS liquid spin coating process, the deposition time per wafer is only 30–60 seconds, significantly superior to traditional CVD processes. For example, to deposit 130 μm SiO2, the CVD process takes 650–13000 minutes, while the spin coating process greatly increases the wafer throughput per hour (WPH) and significantly reduces manufacturing costs.

[0043] Room temperature process compatibility: The process of reacting PHPS with water to generate SiO2 can be completed below 150°C, avoiding the positional misalignment issues at the chip-wafer bonding interface caused by differences in thermal expansion coefficients that may occur with high-temperature processes (such as above 150°C). After PHPS is converted into SiO2, a stable support structure is formed between the chips, ensuring the positional stability of the chips even if subsequent processes involve heating.

[0044] Simplified backside processing: Since PHPS is liquid, it can be easily removed from the top of the chip by controlling the spin coating speed, avoiding the deposition of SiO2 on the backside. Compared to traditional CVD processes that require additional grinding to remove SiO2 on the backside (such as the 130um SiO2 mentioned above), this invention significantly reduces the process burden of subsequent grinding / CMP.

[0045] Material compatibility and reliability: The final SiO2 is a conventional dielectric material used in semiconductor manufacturing (Fab) and is fully compatible with existing processes. At the same time, the SiO2 material ensures the electrical performance and long-term reliability of the chip.

[0046] In this invention, when removing excess polysiloxane (PHPS) from the top of the chip by controlling the spin coating speed, the gaps between chips may not be completely filled, resulting in the height of the PHPS (after conversion to SiO2) being slightly lower than the chip height. However, this difference does not affect the final result. As long as the height of the PHPS is higher than the target thickness of the final chip after thinning, the process meets the requirements. Even if chip portions not fully supported by PHPS may suffer damage during the thinning and grinding process, these damaged areas will be completely removed during the thinning process. Simultaneously, the sidewalls of the ultimately retained chip are supported by SiO2, so damage will not occur in these areas. Therefore, the ultimately retained chip portion remains intact, and structural stability is guaranteed. A schematic diagram is shown in Figure 5. After removing the PHPS from the top of the chip using controlled spin coating speed, the height of the PHPS may be lower than the chip height, and this area may be at risk of splitting during subsequent thinning and grinding. However, since the final chip thickness is lower than the height of the SiO2 (PHPS), the chip integrity is maintained. In addition, the SiO2 filling around the final thinning thickness of the chip provides effective mechanical support, ensuring the stability of the structure and thus effectively preventing chip splitting during the final thinning process.

[0047] In the process of converting PHPS to SiO2, we obtain it through the reaction of PHPS with water. While we can directly use a water-spray coating method to react with PHPS, one drawback of this method is that water has very low viscosity, which could potentially seep into the gaps between the chip and wafer bonding, causing adverse effects. Therefore, we can use a more refined plasma treatment method for the PHPS to SiO2 conversion: The first method involves bombarding the PHPS surface with O2 and N2 plasma after PHPS spin coating and removal from the top of the chip. This generates -OH dangling bonds on the PHPS surface, making the surface hydrophilic. These dangling bonds absorb water from the ambient air, thus converting it to SiO2, completing the PHPS to SiO2 conversion. The schematic diagram is shown in Figure 6. The second method: We can initially define the pattern using photoresist, then bombard the gaps between the chips with O2 and N2 plasma. Since the material between the chips is SiO2 (even though it's Si, Si will naturally oxidize to SiO2 in air), after plasma bombardment, -OH dangling bonds are generated, which also become hydrophilic. These dangling bonds absorb water from the ambient air. After spin-coating PHPS, the PHPS reacts with the water absorbed by the surface hydrophilicity to generate SiO2, thus filling the gaps between the chips with the SiO2 support material. The top of the chip, lacking hydrophilicity, does not absorb water and therefore cannot be converted from PHPS to SiO2, remaining in a liquid state. Therefore, it can be directly removed by controlling the rotation speed. The schematic diagram is shown in Figure 7.

[0048] This invention uses a polysiloxane (PHPS) solution as a precursor for SiO2 deposition. PHPS is dissolved in dibutyl ether solvent, with a concentration controlled between 10 wt% and 30 wt%. After uniformly coating the PHPS solution onto the substrate surface using a spin-coating process, a heat treatment at 100°C–150°C for 5–10 minutes is performed to completely evaporate the solvent. To drive the conversion of PHPS to SiO2, one of two methods can be used: one is to introduce moisture by directly spin-coating water; the other is to enhance the surface hydrophilicity using plasma hydrophilic treatment. If plasma treatment is used, a mixture of O2 and N2 gas is used, with a treatment power of 100–200 W and a duration of 30–90 seconds, to obtain surface -OH dangling bonds, significantly improving surface hydrophilicity and thus promoting the absorption of moisture from the air, providing the necessary conditions for the efficient conversion of PHPS to SiO2. After spin-coating the PHPS solution, the overall height needs to be 5%–10% higher than the chip thickness to ensure sufficient PHPS filling. After adjusting the rotation speed to remove PHPS from the chip surface, the thickness of the PHPS remaining in the gaps between chips should be at least 105% of the final chip thickness. This ensures that there is support around the chip during the thinning process, the sidewalls remain intact, and there is no splitting or damage. This guarantees the final chip thinning effect, as shown in Figure 8.

[0049] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0050] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0051] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0052] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A chip-to-wafer bonding structure with chip support function, characterized in that, include: Base; Multiple chips bonded to the substrate and spaced apart from each other; A silicon dioxide support structure is filled in the gaps between the plurality of chips, and its top surface is lower than the top surface of the plurality of chips. The silicon dioxide support structure is formed by spin-coating and conversion of a polysilazane precursor solution.

2. A method for fabricating a chip-to-wafer bonding structure, characterized in that, Includes the following steps: A substrate is provided on which a plurality of chips are bonded, wherein gaps exist between the plurality of chips; a polysilazane solution is spin-coated onto the substrate, such that the polysilazane solution fills the gaps between the plurality of chips and covers the tops of the plurality of chips; by controlling spin-coating process parameters, the polysilazane solution covering the tops of the plurality of chips is removed, and a polysiloxane solution is retained within the gaps between the plurality of chips; the polysilazane solution retained within the gaps is converted into a silicon dioxide layer to form a mechanical support structure between the plurality of chips.

3. The method for fabricating a chip-to-wafer bonding structure according to claim 2, characterized in that, The steps for converting polysilazane into silicon dioxide include: exposing the structure to a water or water vapor environment to cause the polysilazane to undergo a hydrolysis reaction to generate silicon dioxide.

4. The method for fabricating a chip-to-wafer bonding structure according to claim 2, characterized in that, The steps for converting polysilazane into silicon dioxide include: subjecting the structure to plasma treatment to generate hydrophilic dangling bonds on its surface; absorbing moisture from the environment through the hydrophilic dangling bonds, thereby promoting the hydrolysis of polysilazane into silicon dioxide.

5. The method for fabricating a chip-to-wafer bonding structure according to claim 4, characterized in that, The plasma treatment uses a mixture of oxygen and nitrogen gas, with a processing power of 100 to 200 watts and a processing time of 30 to 90 seconds.

6. The method for fabricating a chip-to-wafer bonding structure according to claim 2, characterized in that, Before spin-coating the polysilazane solution, the process includes a step of selectively hydrophilicizing the gap region between the chips to make it more hydrophilic relative to the top surface of the chips.

7. The method for fabricating a chip-to-wafer bonding structure according to claim 6, characterized in that, The selective hydrophilicity treatment is achieved through plasma treatment, and a mask layer is used to protect the top area of ​​the chip during the treatment.

8. The method for fabricating a chip-to-wafer bonding structure according to claim 2, characterized in that, The polysilazane is a perhydropolysilazane, and its solvent is dibutyl ether, with a solution concentration of 10 wt% to 30 wt%.

9. The method for fabricating a chip-to-wafer bonding structure according to claim 2, characterized in that, After spin-coating the polysilazane solution and before the conversion step, the process also includes a heat treatment at 100°C to 150°C for 5 to 10 minutes to remove the solvent.

10. The method for fabricating a chip-to-wafer bonding structure according to claim 2, characterized in that, The height of the silicon dioxide support structure formed after the conversion is higher than the final target thickness reduction of the chip.

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