Display panel and display device

Abstract

The invention discloses a display panel and a display device, the display panel comprises a first transistor and a second transistor, a second active layer comprises an oxide semiconductor, and the carrier mobility of the second active layer is greater than that of the first active layer. The second active layer comprises a first oxide semiconductor layer and a second oxide semiconductor layer which are stacked. The first oxide semiconductor layer comprises indium, gallium and zinc, the second oxide semiconductor layer comprises indium, gallium, tin and zinc, the first indium ratio is smaller than the second indium ratio, and the first gallium ratio is larger than the second gallium ratio. The first indium ratio is set to be smaller than the second indium ratio and the first gallium ratio is set to be larger than the second gallium ratio in the second active layer, so that the requirement for high mobility of the second transistor is met, the electrical stability of the first oxide semiconductor layer is higher, surrounding hydrogen can be prevented from invading the second oxide semiconductor layer, and the mobility of the second transistor is improved. Therefore, the risk of negative bias of the threshold voltage of the second transistor is reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] In current organic light-emitting diode (OLED) panels, the display area contains pixel circuits, and the bezel area contains gate drive circuits. The thin-film transistors (TFTs) in the pixel circuits need to achieve highly stable drive current output, while the TFTs used in the gate drive circuits need to achieve smaller device size and high driving capability. However, achieving both the stability of the TFTs in the display area and the high mobility of the TFTs in the gate drive circuit area presents a significant technical challenge.

[0003] Secondly, in order to simultaneously achieve the stability of the thin-film transistors in the display area and the high mobility of the thin-film transistors in the gate drive circuit area, the prior art uses all-metal oxide semiconductors as the active layer of the transistor device, and the device in the gate drive circuit uses a high-mobility oxide semiconductor, while the device in the display area uses a high-stability oxide semiconductor. However, since the environmental conditions around the device in the gate drive circuit and the device in the display area are similar, the device in the gate drive circuit is easily affected by environmental conditions (such as hydrogen) due to the requirement of high mobility, resulting in a negative threshold voltage bias. Summary of the Invention

[0004] This application provides a display panel and a display device to at least partially solve the above-mentioned technical problems.

[0005] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, comprising a display area and a non-display area located on at least one side of the display area, the display panel comprising: A first transistor is disposed in the display area, the first transistor including a first active layer, the first active layer including an oxide semiconductor; A second transistor is disposed in the non-display area. The second transistor includes a second active layer, which includes an oxide semiconductor. The carrier mobility of the second active layer is greater than that of the first active layer. The second active layer includes a first oxide semiconductor layer and a second oxide semiconductor layer stacked together. Wherein, the first oxide semiconductor layer includes indium, gallium, and zinc, and the second oxide semiconductor layer includes indium, gallium, tin, and zinc. The percentage of indium atoms in the first oxide semiconductor layer relative to the total number of atoms of all metal elements in the first oxide semiconductor layer is the first indium ratio. The percentage of gallium atoms in the first oxide semiconductor layer relative to the total number of atoms of all metal elements in the first oxide semiconductor layer is the first gallium ratio. The percentage of indium atoms in the second oxide semiconductor layer relative to the total number of atoms of all metal elements in the second oxide semiconductor layer is the second indium ratio. The percentage of gallium atoms in the second oxide semiconductor layer relative to the total number of atoms of all metal elements in the second oxide semiconductor layer is the second gallium ratio. The first indium ratio is less than the second indium ratio, and the first gallium ratio is greater than the second gallium ratio.

[0006] Optionally, in some embodiments of this application, the ratio of the second indium ratio to the first indium ratio is between 1.05 and 1.51, and the ratio of the second gallium ratio to the first gallium ratio is between 0.45 and 0.75.

[0007] Optionally, in some embodiments of this application, the value of the second indium ratio to the second gallium ratio is greater than the value of the first indium ratio to the first gallium ratio.

[0008] Optionally, in some embodiments of this application, the ratio of the second indium ratio to the second gallium ratio is greater than or equal to 2, and the ratio of the first indium ratio to the first gallium ratio is between 0.9 and 1.1.

[0009] Optionally, in some embodiments of this application, the carrier concentration of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer.

[0010] Optionally, in some embodiments of this application, the percentage of the total number of atoms of all metal elements in the second oxide semiconductor layer are as follows: 35≤In at.%≤50, 15≤Ga at.%≤25, 5≤Sn at.%≤10, 20≤Zn at.%≤40; Where In at.% represents the atomic percentage of indium, Ga at.% represents the atomic percentage of gallium, Sn at.% represents the atomic percentage of tin, and Zn at.% represents the atomic percentage of zinc; In the first oxide semiconductor layer, the total atomic ratio of each metal element is indium:gallium:zinc = 1:1:1.

[0011] Optionally, in some embodiments of this application, the thickness ratio of the second oxide semiconductor layer to the first oxide semiconductor layer is between 0.25 and 6.

[0012] Optionally, in some embodiments of this application, the second oxide semiconductor layer is located on the side of the first oxide semiconductor layer near the gate of the second transistor, or; The second oxide semiconductor layer is located on the side of the first oxide semiconductor layer away from the gate of the second transistor.

[0013] Optionally, in some embodiments of this application, the material composition of the first oxide semiconductor layer is the same as that of the first active layer.

[0014] Optionally, in some embodiments of this application, the second active layer further includes a third oxide semiconductor layer, which is disposed between the first oxide semiconductor layer and the third oxide semiconductor layer, wherein the carrier mobility of the third oxide semiconductor layer is less than that of the second oxide semiconductor layer.

[0015] Optionally, in some embodiments of this application, the carrier mobility of the third oxide semiconductor layer is less than or equal to the carrier mobility of the first oxide semiconductor layer.

[0016] Optionally, in some embodiments of this application, the material composition of the third oxide semiconductor layer is the same as that of the first oxide semiconductor layer.

[0017] Optionally, in some embodiments of this application, the display panel includes a substrate, a buffer layer, a first gate insulating layer, a second gate insulating layer, a first metal layer, a third gate insulating layer, a second metal layer, an interlayer dielectric layer, a third metal layer, and a passivation layer; The buffer layer is disposed on the substrate, the first active layer is disposed on the side of the buffer layer away from the substrate, the first gate insulating layer covers the first active layer, the second active layer is disposed on the side of the first gate insulating layer away from the substrate, the second gate insulating layer covers the first gate insulating layer and the second active layer, the first metal layer is disposed on the side of the second gate insulating layer away from the substrate, and the first metal layer includes the gate of the first transistor and the gate of the second transistor. The third gate insulating layer covers the first metal layer, the second metal layer is disposed on the side of the third gate insulating layer away from the substrate, the interlayer dielectric layer covers the second metal layer and the third gate insulating layer, the third metal layer is disposed on the side of the interlayer dielectric layer away from the substrate, the third metal layer includes the source and drain of the first transistor and the source and drain of the second transistor, and the passivation layer covers the third metal layer. The hydrogen content of the second gate insulating layer is lower than that of the first gate insulating layer, and the hydrogen content of both the first and second gate insulating layers is lower than that of the interlayer dielectric layer and the passivation layer.

[0018] Optionally, in some embodiments of this application, the first transistor is applied to a pixel circuit, and the second transistor is applied to at least one of a gate driving circuit and a demultiplexing circuit.

[0019] According to a second aspect of this application, a display device is provided, which includes a display panel as described in any of the above embodiments.

[0020] In the display panel and display device of this application embodiment, the display panel includes a first transistor located in the display area and a second transistor located in the non-display area. The second active layer includes an oxide semiconductor, and the carrier mobility of the second active layer is greater than that of the first active layer. The second active layer includes a first oxide semiconductor layer and a second oxide semiconductor layer stacked together. The first oxide semiconductor layer includes indium, gallium, and zinc, and the second oxide semiconductor layer includes indium, gallium, tin, and zinc. The first indium ratio is less than the second indium ratio, and the first gallium ratio is greater than the second gallium ratio.

[0021] It is understood that the display panel and display device of this application embodiment set the carrier mobility of the second active layer to be greater than that of the first active layer to meet the requirements of high stability of the first transistor and high mobility of the second transistor. Secondly, in the second active layer, the first indium ratio is set to be less than the second indium ratio and the first gallium ratio is set to be greater than the second gallium ratio, so that the indium atom ratio of the second oxide semiconductor layer is higher and the gallium atom ratio is lower than that of the first oxide semiconductor layer. Therefore, the mobility of the second oxide semiconductor layer is higher to meet the requirement of high mobility of the second transistor. The first oxide semiconductor layer has higher electrical stability and can prevent surrounding hydrogen from penetrating the second oxide semiconductor layer to reduce the risk of negative bias of the threshold voltage of the second transistor.

[0022] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0024] Figure 1 This is a top view of the display panel provided in an exemplary embodiment of this disclosure; Figure 2 This is a schematic diagram of the structure of the display panel provided in an exemplary embodiment of this disclosure; Figure 3 This is a partial schematic diagram of a display panel provided in an exemplary embodiment of this disclosure; Figure 4 This is another partial schematic diagram of the display panel provided in an exemplary embodiment of this disclosure; Figure 5 This is another partial schematic diagram of a display panel provided in an exemplary embodiment of this disclosure; Figure 6 This is another structural schematic diagram of the display panel provided in an exemplary embodiment of this disclosure; Figure 7 This is a schematic diagram of the structure of a display device provided in an exemplary embodiment of this disclosure.

[0025] Explanation of reference numerals in the attached figures: Display panel 100; first transistor T1; second transistor T2; display area AA; non-display area NA; gate drive circuit area NA1; demultiplexing circuit area NA2; first active layer y1; second active layer y2; first oxide semiconductor layer y21; second oxide semiconductor layer y22; third oxide semiconductor layer y23; substrate 101; buffer layer 102; light-shielding layer 103; first gate insulating layer 111; second gate insulating layer 112; first metal layer 121; third gate insulating layer 113; second metal layer 122; interlayer dielectric layer 114; third metal layer 123; passivation layer 115; first planarization layer 116; fourth metal layer 124; second planarization layer 117; anode 131; pixel definition layer 132; light-shielding part 13a; first electrode plate 13b; second electrode plate 12a; third electrode plate 12b; first transition part 12c; second transition part 12d; display device 1000. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0027] This application provides a display panel 100; please refer to [link / reference]. Figures 1 to 4 , Figure 1 This is a top view of the display panel 100 provided in an exemplary embodiment of this disclosure; Figure 2 This is a schematic diagram of the structure of the display panel 100 provided in an exemplary embodiment of this disclosure; Figure 3 This is a partial schematic diagram of the display panel 100 provided in an exemplary embodiment of this disclosure; Figure 4 This is another partial schematic diagram of the display panel 100 provided in an exemplary embodiment of this disclosure.

[0028] It should be noted that, Figure 2 The example embodiment is one of the embodiments of this application, but is not limited thereto. For example, the structures of the first transistor T1 and the second transistor T2 may differ. Figure 2 In the illustrated implementation, for example, the first transistor T1 and the second transistor T2 can each be a bottom-gate type, a back-channel type, etc.

[0029] Optionally, the display panel 100 is an electroluminescent panel, and the following description uses an organic light-emitting diode panel as an example, but it is not limited to this. For example, it can be a quantum dot light-emitting diode panel.

[0030] This application provides a display panel 100, which includes a display area AA and a non-display area NA located on at least one side of the display area AA.

[0031] The display area AA can be a region that includes sub-pixels of the displayed image. The sub-pixels can be arranged in a matrix. In a planar view, the sub-pixels can have a rectangular, rhomboid, or square shape, but the implementation is not limited to these.

[0032] The non-display area NA can be a region that does not include subpixels and therefore does not display an image. The non-display area NA can be located near (or around) the display area AA. For example, the non-display area NA can surround the display area AA, but the implementation is not limited to this.

[0033] Optionally, the display panel 100 includes a pixel circuit, a gate driving circuit, and a demultiplexing circuit. The pixel circuit is disposed in the display area AA and is configured to control the emission of sub-pixels. The gate driving circuit is disposed in the gate driving circuit area NA1 of the non-display area NA, and the demultiplexing circuit is disposed in the demultiplexing circuit area NA2 of the non-display area NA. The gate driving circuit area NA1 may be located on the opposite side or one side of the display area AA, and the demultiplexing circuit area NA2 is located on the side of the display area AA closer to the bonding area.

[0034] Optionally, in some embodiments of this application, the display panel 100 includes a first transistor T1 and a second transistor T2.

[0035] The first transistor T1 is used in the pixel circuit, and the second transistor T2 is used in at least one of the gate driving circuit and the demultiplexing circuit.

[0036] Understandably, the pixel circuit uses the first transistor T1 to achieve a highly stable drive circuit output. The gate drive circuit and demultiplexing circuit use the second transistor T2 to achieve device miniaturization, reduce the bezel size, and achieve high driving capability of the circuit.

[0037] Optionally, in some embodiments of this application, a first transistor T1 is disposed in the display area AA. The first transistor T1 includes a first active layer y1, which comprises an oxide semiconductor.

[0038] The second transistor T2 is disposed in the non-display area NA. The second transistor T2 includes a second active layer y2, which is an oxide semiconductor. The carrier mobility of the second active layer y2 is greater than that of the first active layer y1. The second active layer y2 includes a first oxide semiconductor layer y21 and a second oxide semiconductor layer y22 stacked together.

[0039] The first oxide semiconductor layer y21 comprises indium, gallium, and zinc, and the second oxide semiconductor layer y22 comprises indium, gallium, tin, and zinc. The percentage of indium atoms in the first oxide semiconductor layer y21 relative to the total number of atoms of all metal elements in the first oxide semiconductor layer y21 is the first indium ratio. The percentage of gallium atoms in the first oxide semiconductor layer y21 relative to the total number of atoms of all metal elements in the first oxide semiconductor layer y21 is the first gallium ratio. The percentage of indium atoms in the second oxide semiconductor layer y22 relative to the total number of atoms of all metal elements in the second oxide semiconductor layer y22 is the second indium ratio. The percentage of gallium atoms in the second oxide semiconductor layer y22 relative to the total number of atoms of all metal elements in the second oxide semiconductor layer y22 is the second gallium ratio.

[0040] The first indium ratio is less than the second indium ratio, and the first gallium ratio is greater than the second gallium ratio.

[0041] It should be noted that all metal elements in the first oxide semiconductor layer y21 are all metal elements except oxygen, specifically indium, gallium, and zinc. All metal elements in the second oxide semiconductor layer y22 are all metal elements except oxygen, specifically indium, gallium, tin, and zinc.

[0042] Gallium is an element that suppresses oxygen defects and improves the electrical stability of oxide semiconductor layers. However, an excessive number of gallium atoms can reduce mobility. Indium, on the other hand, is an element that improves the conductivity of oxide semiconductor layers, thus contributing to increased mobility.

[0043] Therefore, the display panel 100 of this application embodiment sets the carrier mobility of the second active layer y2 to be greater than that of the first active layer y1 to meet the requirements of high stability of the first transistor T1 and high mobility of the second transistor T2. Secondly, in the second active layer y2, the first indium ratio is set to be less than the second indium ratio, and the first gallium ratio is set to be greater than the second gallium ratio, so that the indium atom ratio of the second oxide semiconductor layer y22 is higher and the gallium atom ratio is lower than that of the first oxide semiconductor layer y21. Therefore, the mobility of the second oxide semiconductor layer y22 is higher to meet the requirement of high mobility of the second transistor T2, while the first oxide semiconductor layer y21 has higher electrical stability and can prevent surrounding hydrogen from invading the second oxide semiconductor layer y22, thereby reducing the risk of negative bias of the threshold voltage of the second transistor T2.

[0044] Optionally, in some embodiments of this application, the ratio of the second indium ratio to the first indium ratio is between 1.05 and 1.51, and the ratio of the second gallium ratio to the first gallium ratio is between 0.45 and 0.75.

[0045] Understandably, increasing the indium atomic ratio and decreasing the gallium atomic ratio can improve the device's mobility. However, an excessively high indium atomic ratio can lead to excessively high carrier density, resulting in a negative threshold voltage bias. Conversely, an excessively low gallium atomic ratio can reduce the electrical stability of the oxide semiconductor layer, increasing the risk of a negative threshold voltage bias. Therefore, to effectively utilize the high mobility of the second transistor T2 while reducing the risk of a negative threshold voltage bias, the ratio of the second indium ratio to the first indium ratio should be set between 1.05 and 1.51, and the ratio of the second gallium ratio to the first gallium ratio should be set between 0.45 and 0.75.

[0046] For example, the ratio of the second indium ratio to the first indium ratio can be 1.05, 1.06, 1.07, 1.08, 1.09, 1.10, 1.11, 1.12, 1.13, 1.14, 1.15, 1.16, 1.17, 1.18, 1.19, 1.20, 1.21, 1.22, 1.23, 1.24, 1.25, 1 .26, 1.27, 1.28, 1.29, 1.30, 1.31, 1.32, 1.33, 1.34, 1.35, 1.36, 1.37, 1.38, 1.39, 1.40, 1.41, 1.42, 1.43, 1.44, 1.45, 1.46, 1.47, 1.48, 1.49, 1.50, 1.51.

[0047] The ratio of the second gallium ratio to the first gallium ratio can be 0.45, 0.46, 0.47, 0.48, 0.49, 0.5, 0.51, 0.52, 0.53, 0.54, 0.55, 0.56, 0.57, 0.58, 0.59, 0.6, 0.61, 0.62, 0.63, 0.64, 0.65, 0.66, 0.67, 0.68, 0.69, 0.7, 0.71, 0.72, 0.73, 0.74, or 0.75.

[0048] Optionally, in some embodiments of this application, the value of the second indium ratio to the second gallium ratio is greater than the value of the first indium ratio to the first gallium ratio.

[0049] Understandably, the higher the indium atom ratio / gallium atom ratio, the higher the conductivity of the oxide semiconductor layer, and thus the higher its carrier mobility. Therefore, the second indium ratio / second gallium ratio is greater than the first indium ratio / first gallium ratio, resulting in higher mobility for the second transistor T2 and reducing the risk of negative bias at its threshold voltage.

[0050] Optionally, in some embodiments of this application, the ratio of the second indium ratio to the second gallium ratio is greater than or equal to 2, and the ratio of the first indium ratio to the first gallium ratio is between 0.9 and 1.1.

[0051] Understandably, the ratio of the second indium ratio to the second gallium ratio is greater than or equal to 2 to ensure that the second transistor T2 has high mobility, for example, at 20.0 cm⁻¹. 2 / Vs and above. The ratio of the first indium ratio to the first gallium ratio is between 0.9 and 1.1 to ensure the high stability of the first oxide semiconductor layer y21 and reduce the risk of its negative bias.

[0052] Optionally, the ratio of the second indium ratio to the second gallium ratio can be 2, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 3.0, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6, 3.7, 3.8, 3.9, and 4.0.

[0053] The ratio of the first indium ratio to the first gallium ratio can be 0.9, 1, or 1.1.

[0054] Optionally, in some embodiments of this application, the carrier concentration of the second oxide semiconductor layer y22 is greater than the carrier concentration of the first oxide semiconductor layer y21.

[0055] It is understandable that the higher the carrier concentration of the oxide semiconductor layer, the greater its mobility. Therefore, the carrier concentration of the second oxide semiconductor layer y22 is greater than that of the first oxide semiconductor layer y21 to meet the requirements of high stability of the first oxide semiconductor layer y21 and high mobility of the second oxide semiconductor layer y22.

[0056] Optionally, in some embodiments of this application, the percentage of the total number of atoms of all metal elements in the second oxide semiconductor layer y22 is as follows: 35≤In at.%≤50, 15≤Ga at.%≤25, 5≤Sn at.%≤10, 20≤Zn at.%≤40.

[0057] Where In at.% represents the atomic percentage of indium, Ga at.% represents the atomic percentage of gallium, Sn at.% represents the atomic percentage of tin, and Zn at.% represents the atomic percentage of zinc.

[0058] It should be noted that In at.% = number of In atoms / (number of In atoms + number of Ga atoms + number of Sn atoms + number of Zn atoms) × 100%, Ga at.% = number of Ga atoms / (number of In atoms + number of Ga atoms + number of Sn atoms + number of Zn atoms) × 100%, Sn at.% = number of Sn atoms / (number of In atoms + number of Ga atoms + number of Sn atoms + number of Zn atoms) × 100%, and Zn at.% = number of Zn atoms / (number of In atoms + number of Ga atoms + number of Sn atoms + number of Zn atoms) × 100%.

[0059] Understandably, regarding the In atom number ratio, the higher the In atom number ratio, i.e., the greater the amount of In in the metal element, the higher the conductivity of the second oxide semiconductor layer y22, and therefore the greater the field-effect mobility. To effectively achieve high mobility in the second transistor T2, the In atom number ratio is set to 0.35 or higher, for example, 0.35, 0.36, 0.37, 0.38, 0.39, 0.4, 0.41, 0.42, 0.43, 0.44, and 0.45 or higher. However, if the In atom number ratio is too large, there are problems such as excessively high carrier density and a lower threshold voltage; therefore, it is set to 0.50 or lower, for example, 0.5, 0.49, 0.48, 0.47, 0.46, and 0.45 or lower.

[0060] Regarding the Ga atom ratio, a higher Ga atom ratio results in higher electrical stability of the second oxide semiconductor layer y22, thus effectively suppressing excessive carrier generation. To effectively achieve this effect, the Ga atom ratio is set to 0.15 or higher, such as 0.15, 0.16, 0.17, 0.18, 0.19, and 0.20 or higher. However, if the Ga atom ratio is too high, the conductivity of the second oxide semiconductor layer y22 decreases, and the field-effect mobility becomes more prone to decrease. Therefore, to meet the requirement of high mobility, the Ga atom ratio is set to 0.25 or lower, such as 0.25, 0.24, 0.23, 0.22, and 0.21 or lower.

[0061] Regarding the Sn atomic ratio, the higher the Sn atomic ratio, i.e., the greater the amount of Sn among all metal elements, the more difficult the etching process of the second oxide semiconductor layer y22 using the organic or inorganic acid etching solution used in patterning becomes. Secondly, compared to the first oxide semiconductor layer y21, the second oxide semiconductor layer y22 with added Sn exhibits an increase in carrier density through hydrogen diffusion, thereby improving the field-effect mobility. Therefore, to effectively utilize this effect and better increase the mobility of the second oxide semiconductor layer y22, the Sn atomic ratio is selected between 0.05 and 0.1, for example, 0.05, 0.06, 0.07, 0.08, 0.09, or 1.

[0062] The Zn-O bond energy corresponding to Zn is the lowest, and the Zn-O bond is easily broken. When the Zn ratio is high, the collapse voltage of the second oxide semiconductor layer Y22 under a horizontal electric field is small, which plays a role in stabilizing the structure. Therefore, in order to effectively exert the above-mentioned role, the Zn atomic ratio is selected between 0.2 and 0.4, for example, it can be 0.2, 0.21, 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29, 0.3, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37, 0.38, 0.39, or 0.4.

[0063] Optionally, in some embodiments of this application, the total atomic ratio of each metal element in the first oxide semiconductor layer y21 is indium:gallium:zinc = 1:1:1.

[0064] Understandably, compared to the second oxide semiconductor layer y22, the number of indium, gallium, and zinc atoms in the first oxide semiconductor layer y21 is equal, which reduces the indium atom ratio and increases the gallium atom ratio, in order to reduce the risk that the threshold voltage of the second transistor T2 is prone to negative bias.

[0065] Optionally, in some embodiments of this application, the material composition of the first oxide semiconductor layer y21 is the same as that of the first active layer y1.

[0066] It is understandable that the material composition of the first oxide semiconductor layer y21 is the same as that of the first active layer y1. That is, the first active layer y1 and the first oxide semiconductor layer y21 not only have the same types of metal oxides, such as indium, gallium and zinc oxides, but also have the same atomic ratio of indium, gallium and zinc.

[0067] Secondly, the material composition of the first active layer y1 is the same as that of the first oxide semiconductor layer y21, which makes the first transistor T1 highly stable.

[0068] Optionally, in some embodiments of this application, the thickness ratio of the second oxide semiconductor layer y22 to the first oxide semiconductor layer y21 is between 0.25 and 6.

[0069] Understandably, with the total thickness of the second active layer y2 remaining constant, a larger thickness of the second oxide semiconductor layer y22 results in higher mobility, but also a greater risk of negative bias in the second transistor T2. Conversely, based on the high stability of the first oxide semiconductor layer y21, a larger thickness of y21 enhances its hydrogen blocking effect, but reduces the mobility of the second transistor T2. Therefore, to satisfy both high mobility and low risk of negative bias in the second transistor T2, the thickness ratio of the second oxide semiconductor layer y22 to the first oxide semiconductor layer y21 needs to be between 0.25 and 6.

[0070] Optionally, the ratio of the thickness of the second oxide semiconductor layer y22 to the thickness of the first oxide semiconductor layer y21 can be 0.25, 0.5, 0.75, 1, 1.25, 1.5, 1.75, 2, 2.25, 2.5, 2.75, 3, 3.25, 3.5, 3.75, 4, 4.25, 4.5, 4.75, 5, 5.25, 5.5, 5.75, or 6.

[0071] Alternatively, please refer to Figure 3 In some embodiments of this application, the second oxide semiconductor layer y22 is located on the side of the first oxide semiconductor layer y21 near the gate g2 of the second transistor T2.

[0072] Understandably, the second oxide semiconductor layer y22 is closer to the gate g2 of the second transistor T2 to improve the carrier mobility of the second transistor T2. Secondly, the first oxide semiconductor layer y21 can block hydrogen from penetrating the underlying second oxide semiconductor layer y22 to reduce the risk of negative bias in the threshold voltage of the second transistor T2.

[0073] Alternatively, please refer to Figure 4In some embodiments of this application, the second oxide semiconductor layer y22 is located on the side of the first oxide semiconductor layer y21 away from the gate of the second transistor T2.

[0074] It is understandable that keeping the second oxide semiconductor layer y22 away from the gate g2 of the second transistor T2 can improve the stability of the second transistor T2 and reduce the risk of its threshold voltage being negatively biased. Secondly, the first oxide semiconductor layer y21 can also block hydrogen from penetrating the second oxide semiconductor layer y22 and protect the second oxide semiconductor layer y22 from being bombarded by dry etching gas and plasma during the conductor and patterning process, further reducing the risk of the threshold voltage of the second transistor T2 being negatively biased.

[0075] Alternatively, please refer to Figure 5 In some embodiments of this application, the second active layer y2 further includes a third oxide semiconductor layer y23. The second oxide semiconductor layer y22 is disposed between the first oxide semiconductor layer y21 and the third oxide semiconductor layer y23, and the carrier mobility of the third oxide semiconductor layer y23 is less than that of the second oxide semiconductor layer y22.

[0076] Understandably, sandwiching the second oxide semiconductor layer y22, which has a higher carrier mobility, between the first oxide semiconductor layer y21 and the third oxide semiconductor layer y23, which have higher stability, simultaneously blocks hydrogen from penetrating the second oxide semiconductor layer y22 from above and below. This also increases the distance between the second oxide semiconductor layer y22 and the gate of the second transistor T2, thereby reducing the risk of negative threshold voltage bias in the second transistor T2. Secondly, it also reduces the risk of the second oxide semiconductor layer y22 being bombarded by etching gas and / or plasma, thus reducing the risk of negative threshold voltage bias in the second transistor T2.

[0077] Optionally, in some embodiments of this application, the carrier mobility of the third oxide semiconductor layer y23 is less than or equal to the carrier mobility of the first oxide semiconductor layer y21.

[0078] Understandably, the carrier mobility of the third oxide semiconductor layer y23 is not higher than that of the first oxide semiconductor layer y21, in order to improve the stability of the second transistor T2 and reduce the risk of negative bias of the threshold voltage of the second transistor T2.

[0079] Optionally, in some embodiments of this application, the material composition of the third oxide semiconductor layer y23 is the same as that of the first oxide semiconductor layer y21.

[0080] It is understandable that the material composition of the first oxide semiconductor layer y21 is the same as that of the third oxide semiconductor layer y23. That is, the third oxide semiconductor layer y23 and the first oxide semiconductor layer y21 not only have the same types of metal oxides, such as indium, gallium and zinc oxides, but also have the same atomic ratio of indium, gallium and zinc.

[0081] Secondly, the material composition of the third oxide semiconductor layer y23 is the same as that of the first oxide semiconductor layer y21, which makes the second transistor T2 highly stable.

[0082] Optionally, in some embodiments of this application, the display panel 100 includes a substrate 101, a buffer layer 102, a first gate insulating layer 111, a second gate insulating layer 112, and a first metal layer 121.

[0083] A buffer layer 102 is disposed on a substrate 101. A first active layer y1 is disposed on the side of the buffer layer 102 away from the substrate 101. A first gate insulating layer 111 covers the first active layer y1. A second active layer y2 is disposed on the side of the first gate insulating layer 111 away from the substrate 101. A second gate insulating layer 112 covers the first gate insulating layer 111 and the second active layer y2. A first metal layer 121 is disposed on the side of the second gate insulating layer 112 away from the substrate 101. The first metal layer 121 includes the gate g1 of the first transistor T1 and the gate g2 of the second transistor T2.

[0084] The hydrogen content of the second gate insulating layer 112 is lower than that of the first gate insulating layer 111.

[0085] It is understood that a first gate insulating layer 111 and a second gate insulating layer 112 are disposed between the gate g1 and the first active layer y1 of the first transistor T1, while a second gate insulating layer 112 is disposed between the gate g2 and the second active layer y2 of the second transistor T2. That is, the first transistor T1 uses a double gate insulating layer, which has a stronger ability to block hydrogen intrusion from above to meet its high stability requirements, while the second transistor T2 uses a single gate insulating layer. When a gate voltage is applied, the electric field between the gate g2 and the second active layer y2 is larger, and the second transistor T2 has a larger current to meet the high mobility requirements of the second transistor T2.

[0086] Secondly, since the second gate insulating layer 112 is in direct contact with the second active layer y2, and the second transistor T2 has high mobility, it is more susceptible to the influence of ambient hydrogen than the first transistor T1, which can cause its threshold voltage to be negatively biased. Therefore, the hydrogen content of the second gate insulating layer 112 is lower to reduce the risk of negative bias of the second transistor T2.

[0087] Optionally, in some embodiments of this application, the density of the second gate insulating layer 112 is higher than that of the first gate insulating layer 111.

[0088] It is understandable that, given that the second gate insulating layer 112 is in direct contact with the second active layer y2, and that the second transistor T2 has high mobility, it is more susceptible to the influence of ambient hydrogen than the first transistor T1, which would cause its threshold voltage to be negatively biased. Therefore, the second gate insulating layer 112 has a higher density to better block the intrusion of hydrogen, thereby reducing the risk of the second transistor T2 being negatively biased.

[0089] It should be noted that density is the mass per unit volume.

[0090] Optionally, in some embodiments of this application, the display panel 100 further includes a third gate insulating layer 113, a second metal layer 122, an interlayer dielectric layer 114, and a third metal layer 123.

[0091] A third gate insulating layer 113 covers the first metal layer 121. A second metal layer 122 is disposed on the side of the third gate insulating layer 113 away from the substrate 101. An interlayer dielectric layer 114 covers the second metal layer 122 and the third gate insulating layer 113. A third metal layer 123 is disposed on the side of the interlayer dielectric layer 114 away from the substrate 101. The third metal layer 123 includes the source s1 and drain d1 of the first transistor T1 and the source s2 and drain d2 of the second transistor T2.

[0092] The hydrogen content of the first gate insulating layer 111 and the hydrogen content of the second gate insulating layer 112 are both lower than the hydrogen content of the interlayer dielectric layer 114.

[0093] Understandably, the hydrogen content of the first gate insulating layer 111 and the second gate insulating layer 112 are both lower than the hydrogen content of the interlayer dielectric layer 114, resulting in lower hydrogen content in the first gate insulating layer 111 and the second gate insulating layer 112, thereby reducing the risk of negative bias in the first transistor T1 and the second transistor T2. Meanwhile, the hydrogen content of the interlayer dielectric layer 114 is higher, which can reduce the total stress of its film layer, thereby reducing the risk of separation or film breakage.

[0094] Optionally, in some embodiments of this application, the display panel 100 further includes a passivation layer 115, which covers a third metal layer 123. The hydrogen content of the first gate insulating layer 111 and the hydrogen content of the second gate insulating layer 112 are both lower than the hydrogen content of the passivation layer 115.

[0095] Understandably, the hydrogen content of the first gate insulating layer 111 and the second gate insulating layer 112 are both lower than the hydrogen content of the passivation layer 115, resulting in lower hydrogen content in the first gate insulating layer 111 and the second gate insulating layer 112, thereby reducing the risk of negative bias in the first transistor T1 and the second transistor T2. On the other hand, the passivation layer 115 has a higher hydrogen content, which can reduce the total stress of its film layer, thereby reducing the risk of separation or film breakage.

[0096] Optionally, the first gate insulating layer 111, the second gate insulating layer 112, the third gate insulating layer 113, the interlayer dielectric layer 114, and the passivation layer 115 can each be an inorganic material, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc. Optionally, the passivation layer 115 can include a stacked structure of silicon oxide and silicon nitride layers. Silicon nitride has a higher hydrogen content, but it also has a stronger ability to block water vapor.

[0097] Optionally, in some embodiments of this application, the display panel 100 includes a light-shielding layer 103, a first planarization layer 116, an anode 131, and a pixel definition layer 132. The light-shielding layer 103 is disposed between a substrate 101 and a buffer layer 102. The light-shielding layer 103 is configured to block a first transistor T1. The first planarization layer 116 covers a passivation layer 115. The anode 131 is disposed on the side of the first planarization layer 116 away from the substrate 101. The anode 131 connects to a portion of a third metal layer 123. The pixel definition layer 132 is disposed on the side of the anode 131 away from the substrate 101.

[0098] The light-shielding layer 103 includes a light-shielding portion 13a and a first electrode plate 13b, with the light-shielding portion 13a shielding the first transistor T1. The first metal layer 121 includes a second electrode plate 12a, and the second metal layer 122 includes a third electrode plate 12b. The third metal layer 123 includes a first transition portion 12c, which connects the first electrode plate 13b and the third electrode plate 12b. The first electrode plate 13b, the second electrode plate 12a, and the third electrode plate 12b are stacked to form a storage capacitor.

[0099] It is understandable that the first electrode plate 13b is formed by using a light-shielding layer 103 to save on the photomask while increasing the capacitance of the storage capacitor.

[0100] Optionally, the materials of the first metal layer 121, the second metal layer 122, and the third metal layer 123 may each include either copper or aluminum. The source and drain regions of the first active layer y1 and the second active layer y2 may be conductive by IMP or plasma bombardment.

[0101] Please refer to Figure 6 , Figure 6 This is another structural schematic diagram of the display panel 100 according to an embodiment of this application. Figure 6 In this section, the parts that differ from the above embodiments will be described in order to avoid redundant descriptions.

[0102] Optionally, in some embodiments of this application, the display panel 100 includes a light-shielding layer 103, a first planarization layer 116, a fourth metal layer 124, a second planarization layer 117, an anode 131, and a pixel definition layer 132. The light-shielding layer 103 is disposed between a substrate 101 and a buffer layer 102. The light-shielding layer 103 is configured to block a first transistor T1. The first planarization layer 116 covers a passivation layer 115. The fourth metal layer 124 is disposed on the side of the first planarization layer 116 away from the substrate 101. The second planarization layer 117 covers the fourth metal layer 124. The anode 131 is disposed on the side of the second planarization layer 117 away from the substrate 101. The anode 131 connects to a portion of the fourth metal layer 124. The pixel definition layer 132 is disposed on the side of the anode 131 away from the substrate 101.

[0103] The light-shielding layer 103 includes a light-shielding portion 13a and a first electrode plate 13b, with the light-shielding portion 13a shielding the first transistor T1. The first metal layer 121 includes a second electrode plate 12a, and the second metal layer 122 includes a third electrode plate 12b. The third metal layer 123 includes a first connecting portion 12c, which connects the first electrode plate 13b and the third electrode plate 12b. The first electrode plate 13b, the second electrode plate 12a, and the third electrode plate 12b are stacked to form a storage capacitor.

[0104] It is understandable that the first electrode plate 13b is formed by using a light-shielding layer 103 to save on the photomask while increasing the capacitance of the storage capacitor.

[0105] Optionally, the fourth metal layer 124 further includes a second transition portion 12d, and the anode 131 is connected to the second transition portion 12d.

[0106] It is understood that, compared with the above embodiments, this embodiment adds a fourth metal layer 124, which can reduce the wiring space in the plane to narrow the bezel; secondly, the addition of the fourth metal layer 124 allows the traces to be connected in parallel with the traces of the fourth metal layer 124 to reduce impedance and improve charging rate.

[0107] Please refer to Figure 7 , Figure 7 This is a schematic diagram of the structure of the display device 1000 provided in the embodiments of this application.

[0108] This application provides a display device 1000, which includes a display panel 100 as described in any of the above embodiments.

[0109] It should be noted that the structure of the display panel 100 of the display device 1000 in this application embodiment is similar to or the same as the structure of the display panel 100 in the above embodiment. For details, please refer to [link / reference]. Figures 1 to 6 Therefore, the relevant explanations will not be repeated here.

[0110] Optionally, the display device 1000 can be at least one of the following: smartphone, tablet, mobile phone, video phone, e-book reader, desktop computer, laptop, netbook, workstation, server, personal digital assistant, portable media player, MP3 player, television, mobile medical device, camera, game console, digital camera, car navigation system, in-vehicle display, electronic billboard, ATM, or wearable device, VR device, AR device.

[0111] It is understood that in the display device 1000 of this application embodiment, the display panel 100 includes a first transistor T1 located in the display area AA and a second transistor T2 located in the non-display area NA. The second active layer y2 includes an oxide semiconductor, and the carrier mobility of the second active layer y2 is greater than that of the first active layer y1. The second active layer y2 includes a first oxide semiconductor layer y21 and a second oxide semiconductor layer y22 stacked together. The first oxide semiconductor layer y21 includes indium, gallium, and zinc, and the second oxide semiconductor layer y22 includes indium, gallium, tin, and zinc. The first indium ratio is less than the second indium ratio, and the first gallium ratio is greater than the second gallium ratio.

[0112] It is understood that the display panel 100 and display device 1000 of this application embodiment set the carrier mobility of the second active layer y2 to be greater than that of the first active layer y1, so as to meet the requirements of high stability of the first transistor T1 and high mobility of the second transistor T2. Secondly, in the second active layer y2, the first indium ratio is set to be less than the second indium ratio and the first gallium ratio is set to be greater than the second gallium ratio, so that the indium atom ratio of the second oxide semiconductor layer y22 is higher and the gallium atom ratio is lower than that of the first oxide semiconductor layer y21. Therefore, the mobility of the second oxide semiconductor layer y22 is higher, so as to meet the requirement of high mobility of the second transistor T2. The first oxide semiconductor layer y21 has higher electrical stability and can block the surrounding hydrogen from penetrating the second oxide semiconductor layer y22, thereby reducing the risk of negative bias of the threshold voltage of the second transistor T2.

[0113] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0114] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0115] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0116] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area located on at least one side of the display area, characterized in that the display panel comprises: A first transistor is disposed in the display area, the first transistor including a first active layer, the first active layer including an oxide semiconductor; A second transistor is disposed in the non-display area. The second transistor includes a second active layer, which includes an oxide semiconductor. The carrier mobility of the second active layer is greater than that of the first active layer. The second active layer includes a first oxide semiconductor layer and a second oxide semiconductor layer stacked together. Wherein, the first oxide semiconductor layer includes indium, gallium, and zinc, and the second oxide semiconductor layer includes indium, gallium, tin, and zinc. The percentage of indium atoms in the first oxide semiconductor layer relative to the total number of atoms of all metal elements in the first oxide semiconductor layer is the first indium ratio. The percentage of gallium atoms in the first oxide semiconductor layer relative to the total number of atoms of all metal elements in the first oxide semiconductor layer is the first gallium ratio. The percentage of indium atoms in the second oxide semiconductor layer relative to the total number of atoms of all metal elements in the second oxide semiconductor layer is the second indium ratio. The percentage of gallium atoms in the second oxide semiconductor layer relative to the total number of atoms of all metal elements in the second oxide semiconductor layer is the second gallium ratio. The first indium ratio is less than the second indium ratio, and the first gallium ratio is greater than the second gallium ratio.

2. The display panel according to claim 1, characterized in that, The ratio of the second indium ratio to the first indium ratio is between 1.05 and 1.51, and the ratio of the second gallium ratio to the first gallium ratio is between 0.45 and 0.

75.

3. The display panel according to claim 2, characterized in that, The ratio of the second indium ratio to the second gallium ratio is greater than the ratio of the first indium ratio to the first gallium ratio.

4. The display panel according to claim 3, characterized in that, The ratio of the second indium ratio to the second gallium ratio is greater than or equal to 2, and the ratio of the first indium ratio to the first gallium ratio is between 0.9 and 1.

1.

5. The display panel according to claim 2, characterized in that, The carrier concentration of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer.

6. The display panel according to any one of claims 1-5, characterized in that, In the second oxide semiconductor layer, the percentage of the total number of atoms of all metal elements are as follows: 35≤In at.%≤50, 15≤Ga at.%≤25, 5≤Sn at.%≤10, 20≤Zn at.%≤40; Where In at.% represents the atomic percentage of indium, Ga at.% represents the atomic percentage of gallium, Sn at.% represents the atomic percentage of tin, and Zn at.% represents the atomic percentage of zinc; In the first oxide semiconductor layer, the total atomic ratio of each metal element is indium:gallium:zinc = 1:1:

1.

7. The display panel according to any one of claims 1-5, characterized in that, The thickness ratio of the second oxide semiconductor layer to the first oxide semiconductor layer is between 0.25 and 6.

8. The display panel according to any one of claims 1-5, characterized in that, The second oxide semiconductor layer is located on the side of the first oxide semiconductor layer near the gate of the second transistor, or; The second oxide semiconductor layer is located on the side of the first oxide semiconductor layer away from the gate of the second transistor.

9. The display panel according to claim 8, characterized in that, The material composition of the first oxide semiconductor layer is the same as that of the first active layer.

10. The display panel according to claim 8, characterized in that, The second active layer further includes a third oxide semiconductor layer, which is disposed between the first oxide semiconductor layer and the third oxide semiconductor layer, wherein the carrier mobility of the third oxide semiconductor layer is less than that of the second oxide semiconductor layer.

11. The display panel according to claim 10, characterized in that, The carrier mobility of the third oxide semiconductor layer is less than or equal to that of the first oxide semiconductor layer.

12. The display panel according to claim 11, characterized in that, The material composition of the third oxide semiconductor layer is the same as that of the first oxide semiconductor layer.

13. The display panel according to claim 8, characterized in that, The display panel includes a substrate, a buffer layer, a first gate insulating layer, a second gate insulating layer, a first metal layer, a third gate insulating layer, a second metal layer, an interlayer dielectric layer, a third metal layer, and a passivation layer; The buffer layer is disposed on the substrate, the first active layer is disposed on the side of the buffer layer away from the substrate, the first gate insulating layer covers the first active layer, the second active layer is disposed on the side of the first gate insulating layer away from the substrate, the second gate insulating layer covers the first gate insulating layer and the second active layer, the first metal layer is disposed on the side of the second gate insulating layer away from the substrate, and the first metal layer includes the gate of the first transistor and the gate of the second transistor. The third gate insulating layer covers the first metal layer, the second metal layer is disposed on the side of the third gate insulating layer away from the substrate, the interlayer dielectric layer covers the second metal layer and the third gate insulating layer, the third metal layer is disposed on the side of the interlayer dielectric layer away from the substrate, the third metal layer includes the source and drain of the first transistor and the source and drain of the second transistor, and the passivation layer covers the third metal layer. The hydrogen content of the second gate insulating layer is lower than that of the first gate insulating layer, and the hydrogen content of both the first and second gate insulating layers is lower than that of the interlayer dielectric layer and the passivation layer.

14. The display panel according to any one of claims 1-5, characterized in that, The first transistor is used in the pixel circuit, and the second transistor is used in at least one of the gate driving circuit and the demultiplexing circuit.

15. A display device, characterized in that, Includes the display panel as described in any one of claims 1-14.

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