Transistor and manufacturing method thereof

Abstract

A transistor may include a substrate, a drain layer formed within the substrate at a first side of the substrate. The first well implant has a first implant depth, the second well implant has a second implant depth, and the third well implant has a third implant depth. A first well implant, a second well implant, and a third well implant are formed within the substrate at a second side of the substrate. The second implant depth is greater than the first implant depth, and the third implant depth is greater than the second implant depth. A gate is formed at the second side of the substrate. The gate overlaps the first well implant by a first distance, the gate overlaps the second well implant by a second distance, and the gate overlaps the third well implant by a third distance.

Description

Cross-reference to related applications

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 542,735, filed October 5, 2023, and U.S. Non-Provisional Patent Application No. 18 / 736,957, filed June 7, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates generally to transistors, and more specifically to stepped-channel power metal-oxide-semiconductor field-effect transistors (MOSFETs) and methods for manufacturing the same to reduce the drain-source on-resistance R of the transistor. DS(on) . Summary of the Invention

[0003] According to one or more examples, a transistor is provided, the transistor comprising: a substrate; a drain layer formed on a first side of the substrate within the substrate; a first well implantation formed on a second side of the substrate within the substrate, the first well implantation having a first implantation depth; a second well implantation formed on a second side of the substrate within the substrate, the second well implantation having a second implantation depth, wherein the second implantation depth is greater than the first implantation depth; a third well implantation formed on a second side of the substrate within the substrate, the third well implantation having a third implantation depth, wherein the third implantation depth is greater than the second implantation depth; and a gate formed on the second side of the substrate, wherein the gate overlaps the first well implantation by a first distance, the gate overlaps the second well implantation by a second distance, and the gate overlaps the third well implantation by a third distance. The first implantation depth may be approximately 5 nm to 50 nm. The second implantation depth may be approximately 10 nm to 100 nm. The third implantation depth may be approximately 15 nm to 150 nm. The first distance may be greater than the second distance. The second distance may be greater than the third distance. The substrate may include a first type of dopant, and the first well implantation, the second well implantation, and the third well implantation may include a second type of dopant. The substrate may include a first type of dopant at a first concentration, and the drain layer may include a first type of dopant at a second concentration. The second concentration may be greater than the first concentration. The substrate may include a second type of dopant, and the first well implantation, second well implantation, and third well implantation may include first type of dopant. The substrate may include a first concentration of second type of dopant, and the drain layer may include a second concentration of second type of dopant. The second concentration may be greater than the first concentration.

[0004] According to one or more examples, a method of manufacturing a transistor is provided. The method may include: providing a substrate; forming a drain layer within the substrate at a first side of the substrate; forming a first well implantation within the substrate at a second side of the substrate, the first well implantation having a first implantation depth; forming a second well implantation within the substrate at a second side of the substrate, the second well implantation having a second implantation depth, wherein the second implantation depth is greater than the first implantation depth; forming a third well implantation within the substrate at a second side of the substrate, the third well implantation having a third implantation depth, wherein the third implantation depth is greater than the second implantation depth; and forming a gate at a second side of the substrate, wherein the gate overlaps the first well implantation by a first distance, the gate overlaps the second well implantation by a second distance, and the gate overlaps the third well implantation by a third distance. The first implantation depth may be approximately 5 nm to 50 nm. The second implantation depth may be approximately 10 nm to 100 nm. The third implantation depth may be approximately 15 nm to 150 nm. The first distance may be greater than the second distance. The second distance may be greater than the third distance. The substrate may include a first type of dopant, and the first well implantation, second well implantation, and third well implantation may include a second type of dopant. The substrate may include a first type of dopant at a first concentration, and the drain layer may include a first type of dopant at a second concentration. The second concentration may be greater than the first concentration. The substrate may include a second type of dopant, and the first well implantation, second well implantation, and third well implantation may include first type of dopant. The substrate may include a first concentration of second type of dopant, and the drain layer may include a second concentration of second type of dopant. The second concentration may be greater than the first concentration. Attached Figure Description

[0005] Figure 1 An illustration of a transistor based on one or more examples is shown.

[0006] Figure 2A It is a cross-sectional view of some steps in a method of manufacturing a transistor according to one or more examples.

[0007] Figure 2B It is a cross-sectional view of some steps in a method of manufacturing a transistor according to one or more examples.

[0008] Figure 2C It is a cross-sectional view of some steps in a method of manufacturing a transistor according to one or more examples.

[0009] Figure 2D It is a cross-sectional view of some steps in a method of manufacturing a transistor according to one or more examples.

[0010] Figure 2E It is a cross-sectional view of some steps in a method of manufacturing a transistor according to one or more examples. Detailed Implementation

[0011] Reference will now be made in detail to the various examples shown in the accompanying drawings, in which the same reference numerals always denote the same elements. The examples below can take many forms, and are not limited to those described herein.

[0012] Figure 1 A diagram of a transistor 10 according to one or more examples is shown. Transistor 10 may be represented and referred to as a stepped-channel power MOSFET, but is not limited thereto. Transistor 10 includes a gate 70, a source contact 80 (which may include metal), a source injection 82, and a drain layer 30. When a gate-to-source voltage is applied to transistor 10, current flows from the source contact 80 to the drain layer 30. The drain-source on-resistance R of transistor 10 is shown. DS(on) This is the total resistance between the drain layer 30 and the source contact 80 when transistor 10 is turned on (i.e., conducting current from the source contact 80 to the drain layer 30). Reducing the R0 of transistor 10... DS(on) It can improve device performance and reduce power loss when current flows from the source contact 80 to the drain layer 30.

[0013] Figure 1 Example transistor 10 (stepped channel power MOSFET) includes a substrate 20, which may be made of a semiconductor material such as silicon, silicon carbide or other suitable material. Figure 1 The substrate 20 shown may have a first concentration of a first type of dopant, for example, 5E18 (i.e., 5 x 10⁻⁶). 18 The drain layer 30 can be formed on one side of the substrate 20 by forming a heavier doped portion of the first type of dopant (a higher second concentration of the first type of dopant, for example, a concentration greater than 5E18). Figure 1 The transistor may further include a gate 70 formed on a second side of the substrate 20, the second side of the substrate 20 being opposite to a first side of the substrate 20 where the drain layer 30 is formed. The gate 70 may be made of metal, polysilicon, or other suitable material. A gate oxide layer 105 may be formed between the gate 70 and the substrate 20.

[0014] Figure 1The example transistor 10 (stepped-channel power MOSFET) may include a first well implant 40 that can be formed within a substrate 20, the first well implant 40 being at least partially beneath a gate oxide layer 105 on a second side of the substrate 20. The first well implant 40 may overlap a portion of a gate 70 by a first distance 42. In other words, a portion of the gate 70 may laterally overlap a portion of the first well implant 40, the amount of which is represented by the first distance 42. For the first distance 42, the lateral overlap of the first well implant 40 may range from 0.5 micrometers to 1.5 micrometers. The first well implant 40 may have a peak doping level in the range of 1E17 to 5E18, where the surface doping is in the range of 1E16 to 5E17. The first well implant 40 may have a first implantation depth of approximately 5 nm to 50 nm. Implantation depth is defined herein as the junction depth in the bulk semiconductor formed by implantation. The first well implant 40 may include a second type of dopant, while the substrate 20 may include a first type of dopant. In one example, the first type of dopant may be an n-type dopant, and the second type of dopant may be a p-type dopant. In another example, the first type of dopant can be a p-type dopant, and the second type of dopant can be an n-type dopant.

[0015] Figure 1 The example transistor 10 may further include a second well implant 50 that can be formed within the substrate 20. The second well implant 50 is located below at least a portion of the first well implant 40. The second well implant 50 may include a second type of dopant. The second well implant 50 may have a peak doping in the range of 1E17 to 1E18, wherein the surface doping is less than 5E16. A portion of the second well implant 50 may overlap with a portion of the gate 70 by a second distance 52. In other words, a portion of the gate 70 may laterally overlap with a portion of the second well implant 50, the amount of which is represented by the second distance 52. For the second distance 52, the lateral overlap of the second well implant 50 may range from 0.1 micrometers to 0.5 micrometers. The second well implant 50 may have a peak doping in the range of 1E17 to 1E18, wherein the surface doping is less than 5E16. The second well implant 50 may have a second implantation depth greater than the first implantation depth of the first well implant 40. The second well implant 50 may have a second implantation depth of approximately 10 nm to 100 nm, which is greater than the first implantation depth of the first well implant 40. The first distance 42 where the gate 70 overlaps with the first well injection 40 can be greater than the second distance 52 where the gate 70 overlaps with the second well injection 50.

[0016] Figure 1Example transistor 10 may further include a third well implant 60, which may be formed within substrate 20 below a portion of second well implant 50. Third well implant 60 may include a second type of dopant. Third well implant 60 may have a peak doping level in the range of 1E17 to 1E18, wherein the surface doping is less than 5E16. A portion of third well implant 60 may overlap with a portion of gate 70 by a third distance 62. In other words, a portion of gate 70 may laterally overlap with a portion of third well implant 60, the amount of which is represented by the third distance 62. For the third distance 62, the lateral overlap range of third well implant 60 may be in the range of 0.1 micrometer to 0.5 micrometer. Third well implant 60 may have a third implantation depth greater than the second implantation depth of second well implant 50. Third well implant 60 may have a third implantation depth of approximately 15 nm to 150 nm, which is greater than the second implantation depth. The second distance 52 at which gate 70 overlaps with second well implant 50 may be greater than the third distance 62 at which gate 70 overlaps with third well implant 60.

[0017] The different injection depths of the first well injection 40, the second well injection 50, and the third well injection 60, together with the corresponding distances 42, 52, and 62 where the gate 70 overlaps with the first well injection 40, the second well injection 50, and the third well injection 60, form a "stepped" channel for current flow when the transistor is turned on, as explained in more detail below.

[0018] In operation, when a positive voltage is applied to the gate 70, a channel 44 is formed in the first well implant 40, and current flows laterally from the source implant 82 through the channel 44 to the substrate 20, and then vertically through the substrate 20, which acts as a drift region, to the drain layer 30. The drift region is narrower in the region adjacent to the first well implant 40, wider in the region adjacent to the second well implant 50, and still wider in the region adjacent to the third well implant 60, which provides reduced on-resistance. The source implant 82 may include a second type of dopant having a concentration greater than 1E18 at the surface. The different depths of the first well implant 40, the second well implant 50, and the third well implant 60, and the different corresponding distances 42, 52, 62 of the gate 70 overlapping with the first well implant 40, the second well implant 50, and the third well implant 60, can reduce the R0 of the transistor 10. DS(on) Without reducing the channel length 44, which improves device performance compared to prior art transistors, the channel length 44 in transistor 10 is defined as the distance from the end of the first well implantation 40 below the gate 70 to the edge of the source implantation 82. The channel length 44 is the surface region below the gate 70 with a first doping type, and therefore the region where the channel inversion layer of transistor 10 is formed. The channel length 44 can be approximately 0.5 micrometers and can range from 0.3 micrometers to 1.0 micrometers.

[0019] Figures 2A to 2EA method for manufacturing transistor 10 according to one or more examples is shown. Although Figures 2A to 2E The example method shown includes steps in a specific order, but these steps may be performed in a different order and may include additional steps not explicitly shown.

[0020] Figure 2A This is a cross-sectional view of some steps in a method of manufacturing a transistor according to one or more examples. Figure 2A In this example method, a drain layer 30 may be formed at a first side of a semiconductor substrate 20. The substrate 20 may have a first concentration of a first type of dopant, for example, 5E18 (i.e., 5 x 10⁻⁶). 18 The drain layer 30 may be formed from a more heavily doped portion of the substrate 20 (a higher second concentration of the first type of dopant, for example, a concentration greater than 5E18). The substrate 20 and the drain layer 30 may be formed from a doped semiconductor material (such as silicon or silicon carbide), but other materials may be used.

[0021] Figure 2B It is a cross-sectional view of some steps in a method of manufacturing a transistor according to one or more examples. Figure 2B The first well implantation 40 is formed at a second side of the substrate 20, opposite to the drain layer 30. The first well implantation 40 may include a second type of dopant. The first well implantation 40 may have a peak doping in the range of 1E17 to 5E18, wherein the surface doping is in the range of 1E16 to 5E17. The first well implantation 40 may have a first implantation depth of approximately 5 nm to 50 nm. Figure 2B The method steps shown may further include forming an implantation mask 100 made of polysilicon or silicon dioxide adjacent to a second side of the substrate 20. An oxide layer or polysilicon layer 75 may be formed on the implantation mask 100.

[0022] Figure 2C This is a cross-sectional view of some steps in a method of manufacturing a transistor according to one or more examples. Figure 2CIn the illustrated method steps, a first spacer 110 may be formed on both sides of an oxide layer or a polysilicon layer 75. The first spacer 110 at least partially overlaps with a first well implantation 40. After forming the first spacer 110, a source implantation 82 may be implanted together with a second well implantation 50, which is formed below the first well implantation 40. The source implantation 82 may include a first type of dopant and may have a concentration in the range of 1E18 to 1E20 to provide good ohmic contact with the source contact 80. The second well implantation 50 may include a second type of dopant. The second well implantation 50 may have a peak doping in the range of 1E17 to 1E18, wherein the surface doping is less than 5E16. The second well implantation 50 may have a second implantation depth greater than the first implantation depth of the first well implantation 40. The second well implantation 50 may have a second implantation depth of approximately 10 nm to 100 nm greater than the first implantation depth. During the step of implanting the second well implant 50, the oxide layer or polysilicon layer 75 and the first spacer 110 prevent the second well implant 50 and the source implant 82 from forming beneath the oxide layer or polysilicon layer 75 and the first spacer 110.

[0023] Figure 2D This is a cross-sectional view of some steps in a method of manufacturing a transistor according to one or more examples. Figure 2D In this process, a second spacer 120 may be formed on both sides of the oxide layer or polysilicon layer 75 adjacent to the first spacer 110. The second spacer 120 at least partially overlaps laterally with the source implantation 82 and the second well implantation 50. After the formation of the second spacer 120, a third well implantation 60 is formed below the second well implantation 50. The third well implantation 60 may include a second type of dopant. The third well implantation 60 may have a peak doping in the range of 1E17 to 1E18, wherein the surface doping is less than 5E16. The third well implantation 60 may have a third implantation depth greater than the second implantation depth of the second well implantation 50. The third well implantation 60 may have a third implantation depth of approximately 15 nm to 150 nm greater than the second implantation depth. During the step of implanting the third well implantation 60, the oxide layer or polysilicon layer 75, the first spacer 110, and the second spacer 120 prevent the third well implantation 60 from forming below the oxide layer or polysilicon layer 75, the first spacer 110, and the second spacer 120.

[0024] exist Figure 2E In the middle, it can be removed Figures 2B to 2D Oxide layer / polysilicon layer 75, injection mask 100, Figures 2C to 2D Spacer 110 and Figure 2D The spacer 120. Source contact 80 may be formed above source implantation 82 and the first well implantation 40. The source contact may be made of metal. Figure 2EAs shown, a gate oxide layer 105 may be formed over a portion of the substrate 20 and a portion of the first well implant 40, and a gate 70 may be formed over the gate oxide layer 105. The gate 70 may be made of oxide, polysilicon, or other suitable materials. The gate 70 may overlap with the first well implant 40 by a first distance 42. For the first distance 42, the lateral overlap range of the first well implant 40 may be in the range of 0.5 micrometers to 1.5 micrometers. The gate 70 may overlap with a second well implant 50 by a second distance 52. For the second distance 52, the lateral overlap range of the second well implant 50 may be in the range of 0.1 micrometers to 0.5 micrometers. The gate 70 may overlap with a third well implant 60 by a third distance 62. For the third distance 62, the lateral overlap range of the third well implant 60 may be in the range of 0.1 micrometers to 0.5 micrometers. The different implantation depths of the first well implantation 40, the second well implantation 50, and the third well implantation 60, together with the corresponding overlap distances 42, 52, and 62 between the gate 70 and the first well implantation 40, the second well implantation 50, and the third well implantation 60, form a "stepped" channel for current flow when the transistor is turned on. The different depths of the first well implantation 40, the second well implantation 50, and the third well implantation 60, and the corresponding overlap distances 42, 52, and 62 between the gate 70 and the first well implantation 40, the second well implantation 50, and the third well implantation 60, can reduce the RDS(on) of the transistor 10 without reducing the channel length 44, which improves device performance compared to prior art transistors. The channel length 44 in the transistor 10 is defined as the distance from the end of the first well implantation 40 below the gate 70 to the edge of the source implantation 82. The channel length 44 can be approximately 0.5 micrometers and can range from 0.3 micrometers to 1.0 micrometers.

[0025] manufacture Figures 2A to 2E An example method for transistor 10 may allow the first type of dopant to be an n-type dopant and the second type of dopant to be a p-type dopant. Alternatively, the first type of dopant may be an n-type dopant and the second type of dopant may be a p-type dopant.

[0026] Various examples have been disclosed herein in conjunction with the foregoing description and accompanying drawings. It should be understood that describing and illustrating each combination and sub-combination of these examples literally would be an undue repetition. Therefore, all examples can be combined in any manner and / or combination, and this specification (including the accompanying drawings) should be construed as constituting a complete written description of all combinations and sub-combinations of the examples described herein, as well as the manner and process of their preparation and use, and should support the claims for any such combinations or sub-combinations.

[0027] Those skilled in the art will understand that the examples described herein are not limited to those specifically shown and described above. Furthermore, unless the contrary is mentioned above, it should be noted that all figures are not drawn to scale. Various modifications and variations are possible in accordance with the above teachings.

Claims

1. A transistor, the transistor comprising: Substrate; A drain layer is formed in the substrate at a first side of the substrate; A first well implantation is formed within the substrate at a second side of the substrate, and the first well implantation has a first implantation depth; A second well implantation is formed within the substrate at a second side of the substrate, the second well implantation having a second implantation depth, wherein the second implantation depth is greater than the first implantation depth; A third well implantation is formed in the substrate at the second side of the substrate, the third well implantation having a third implantation depth, wherein the third implantation depth is greater than the second implantation depth; and A gate, formed on the second side of the substrate, wherein the gate overlaps with the first well implant by a first distance, the gate overlaps with the second well implant by a second distance, and the gate overlaps with the third well implant by a third distance.

2. The transistor according to claim 1, wherein the first distance is greater than the second distance.

3. The transistor according to claim 2, wherein the second distance is greater than the third distance.

4. The transistor of claim 1, wherein the substrate comprises a first type of dopant, and the first well implantation, the second well implantation, and the third well implantation comprise a second type of dopant.

5. The transistor of claim 4, wherein the substrate comprises a first concentration of the first type of dopant, and the drain layer comprises a second concentration of the first type of dopant.

6. The transistor of claim 5, wherein the second concentration is greater than the first concentration.

7. The transistor of claim 6, wherein the first type of dopant comprises an n-type dopant, and the second type of dopant comprises a p-type dopant.

8. The transistor of claim 6, wherein the first type of dopant comprises a p-type dopant and the second type of dopant comprises an n-type dopant.

9. A method for manufacturing a transistor, the method comprising: Provide substrate; A drain layer is formed on a first side of the substrate within the substrate; A first well implant is formed within the substrate at a second side of the substrate, the first well implant having a first implantation depth; A second well implant is formed within the substrate at the second side of the substrate, the second well implant having a second implantation depth, wherein the second implantation depth is greater than the first implantation depth; A third well implant is formed within the substrate at the second side of the substrate, the third well implant having a third implantation depth, wherein the third implantation depth is greater than the second implantation depth; as well as A gate is formed on the second side of the substrate, wherein the gate overlaps with the first well implant by a first distance, the gate overlaps with the second well implant by a second distance, and the gate overlaps with the third well implant by a third distance.

10. The method of claim 9, wherein the first distance is greater than the second distance.

11. The method of claim 10, wherein the second distance is greater than the third distance.

12. The method of claim 9, wherein the substrate comprises a first type of dopant, and the first well implantation, the second well implantation, and the third well implantation comprise a second type of dopant.

13. The method of claim 12, wherein the substrate comprises a first concentration of the first type of dopant, and the drain layer comprises a second concentration of the first type of dopant.

14. The method of claim 13, wherein the second concentration is greater than the first concentration.

15. The method of claim 14, wherein the first type of dopant comprises an n-type dopant, and the second type of dopant comprises a p-type dopant.

16. The method of claim 14, wherein the first type of dopant comprises a p-type dopant, and the second type of dopant comprises an n-type dopant.

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