Generating violation exemption terms for static LINT checks

Abstract

The invention relates to generating violation exemption terms for static lint checks. In one example, a method includes converting source code for register transfer level design into a directed graph; acquiring a first violation generated by analyzing the source code; identifying a violation statement sub-graph associated with the first violation in the directed graph; extracting a reduced sub-graph representing the first violation from the directed graph, wherein the violation statement sub-graph comprises a starting point of the reduced sub-graph; converting the reduced sub-graph into a first vector; calculating a graph similarity between the first vector and a second vector representing a second violation of the source code for which an existing exempt item has been generated; determining, by a processing device, that the graph similarity satisfies a threshold similarity; and generating an exemption item for the first violation in response to the determination.

Description

Technical Field

[0001] This disclosure generally relates to register-transfer-level (RTL) design, and more specifically, to generating violation exemptions for static lint checks. Background Technology

[0002] Static linting tools are used to detect programming errors, vulnerabilities, style errors, and suspicious structures in source code. When an error or vulnerability is detected, many static linting tools generate alerts or violations. Summary of the Invention

[0003] Therefore, in one instance, a method according to this disclosure includes: converting source code for register-transfer level design into a directed graph; obtaining a first violation generated by analyzing the source code; identifying a violation statement subgraph associated with the first violation in the directed graph; extracting a reduced subgraph representing the first violation from the directed graph, wherein the violation statement subgraph includes the starting point of the reduced subgraph; converting the reduced subgraph into a first vector; calculating a graph similarity between the first vector and a second vector representing a second violation for which an existing exemption has been generated in the source code; determining by a processing device that the graph similarity satisfies a threshold similarity; and generating an exemption for the first violation in response to the determination.

[0004] In another embodiment according to this disclosure, a method includes: converting source code for a register-transfer level design into a directed graph; obtaining a first violation generated by a static lint inspection tool that analyzes the source code; identifying a violation statement subgraph associated with the first violation in the directed graph; extracting a minimal subgraph representing the first violation from the directed graph, wherein the violation statement subgraph includes the starting point of the minimal subgraph; executing a machine learning model that predicts the probability that the minimal subgraph matches a minimal subgraph of a second violation for which exemptions have been generated from different source code; determining by a processing device that the probability is at least equal to a threshold probability; and generating an exemption for the first violation in response to the determination.

[0005] In another example, a non-transitory computer-readable medium storage instruction according to this disclosure, when executed by a processor, causes the processor to: convert source code for register-transfer level design into a directed graph; obtain a first violation generated by a static lint checker tool analyzing the source code; identify a violation statement subgraph associated with the first violation in the directed graph; extract a minimal subgraph representing the first violation from the directed graph; convert the minimal subgraph into a first vector, wherein the violation statement subgraph includes the starting point of the minimal subgraph; calculate a graph similarity between the first vector and a second vector representing a second violation for which an existing exemption has been generated in the source code; determine that the graph similarity is less than a threshold similarity; in response to the graph similarity being less than the threshold similarity, execute a machine learning model that predicts the probability of the minimal subgraph being a minimal subgraph of a second violation for which an exemption has been generated in a different source code; determine that the probability is at least equal to a threshold probability; and generate an exemption for the first violation in response to the determination. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings illustrating embodiments of the present disclosure. The drawings are provided to give knowledge and understanding of embodiments of the present disclosure and are not intended to limit the scope of the disclosure to these specific embodiments. Furthermore, the drawings are not necessarily drawn to scale.

[0007] Figure 1 This is a flowchart illustrating an example of a method for automatically generating violation exemptions for static lint checks.

[0008] Figure 2 Explanation is available Figure 1 The method described herein generates the minimum subgraph of instances.

[0009] Figure 3 This illustrates a graphical representation of the methods used to compare existing exemptions generated for the same source code that has generated violations.

[0010] Figure 4 A graphical representation illustrating a method for using a machine learning model (which is trained using existing exemptions) to predict new exemptions from source code that differs from existing source code from which the existing exemptions are generated.

[0011] Figures 5A to 5D The instructions can be used for execution Figure 1 A systematic graphical representation of at least some steps of the method described herein.

[0012] Figure 6 Flowcharts depicting various processes used during the design and manufacture of integrated circuits according to some embodiments of the present disclosure.

[0013] Figure 7 A diagram depicting an example computer system in which embodiments of the present disclosure may operate. Detailed Implementation

[0014] This disclosure relates to the automatic generation of violation exemptions for static lint checks. As discussed above, static lint tools are used to detect programming errors, vulnerabilities, style errors, and suspicious structures in source code. When an error or vulnerability is detected, many static lint tools generate alerts or violations. These violations are then manually reviewed by the programmer or register-transfer-level (RTL) designer.

[0015] Many violations generated by static lint checking tools end up being either false positives or redundant examples of the same violation. When a false positive or redundant violation is detected, the person reviewing the violation generates an exemption. An exemption indicates that the violation associated with the exemption can be ignored. However, having to manually review these false positives and redundant violations can significantly increase the amount of time spent reviewing violations without providing any new useful information.

[0016] Examples of this disclosure use machine learning techniques to review static lint check violations and automatically generate exemptions when a violation is predicted to be a false positive or a redundant violation. In one example, examples of source code are converted into a graph from which a reduced (e.g., minimal) subgraph representing a violation can be extracted. The reduced subgraph can then be compared to reduced subgraphs of violations exempted for the same source code, for historical examples of the source code, or for both, and a similarity metric is calculated. If the similarity metric at least meets a threshold similarity metric, then an exemption can be generated for the violation corresponding to the extracted reduced subgraph. In another example, machine learning techniques can be used to compare a reduced subgraph with a reduced subgraph of exemptions generated for historical (other) examples of the source code. The machine learning techniques can predict, based on the comparison, whether a violation represented by the reduced subgraph should be exempted.

[0017] The technical advantages of this disclosure include, but are not limited to, reducing the time spent reviewing static lint checks for exemptions from days or weeks to hours without sacrificing accuracy. Furthermore, examples of this disclosure improve the operation of computer or electronic designs / systems by accurately distinguishing between genuine lint violations and false positives or redundancies in the source code, thereby resulting in better-performing source code with fewer vulnerabilities and errors.

[0018] Figure 1 This is a flowchart illustrating an example of a method 100 for automatically generating violation exemptions for static lint checks. In one instance, method 100 may be provided by a processing device (e.g., Figure 7The processing device 702) executes the method. However, in other instances, method 100 may be executed by another computing device or system. For example, Figures 5A to 5D The instructions can be used for execution Figure 1 A graphical representation of at least some steps of method 100 as illustrated in the diagram is provided for system 500. By way of example, method 100 is described below as being performed by a processing system.

[0019] In step 102, the processing system can convert the source code used for register transfer stage design into a directed graph.

[0020] In one instance, an Abstract Syntax Tree (AST) parser can be used to perform a top-down RTL code decompilation, transforming RTL code into a directed graph (e.g., an AST graph). In another instance, the directed graph may include multiple nodes connected by multiple edges, each node having the following attributes: operator type and operator value (e.g., an "if" variable). In yet another instance, computational dependencies can be searched for each variable (leaf node) in the directed graph, and a global dictionary can be created from these dependencies. If a variable has more than one parent node, then that variable is part of multiple RTL statements and therefore computationally depends on multiple variables.

[0021] For example, Figure 5A This describes an instance system 500 that can be used to perform step 102 and other steps of method 100. Figure 5A In the middle, the components of system 500 are enclosed by dashed lines. These components can be used to generate the AST graph of each RTL module, search the computational dependencies of variables in the AST graph, and generate a global code dependency dictionary.

[0022] In step 104, the processing system may obtain the first violation generated by analyzing the source code.

[0023] In one instance, a violation can be generated by a static lint checking tool that has analyzed the source code. The static lint checking tool can be any available static lint checking tool. In one instance, the static lint checking tool can generate multiple violations against the source code, and can execute method 100 for each of the multiple violations. Therefore, the first violation can be one of the multiple violations. However, the use of the term "first" is only to help distinguish it from other violations among the multiple violations and is not intended to imply any kind of order in which the multiple violations are processed. That is, the first violation is not necessarily the first of the multiple violations to be processed.

[0024] In step 106, the processing system can identify the violation statement subgraph in the directed graph that is associated with the first violation.

[0025] That is, the processing system can identify subgraphs within the directed graph of the source code (generated in step 102), where the subgraph represents the portion of the source code corresponding to the first violation generated by the static lint checking tool.

[0026] To facilitate step 106, it should be noted that the directed graph of the source code contains multiple nodes with the following attributes: operator category and operator value. In one instance, the AST parser can also tag nodes of the directed graph with additional attributes to mark the subgraph of violating statements (e.g., such as...). Figure 1 The starting point (identified in step 106).

[0027] In step 108, the processing system may extract a reduced subgraph representing the first violation from the directed graph, wherein the violation statement subgraph includes the starting point of the reduced subgraph of the first violation.

[0028] In one instance, a reduced subgraph can be a minimal subgraph. For example, Figure 2 This describes the smallest subgraph 200 that can be generated in step 108. Figure 2 In the example directed graph 200, the violation statement subgraph is indicated by nodes outlined with dashed lines. Figure 5B The components of system 500 are illustrated within the dashed lines. These components can be used to mark nodes with attributes to indicate the starting point of a violation statement subgraph (e.g., as discussed in conjunction with step 106).

[0029] In one instance, once a violation statement subgraph is identified, the AST parser can traverse the directed graph backward from the node marking the start of the violation statement subgraph to the root node of the directed graph to determine whether the violation statement is part of a block statement (e.g., if-else, for, etc.). Figure 5C The components of system 500 are illustrated within the dashed lines. These components can be used to backward traverse the directed graph to determine whether a violation statement subgraph is part of a block statement. If a violation statement is determined to be part of a block statement, the AST parser can create a subgraph for the block statement and add the block statement subgraph to the violation statement subgraph to produce an expanded violation statement subgraph. Figure 2 In the diagram, nodes outlined with solid lines represent subgraphs of block statements (if loops) that have been added to the subgraph of the violating statement subgraph. Therefore, Figure 2 The expanded subgraph of the violation statement will include all nodes outlined with solid or dashed lines and all edges connecting these nodes.

[0030] In one instance, once any block statement subgraph has been added to the violation statement subgraph, any variables (e.g., leaf nodes) in the resulting expanded violation statement subgraph can be identified, and their computational dependencies on other variables of the directed graph can be determined (e.g., from the global dictionary discussed above). The variable subgraph of the code statements whose variables are computationally dependent on other variables can be identified and added to the expanded violation statement subgraph to produce a minimal subgraph. Figure 2 In this context, the variable subgraph is indicated by nodes outlined with dashed lines; therefore, the smallest subgraph contains all nodes outlined with solid, dashed, or dotted lines and all edges connecting these nodes. Figure 5D The components of system 500 are illustrated within the dashed lines. These components can be used to find computational dependencies of variables and add them to the expanded violation statement graph.

[0031] Expanding the violation statement subgraph with block statement subgraphs and / or variable subgraphs provides local and global dependency context for violations. This illustrates how... Figure 1 The extraction of the reduced subgraph of the violation is described in step 108. More broadly, the extraction of the reduced subgraph is achieved by expanding around the violating subgraph to a finite degree (e.g., to the minimum necessary degree in the case of a minimal subgraph) to capture the context of the violation in the directed graph of the source code of the entire RTL design.

[0032] In optional step 110 (illustrated by dashed lines), the processing system can convert the reduced subgraph into a first vector.

[0033] In one instance, the first vector may include an embedding vector generated using any transformation architecture capable of taking the violating reduced subgraph as input and generating an embedding vector as output that provides a unique representation of the reduced subgraph. In one instance, the graph node attributes embedded in the first vector may include at least one of the following: operator category (e.g., IF, FOR, ASSIGN, UNARY, etc.) or operand category (e.g., INT, UINT, CONSTANT, FLOAT, etc.).

[0034] In optional step 112 (illustrated by dashed lines), the processing system may calculate the graph vector similarity between the first vector and a second vector representing the source code for which an existing exemption has been generated.

[0035] In one instance, a second vector can be generated from a second violation in the same manner as generating a first vector from a first violation. The second vector can be one of a plurality of vectors generated in this way, where each of the plurality of vectors corresponds to an exemption or violation identified against the source code. In one instance, further iterations of method 100 (or steps of method 100) can be performed to compare the first vector with each of the plurality of vectors.

[0036] In one instance, graph vector similarity can be cosine similarity.

[0037] In optional step 114 (illustrated by dashed lines), the processing system can determine whether the graph vector similarity meets the threshold similarity.

[0038] In one instance, graph vector similarity satisfies the threshold similarity if the graph vector similarity is greater than or equal to the threshold similarity. In one instance, the threshold similarity is configurable (e.g., configured by a human operator). Therefore, the threshold similarity can be tuned to suit desired accuracy levels, time constraints, or other considerations. However, in general, a higher threshold similarity typically results in fewer automatically generated exemptions (and most likely, a lower probability of genuine violations being wrongly exempted). A lower threshold similarity typically results in more automatically generated exemptions (and most likely, a higher probability of genuine violations being wrongly exempted).

[0039] If the processing system determines in step 114 that the similarity of the graph vectors meets (e.g., is greater than or equal to) a threshold similarity, then method 100 may proceed to step 116. In optional step 116 (illustrated by dashed lines), the processing system may generate an exemption for the first violation.

[0040] Therefore, if the first violation is determined to be sufficiently similar to a previously reviewed violation for which an exemption has already been generated, then an exemption is also generated for the first violation. The exemption generated for the first violation can then be added to a set of existing exemptions in the source code and used for comparison with other violations for which exemptions have not yet been reviewed.

[0041] On the other hand, if the processing system determines in step 114 that the similarity of the graph vectors does not meet (e.g., is less than) the threshold similarity, then method 100 may proceed to step 118. In optional step 118 (illustrated by dashed lines), the processing system may add the first violation to a set of existing violations in the source code.

[0042] Therefore, if the first violation is determined to be insufficiently similar to a previously reviewed violation for which an exemption has been generated, then the first violation can be considered a genuine violation (e.g., not a false positive or redundancy). The first violation can then be added to a set of existing violations in the source code.

[0043] In some instances, if the processing system determines in step 114 that the image similarity is less than a threshold similarity, then method 100 may bypass step 118 and proceed to step 120. Alternatively, method 100 may proceed to step 120 after performing step 118 as a means of verifying the results of steps 104 to 118.

[0044] In optional step 120 (illustrated by dashed lines), the processing system may execute a machine learning model that predicts the probability that the reduced subgraph matches a second, violated reduced subgraph for which exemptions have been generated.

[0045] In one instance, the machine learning model includes a Graph Convolutional Network (GCN) trained using a set of labeled, reduced subgraphs of violations and exemptions from one or more historical examples of source code (i.e., source code excluding those currently under review for violations). The GCN can be trained as a binary classification model that takes the reduced subgraphs of violations as input and generates a classification as output indicating whether the input subgraph indicates an exemption or a genuine violation. For example, the output could be a single bit vector (e.g., 0 or 1, where 0 indicates an exemption and 1 indicates a genuine violation). In one instance, the GCN may include two GCN layers, a MAX POOL layer, a hidden fully connected (FC) layer, and an output layer.

[0046] In optional step 122 (illustrated by dashed lines), the processing system can determine whether the probability is greater than or equal to the threshold probability.

[0047] In one instance, the threshold probability is configurable (e.g., configured by a human operator). Therefore, the threshold probability can be tuned to suit desired accuracy levels, time constraints, or other considerations. For example, a threshold probability of 50% (or 0.5%) will result in any violation that is more likely to be exempted being exempted. However, in general, a higher threshold probability will typically result in fewer automatically generated exemptions (and most likely, a lower probability of a genuine violation being incorrectly exempted). A lower threshold probability will typically result in more automatically generated exemptions (and most likely, a higher probability of a genuine violation being incorrectly exempted).

[0048] If the processing system determines a violation in step 122 with a probability greater than or equal to a threshold probability, then method 100 may proceed to step 124. In optional step 124, the processing system may generate an exemption for the first violation.

[0049] Therefore, if the machine learning model classifies the first violation as an exemption, then an exemption is generated for the first violation. The exemption generated for the first violation can then be added to a set of existing exemptions in the source code and used for comparison with other violations for which exemptions have not yet been reviewed.

[0050] On the other hand, if the probability of a violation in step 122 is less than a threshold probability, then method 100 may proceed to step 126. In optional step 126, the processing system may add the first violation to a set of existing violations in the source code.

[0051] Therefore, if the machine learning model classifies the first violation as a genuine violation, then the first violation can be considered a genuine violation (e.g., not a false positive or redundancy). The first violation can then be added to a set of existing violations in the source code.

[0052] As discussed above, steps 102 to 126 can be performed for each violation generated for the source code. Therefore, executable method 100 can automatically determine for each violation whether the violation should be considered a genuine violation or should be exempted.

[0053] In summary, steps 110 to 118 represent a method by which exemptions are automatically generated from static lint checks using a reduced subgraph of the violation, while steps 120 to 126 represent a second method by which exemptions are automatically generated from static lint checks using a reduced subgraph of the violation. More specifically, the first method relies on comparisons with existing exemptions generated for the same source code for which a violation has been generated, while the second method relies on comparisons with exemptions generated for source code different from the source code for which a violation has been generated. For example, Figure 3 A graphical representation 300 illustrating methods for comparing existing exemptions generated for the same source code that has generated violations (e.g., according to...) Figure 1 Steps 102 to 118). Figure 4 A graphical representation 400 illustrating a method for using a machine learning model (trained with existing exemptions) to predict new exemptions from source code that differs from existing source code from which the existing exemptions are generated (e.g., based on...). Figure 1 Steps 120 to 126).

[0054] For greater rigor, the first and second methods may be used in combination; however, either the first or second method may be used alone, and still significantly reduce the amount of time required to review violations to obtain exemptions. Therefore, although steps 110 to 126 are described above as optional, it should be understood that when method 100 is performed, at least one of steps 110 to 118 and steps 120 to 126 will always be performed.

[0055] In some instances, for accuracy, exemptions automatically generated using machine learning models in steps 120 through 126 may be reviewed by a human operator. This can lead to the discovery of new exemption patterns by the human operator. In future iterations of method 100, specifically in steps 112 through 118, a reduced exemption subgraph representing the new exemption patterns may be used. These future iterations may be iterations for unchecked violations of the same source code, or iterations for violations generated in the future from different source codes.

[0056] Figure 6This describes a set of example processes 600 used during the design, inspection, and fabrication of, for example, integrated circuits, to convert and inspect design data and instructions representing integrated circuits. Each of these processes can be structured and enabled as multiple modules or operations. The term 'EDA' stands for 'Electronic Design Automation'. These processes begin with the creation of a product concept 310 using information provided by the designer, which is converted to create an article of art using a set of EDA processes 612. When the design is complete, it is tape-out 634, which occurs when the original pattern (e.g., geometric pattern) of the integrated circuit is sent to a fabrication facility to create a mask set, which is then used to manufacture the integrated circuit. After tape-out, semiconductor dies are fabricated 636, and packaging and assembly processes 638 are performed to produce the finished integrated circuit 640.

[0057] Specifications for circuits or electronic structures can range from low-level transistor material placement to high-level description languages. High-level representations can be used to design circuits and systems using hardware description languages ​​('HDL') such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. HDL descriptions can be translated into logic-level register-transfer-level ('RTL') descriptions, gate-level descriptions, placement-level descriptions, or mask-level descriptions. Each lower-level representation, as a more detailed description, adds more useful details to the design description, such as more details about the described modules. Lower-level representations, as more detailed descriptions, can be computer-generated, exported from a design library, or created by another design automation process. An example of a lower-level specification language used to specify a more detailed representation language is SPICE, used for detailed descriptions of circuits with many analog components. This allows the description of each representation level to be used by the corresponding system (e.g., a formal verification system) of that layer. The design process can use... Figure 6 The sequence described herein. The described process can be enabled by an EDA product (or EDA system).

[0058] During system design 614, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. At this stage, the design can be divided into different types of modules or components.

[0059] During logic design and functional verification 616, modules or components in the circuit are specified using one or more description languages, and the functional accuracy of the specifications is checked. For example, components of the circuit can be verified to generate outputs that match the specification requirements of the designed circuit or system. Functional verification can be performed using simulators and other programs, such as test bench generators, static HDL checkers, and formal verification tools. In some embodiments, a special system for components, referred to as a 'simulator' or 'prototyping system', is used to accelerate functional verification.

[0060] During the synthesis and test design 618, HDL code is converted into a netlist. In some embodiments, the netlist may be a graphical structure, wherein the edges of the graphical structure represent components of the circuit, and wherein the nodes of the graphical structure represent how the components are interconnected. Both HDL code and netlist are artifacts that can be used by EDA products to verify that the integrated circuit performs according to a specified design during manufacturing. The netlist can be optimized for a target semiconductor manufacturing technology. Additionally, the finished integrated circuit can be tested to verify that the integrated circuit meets specification requirements.

[0061] During netlist verification (620), the netlist is checked to ensure it meets timing constraints and corresponds to the HDL code. During design planning (622), the overall plan view of the integrated circuit is constructed, and timing and top-level routing are analyzed.

[0062] During layout or physical implementation 624, physical placement (e.g., positioning circuit components of transistors or capacitors) and wiring (connecting circuit components via multiple conductors) are performed, and cells can be selected from a library to implement a specific logic function. As used herein, the term 'cell' can specify a set of transistors, other components, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (e.g., flip-flops or latches). As used herein, a circuit 'block' can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and can be enabled as both physical structures and simulations. Parameters, such as size, are specified for the selected cells (based on 'standard cells') to make them accessible in a database for use in EDA products.

[0063] During the analysis and extraction phase 626, circuit functionality is verified at the layout level, allowing for refinement of the layout design. During physical inspection 628, the layout design is checked to ensure that manufacturing constraints, such as DRC constraints, electrical constraints, and lithographic constraints, are correct, and that the circuit functionality matches the HDL design specifications. During resolution enhancement 630, the geometry of the layout is transformed to improve the fabrication methods of the circuit design.

[0064] During the tape-out process, data is created for the production of the photomask (if appropriate, after the application of photolithography enhancement). During mask data preparation 632, the 'tape-out' data is used to generate the photomask used to produce the finished integrated circuit.

[0065] Computer systems (e.g.) Figure 7 The storage subsystem of the computer system 700 can be used to store programs and data structures used by some or all of the EDA products described herein, as well as products for library development units and physical and logical designs for using the libraries.

[0066] Figure 7 The computer system 700 describes an example machine that can execute a set of instructions to cause the machine to perform any or more of the methods discussed herein. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client in a cloud computing infrastructure or environment.

[0067] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying the actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be considered to include any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0068] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM)), static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.) and a data storage device 718, which communicate with each other via a bus 730.

[0069] Processing device 702 represents one or more processors, such as microprocessors, central processing units, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 702 may be configured to execute instructions 726 for performing the operations and steps described herein.

[0070] The computer system 700 may further include a network interface device 708 for communication via a network 720. The computer system 700 may also include a video display unit 710 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 712 (e.g., a keyboard), a cursor control device 714 (e.g., a mouse), a graphics processing unit 722, a signal generation device 716 (e.g., a speaker), a graphics processing unit 722, a video processing unit 728, and an audio processing unit 732.

[0071] Data storage device 718 may include machine-readable storage medium 724 (also known as non-transitory computer-readable medium) storing one or more sets of instructions 726 or software embodying any one or more of the methods or functions described herein. During execution of instructions 726 by computer system 700, instructions 726 may also reside wholly or at least partially in main memory 704 and / or processing device 702, which also constitute machine-readable storage media.

[0072] In some embodiments, instruction 726 includes instructions that implement functionality corresponding to this disclosure. While machine-readable storage medium 724 is shown as a single medium in example embodiments, the term "machine-readable storage medium" should be considered as including a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered as including any medium capable of storing or encoding a set of instructions for machine execution and causing the machine and processing device 702 to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered as including, but not limited to, solid-state memory, optical media, and magnetic media.

[0073] Some of the parts described in detail above have been presented based on algorithms and symbolic representations of operations on data bits in computer memory. These algorithmic descriptions and representations are the most effective way for those skilled in the art of data processing to communicate the essence of their work to others skilled in the art. An algorithm can be a sequence of operations that leads to a desired result. These operations are operations that require physical manipulation of physical quantities. These quantities can take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals can be referred to as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0074] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for those quantities. Unless otherwise expressly stated from this disclosure, it should be understood that throughout the description, certain terms refer to the actions and processes by which a computer system or similar electronic computing device manipulates data representing physical (electronic) quantities in the registers and memories of the computer system and converts them into other data similarly represented in the memory or registers of the computer system or other such information storage devices.

[0075] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for its intended purpose, or may comprise a computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0076] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various other systems may be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. Furthermore, this disclosure is not described with reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0077] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, said instructions which can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0078] In the foregoing disclosure, embodiments of the present disclosure have been described with reference to specific examples. Clearly, various modifications may be made thereto without departing from the broader spirit and scope of the present disclosure as set forth in the following claims. Where the present disclosure relates to elements in a singular form, more than one element may be depicted in the figures, and the same elements may be labeled with the same numbers. Therefore, this disclosure and the accompanying drawings should be considered illustrative rather than restrictive.

Claims

1. A method comprising: Convert the source code used for register-transfer level design into a directed graph; Obtain the first violation generated by analyzing the source code; Identify the violation statement subgraph in the directed graph that is associated with the first violation; Extract a reduced subgraph representing the first violation from the directed graph, wherein the violation statement subgraph includes the starting point of the reduced subgraph; Transform the reduced subgraph into a first vector; Calculate the graph similarity between the first vector and a second vector representing the second violation of the source code for which existing exemptions have been generated; The processing device determines that the graph similarity satisfies a threshold similarity; and In response to the determination, an exemption is generated for the first violation.

2. The method of claim 1, wherein the transformation comprises using an abstract syntax tree parser to perform a top-down register-transfer level code decompilation of the source code for the register-transfer level design into the directed graph.

3. The method according to claim 1, wherein extracting the reduced subgraph comprises: Based on the labels that mark the starting point of the illegal statement subgraph from the directed graph, the illegal statement subgraph is extracted from the directed graph, wherein the illegal statement subgraph includes the starting point and the portion of the directed graph below the starting point; The violation statement subgraph is expanded with a subgraph of the block statement to produce an expanded violation statement subgraph, wherein the violation statement associated with the violation is part of the block statement; The extended illegal statement subgraph is expanded using a variable subgraph of the code statements of the directed graph that is computationally dependent on the variables of the extended illegal statement subgraph.

4. The method of claim 1, wherein the first vector comprises an embedding vector of attributes of the nodes of the reduced subgraph.

5. The method according to claim 1, wherein the graph similarity is cosine similarity.

6. The method of claim 1, wherein the second vector is one of a plurality of vectors, wherein each of the plurality of vectors corresponds to an exemption or a violation identified for the source code.

7. The method of claim 6, further comprising: Calculate multiple graph similarities between a third vector, representing the transformation of a reduced subgraph of a third violation generated by analyzing the source code, and each of the plurality of vectors; Determine that all graph similarities among the plurality of graph similarities are below the threshold similarity; and In response to the determination that all graph similarities among the plurality of graph similarities are below the threshold similarity, the third violation is added to a set of existing violations in the source code.

8. A method comprising: Convert the source code used for register-transfer level design into a directed graph; Obtain the first violation generated by the static lint checker that analyzes the source code; Identify the violation statement subgraph in the directed graph that is associated with the first violation; Extract the minimum subgraph representing the first violation from the directed graph, wherein the violation statement subgraph includes the starting point of the minimum subgraph; A machine learning model is executed to predict the probability that the minimum subgraph matches a second minimum subgraph of violation for which exemptions have been generated. The processing device determines that the probability is at least equal to the threshold probability; and In response to the determination, an exemption is generated for the first violation.

9. The method of claim 8, wherein the transformation comprises using an abstract syntax tree parser to perform a top-down register-transfer level code decompilation of the source code for the register-transfer level design into the directed graph.

10. The method of claim 8, wherein the extraction comprises: Based on the labels that mark the starting point of the illegal statement subgraph from the directed graph, the illegal statement subgraph is extracted from the directed graph, wherein the illegal statement subgraph includes the starting point and the portion of the directed graph below the starting point; The violation statement subgraph is expanded with a subgraph of the block statement to produce an expanded violation statement subgraph, wherein the violation statement associated with the violation is part of the block statement; The extended illegal statement subgraph is expanded using a variable subgraph of the code statements of the directed graph that is computationally dependent on the variables of the extended illegal statement subgraph.

11. The method of claim 8, wherein the machine learning model comprises a graph convolutional network trained using a set of labeled minimum subgraphs of violations and exemptions from a plurality of historical examples of source code that does not contain the source code.

12. The method of claim 8, wherein the machine learning model is trained as a binary classification model, the binary classification model taking the minimum subgraph as input and generating a classification indicating whether the minimum subgraph indicates an exemption or a genuine violation as output.

13. The method of claim 8, further comprising, in response to a human operator verifying that the exemption is valid, adding the minimum subgraph to a set of minimum subgraphs for determining whether a third violation generated by a static lint checking tool that analyzes source code should be exempted, wherein each minimum subgraph in the set of minimum subgraphs represents an existing exemption previously generated for a violation previously analyzed by the static lint checking tool that analyzes source code.

14. The method of claim 13, further comprising: Transform the third violation into a new directed graph; Extract a new minimum subgraph representing the third violation from the new directed graph; Transform the new minimum subgraph into a first vector; Calculate multiple graph similarities, wherein each graph similarity represents the similarity between the first vector and a vector in a set of vectors, wherein each vector in the set of vectors is derived from a minimum subgraph in the set of minimum subgraphs; The graph similarity among the plurality of graph similarities is determined to be at least equal to the threshold similarity; and In response to determining that the graph similarity among the plurality of graph similarities is at least equal to the threshold similarity, an exemption is generated for the third violation.

15. The method of claim 13, further comprising: Transform the third violation into a new directed graph; Extract a new minimum reduced subgraph representing the third violation from the new directed graph; Transform the new minimum reduced subgraph into a first vector; Calculate multiple graph similarities, wherein each graph similarity represents the similarity between the first vector and a vector in a set of vectors, wherein each vector in the set of vectors is derived from a minimum reduced subgraph in the set of minimum reduced subgraphs; It is determined that none of the graph similarities among the plurality of graph similarities is at least equal to the threshold similarity; and In response to determining that no graph similarity among the plurality of graph similarities is at least equal to a threshold similarity, the third violation is added to a set of existing violations in the source code.

16. A non-transitory computer-readable medium comprising stored instructions that, when executed by a processor, cause the processor to: Convert the source code used for register-transfer level design into a directed graph; Obtain the first violation generated by a static lint checker that analyzes the source code; Identify the violation statement subgraph in the directed graph that is associated with the first violation; Extract the minimum subgraph representing the first violation from the directed graph, wherein the violation statement subgraph includes the starting point of the minimum subgraph; Transform the minimum subgraph into a first vector; Calculate the graph similarity between the first vector and a second vector representing the second violation of the source code for which existing exemptions have been generated; The graph similarity is determined to be less than the threshold similarity. In response to the graph similarity being less than the threshold similarity, a machine learning model is executed, which predicts the probability that the minimum subgraph matches a second minimum subgraph of a different violation for which exemptions have been generated; Determine that the probability is at least equal to the threshold probability; and In response to the determination, an exemption is generated for the first violation.

17. The non-transitory computer-readable medium of claim 16, wherein converting the minimum subgraph into the first vector comprises using an abstract syntax tree parser to perform a top-down register transfer level code decompilation that converts each register transfer level module of the first violation into the directed graph.

18. The non-transitory computer-readable medium of claim 16, wherein extracting the minimum subgraph representing the first violation from the directed graph further enables the processor to: Based on the labels that mark the starting points of the illegal statement subgraphs in the directed graph, the illegal statement subgraphs are extracted from the directed graph; The violation statement subgraph is expanded with a subgraph of the block statement to produce an expanded violation statement subgraph, wherein the violation statement associated with the violation is part of the block statement; The extended illegal statement subgraph is expanded using a variable subgraph of the code statements of the directed graph that is computationally dependent on the variables of the extended illegal statement subgraph.

19. The non-transitory computer-readable medium of claim 16, wherein the graph similarity is cosine similarity.

20. The non-transitory computer-readable medium of claim 16, wherein the machine learning model comprises a graph convolutional network trained using a set of labeled minimum subgraphs of violations and exemptions from a plurality of historical examples of source code that does not contain the source code.

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