SPI interface software based on AD5781

Abstract

The invention discloses SPI interface software based on AD5781, and relates to the technical field of optical fiber gyroscopes. Comprising a pin configuration module, a clock configuration module, a frame format processing module, an SPI sequential logic module and a data framing sending module. The problem that high-speed and high-precision conversion of analog voltage data of the fiber-optic gyroscope is difficult to realize in the prior art is solved.

Description

Technical Field

[0001] This application relates to the field of fiber optic gyroscope technology, and in particular to SPI interface software based on AD5781. Background Technology

[0002] Upgrading and modifying fiber optic gyroscopes to possess the characteristics of other gyroscopes while retaining their own advantages has become a novel design approach. A key challenge is achieving breakthroughs in high-precision digital-to-analog conversion circuit design technology. This would allow the gyroscope to possess the analog voltage output characteristics of a liquid-floated gyroscope while also offering the advantages of a digital closed-loop fiber optic gyroscope, such as good vibration resistance, large dynamic range, resistance to harsh environments, magnetic field shielding, insensitivity to gravitational acceleration, ease of manufacturing, high yield, and low cost. Current design solutions are diverse, but none can fully achieve the high-speed, high-precision voltage conversion effect. Specifically, existing liquid-floated gyroscopes have complex manufacturing processes and large sizes, and their measurement accuracy, stability, and reliability still fall short of current requirements. Fiber optic gyroscopes, as a new type of all-solid-state gyroscope, have outstanding advantages such as being all-solid-state, digital, highly adaptable to various environments, and simple to apply, but they lack an analog output interface. Summary of the Invention

[0003] The purpose of this application is to provide SPI interface software based on AD5781 to solve the problem that existing technologies cannot achieve high-speed and high-precision conversion of analog voltage data from fiber optic gyroscopes.

[0004] To achieve the above objectives, this application adopts the following technical solution:

[0005] This application provides SPI interface software based on AD5781, including:

[0006] Pin configuration module, used to configure the functions of DA driver module and related interface I / O;

[0007] The clock configuration module is responsible for generating, distributing, and synchronizing the clock signals required by each module. It uses a crystal oscillator + PLL phase-locked loop scheme to multiply the 25MHz crystal oscillator to 100MHz.

[0008] The frame format processing module is automatically optimized into an advanced gate circuit through synthesis tools for determining the validity of signals in bit stream transmission; at the same time, it solves bit order alignment, timing synchronization, and valid signal handshake through parallel splicing of serial bit streams to avoid misreading; it generates receive and transmit pulses for receiving and transmitting data from the AD5781.

[0009] The SPI timing logic module uses the AD5781 for SPI bus communication. The software timing is matched with the AD5781's three-wire serial interface SYNC, SCLK, and SDIN. SYNC is the frame synchronization signal for serial input data; SCLK is the serial communication clock signal; and SDIN is the serial data input pin. The input pin updates the voltage output on the rising edge of SYNC. The SYNC, SCLK, and SDIN signals are generated through the FPGA chip's I / O pins and input to the AD5781 to achieve analog voltage-to-data conversion.

[0010] The data framing and transmission module receives the 24-bit wide DAC register to be transmitted as valid data, fills in each field according to the preset frame structure, including the frame header, 24 data bits, and calculates the CRC check value, and completes the SPI transmission frame assembly.

[0011] Optionally, the SPI timing logic module includes a working mode configuration submodule:

[0012] After powering on, the AD5780 must be placed in normal operating mode before its output can be programmed. The control register controls the operating mode of the AD5781. By writing the corresponding configuration word into the control register of the AD5781, the AD5781 enters normal operating mode. The AD5781's internal reference voltage and output amplifier can be configured by software to achieve dynamic switching of the output range. That is, the RBUF bit of the control register is set to logic 0, thereby configuring the output amplifier with a gain of 2 to achieve a bipolar output mode from a single-ended reference input.

[0013] Optionally, the SPI timing logic module also includes an SPI precise timing control submodule:

[0014] Once the control register is configured, data can be written to the AD5781. The input DAC register is 24 bits wide. Under the control of the serial clock SCLK with a maximum operating speed of 35MHz, the 24 bits of data are loaded into the device in MSB priority mode. The input DAC register includes R / W bits, 3 address bits, and 20 data bits.

[0015] Optionally, the SPI precise timing control submodule is also used to start the write cycle on the first falling edge of SYNC. At this time, the data is output bit by bit on the rising edge of SCLK and is valid on the falling edge of SCLK. After 24 falling edges of the clock, SCLK pulls SYNC high again. After the serial transmission is completed, the data is automatically transferred from the input shift register to the address register and appears on the SDIN line, thereby updating the output. The SPI precise timing control module pulls the SYNC signal low, and then sends the data bit by bit through the SCLK signal that is strictly matched to the sampling timing of AD5781. After the transmission is completed, SYNC is pulled high, and the system waits for AD5781 to complete the conversion.

[0016] Optionally, the ideal transfer function of the DAC is:

[0017]

[0018] Where: VREFN is the negative voltage applied to the VREFNS input pin; VREFP is the positive voltage applied to the VREFPS input pin; D is the 18-bit code written to the DAC, which controls the AD5781 to achieve digital-to-analog conversion.

[0019] Based on the above technical solution, this application can achieve the following technical effects:

[0020] This paper addresses the shortcomings of existing liquid-float gyroscopes by optimizing their design. Through key breakthroughs in high-precision digital-to-analog converter (DAC) circuit software design, and combining this with the deep integration and modular design principles of fiber optic gyroscopes, a software design based on the AD5781 is proposed. This effectively combines the liquid-float and fiber optic gyroscopes, retaining the analog voltage output characteristics of liquid-float gyroscopes while possessing the advantages of fiber optic gyroscopes such as good vibration resistance and tolerance to harsh environments. Furthermore, this software design effectively improves upon the limitations of existing DAC circuits, such as limited accuracy, complex operation, and inability to fully utilize the high precision of the AD5781, thus failing to meet the stringent requirements of high-end equipment for DAC conversion. This design has broad application prospects in the design of high-precision DAC circuits and the expansion of fiber optic gyroscope applications. Attached Figure Description

[0021] Figure 1 This is a block diagram illustrating the functional implementation of a DA driver module according to an embodiment of this application;

[0022] Figure 2 This is a timing diagram of the write mode provided in an embodiment of this application;

[0023] Figure 3 This is a software design flowchart provided in one embodiment of this application. Detailed Implementation

[0024] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present application will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and are not to scale, and are only used to facilitate and clarify the illustration of the embodiments of the present application.

[0025] It should be noted that, in order to clearly illustrate the content of this application, several embodiments are provided to further explain the different implementations of this application. These embodiments are enumerated rather than exhaustive. Furthermore, for the sake of brevity, content mentioned in the preceding embodiments is often omitted in the following embodiments. Therefore, content not mentioned in the following embodiments can be referred to in the preceding embodiments.

[0026] Example 1

[0027] The SPI interface software based on AD5781 provided in this embodiment includes:

[0028] Pin configuration module, used to configure the functions of DA driver module and related interface I / O;

[0029] The clock configuration module is responsible for generating, distributing, and synchronizing the clock signals required by each module. It uses a crystal oscillator + PLL phase-locked loop scheme to multiply the 25MHz crystal oscillator to 100MHz.

[0030] The frame format processing module is automatically optimized into an advanced gate circuit through synthesis tools for determining the validity of signals in bit stream transmission; at the same time, it solves bit order alignment, timing synchronization, and valid signal handshake through parallel splicing of serial bit streams to avoid misreading; it generates receive and transmit pulses for receiving and transmitting data from the AD5781.

[0031] The SPI timing logic module uses the AD5781 for SPI bus communication. The software timing is matched with the AD5781's three-wire serial interface SYNC, SCLK, and SDIN. SYNC is the frame synchronization signal for serial input data; SCLK is the serial communication clock signal; and SDIN is the serial data input pin. The input pin updates the voltage output on the rising edge of SYNC. The SYNC, SCLK, and SDIN signals are generated through the FPGA chip's I / O pins and input to the AD5781 to achieve analog voltage-to-data conversion.

[0032] The data framing and transmission module receives the 24-bit wide DAC register to be transmitted as valid data, fills in each field according to the preset frame structure, including the frame header, 24 data bits, and calculates the CRC check value, and completes the SPI transmission frame assembly.

[0033] In one specific embodiment, the software works as follows: Through an integrated solution of "precise timing generation + dynamic range switching + SPI anti-interference design," it achieves efficient control of the AD5781 by the FPGA. The specific technical solution is as follows:

[0034] The software uses the AD5781 digital-to-analog converter chip as the application platform to complete the Verilog HDL code design and application of SPI (Serial Peripheral Interface) in FPGA. The FPGA software needs to match the timing of the AD5781 three-wire serial interface (SYNC, SCLK and SDIN). The SYNC, SCLK and SDIN signals generated by the I / O pins of the FPGA chip drive the AD5781 DA chip to realize analog voltage data conversion.

[0035] The basic design unit in Verilog is the module. A module consists of two parts: one part describes the interface and the other part describes the logical function. It mainly includes port definitions, I / O descriptions, and internal signal declarations and functions.

[0036] 1. Initialization Phase -- Pin Configuration Module, Clock Configuration Module, and Data Transceiver Module

[0037] (1) Pin configuration module

[0038] like Figure 1 As shown, the left side is the module's input, and the right side is the module's output (the DA chip driven by the receiver).

[0039] As shown in Table 2, the relevant interface IO information is as follows.

[0040] Table 1 DA Driver Module IO Items

[0041]

[0042] (2) Clock configuration module

[0043] The FPGA clock module is the core of the system's timing stability, responsible for generating, distributing, and synchronizing the clock signals required by each module. The design uses a crystal oscillator + PLL phase-locked loop scheme, multiplying the 25MHz crystal oscillator to 100MHz to correct jitter and effectively avoid the drift problem of the RC oscillator. At the same time, it adopts a "state machine precise counting" design, with the SCLK frequency supporting adjustable steps from 1MHz to 50MHz. The setup / hold time of the SYNC signal is precisely controlled by a delay register, and the timing matching degree is improved by 90% compared with traditional IP cores.

[0044] (3) Frame format processing module

[0045] This module uses "combinational logic direct mapping" without relying on a clock. It is automatically optimized into high-level gate circuits by synthesis tools for signal validity judgment in bit stream transmission. At the same time, it solves bit order alignment, timing synchronization, and valid signal handshake by parallel splicing of serial bit streams to avoid misreading. It generates receive and transmit pulses for AD5781 to receive and transmit external data.

[0046] 2. Communication Phase – SPI Timing Logic Module

[0047] The AD5781 uses SPI bus communication, and the software must be compatible with the timing of the AD5781's three-wire serial interface (SYNC, SCLK, and SDIN). Figure 2 This is a timing diagram for the write mode, where SCLK is the frame synchronization signal for serial input data; SDIN is the serial communication clock signal; SDIN is the serial data input pin. When the input pin is low, the voltage output is updated on the rising edge of SYNC. The SYNC, SCLK and SDIN signals are generated by the I / O pins of the FPGA chip and input to the AD5781 to realize analog voltage data conversion.

[0048] (1) Working mode configuration module

[0049] After power-on, the AD5780 must be placed in normal operating mode before the output can be programmed. The control register controls the operating mode of the AD5781. Writing the corresponding configuration word (24'h200000) into the AD5781's control register will put the AD5781 into normal operating mode. The AD5781's internal reference voltage and output amplifier can be configured via software to achieve dynamic switching of the output range. Specifically, setting the RBUF bit of the control register to logic 0 configures the output amplifier with a gain of 2, enabling a bipolar output mode from a single-ended reference input. The specific configuration is shown in Table 4.

[0050] Table 4 Control Registers

[0051]

[0052] (2) SPI Precision Timing Control Module

[0053] Once the control register is configured, data can be written to the AD5781. The input DAC register is 24 bits wide. Under the control of the serial clock SCLK with a maximum operating speed of 35MHz, the 24 bits of data are loaded into the device in MSB priority mode. The input DAC register includes R / W bits, 3 address bits and 20 data bits. The specific configuration is shown in Table 5.

[0054] Table 5 DAC Registers

[0055]

[0056] according to Figure 2As shown in the write mode timing diagram, the maximum SCLK frequency is 35MHz, and this module uses 1.5625MHz, meaning each sampling clock cycle is 640ns. The write cycle is started on the first falling edge of SYNC. At this time, the data is output one by one on the rising edge of SCLK and is valid on the falling edge of SCLK. After 24 falling edges of SCLK, SYNC is pulled high again. After the serial transmission is completed, the data is automatically transferred from the input shift register to the address register and appears on the SDIN line, thereby updating the output. The SPI precise timing control module pulls the SYNC signal low, and then sends the data bit by bit through the SCLK signal that is strictly matched to the sampling timing of AD5781. After the transmission is completed, SYNC is pulled high, waiting for AD5781 to complete the conversion.

[0057] The ideal transfer function of a DAC is:

[0058]

[0059] Where: VREFN is the negative voltage applied to the VREFNS input pin; VREFP is the positive voltage applied to the VREFPS input pin; D is the 18-bit code written to the DAC, which controls the AD5781 to convert digital signals to analog signals. The specific software design flow is as follows: Figure 3 As shown.

[0060] 3. Data Frame Transmission Module

[0061] The system receives the 24-bit wide DAC register to be transmitted as valid data, fills in each field according to the preset frame structure, including the frame header, 24 data bits, and calculates the CRC check value, and completes the SPI transmission frame assembly. Through standardized frame structure design, it ensures that the receiving end can quickly identify the frame boundary and solve the frame synchronization problem of SPI transmission.

[0062] In summary, this paper addresses the numerous shortcomings of existing liquid-float gyroscopes through optimized design. By focusing on breakthroughs in high-precision digital-to-analog converter (DAC) circuit software design and combining it with the design principles of deep integration and modular functionality of fiber optic gyroscopes, a software design based on the AD5781 is proposed. This design effectively combines liquid-float and fiber optic gyroscopes, retaining the analog voltage output characteristics of liquid-float gyroscopes while possessing the advantages of fiber optic gyroscopes such as good vibration resistance and tolerance to harsh environments. Furthermore, this software design effectively improves upon the limitations of existing DAC circuits, such as limited accuracy, complex operation, and inability to fully utilize the high precision of the AD5781, thus failing to meet the stringent requirements of high-end equipment for DAC conversion. This design has broad application prospects in the design of high-precision DAC circuits and the expansion of fiber optic gyroscope applications.

[0063] The above description is merely an embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of this application should be included within the scope of the claims of this application.

Claims

1. SPI interface software based on AD5781, characterized in that, include: Pin configuration module, used to configure the functions of DA driver module and related interface I / O; The clock configuration module is responsible for generating, distributing, and synchronizing the clock signals required by each module. It uses a crystal oscillator + PLL phase-locked loop scheme to multiply the 25MHz crystal oscillator to 100MHz. The frame format processing module is automatically optimized into an advanced gate circuit through synthesis tools for determining the validity of signals in bit stream transmission; at the same time, it solves bit order alignment, timing synchronization, and valid signal handshake through parallel splicing of serial bit streams to avoid misreading; it generates receive and transmit pulses for receiving and transmitting data from the AD5781. The SPI timing logic module uses the AD5781 for SPI bus communication. The software timing is matched with the AD5781's three-wire serial interface SYNC, SCLK, and SDIN. SYNC is the frame synchronization signal for serial input data; SCLK is the serial communication clock signal; and SDIN is the serial data input pin. The input pin updates the voltage output on the rising edge of SYNC. The SYNC, SCLK, and SDIN signals are generated through the FPGA chip's I / O pins and input to the AD5781 to achieve analog voltage-to-data conversion. The data framing and transmission module receives the 24-bit wide DAC register to be transmitted as valid data, fills in each field according to the preset frame structure, including the frame header, 24 data bits, and calculates the CRC check value, and completes the SPI transmission frame assembly.

2. The SPI interface software according to claim 1, characterized in that, The SPI timing logic module includes a working mode configuration submodule: After powering on, the AD5780 must be placed in normal operating mode before its output can be programmed. The control register controls the operating mode of the AD5781. By writing the corresponding configuration word into the control register of the AD5781, the AD5781 enters normal operating mode. The AD5781's internal reference voltage and output amplifier can be configured by software to achieve dynamic switching of the output range. That is, the RBUF bit of the control register is set to logic 0, thereby configuring the output amplifier with a gain of 2 to achieve a bipolar output mode from a single-ended reference input.

3. The SPI interface software according to claim 1, characterized in that, The SPI timing logic module also includes an SPI precise timing control submodule: Once the control register is configured, data can be written to the AD5781. The input DAC register is 24 bits wide. Under the control of the serial clock SCLK with a maximum operating speed of 35MHz, the 24 bits of data are loaded into the device in MSB priority mode. The input DAC register includes R / W bits, 3 address bits, and 20 data bits.

4. The SPI interface software according to claim 3, characterized in that, The SPI precise timing control submodule is also used to start the write cycle on the first falling edge of SYNC. At this time, the data is output bit by bit on the rising edge of SCLK and is valid on the falling edge of SCLK. After 24 falling edges of the clock, SCLK pulls SYNC high again. After the serial transmission is completed, the data is automatically transferred from the input shift register to the address register and appears on the SDIN line, thereby updating the output. The SPI precise timing control module pulls the SYNC signal low, and then sends the data bit by bit by the SCLK signal that is strictly matched to the sampling timing of AD5781. After the transmission is completed, SYNC is pulled high, and the module waits for AD5781 to complete the conversion.

5. The SPI interface software according to claim 1, characterized in that, The ideal transfer function of a DAC is: Where: VREFN is the negative voltage applied to the VREFNS input pin; VREFP is the positive voltage applied to the VREFPS input pin; D is the 18-bit code written to the DAC, which controls the AD5781 to achieve digital-to-analog conversion.

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