Automatic wiring method for Chiplet

Abstract

The invention discloses an automatic wiring method for Chiplet. The method comprises the following steps: S1, preprocessing; the method comprises the following steps: acquiring Chiplet wiring data, splitting a multi-end wire network into two-end wire networks, performing via hole planning and terminal point distribution of an FA wire network, and constructing global wiring map resources by using a Voronoi grid; step S2, planning an Inter-Chip line network; grouping, layer distribution, escape line sequence planning, escape point determination and punching area and wiring area division are carried out on the Inter-Chip line network, and an optimal fan-out mode is selected for each line network to determine a via hole position; s3, carrying out 3D-A * wiring; and based on global wiring map resources and planning results, performing wiring by using a 3D-A * algorithm with cross perception. According to the method, the global wiring function in 2.5 D Chiplet packaging is realized, and the wiring efficiency and the wiring quality in detailed wiring can be effectively improved.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation, and more specifically to an automatic routing method for chiplets. Background Technology

[0002] With the increasing demand for higher chip integration density, better electrical performance, lower timing delays, and shorter vertical interconnects, semiconductor products are evolving from two-dimensional to three-dimensional, leading to the emergence of advanced packaging technologies such as flip-chip and 2.5D packaging. These technologies not only provide strong support for improving the performance, reducing power consumption, and miniaturizing the size of integrated circuits, but also play a crucial role in driving electronic products towards higher integration, smaller size, and lower cost.

[0003] In 2.5D package routing, the redistribution layer (RDL) plays a crucial role. Inside the package, the RDL is used to connect the input / output (I / O) pads and the bottom bump pads. Figure 1 This illustrates the structure of a multi-chip, multi-layer RDL package. Multiple RDLs are used beneath the multiple chips to redistribute signal connections. These RDLs consist of alternating stacked via layers and wiring layers, with the top RDL connected to I / O pads and the bottom RDL connected to the bottom C4 Bump pad.

[0004] 2.5D package routing can be understood as routing on the RDL. RDL routing problems can be divided into three types: (1) Free-Assignment (FA Net) routing, (2) Pre-Assignment (PA Net) routing, and (3) Inter-Chip Net routing. In Free-Assignment net routing, the router can freely connect a net between any I / O Pad and any Bump Pad. In Pre-Assignment net routing, the net connection between the I / O Pad and the Bump Pad is predefined before routing. In Inter-Chip net routing, the nets are defined in two dies respectively.

[0005] For 2.5D package routing with multiple chips and multiple RDL layers, the routing scenarios and problems are complex, and the number of routing nets is extremely large. Due to the sharp increase in routing scale, it is necessary to break down the routing problem into global routing and detailed routing. Global routing provides routing guidance for detailed routing, and detailed routing completes the final signal line connection under the guidance of global routing.

[0006] Therefore, designing a global routing method for 2.5D Chiplet packages, which can complete layer allocation and reduce routing length while satisfying rule constraints, has become an urgent problem to be solved in the current technical field. Summary of the Invention

[0007] The main objective of this invention is to provide an automatic routing method for Chiplet packages to complete global routing for 2.5D Chiplet packages.

[0008] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: In a first aspect, the present invention provides an automatic routing method for Chiplet, the method comprising: Step S1: Preprocessing; Obtain Chiplet routing data, split multi-terminal nets into two-terminal nets, perform via planning and FA net endpoint allocation, and construct a global routing map resource using Voronoi grid; Step S2: Inter-Chip Net Planning; Grouping, layering, planning escape sequence, determining escape points, and dividing the via area and routing area for the Inter-Chip net, and selecting the optimal fan-out mode for each net to determine the via location; Step S3: 3D-A* routing; Based on the global wiring map resources and planning results, the 3D-A* algorithm with cross-awareness is used for routing.

[0009] Following the above technical solution, the via planning includes: (1) Through-hole planning preprocessing; For PA nets, vias are set at the positions of I / O pads and bump pads in each redistribution layer; For FA nets, the position of the bump pads is optimized using the simulated annealing algorithm (SA) to convert the FA nets into PA nets. Similarly, vias are set at the positions of the I / O pads and bump pads in each redistribution layer. The optimization objectives of the simulated annealing algorithm (SA) include the number of crossovers and the length of the flying wires. (2) Final processing of via planning; Divide the cabling map into areas of equal size; Project the I / O pads, bump pads, and via information from the previous layer, as well as the C4 Bump layer information, onto the current redistribution layer. If the number of pads in the projected area is less than a preset value, a new via is generated at the center of the area. After global routing is complete, delete any unused vias.

[0010] Following the above technical solution, the initial solution of the simulated annealing algorithm SA is obtained. For each I / O pad in the FA net, select the nearest bump pad to match it; The perturbation rules include: swapping the bump pads of two FA nets and reselecting an unselected bump pad for the FA net.

[0011] Following the above technical solution, a global wiring map resource is constructed using Voronoi grids, including: Identify escape zones and non-escape zones within the cabling area. Use a regular quadrilateral grid in the escape zone and a Voronoi grid in the non-escape zone. The escape zone is used for routing Inter-Chip nets, while the non-escape zone includes PA and FA areas for routing PA and FA nets. Based on the via planning results, routing nodes are constructed at the midpoint of each Voronoi edge and at the via location as global routing resources. The capacity of the routing node at the midpoint of the Voronoi edge is set according to the length of the Voronoi edge and the line width and line spacing. The capacity of the via routing node is 1. Each time a routing node passes through the midpoint of a Voronoi edge, two new routing nodes are generated on both sides based on the trace width and spacing. For routing nodes that are not at the midpoint of a Voronoi edge, a new routing node is generated on one side of it. When generating new routing nodes, the set capacity is guaranteed to be exceeded.

[0012] Based on the above technical solution, the groups include: Obtain the netlist information after net splitting and net classification, and divide the Inter-Chip net into multiple groups according to the connection relationship between different devices. That is, the Inter-Chip net is split into two interconnected sub-models according to the group. For each sub-model, it is divided into several groups according to the physical location of the pads; Layer allocation includes: For each group, determine the escape boundary and boundary capacity, and allocate the pads of each group to different redistribution layers according to the boundary capacity: if the escape boundary is sufficient for all pads in the group to escape, then only one redistribution layer is used to route all pads in the group; otherwise, all pads in the group are divided into multiple parts from left to right, and each part corresponds to one redistribution layer. Escape sequence planning includes: For each group, all pads in each redistribution layer are divided into upper and lower parts. The order of the upper part of the pads is arranged first, and the order of the lower part of the pads is arranged last. The upper and lower parts form a topological disk. The assigned line order is expanded on both sides of the escape point and the order is the same, so as to transform the simultaneous escape routing into ordered escape routing and obtain the escape order on the escape boundary. Determining the escape point includes: After determining the escape order, the order is expanded from left to right to the escape boundary; for the pads in the upper half, the expansion is carried out from top to bottom, and for the lower half, the expansion is carried out from bottom to top, in order to determine each escape point.

[0013] Following the above technical solution, the division between the drilling area and the wiring area includes: Each redistribution layer is divided into a via area, a routing via area, and a blank area. The via area is where the netting from the next redistribution layer remains in the via area of ​​the previous redistribution layer. The routing via area contains both vias and routing. The blank area contains neither vias nor routing. Specifically: Each redistribution layer is as follows: the nets of the bottom redistribution layer remain in the via area of ​​the current redistribution layer, and the nets of the next redistribution layer remain in the via area, routing hole area, and blank area of ​​the current redistribution layer; the first redistribution layer has no blank area, and the bottom redistribution layer has no hole area.

[0014] Following the above technical solution, the optimal fan-out mode is selected for each net to determine the via location, including: Each pad is configured with four fan-out directions, and each fan-out direction is configured with three fan-out modes, resulting in a total of 12 fan-out modes for each pad. For each pad, an optimal fan-out mode is selected based on evaluation metrics, and the hole location is finally determined. The evaluation metrics include: whether it is located within the hole area, whether it conflicts with other nets in the RDL layer, and the line length.

[0015] Following the above technical solution, step S3 includes: For PA, FA, and Inter-Chip meshes, the 3D-A* algorithm with cross-awareness is used for routing. For each Voronoi mesh, a disk model is generated to determine whether the routing crosses, thus achieving cross-awareness, and congestion is calculated to assess the congestion level.

[0016] In a second aspect, the present invention provides a computer device / apparatus / system, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the method described in the first aspect.

[0017] Thirdly, the present invention provides a computer-readable storage medium having a computer program / instructions stored thereon, which, when executed by a processor, implement the steps of the method described in the first aspect.

[0018] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects: This invention provides an automatic routing method for chiplets, which realizes global routing functionality in 2.5D chiplet packages and can effectively improve routing efficiency and quality in detailed routing. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of an existing multi-chip, multi-layer RDL package; Figure 2 This is a schematic diagram of the multi-terminal wire mesh splitting process according to an embodiment of the present invention; Figure 3A This is a schematic diagram of a multi-terminal wire mesh before splitting according to an embodiment of the present invention; Figure 3B This is a schematic diagram of a multi-terminal wire mesh after splitting according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the via planning process according to an embodiment of the present invention; Figure 5 This is a schematic diagram illustrating the allocation of FA IO endpoints according to the proximity principle in an embodiment of the present invention; Figure 6 This is a schematic diagram of SA-optimized FA Nets and PA Nets according to an embodiment of the present invention; Figure 7 This is a schematic diagram of a wiring area divided into bins of equal size according to an embodiment of the present invention; Figure 8A This is a schematic diagram of the escape zone grid according to an embodiment of the present invention; Figure 8B This is a schematic diagram of a non-escape zone grid according to an embodiment of the present invention; Figure 9 This is a schematic diagram illustrating the determination of wiring nodes according to an embodiment of the present invention; Figure 10 This is a schematic diagram of the overall process of the Inter-Chip according to an embodiment of the present invention; Figure 11 This is a schematic diagram illustrating the determination of the escape boundary according to an embodiment of the present invention; Figure 12 This is a schematic diagram of the two-layer allocation result according to an embodiment of the present invention; Figure 13 This is a schematic diagram of line sequence planning and line sequence topology disk according to an embodiment of the present invention; Figure 14 This is a schematic diagram of the escape point distribution of the left-side device according to an embodiment of the present invention; Figure 15 This is a schematic diagram of the escape point distribution of the right-hand device according to an embodiment of the present invention; Figure 16 This is a schematic diagram of region division according to an embodiment of the present invention; Figure 17This is a schematic diagram of the surface fan-out mode according to an embodiment of the present invention; Figure 18 This is a schematic diagram of the hole position planning according to an embodiment of the present invention; Figure 19 This is a schematic diagram of a congestion assessment model according to an embodiment of the present invention; Figure 20A This is a schematic diagram illustrating the overall operation results of an embodiment of the present invention; Figure 20B This is a schematic diagram of surface fan-out perforation according to an embodiment of the present invention; Figure 20C This is a schematic diagram of the first layer routing of an RDL according to an embodiment of the present invention; Figure 20D This is a schematic diagram of the second layer routing of the RDL according to an embodiment of the present invention; Figure 20E This is a schematic diagram of the PA wire mesh routing according to an embodiment of the present invention; Figure 21 This is a flowchart illustrating an embodiment of the automatic routing method for Chiplet according to the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. All other embodiments obtained by those skilled in the art based on the embodiments provided by this invention without inventive effort are within the scope of protection of this invention.

[0021] Obviously, the accompanying drawings described below are merely some examples or embodiments of the present invention. Those skilled in the art can apply the present invention to other similar scenarios based on these drawings without any inventive effort. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this invention, modifications to design, manufacturing, or production based on the technical content disclosed in this invention are merely conventional technical means and should not be construed as insufficient disclosure of the present invention.

[0022] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this invention may be combined with other embodiments without conflict.

[0023] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "a," "an," "an," "the," and similar words used in this invention do not indicate quantity limitation and may indicate singular or plural. The terms "comprising," "including," "having," and any variations thereof used in this invention are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms "connected," "linked," "coupled," and similar words used in this invention are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "A plurality" used in this invention refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships may exist; for example, "A and / or B" can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects have an "or" relationship. The terms "first," "second," and "third" used in this invention are merely to distinguish similar objects and do not represent a specific ordering of the objects.

[0024] As routing scenarios become increasingly complex and routing resources become more limited, current algorithms struggle to handle the routing regions of 2.5D Chiplet packages in complex multi-terminal scenarios. To improve the processing capability for complex 2.5D Chiplet package routing scenarios, improvements are needed tailored to specific routing scenarios. Regarding the region partitioning problem for multi-terminal 2.5D Chiplet packages, the following issues still require further research: (1) As the scale of the circuit increases, the wiring area increases dramatically, and the traditional area division method is very limited. There is an urgent need for a new area division method.

[0025] (2) For 2.5D Chiplet packages, current research cannot solve the problem of simultaneous escape of nets, nor can it solve some nets with unassigned endpoints well. Assignment is required during the routing process.

[0026] (3) The current routing algorithm does not take into account the layer allocation problem, which makes the final routing very difficult.

[0027] To this end, this invention proposes an automatic routing method for Chiplet, which includes: (1) Preprocessing: reading Chiplet data, splitting multi-end nets, via planning, Free-Assignment IO endpoint allocation, and constructing routing map resources using Voronoi grids; (2) Inter-Chip net planning: dividing the areas for vias and routing, ensuring topology compatibility by adjusting the wiring sequence within each group, selecting an optimal fan-out mode for each net, ensuring maximum utilization of routing resources, obtaining layer allocation information, and optimizing line length to a certain extent; (3) 3D-A* routing: using 3D-A* routing with cross-awareness to route the planned results. This invention realizes global routing functionality in 2.5D Chiplet packaging, which can effectively improve routing efficiency and quality in detailed routing.

[0028] like Figure 21 As shown, the automatic routing method for Chiplet according to an embodiment of the present invention includes: Step S1: Preprocessing; Obtain Chiplet routing data, split multi-terminal nets into two-terminal nets, perform via planning and FA net endpoint allocation, and construct a global routing map resource using Voronoi grid; Step S2: Inter-Chip Net Planning; Grouping, layering, planning escape sequence, determining escape points, and dividing the via area and routing area for the Inter-Chip net, and selecting the optimal fan-out mode for each net to determine the via location; Step S3: 3D-A* routing; Based on the global wiring map resources and planning results, the 3D-A* algorithm with cross-awareness is used for routing.

[0029] Specifically, step S1 includes: S11. Preprocessing: Net splitting and classification.

[0030] For multi-terminal nets, a minimum spanning tree is used for splitting, and each branch of the minimum spanning tree is used as the connection relationship for the new two-terminal nets after the split, such as... Figure 2 As shown. After splitting the multi-terminal net, all nets become two-terminal nets, as follows. Figure 3A and Figure 3B As shown.

[0031] S12, Pre-processing: Via planning.

[0032] Via planning can be divided into two parts: the first part is Pre-Via Planning (pre-processing), and the second part is Via Planning (final processing). Figure 4 As shown.

[0033] Pre-Via Planning can be divided into two parts. The first part is to set up vias for the PA Net, and to set vias for the positions of I / O pads and bump pads in each layer of RDL.

[0034] The second part is the SA optimization of the FA Net's bump pad location selection, which converts the FA Net into a PA Net. The SA allocates a suitable bump pad for each unallocated FA Net IO to minimize the total flying wire crossover and bus length cost. Its pseudocode is shown in Table 1.

[0035] Table 1 Pseudocode: SA Optimization of FA Net Bump Pad Location Selection

[0036] Optimization Objective It consists of the number of crosses of the fly wire and the length of the fly wire, as shown in the formula below: ; in, This represents the total number of crossovers in the flying lines. This represents the total length of the fly wire.

[0037] Initial solution For each I / O pad in the FA Net, a nearby bump pad is selected for matching. There are two rules for perturbation: one is to swap the bump pads in the two FA Nets, and the other is to select a bump pad that has not been selected before.

[0038] Before SA optimization, the nearest bump pad for each FA IO is selected as its temporary endpoint. The result of this proximity principle allocation is used as the initial solution for SA, as shown in the example below. Figure 5 As shown. By Figure 5 It can be seen that, even after allocation based on the proximity principle, 13 flying wires still exist. After SA optimization, in this embodiment, all PA Net and FANet flying wires can be made free of intersection, such as... Figure 6 As shown. Orange dots represent I / O pads in FA Nets, yellow dots represent I / O pads in PA Nets (those without flywire interconnections are "VSS" or "VDD" networks), blue dots represent bump pads, and gray dots represent bump pads in "VSS" or "VDD" networks.

[0039] Depend on Figure 6As can be seen, there are no trace intersections between the results after iterative optimization. After obtaining the connection information in the FA Nets, the FA Nets can be converted into PA Nets, and the punching rules for the PA Nets in the previous step can be used to punch holes in these successfully paired FA Nets.

[0040] After determining the pre-drilling information for Pre-Via Planning, the following section will introduce Via Planning.

[0041] First, divide the cabling map into bins (regions) of equal size, such as... Figure 7 As shown.

[0042] After obtaining the partitioned bins, the information from the previous layer (I / O pads, bump pads, and Via) and the information from the C4 bumps layer are projected into the current RDL layer. If the number of pads in the bin after projection is less than 2, a new via is generated at the center of the bin. The pseudocode is shown in Table 2.

[0043] Table 2 Pseudocode: Via Planning

[0044] The number of vias generated in this way is obviously quite large. After global routing is completed, unused vias will be deleted.

[0045] S13. Preprocessing: Voronoi mesh construction and global wiring map construction.

[0046] Before constructing the Voronoi mesh, escape regions and non-escape regions are automatically identified. A regular quadrilateral mesh is used in the escape region, and a Voronoi mesh is used in the non-escape region. Via planning yields via information for each layer, and the Voronoi mesh is generated based on this information. Figure 8A and Figure 8B As shown: Due to the uniqueness of the 2.5D Chiplet package, the routing area can be roughly divided into PA and FA regions for routing, and an escape region. The PA and FA regions are used for PA Net and FA Net routing, and the escape region is used for Inter-Chip Net routing.

[0047] Because the mesh density is high in the escape region, the Voronoi mesh performs poorly in the escape routing section. Therefore, this dynamic meshing is adopted to adapt to the routing in the PA and FA regions as well as the routing in the escape region.

[0048] After constructing the Voronoi mesh, routing nodes are created at the midpoint of each Voronoi edge and at via locations as global routing resources. Each routing node has its own capacity, and the capacity of the via routing node VN is 1. The capacities of edge nodes EN are as follows: ; in, Let be the capacity of the edge node. Let this be the length of the Voronoi edge. For line width, This refers to the line spacing.

[0049] The node capacity is the number of traces that can actually pass through the node in subsequent routing.

[0050] S14. Preprocessing: Construction of cabling resources.

[0051] First, a routing node is generated at the midpoint of each Voronoi edge. Each time this routing node is passed, new routing nodes are added to its vicinity. For example... Figure 9 As shown, firstly, we generate a routing node (l, u, r, d) at the midpoint of each Voronoi edge. After routing line b passes through routing node (l, r), two new routing nodes will be generated on both sides of it according to the line width + line spacing. For routing nodes that are not at the midpoint ( , , , Then a new wiring node is generated on one side of it.

[0052] S2, Inter-Chip Network Planning: Analysis and Description of Problems in Global Routing for Inter-Chip Net.

[0053] During the routing of Inter-Chip nets, due to the large number and dense distribution of Inter-Chip nets, a lack of a reasonable Inter-Chip routing scheme may lead to routing loops or even routing failures. The key to the rationality of an Inter-Chip routing scheme lies in whether the IOPads within the Inter-Chip nets can successfully escape to the device boundary and whether they can be successfully connected in the channel area. Therefore, the routing problem of Inter-Chip nets can be considered as the escape problem of IOPads under this net.

[0054] The input for this stage is the netlist information after net splitting and net classification, which mainly includes the following parts: (1) Devices: Let the set ,in This represents a basic device, and each device consists of a pin list and a parameter list. The parameter list represents the device's dimensions and positional information. In this project, there are four devices: U1, U2, U3, and C4 Bumps. U1, U2, and U3 are on the same plane, while C4 Bumps is on another plane. For now, we will not consider the C4 Bumps device.

[0055] (2) Net: Let the set ,in This represents a net, and each net contains several pins, which contain relevant location information and connection relationships. In this section, only Inter-Chip nets are included; other nets are not considered.

[0056] Figure 10 The overall process for Global Routing for Inter-Chip is as follows: First, input the netlist information after netlist splitting and classification. Divide the Inter-Chip net into multiple groups according to the connection relationships between different devices. Each group is then further divided into interconnected sub-models. For each sub-model, it is first divided into several subgroups based on physical location, and each subgroup is analyzed separately. For each subgroup, first determine the escape boundary and boundary capacity. Allocate Pads layers for each group based on the boundary capacity. For the layer allocation results of each subgroup, plan a topology-compatible routing sequence (calculated separately for each layer). Then, convert the sequence into defined escape points and escape order. Construct a Hanan mesh on the surface layer, and build a routing map based on the mesh, where edges represent capacity. Each cell stores the routing results to prevent trace crossings. Perform surface layer fan-out vias according to the fan-out mode selection principle, and then perform RDL layer routing. This is the overall process for Global Routing for Inter-Chip.

[0057] S21, Inter-Chip Network Planning: Pads Grouping.

[0058] After dividing the escape region, calculate the y-axis coordinate difference between all Pads within the escape region, and record the minimum y-axis coordinate difference as y-axis coordinate difference. The difference in Pads y-axis coordinates of all Inter-Chip meshes is... They are grouped together.

[0059] S22, Inter-Chip Network Planning: Layer Allocation.

[0060] like Figure 11As shown, first, the escape boundary of the Pads after initial grouping is determined, and the number of wires that the escape boundary can accommodate is estimated. Then, the Pads are divided into multiple layers according to the Bus line and differential line. When the escape boundary is sufficient for all Pads in the group to escape, only one layer is needed to connect all Pads in the group. The two-layer allocation result is as follows. Figure 12 As shown, device 1 is to the left of the escape boundary, and device 2 is to the right of the escape boundary. Device 1 and device 2 each have two blue boxes representing all the pads in the box. Pads in the same device are divided into left and right parts, and the corresponding connection relationship is shown by the arrow.

[0061] If there are many pads in the same device, it can be divided into several regions. Connect the leftmost parts of the devices on both sides of the escape boundary as one layer, and then expand to the right.

[0062] S23, Inter-Chip Network Planning: Escape Sequence Planning.

[0063] Due to the large scale of the scene, selecting a reasonable sequence and planning a reasonable position on the escape boundary can effectively reduce the line length and avoid topological intersections in the channel area.

[0064] Line sequence planning such as Figure 13 As shown, the pads within the same group are divided into two parts, with the upper part's pads ordered first and the lower part's pads ordered last. This reduces the sum of the Manhattan distances from all pads to the escape point when assigning escape points. Simultaneously, the upper and lower parts each form a topological disk, as shown... Figure 13 As shown in the right figure, the assigned line sequence unfolds on both sides of the escape point, requiring that the sequence on both sides be exactly the same, which means that there are no topological intersections in the channel area.

[0065] After completion, the simultaneous escape routing will be transformed into ordered escape routing. At the same time, the escape order at the boundary can be obtained.

[0066] S24, Inter-Chip Network Planning: Escape Point Determination.

[0067] Through the above steps, an order of pairwise connected models at their boundaries can be obtained. After obtaining the order of all pairwise models, for the escape point distribution of the left device, these orders are expanded to the escape boundary in an increasing order from left to right. For the Pads in the upper half of the left device, the expansion follows a top-to-bottom pattern on the escape boundary, while the lower half is expanded from bottom to top, as shown below. Figure 14 As shown. For the device on the right, as... Figure 15 As shown.

[0068] The escape point is determined as a pass point of the escape region and used for subsequent 3D-A* algorithm routing.

[0069] S25, Inter-Chip Network Planning: Regional Division.

[0070] Because vias allocated to nets on RDL2 layer can affect the routing of nets on RDL1 layer, since the pad distribution between the two devices is basically consistent, if the left half of device one is allocated to RDL1 layer, then the right half of device one will affect the routing of the left half. Figure 12 If the routing is distributed, the left half of device 2 will affect the right half of the routing. Therefore, there will always be a device whose via near the escape boundary will affect the other part of the routing, which is unavoidable.

[0071] To prevent the vias in the RDL2 layer from affecting the routing in the RDL1 layer, the vias in the RDL2 layer need to be allocated outside the routing area of ​​the RDL1 layer. Therefore, the division between the via area and the routing area is extremely important.

[0072] Specific regional divisions are as follows: Figure 16 It is divided into a punched area, a routing punched area, and a blank area. The punched area is the hole left on the RDL1 layer for the net of the left device on the RDL2 layer. The punched routing area is the area with both punched holes and routing. In this area, the blue solid-filled area is the routing area, the blank area is the punched area, and the last area is the blank area, which has neither punched holes nor routing.

[0073] In the diagram, the gray rectangle in the middle represents the escape boundary. The device to the left of the escape boundary is the left device, and the device to the right of the escape boundary is the right device. The left device is divided into two parts: the left half is the net assigned to the RDL2 layer, and the right half is the net assigned to the RDL1 layer. The same applies to the right device.

[0074] By separating the routing area from the punching area, the holes generated by the nets allocated in the RDL2 layer can be cleverly avoided from affecting the routing of other nets.

[0075] Each redistribution layer consists of the following: the nets of the bottom redistribution layer remain in the via area of ​​the current redistribution layer, and so on up to the nets of the next redistribution layer, which remain in the via area, routing via area, and blank area of ​​the current redistribution layer; the first redistribution layer has no blank area, and the bottom redistribution layer has no via area. If there is an additional redistribution layer, an additional routing via area is required on the right side of the escape boundary between RDL1 and RDL2 layers.

[0076] S26, Inter-Chip mesh planning: Hole location planning.

[0077] After the area division is completed, the positions of the holes need to be allocated in the punching area to ensure that punching does not affect the routing of other wires.

[0078] Each pad has four fan-out directions, and each direction has three fan-out modes, resulting in a total of 12 fan-out modes for each pad. Figure 17 As shown. Each pad needs to find the most suitable direction for punching vias among 12 patterns and finally determine the position. The quality of the fan-out pattern is evaluated based on three indicators: whether it is within the punching area, whether it conflicts with other nets in the RDL layer, and the line length. After evaluating all patterns, the optimal pattern is selected and the punching position is finally determined.

[0079] The determination of whether there is a conflict with other nets in the RDL layer refers to a special case: in the hole planning, for the portion increasing from left to right, the x-coordinate of the holes in each pad must also be arranged from left to right; conversely, for the portion increasing from right to left, the x-coordinate of the holes in each pad must also be arranged from right to left. For example: Figure 18 In the diagram, the horizontal coordinate of hole #2 in the section increasing from left to right needs to be greater than the horizontal coordinate of hole #1, while the horizontal coordinate of hole #10 in the section increasing from right to left needs to be less than the horizontal coordinate of hole #9, and so on.

[0080] S31, 3D-A* routing: 3D A* algorithm with cross-awareness.

[0081] For the already processed Inter-Chip, FA, and PA meshes, actual routing is performed using 3D A* with cross-awareness. For each Voronoi mesh, a disk model is generated to determine whether the routing crosses. If the interconnects in the disk cross, the routing is considered to have crossed.

[0082] S32, 3D-A* routing: congestion assessment model.

[0083] After performing the above net planning, we obtain a topology-compatible net allocation for each layer. Finally, a path search method is needed to connect all the nets, which we achieve using the 3D-A* algorithm. Compared to the ordinary A* algorithm, 3D-A* includes a z-axis search to enable cross-layer search operations.

[0084] Based on the obtained wiring map, assuming the pins The corresponding point in the grid map is Set the starting point of The value is 0. Value , Add the starting point to the open list middle, For min-heaps; loop from pop-up The node with the smallest value is selected as the current node. Then, the neighboring nodes of the current node are traversed, and the minimum value is calculated for each neighboring node. Value, if the neighboring node is not present In the middle, then add it. And update In this node Nodes and Value; it's worth noting that when expanding the neighbors of the starting point, the expansion direction can be any eight directions in the same direction, as well as the up and down directions. When expanding the neighbors of a non-starting point node, the expansion direction can be restricted to avoid right-angle turns; during the iterative node retrieval process, if the retrieved node is the ending point... If the path search is successful, then the path search will proceed from the destination. Start iterating through the nodes. A node can trace back the connected path from its starting point to its ending point, if until... The endpoint was not retrieved even when the result was empty. This means There is no path between the two points; the above The specific formula for calculating the value is: ; Where x and y represent coordinates. Function It combines the characteristics of diagonal distance and Manhattan distance.

[0085] Since global routing is based on a Voronoi grid, the congestion assessment model proposed by the algorithm is also based on a Voronoi grid. The congestion assessment model is as follows: Figure 19 As shown. For each Voronoi grid that is traversed, its congestion degree is calculated. The congestion degree of a Voronoi grid is evaluated by C0 / C1.

[0086] The final wiring result is as follows Figures 20A to 20E As shown, the number of nets is 8862, the routing rate is 100%, the bus length is 8574888.816026, the number of vias used is 11065, and the total duration is 87.380412s.

[0087] In summary, for complex 2.5D Chiplet routing scenarios, this invention proposes a global routing method based on 2.5D Chiplet packaging. This method includes: (1) Preprocessing: reading Chiplet data, splitting multi-end nets, via planning, Free-Assignment IO endpoint allocation, and constructing routing map resources using Voronoi grids; (2) Inter-Chip net planning: dividing the areas for vias and routing, ensuring topology compatibility by adjusting the intra-group wiring sequence, selecting an optimal fan-out mode for each net, ensuring maximum utilization of routing resources, obtaining layer allocation information, and optimizing line length to a certain extent; (3) 3D-A* routing: using 3D-A* routing with cross-awareness to route the planned results. In a test of a large-scale board with 8862 nets, a routing rate of 100%, a bus length of 8574888.816026, 11065 vias used, and a total duration of 87.380412s. The effectiveness of the proposed method was verified through actual wiring results.

[0088] Furthermore, the present invention also provides a computer device / apparatus / system, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above-described method.

[0089] The present invention also provides a computer-readable storage medium having a computer program / instructions stored thereon, which, when executed by a processor, implement the steps of the above-described method.

[0090] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, systems, and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0091] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more blocks in a block diagram.

[0092] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable data processing apparatus to produce a computer-implemented process, thereby providing steps for implementing the functions specified in one or more flowcharts and / or one or more blocks in a block diagram.

[0093] It should be noted that, depending on the implementation needs, the various steps / components described in this invention can be broken down into more steps / components, or two or more steps / components or parts of the operation of steps / components can be combined into new steps / components to achieve the purpose of this invention.

[0094] Those skilled in the art will readily understand that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An automatic routing method for Chiplet, characterized in that, The method includes: Step S1: Preprocessing; Obtain Chiplet routing data, split multi-terminal nets into two-terminal nets, perform via planning and FA net endpoint allocation, and construct a global routing map resource using Voronoi grid; Step S2: Inter-Chip Net Planning; Grouping, layering, planning escape sequence, determining escape points, and dividing the via area and routing area for the Inter-Chip net, and selecting the optimal fan-out mode for each net to determine the via location; Step S3: 3D-A* routing; Based on the global wiring map resources and planning results, the 3D-A* algorithm with cross-awareness is used for routing.

2. The automatic routing method for Chiplet according to claim 1, characterized in that, Via planning includes: (1) Through-hole planning preprocessing; For PA nets, vias are set at the positions of I / O pads and bump pads in each redistribution layer; For FA nets, the position of the bump pads is optimized using the simulated annealing algorithm (SA) to convert the FA nets into PA nets. Similarly, vias are set at the positions of the I / O pads and bump pads in each redistribution layer. The optimization objectives of the simulated annealing algorithm (SA) include the number of crossovers and the length of the flying wires. (2) Final processing of via planning; Divide the cabling map into areas of equal size; Project the I / O pads, bump pads, and via information from the previous layer, as well as the C4 Bump layer information, onto the current redistribution layer. If the number of pads in the projected area is less than a preset value, a new via is generated at the center of the area. After global routing is complete, delete any unused vias.

3. The automatic routing method for Chiplet according to claim 2, characterized in that, Initial solution of simulated annealing algorithm SA For each I / O pad in the FA net, select the nearest bump pad to match it; The perturbation rules include: swapping the bump pads of two FA nets and reselecting an unselected bump pad for the FA net.

4. The automatic routing method for Chiplet according to claim 1, characterized in that, Constructing a global wiring map resource using Voronoi grids, including: Identify escape zones and non-escape zones within the cabling area. Use a regular quadrilateral grid in the escape zone and a Voronoi grid in the non-escape zone. The escape zone is used for routing Inter-Chip nets, while the non-escape zone includes PA and FA areas for routing PA and FA nets. Based on the via planning results, routing nodes are constructed at the midpoint of each Voronoi edge and at the via location as global routing resources. The capacity of the routing node at the midpoint of the Voronoi edge is set according to the length of the Voronoi edge and the line width and line spacing. The capacity of the via routing node is 1. Each time a routing node passes through the midpoint of a Voronoi edge, two new routing nodes are generated on both sides based on the trace width and spacing. For routing nodes that are not at the midpoint of a Voronoi edge, a new routing node is generated on one side of it. When generating new routing nodes, the set capacity is guaranteed to be exceeded.

5. The automatic routing method for Chiplet according to claim 1, characterized in that, Grouping includes: Obtain the netlist information after net splitting and net classification, and divide the Inter-Chip net into multiple groups according to the connection relationship between different devices. That is, the Inter-Chip net is split into two interconnected sub-models according to the group. For each sub-model, it is divided into several groups according to the physical location of the pads; Layer allocation includes: For each group, determine the escape boundary and boundary capacity, and allocate the pads of each group to different redistribution layers according to the boundary capacity: if the escape boundary is sufficient for all pads in the group to escape, then only one redistribution layer is used to route all pads in the group; otherwise, all pads in the group are divided into multiple parts from left to right, and each part corresponds to one redistribution layer. Escape sequence planning includes: For each group, all pads in each redistribution layer are divided into upper and lower parts. The order of the upper part of the pads is arranged first, and the order of the lower part of the pads is arranged last. The upper and lower parts form a topological disk. The assigned line order is expanded on both sides of the escape point and the order is the same, so as to transform the simultaneous escape routing into ordered escape routing and obtain the escape order on the escape boundary. Determining the escape point includes: After determining the escape order, the order is expanded from left to right to the escape boundary; for the pads in the upper half, the expansion is carried out from top to bottom, and for the lower half, the expansion is carried out from bottom to top, in order to determine each escape point.

6. The automatic routing method for Chiplet according to claim 1, characterized in that, The division between the drilling area and the wiring area includes: Each redistribution layer is divided into a via area, a routing via area, and a blank area. The via area is where the netting from the next redistribution layer remains in the via area of ​​the previous redistribution layer. The routing via area contains both vias and routing. The blank area contains neither vias nor routing. Specifically: Each redistribution layer is as follows: the nets of the bottom redistribution layer remain in the via area of ​​the current redistribution layer, and the nets of the next redistribution layer remain in the via area, routing hole area, and blank area of ​​the current redistribution layer; the first redistribution layer has no blank area, and the bottom redistribution layer has no hole area.

7. The automatic routing method for Chiplet according to claim 6, characterized in that, Select the optimal fan-out pattern for each net to determine the via location, including: Each pad is configured with four fan-out directions, and each fan-out direction is configured with three fan-out modes, resulting in a total of 12 fan-out modes for each pad. For each pad, an optimal fan-out mode is selected based on evaluation metrics, and the hole location is finally determined. The evaluation metrics include: whether it is located within the hole area, whether it conflicts with other nets in the RDL layer, and the line length.

8. The automatic routing method for Chiplet according to claim 1, characterized in that, Step S3 includes: For PA, FA, and Inter-Chip meshes, the 3D-A* algorithm with cross-awareness is used for routing. For each Voronoi mesh, a disk model is generated to determine whether the routing crosses, thus achieving cross-awareness, and congestion is calculated to assess the congestion level.

9. A computer device / equipment / system, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program / instructions stored thereon, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the method according to any one of claims 1 to 8.

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