Quantum bit working frequency allocation method and system and quantum computer
By presetting the initial operating frequency range and calibrating the logic gate parameters using a directed acyclic graph on the quantum processor, and combining this with random benchmark testing to select a suitable operating frequency, the crosstalk problem in qubit logic gate operations is solved, and the execution accuracy of the quantum computer is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ORIGIN QUANTUM COMPUTING TECH (HEFEI) CO LTD
- Filing Date
- 2024-10-30
- Publication Date
- 2026-05-08
AI Technical Summary
The logic gate operations of qubits in quantum computers are prone to errors, leading to interference. Existing technologies are unable to effectively reduce the crosstalk between qubits.
By presetting the initial operating frequency range of each qubit on the quantum processor, the logic gate parameters are calibrated using a directed acyclic graph, and the fidelity of the quantum state is obtained through random benchmark testing. The initial frequency value that meets the preset threshold is selected as the appropriate operating frequency.
This effectively reduces interference between qubits, ensures that each qubit operates at a suitable frequency, and improves the execution accuracy of quantum logic gates.
Smart Images
Figure CN121998111A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of quantum computing technology, and in particular to a method, system and quantum computer for allocating the operating frequency of qubits. Background Technology
[0002] Quantum computing and quantum information is an interdisciplinary field that uses the principles of quantum mechanics to perform computational and information processing tasks. It is closely related to quantum physics, computer science, and informatics. It has experienced rapid development in the last two decades. Quantum algorithms based on quantum computers in scenarios such as factorization and unstructured search have demonstrated performance far exceeding that of existing algorithms based on classical computers, leading to expectations that this field will surpass current computing capabilities. Because quantum computing has the potential to far exceed the performance of classical computers in solving specific problems, realizing a quantum computer requires a quantum processor containing a sufficient number and quality of qubits, capable of performing high-fidelity quantum logic gate operations and readouts on these qubits. The quantum processor is to a quantum computer what a CPU is to a traditional computer; it is the core component of a quantum computer, the processor that performs quantum computations. Before each quantum processor is officially put into use, the parameters of the qubits in the quantum processor must be tested and characterized.
[0003] For each qubit in a quantum processor, to complete as many computations as possible within its finite lifetime, the fastest possible qubit logic gates are required. Generally, the execution time of a qubit logic gate is three to four orders of magnitude faster than its lifetime. However, fast qubit logic gate operations can lead to errors during execution. There are many reasons for qubit logic gate errors, such as parasitic coupling between nearest and second nearest neighbor qubits, spectral spread level system (TLS) defects, parasitic microwave modes, coupling with control lines and readout resonators, frequency control electronics noise, frequency control pulse distortion, microwave control pulse distortion, and microwave carrier leakage. When each qubit in the quantum processor operates at an appropriate frequency, the effects of these interferences can be effectively reduced.
[0004] It should be noted that the information disclosed in the background section of this application is intended only to enhance the understanding of the general background of this application, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0005] The purpose of this application is to provide a method, system, and quantum computer for allocating the operating frequency of qubits, which can allocate the operating frequency of qubits on a quantum processor so that each qubit is at a suitable operating frequency, thereby effectively reducing the impact of interference.
[0006] To solve the above technical problems, the technical solution of this application is as follows:
[0007] The first aspect of this application proposes a method for allocating the operating frequency of qubits, including:
[0008] The initial operating frequency range of each qubit on the quantum processor is preset; wherein, the initial operating frequency range includes several initial frequency values;
[0009] The operating frequency of each qubit is set to the initial value, and the logic gate parameters of each qubit are calibrated according to a directed acyclic graph; wherein, the directed acyclic graph includes the qubit and several node graphs composed of the performance parameters of the resonant cavity coupled to the qubit;
[0010] A random benchmark test is performed on the calibrated logic gate parameters to obtain the initial frequency value of the frequency at which the fidelity of the quantum state of the qubit is within a preset threshold. The random benchmark test is used to test the correspondence between the fidelity of the quantum state of the qubit and the applied logic gate.
[0011] As described above, optionally, the initial operating frequency range of each qubit on the quantum processor is preset, including:
[0012] Obtain the first frequency of each of the qubits; wherein, the first frequency is the operating frequency at which the frequency of the qubit changes at the rate of least change with the control signal applied to the magnetic flux modulation line;
[0013] The initial operating frequency range is preset based on the first frequency; wherein, the first frequency is the cutoff frequency of the initial operating frequency range.
[0014] Optionally, the logic gate parameters of the method described above include characteristic parameters, readout parameters, and control parameters of the qubit and the resonant cavity. The operating frequency of each qubit is set to an initial frequency value, and the logic gate parameters of each qubit are calibrated according to a directed acyclic graph, including:
[0015] Obtain a directed acyclic graph consisting of several nodes, composed of the feature parameters, reading parameters, and control parameters;
[0016] Within the initial operating frequency range, several initial frequency values are traversed, and the characteristic parameters, the read parameters, and the control parameters are calibrated sequentially according to the node order of the directed acyclic graph.
[0017] Optionally, the method described above may involve performing random benchmark tests on the calibrated logic gate parameters, including:
[0018] The driving signals applied to the qubit are iterated so that the operating frequency of the qubit corresponds to each of the initial frequency values in the initial operating frequency range.
[0019] When the operating frequency of the qubit is each of the initial values of the frequency, a combination of logic gates and an inverse logic gate are applied to the qubit; wherein, the combination of logic gates includes several single quantum logic gates for controlling the quantum state of the qubit from the initial state to the target state, and the inverse logic gate is used to control the quantum state of the qubit from the target state to the initial state;
[0020] The fidelity of the quantum state of the qubit as the initial state is measured.
[0021] Optionally, in the method described above, the initial value of the frequency at which the fidelity of the quantum state of the qubit is within a preset threshold is the operating frequency to be assigned to the qubit, including:
[0022] Obtain the preset threshold;
[0023] When the fidelity is within the preset threshold, the initial frequency value is determined as the target operating frequency; wherein, a plurality of the target operating frequencies constitute a set of operating frequencies to be allocated;
[0024] When the fidelity is not within the preset threshold, the corresponding initial frequency value is discarded.
[0025] A second aspect of this application provides a method for characterizing a quantum processor, comprising:
[0026] Obtain the topological structure of qubits on a quantum processor;
[0027] The operating frequency of each of the qubits is allocated according to the topology and using the qubit operating frequency allocation method as described in any of the first aspects above.
[0028] A third aspect of this application provides a quantum bit operating frequency allocation system, comprising:
[0029] The parameter acquisition module is used to acquire the initial operating frequency range of each qubit on the preset quantum processor; wherein, the initial operating frequency range includes several initial frequency values;
[0030] The parameter calibration module is used to set the operating frequency of each qubit to the initial value of the frequency, and to calibrate the logic gate parameters of each qubit according to a directed acyclic graph; wherein the directed acyclic graph is a number of node graphs composed of the qubit and the performance parameters of the resonant cavity coupled to the qubit.
[0031] The frequency allocation module is used to perform random benchmark tests on the logic gate parameters of the qubit to obtain the initial frequency value of the qubit when the fidelity of the quantum state is within a preset threshold as the operating frequency to be allocated to the qubit; wherein, the random benchmark test is the correspondence between the fidelity of the quantum state of the qubit and the applied logic gate.
[0032] The fourth aspect of this application provides a quantum computing measurement and control system, characterized in that it utilizes a quantum bit operating frequency allocation method as described in any one of the first aspects above, or includes a quantum bit operating frequency allocation system as described in the third aspect above.
[0033] The fifth aspect of this application provides a quantum computer, including a quantum processor and a quantum computing measurement and control system as described in the fourth aspect above; or characterizes the operating frequency of qubits on the quantum processor using the method described in the second aspect above.
[0034] The sixth aspect of this application provides a readable storage medium having a computer program stored thereon, which, when executed by a processor, enables the allocation of the operating frequency of qubits on a quantum processor by the method described in any of the first aspects above.
[0035] Compared with the prior art, this application has the following beneficial effects:
[0036] This application first presets several initial frequency values within the initial operating frequency range. Then, it calibrates the logic gate parameters of each qubit according to a directed acyclic graph. Subsequently, at each initial frequency value of the qubit, it performs random benchmark tests using the calibrated logic gate parameters to obtain the correspondence between the quantum state fidelity of the qubit and the applied logic gate. By comparing the obtained fidelity with a preset threshold, the initial frequency value corresponding to the fidelity that meets the preset threshold requirement is selected as the qualified frequency value, which is used as the operating frequency to be assigned. This effectively reduces the impact of interference when each qubit is at a suitable operating frequency.
[0037] The quantum processor characterization method, qubit operating frequency allocation system, quantum computing measurement and control system, quantum computer, and readable storage medium proposed in this application belong to the same concept as the qubit operating frequency allocation method, and therefore have the same beneficial effects, so they will not be elaborated here. Attached Figure Description
[0038] Figure 1 This is a flowchart illustrating a method for allocating the operating frequency of qubits according to an embodiment of this application.
[0039] Figure 2 This is a schematic diagram of a process for setting an initial operating frequency range according to an embodiment of this application;
[0040] Figure 3 This is a schematic diagram of a process for calibrating the logic gate parameters of qubits according to a directed acyclic graph, as proposed in an embodiment of this application.
[0041] Figure 4 This is a schematic diagram of a directed acyclic graph proposed in an embodiment of this application;
[0042] Figure 5 This is a schematic diagram of a process for performing a random benchmark test according to an embodiment of this application;
[0043] Figure 6 This is a schematic diagram illustrating a process for allocating the operating frequency of qubits according to a preset threshold, as proposed in an embodiment of this application.
[0044] Figure 7 This is a flowchart illustrating a quantum processor characterization method proposed in an embodiment of this application.
[0045] Figure 8 This is a schematic diagram of a quantum bit operating frequency allocation system proposed in an embodiment of this application. Detailed Implementation
[0046] The specific embodiments of this application will be described in more detail below with reference to the schematic diagrams. The advantages and features of this application will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this application.
[0047] In the description of this application, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0048] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0049] A qubit is a two-level quantum system, which can be understood as an oscillator consisting of an inductor (i.e., a superconducting Josephson junction loop formed by two parallel superconducting Josephson junctions) and a capacitor connected in parallel. Its oscillation frequency can be understood as its operating frequency. By applying a microwave signal to the qubit to adjust the equivalent inductance of the inductor, the operating frequency of the qubit can be adjusted; that is, the operating frequency of the qubit is directly related to the applied microwave signal. Furthermore, when the applied microwave signal is affected by crosstalk, the operating frequency of the qubit changes.
[0050] When qubits execute quantum logic gates, their operating frequency must first be tuned to a set target frequency. If the operating frequency deviates from the target frequency, it directly affects the execution accuracy of the quantum logic gate; that is, crosstalk between qubits affects the execution accuracy. The crosstalk between qubits is related to the distance between them and the frequency difference. For example, when two qubits are close together on the quantum processor, the closer the frequency difference, the more significant the crosstalk. If the two qubits are far apart, the crosstalk is very weak, and the frequency difference has an even weaker impact on crosstalk. Therefore, it is necessary to allocate the operating frequencies of the multiple qubits on the quantum processor.
[0051] like Figure 1 As shown, this embodiment provides a method for allocating the operating frequency of qubits, including the following steps.
[0052] Step S10: Preset the initial operating frequency range for each qubit on the quantum processor; wherein the initial operating frequency range includes several initial frequency values.
[0053] The initial operating frequency range of the qubits can be predetermined, such as 4GHz-6GHz. Within this range, a step value can be set to obtain several initial frequency values. For example, setting the step value to 100kHz will yield 20 initial frequency values. Furthermore, adjacent qubits are coupled together via a coupler. This coupler is an adjustable coupler with a modulated operating frequency, which can also be preset.
[0054] It is conceivable that the larger the initial operating frequency range is set, and the more initial frequency values there are, the longer the time will be required to perform subsequent testing experiments. Furthermore, the operating frequency of a qubit is controlled by the applied modulation signal, and there is a sinusoidal correspondence between the qubit's operating frequency and the modulation signal; the rate of change of the qubit's operating frequency with the modulation signal is not constant.
[0055] like Figure 2 As shown, the following steps are used to set the initial operating frequency range in this step.
[0056] Step S101: Obtain the first frequency of each qubit; wherein, the first frequency is the operating frequency at which the frequency of the qubit changes the least with the rate of change of the control signal applied on the magnetic flux modulation line.
[0057] When the initial operating frequency range is preset, the first frequency of the qubit is first obtained. This frequency is the operating frequency at which the frequency of the qubit changes the least with the control signal applied to the magnetic flux modulation line. At this operating frequency, the rate of change is the smallest, that is, the change is very small with the applied control signal or when affected by crosstalk, resulting in better stability.
[0058] Step S102: Preset an initial operating frequency range based on the first frequency; wherein, the first frequency is the cutoff frequency of the initial operating frequency range.
[0059] Setting the initial operating frequency range using the first frequency as the cutoff frequency value ensures the stability of several initial frequency values, facilitating the stability of the operating frequency to be assigned through subsequent experiments. For example, the first frequency obtained in step S101 is 5200MHz, and the initial operating frequency range is preset to {4400MHz, 5200MHz}.
[0060] Step S20: Set the operating frequency of each qubit to an initial value, and calibrate the logic gate parameters of each qubit according to a directed acyclic graph; wherein, the directed acyclic graph includes the qubit and several node graphs composed of the performance parameters of the resonant cavity coupled to the qubit.
[0061] After several initial frequency values for the qubits are preset in step S10, the logic gate parameters of the qubits can be calibrated. In this step, the logic gate parameters can include not only the characteristic parameters of the qubits and resonant cavity, but also the signal parameters for controlling and measuring the qubits. These parameters are characterized using a directed acyclic graph.
[0062] A directed acyclic graph consists of several nodes, each corresponding to one of the parameters mentioned above. Each parameter needs to be calibrated, requiring different experiments and procedures, which will not be detailed in this embodiment. Calibration determines the logic gate parameters of the qubits, which can then be used in subsequent testing experiments.
[0063] Step S30: Perform a random benchmark test on the calibrated logic gate parameters to obtain the initial value of the frequency at which the fidelity of the quantum state of the qubit is within a preset threshold as the working frequency to be assigned to the qubit; wherein, the random benchmark test is used to test the correspondence between the fidelity of the quantum state of the qubit and the applied logic gate.
[0064] After calibrating the logic gate parameters of each qubit in step S20, a random benchmark test can be performed using the calibrated logic gate parameters. Specifically, the frequency of the qubit is tuned to one of its initial frequency values, and then a logic gate with calibrated parameters is applied to that qubit. The fidelity of the quantum state of that qubit is measured. The applied logic gate can be one or a combination of multiple gates. The test is repeated multiple times, and the fidelity of the quantum state of the qubit is determined based on the results of these multiple tests. The results obtained from these multiple tests are compared with a preset threshold. The initial frequency value that meets the preset threshold is considered qualified and is used as the working frequency to be assigned.
[0065] As described above, the operating frequency of a qubit directly affects the execution precision (i.e., fidelity) of the applied logic gates. Therefore, random benchmark tests are performed on several preset initial frequency values, and the fidelity of the quantum state in the test results can be used to determine whether the initial frequency value is a qualified frequency value, thereby realizing the allocation of the operating frequency of the qubit.
[0066] This application first presets several initial frequency values within the initial operating frequency range. Then, it calibrates the logic gate parameters of each qubit according to a directed acyclic graph. Subsequently, at each initial frequency value of the qubit, it performs random benchmark tests using the calibrated logic gate parameters to obtain the correspondence between the quantum state fidelity of the qubit and the applied logic gate. By comparing the obtained fidelity with a preset threshold, the initial frequency value corresponding to the fidelity that meets the preset threshold requirement is selected as the qualified frequency value, which is used as the operating frequency to be assigned. This effectively reduces the impact of interference when each qubit is at a suitable operating frequency.
[0067] like Figure 3 As shown, the logic gate parameters include the characteristic parameters of the qubit and the resonant cavity, the readout parameters, and the control parameters. The operating frequency of the qubit is set to the initial frequency value, and the logic gate parameters of each qubit are calibrated according to the directed acyclic graph, including the following steps.
[0068] Step S201: Obtain a directed acyclic graph consisting of feature parameters, read parameters, and control parameters, which includes several nodes.
[0069] Step S202: Traverse several initial frequency values within the initial operating frequency range, and calibrate the characteristic parameters, read the parameters, and control parameters in sequence according to the node order of the directed acyclic graph.
[0070] like Figure 4 The directed acyclic graph shown includes the resonant cavity frequency, bit frequency, frequency and power of the readout signal used to read the quantum state of the qubit, amplitude of the control signal used to control the quantum state of the qubit, and the qubit's T1 (relaxation time) and T2 (decoherence time), etc. Among these, Figure 4 The nodes and the logic gate parameters represented by each node are only examples. In the actual execution process, there are many more logic gate parameters. There are many kinds of logic gates used for quantum state control alone, such as Pauli gates (X gate, Y gate, Z gate) and Hartmann gates (H gate).
[0071] After obtaining the directed acyclic graph (DAG), calibration can be performed according to the type and specific meaning of the logic gate parameters defined for each node in the DAG. The calibration of each logic gate parameter involves executing the corresponding experiment and procedure.
[0072] In this embodiment, the logic gate parameters of the qubits are defined using a directed acyclic graph (DAG) and calibrated sequentially according to the DAG method to ensure the accuracy of the calibrated logic gate parameters, thereby ensuring the accuracy of the fidelity measured during subsequent random benchmark tests.
[0073] like Figure 5 As shown, as one implementation of this embodiment, performing random benchmark tests on the calibrated logic gate parameters may include the following steps.
[0074] Step S301: Iterate through the driving signals applied to the qubits so that the operating frequency of the qubits corresponds to the initial values of each frequency in the initial operating frequency range.
[0075] For each preset initial frequency value of a qubit, it needs to be controlled by an applied driving signal to make the qubit be at that initial frequency value.
[0076] Step S302: When the operating frequency of the qubit is the initial value of each frequency, apply a combination of logic gates and an inverse logic gate to the qubit; wherein, the combination of logic gates includes several single quantum logic gates, which are used to control the quantum state of the qubit from the initial state to the target state, and the inverse logic gate is used to control the quantum state of the qubit from the target state to the initial state.
[0077] Step S303: Measure the fidelity of the quantum state of the qubit as the initial state.
[0078] When performing random benchmark tests, a logic gate combination is first constructed. This combination includes several single quantum logic gates, such as the Pauli X gate, Pauli Y gate, and H gate mentioned above. Furthermore, this logic gate combination corresponds to an inverse logic gate, whose effect on the quantum state of the qubit is opposite to that of the logic gate combination. For example, if the logic gate combination modulates the quantum state of the qubit from the initial state to the excited state, then the inverse logic gate is used to modulate the quantum state of the qubit from the excited state back to the initial state.
[0079] For a given combination of logic gates and its inverse, during execution, several single quantum logic gates from the combination are first applied sequentially to the qubit, followed by the application of the inverse logic gate, and then the measurement of the qubit's quantum state is performed. Ideally, when the qubit's operating frequency is unbiased and there are no other influencing factors, the qubit's quantum state is the initial state after applying the inverse logic gate, and the measurement fidelity is 100%. In reality, the preset initial frequency is not necessarily the ideal operating frequency; therefore, the fidelity of the measured quantum state will vary accordingly.
[0080] Furthermore, during the above measurement process, the logic gate combination and the inverse logic gate are applied repeatedly to perform multiple measurements. The average value of the fidelity obtained from the multiple measurements is then taken, and the average fidelity value is compared with a preset threshold to select the initial frequency value corresponding to the qualified fidelity.
[0081] In addition, the number and type of logic gates in the logic gate combination can be changed, and the above steps S302-S303 can be repeated. Each logic gate combination and inverse logic gate corresponds to an average fidelity. By comparing multiple average fidelity values with a preset threshold, the initial frequency value obtained is more accurate.
[0082] Specifically, such as Figure 6 As shown, the initial value of the frequency at which the fidelity of the quantum state of a qubit is within a preset threshold is the operating frequency to be assigned to the qubit, which includes the following steps.
[0083] Step S311: Obtain the preset threshold.
[0084] Step S312: When the fidelity is within the preset threshold, the initial frequency value is determined as the target operating frequency; wherein, several target operating frequencies constitute the set of operating frequencies to be allocated; when the fidelity is not within the preset threshold, the corresponding initial frequency value is discarded.
[0085] For example, the preset threshold is set to be no less than 99.95%. The average value of the fidelity obtained by the above steps S302-S303 is compared with the preset threshold. When the fidelity is within the preset threshold, the initial frequency value is determined as the target operating frequency. Several target operating frequencies form a set of operating frequencies to be allocated. When the fidelity is not within the preset threshold, the corresponding initial frequency value is discarded.
[0086] like Figure 7 As shown, based on the same application concept, this embodiment also provides a method for characterizing a quantum processor, including the following steps.
[0087] Step S11: Obtain the topology of the qubits on the quantum processor.
[0088] Step S11: Allocate the operating frequency of each qubit according to the topology and using the qubit operating frequency allocation method.
[0089] Steps S10-S30 above allocate the operating frequency for a single qubit. For a quantum processor integrating multiple qubits, the operating frequency of each qubit needs to be allocated. First, the topology of the qubits on the quantum processor is obtained, and then the operating frequency of each qubit is allocated sequentially according to the topology result using steps S10-S30 above.
[0090] like Figure 8 As shown, based on the same application concept, this embodiment also provides a qubit operating frequency allocation system, including a parameter acquisition module, a parameter calibration module, and a frequency allocation module. Specifically, the parameter acquisition module is used to acquire a preset initial operating frequency range for each qubit on the quantum processor; wherein, the initial operating frequency range includes several initial frequency values; the parameter calibration module is used to set the operating frequency of the qubit to the initial frequency value respectively, and to calibrate the logic gate parameters of each qubit according to a directed acyclic graph; wherein, the directed acyclic graph includes the qubit and several node graphs composed of the performance parameters of the resonant cavity coupled to the qubit; the frequency allocation module is used to perform random benchmark tests on the logic gate parameters of the qubit, and to obtain the initial frequency value of the qubit whose quantum state fidelity is within a preset threshold as the operating frequency to be allocated to the qubit; wherein, the random benchmark test is used to test the correspondence between the quantum state fidelity of the qubit and the applied logic gate.
[0091] Based on the same application concept, this embodiment also provides a quantum computing measurement and control system, which utilizes the quantum bit operating frequency allocation method in steps S10-S30 above, or includes the quantum bit operating frequency allocation system described above.
[0092] Based on the same application concept, this embodiment also provides a quantum computer, including a quantum processor and the above-described quantum computing measurement and control system; or uses the method of steps S11-S21 described above to characterize the operating frequency of the qubits on the quantum processor.
[0093] Based on the same application concept, this embodiment also provides a readable storage medium storing a computer program thereon, characterized in that, when the computer program is executed by a processor, it can implement the determination method described above to allocate the operating frequency of qubits on the quantum processor.
[0094] A readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction execution device, such as, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer programs described herein can be downloaded from the readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. Networks can include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. Each computing / processing device's network adapter card or network interface receives the computer program from the network and forwards it for storage on a readable storage medium within the respective computing / processing device. The computer program used to perform the operations of this application can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as "C" or similar languages. The computer program can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), are personalized by utilizing state information from a computer program. These electronic circuits can execute computer-readable program instructions to implement various aspects of this application.
[0095] Various aspects of this application are described herein with reference to flowchart illustrations and / or block diagrams of methods, systems, and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by a computer program. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer programs can also be stored in a readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the readable storage medium storing the computer program includes an article of manufacture comprising instructions for implementing various aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.
[0096] A computer program may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the computer program executing on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.
[0097] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0098] The above are merely preferred embodiments of this application and do not constitute any limitation on this application. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in this application without departing from the scope of the technical solutions of this application shall still fall within the protection scope of this application.
Claims
1. A method for allocating the operating frequency of a qubit, characterized in that, include: The initial operating frequency range of each qubit on the quantum processor is preset; wherein, the initial operating frequency range includes several initial frequency values; The operating frequency of each qubit is set to the initial value, and the logic gate parameters of each qubit are calibrated according to a directed acyclic graph; wherein, the directed acyclic graph includes the qubit and several node graphs composed of the performance parameters of the resonant cavity coupled to the qubit; A random benchmark test is performed on the calibrated logic gate parameters to obtain the initial frequency value of the frequency at which the fidelity of the quantum state of the qubit is within a preset threshold. The random benchmark test is used to test the correspondence between the fidelity of the quantum state of the qubit and the applied logic gate.
2. The method as described in claim 1, characterized in that, The initial operating frequency range for each qubit on the preset quantum processor includes: Obtain the first frequency of each of the qubits; wherein, the first frequency is the operating frequency at which the frequency of the qubit changes at the rate of least change with the control signal applied to the magnetic flux modulation line; The initial operating frequency range is preset based on the first frequency; wherein, the first frequency is the cutoff frequency of the initial operating frequency range.
3. The method as described in claim 1, characterized in that, The logic gate parameters include characteristic parameters, readout parameters, and control parameters of the qubit and the resonant cavity. The operating frequency of each qubit is set to an initial value, and the logic gate parameters of each qubit are calibrated according to a directed acyclic graph, including: Obtain a directed acyclic graph consisting of several nodes, composed of the feature parameters, reading parameters, and control parameters; Within the initial operating frequency range, several initial frequency values are traversed, and the characteristic parameters, the read parameters, and the control parameters are calibrated sequentially according to the node order of the directed acyclic graph.
4. The method as described in claim 1, characterized in that, Perform random benchmark tests on the calibrated logic gate parameters, including: The driving signals applied to the qubit are iterated so that the operating frequency of the qubit corresponds to each of the initial frequency values in the initial operating frequency range. When the operating frequency of the qubit is each of the initial values of the frequency, a combination of logic gates and an inverse logic gate are applied to the qubit; wherein, the combination of logic gates includes several single quantum logic gates for controlling the quantum state of the qubit from the initial state to the target state, and the inverse logic gate is used to control the quantum state of the qubit from the target state to the initial state; The fidelity of the quantum state of the qubit as the initial state is measured.
5. The method as described in claim 4, characterized in that, The initial frequency at which the fidelity of the quantum state of a qubit is within a preset threshold is the operating frequency to be assigned to the qubit, including: Obtain the preset threshold; When the fidelity is within the preset threshold, the initial frequency value is determined as the target operating frequency; wherein, a plurality of the target operating frequencies constitute a set of operating frequencies to be allocated; When the fidelity is not within the preset threshold, the corresponding initial frequency value is discarded.
6. A method for characterizing a quantum processor, characterized in that, include: Obtain the topological structure of qubits on a quantum processor; The operating frequency of each of the qubits is allocated according to the topology and using the qubit operating frequency allocation method as described in any one of claims 1-5.
7. A quantum bit operating frequency allocation system, characterized in that, include: The parameter acquisition module is used to acquire the initial operating frequency range of each qubit on the preset quantum processor; wherein, the initial operating frequency range includes several initial frequency values; The parameter calibration module is used to set the operating frequency of each qubit to the initial value of the frequency, and to calibrate the logic gate parameters of each qubit according to a directed acyclic graph; wherein the directed acyclic graph is a number of node graphs composed of the qubit and the performance parameters of the resonant cavity coupled to the qubit; The frequency allocation module is used to perform random benchmark tests on the logic gate parameters of the qubit to obtain the initial frequency value of the qubit when the fidelity of the quantum state is within a preset threshold as the operating frequency to be allocated to the qubit; wherein, the random benchmark test is the correspondence between the fidelity of the quantum state of the qubit and the applied logic gate.
8. A quantum computing measurement and control system, characterized in that, The method for allocating the operating frequency of qubits as described in any one of claims 1-5, or the system for allocating the operating frequency of qubits as described in claim 7.
9. A quantum computer, characterized in that, This includes a quantum processor and the quantum computing measurement and control system as described in claim 8; or the operating frequency of the qubits on the quantum processor is characterized using the method described in claim 6.
10. A readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it can perform the method of any one of claims 1-5 to allocate the operating frequency of qubits on the quantum processor.