Semiconductor device and electronic system including the same

Abstract

A semiconductor device may include an element isolation film on a substrate, a first gate electrode, and an auxiliary electrode on the element isolation film. The element isolation film may define a first active region of the substrate. First and second source / drain regions of the first conductivity type may be in the first active region. The second source / drain region may be spaced apart from the first source / drain region in the first direction. The first gate electrode may be on a portion of the first active region between the first source / drain region and the second source / drain region. The first gate electrode may extend in a second direction crossing the first direction. The substrate may include an impurity region surrounding the element isolation film. The impurity region may contain a second conductivity type impurity. The auxiliary electrode and the impurity region may be electrically connected to each other.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0154177, filed on November 4, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device and an electronic system including the semiconductor device. More specifically, this disclosure relates to a semiconductor device including memory cells arranged in three dimensions and / or an electronic system including the semiconductor device. Background Technology

[0003] As electronic products become lighter, thinner, and simpler, the demand for high integration in semiconductor devices is increasing. With greater integration, the size of components (e.g., transistors) within semiconductor devices can be further reduced, leading to leakage current. Therefore, controlling leakage current in semiconductor devices is necessary to improve their performance and / or reliability.

[0004] In electronic systems requiring data storage, there is a need for semiconductor devices capable of storing large amounts of data. Therefore, schemes to improve the data storage capacity of semiconductor devices are being researched. For example, in one method for improving the data storage capacity of semiconductor devices, a semiconductor device comprising three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells has been proposed. Summary of the Invention

[0005] This disclosure relates to a semiconductor device with improved performance and reliability.

[0006] This disclosure relates to an electronic system including semiconductor devices with improved performance and reliability.

[0007] The present disclosure is not limited to the aspects described above, and other aspects not mentioned will be readily understood by those skilled in the art based on the description set forth below.

[0008] According to embodiments of this disclosure, a semiconductor device may include: a device isolation film on a substrate, the device isolation film defining a first active region of the substrate, the first active region including a first source / drain region and a second source / drain region within the first active region, the first source / drain region contacting the device isolation film in a first direction and having a first conductivity type, the second source / drain region being spaced apart from the first source / drain region in the first direction and having a first conductivity type; a first gate electrode on a portion of the first active region located between the first source / drain region and the second source / drain region, wherein the first gate electrode extends in a second direction and intersects the first direction; a second gate electrode on the first active region and extending in the second direction, wherein the second source / drain region is between the first gate electrode and the second gate electrode; and a first auxiliary electrode on the device isolation film. In a plan view, the first auxiliary electrode may not overlap with the first source / drain region in the second direction, and the first auxiliary electrode may overlap with the second source / drain region in the second direction.

[0009] According to embodiments of this disclosure, a semiconductor device may include: a substrate; a device isolation film defining a first active region of the substrate, the first active region including a first source / drain region and a second source / drain region having a first conductivity type, the second source / drain region being spaced apart from the first source / drain region in a first direction and having a first conductivity type; a first gate electrode on a portion of the first active region located between the first source / drain region and the second source / drain region, wherein the first gate electrode extends in a second direction and intersects the first direction; and an auxiliary electrode on the device isolation film. The substrate may include an impurity region surrounding the device isolation film. The impurity region may contain impurities having a second conductivity type. The second conductivity type may be different from the first conductivity type, and the auxiliary electrode and the impurity region may be electrically connected to each other.

[0010] According to embodiments of this disclosure, an electronic system may include: a main substrate; a semiconductor device on the main substrate, the semiconductor device including a first substrate having a peripheral circuit region and a second substrate having a cell region; and a main controller on the main substrate and electrically connected to the semiconductor device. The semiconductor device may include: a device isolation film on the first substrate; a first gate electrode, a second gate electrode, and an auxiliary electrode on the device isolation film; a plurality of word lines sequentially stacked on the second substrate; a channel structure on the second substrate intersecting the plurality of word lines; and bit lines contacting the channel structure. The device isolation film may define a first active region in the substrate. The first active region may include a first source / drain region and a second source / drain region. The first source / drain region may contact the device isolation film in a first direction and may have a first conductivity type. The second source / drain region may be spaced apart from the first source / drain region in the first direction and may have a first conductivity type. The first gate electrode may be on the portion of the first active region located between the first source / drain region and the second source / drain region. The first gate electrode may extend in a second direction, and the second direction may intersect the first direction. The second gate electrode may be on the first active region and may extend in the second direction. The second source / drain region may be located between the first gate electrode and the second gate electrode. In a planar view, the auxiliary electrode may not overlap with the first source / drain region in the second direction, and the auxiliary electrode may overlap with the second source / drain region in the second direction.

[0011] According to embodiments of this disclosure, a method of manufacturing a semiconductor device may include: providing a substrate including a trench defining a first active region of the substrate; forming a device isolation film on the substrate, the device isolation film exposing the first active region of the substrate; forming a plurality of electrodes on the substrate, the plurality of electrodes including a first gate electrode, a second gate electrode, and a first auxiliary electrode on the device isolation film; and forming impurities in the substrate, wherein forming impurities in the substrate may include forming a first source / drain region and a second source / drain region in the first active region, the first source / drain region being contacted in a first direction and having a first conductivity type, the second source / drain region being spaced apart from the first source / drain region in the first direction and having a first conductivity type, the first gate electrode being on a portion of the first active region located between the first source / drain region and the second source / drain region, the first gate electrode and the second gate electrode each being extending in a second direction, the second direction being intersecting the first direction, and the second source / drain region being between the first gate electrode and the second gate electrode. In a plan view, the first auxiliary electrode may not overlap with the first source / drain region in the second direction, and the first auxiliary electrode may overlap with the second source / drain region in the second direction.

[0012] In some embodiments, forming impurities in the substrate may further include forming impurity regions in the substrate, and the impurity regions surrounding the device isolation film. The impurity regions may contain impurities having a second conductivity type, and the second conductivity type may be different from the first conductivity type.

[0013] In some embodiments, in a plan view, the first auxiliary electrode may be located between the second source / drain region and the impurity region.

[0014] In some embodiments, the first conductivity type may be n-type, and the second conductivity type may be p-type.

[0015] In some embodiments, the first gate electrode and the first auxiliary electrode may not overlap each other in a first direction.

[0016] Specific details of other embodiments are included in the detailed description and accompanying drawings. Attached Figure Description

[0017] The above and other aspects and features of this disclosure will become clearer from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0018] Figure 1 It is a layout diagram used to illustrate semiconductor devices according to some embodiments of the present disclosure.

[0019] Figure 2 It is along Figure 1 A schematic cross-sectional view of line AA.

[0020] Figure 3 It is along Figure 1 A schematic cross-sectional view of line BB.

[0021] Figure 4 It is along Figure 1 A schematic cross-sectional view of the line CC.

[0022] Figure 5 It is along Figure 1 A schematic cross-sectional view of line DD.

[0023] Figure 6 It is used to show Figure 1 A magnified view of region R1.

[0024] Figure 7 It is a layout diagram used to illustrate semiconductor devices according to some embodiments of the present disclosure.

[0025] Figure 8 It is along Figure 7 A schematic cross-sectional view of line AA.

[0026] Figure 9It is a layout diagram used to illustrate semiconductor devices according to some embodiments of the present disclosure.

[0027] Figure 10 It is along Figure 9 A schematic cross-sectional view of line AA.

[0028] Figure 11 It is a layout diagram used to illustrate semiconductor devices according to some embodiments of the present disclosure.

[0029] Figure 12 It is along Figure 11 A schematic cross-sectional view of line AA.

[0030] Figure 13 It is a layout diagram used to illustrate semiconductor devices according to some embodiments of the present disclosure.

[0031] Figure 14 It is a layout diagram used to illustrate semiconductor devices according to some embodiments of the present disclosure.

[0032] Figure 15 It is a layout diagram used to illustrate semiconductor devices according to some embodiments of the present disclosure.

[0033] Figure 16 It shows Figure 15 A magnified view of the R2 region.

[0034] Figure 17 It is a layout diagram used to illustrate semiconductor devices according to some embodiments of the present disclosure.

[0035] Figure 18 It is along Figure 17 A schematic cross-sectional view of line AA.

[0036] Figure 19 It is along Figure 17 A schematic cross-sectional view of the line CC.

[0037] Figure 20 This is a schematic block diagram illustrating a non-volatile storage device according to some embodiments of the present disclosure.

[0038] Figure 21 This is a schematic cross-sectional view used to illustrate a non-volatile storage device according to some embodiments of the present disclosure.

[0039] Figure 22 and Figure 23 It shows Figure 21 Various magnified views of the R3 region.

[0040] Figure 24 This is a schematic cross-sectional view used to illustrate a semiconductor device according to some embodiments of the present disclosure.

[0041] Figure 25 yes Figure 24 A magnified view of the R3 region.

[0042] Figures 26 to 33 This is a diagram of an intermediate structure corresponding to an intermediate step in a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0043] Figure 34 This is an example block diagram illustrating an electronic system according to some embodiments of the present disclosure.

[0044] Figure 35 This is an example perspective view used to illustrate an electronic system according to some embodiments of the present disclosure.

[0045] Figure 36 and Figure 37 It is along Figure 35 Various schematic cross-sectional views of the line I-I'. Detailed Implementation

[0046] In the following description, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. The same components in the drawings are referred to by the same reference numerals, and repeated descriptions thereof are omitted.

[0047] When phrases such as "at least one of..." follow a list of elements, they modify the entire list of elements, rather than individual elements within the list. For example, "at least one of A, B, and C" and similar language (e.g., "at least one selected from the group consisting of A, B, and C" and "at least one of A, B, or C") can be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C, such as ABC, AB, BC, and AC.

[0048] When the terms “approximately” or “substantially” are used in conjunction with numerical values ​​in this specification, the relevant numerical values ​​are intended to include manufacturing or operational tolerances (e.g., ±10%) around the values. Furthermore, when the terms “generally” and “substantially” are used in conjunction with geometry, it is intended that precision of the geometry is not required, but rather a tolerance of the shape is within the scope of this disclosure. Moreover, regardless of whether numerical values ​​or shapes are modified to “approximately” or “substantially”, it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) around the values ​​or shapes. When ranges are specified, the range includes all values ​​within that range, such as increments of 0.1%.

[0049] Although terms such as first, second, upper, and lower are used herein to describe various elements or components, these elements or components are not limited by these terms. Rather, these terms are used only to distinguish one element or component from another. Therefore, within the spirit of this disclosure, the first element or component mentioned below can also be the second element or component. Furthermore, within the spirit of this disclosure, the lower element or component mentioned below can also be the upper element or component.

[0050] In the following text, refer to Figures 1 to 19 To describe a semiconductor device according to some embodiments.

[0051] Figure 1 It is a layout diagram used to illustrate semiconductor devices according to some embodiments of the present disclosure. Figure 2 It is along Figure 1 A schematic cross-sectional view of line AA. Figure 3 It is along Figure 1 A schematic cross-sectional view of line BB. Figure 4 It is along Figure 1 A schematic cross-sectional view of the line CC. Figure 5 It is along Figure 1 A schematic cross-sectional view of line DD. Figure 6 It is used to show Figure 1 A magnified view of region R1.

[0052] refer to Figures 1 to 6 A semiconductor device according to some embodiments of the present disclosure may include a first substrate 100, an element isolation film 110, first to fourth circuit elements TR1, TR2, TR3 and TR4, first auxiliary electrodes 138_1A, 138_1B, 138_1C and 138_1D (hereinafter referred to as 138_1), second auxiliary electrodes 138_2A, 138_2B, 138_2C and 138_2D (hereinafter referred to as 138_2), an impurity region 150, a gate contact 142, a source / drain contact 144, an auxiliary electrode contact 146, a first impurity region contact 155, a second impurity region contact 156, an interlayer insulating film 160 and a connection pattern 170. For ease of explanation, Figure 1 Gate contact 142 is omitted.

[0053] The first substrate 100 may include a base substrate and an epitaxial layer grown on the base substrate. However, embodiments of this disclosure are not limited thereto. For example, the first substrate 100 may include only the base substrate and not the epitaxial layer. The first substrate 100 may be a silicon substrate, a gallium arsenide substrate, a silicon-germanium substrate, a ceramic substrate, a quartz substrate, a glass substrate for a display, or an SOI (semiconductor on insulator) substrate. In the following, an example is described in which the first substrate 100 is embodied as a silicon substrate.

[0054] In some embodiments of this disclosure, the first substrate 100 may be doped with impurities of a first conductivity type. For example, when each of the first to fourth circuit elements TR1, TR2, TR3, and TR4 described below is an n-type transistor, the first substrate 100 may be doped with p-type impurities. Although not shown, the first substrate 100 may include a well doped with impurities of the first conductivity type.

[0055] The component isolation film 110 may include first component isolation films to fourth component isolation films 110_A, 110_B, 110_C, and 110_D. The component isolation film 110 may define a plurality of active regions 105A, 105B, 105C, and 105D within the first substrate 100. For example, the first component isolation films to fourth component isolation films 110_A, 110_B, 110_C, and 110_D may respectively define a plurality of active regions 105A, 105B, 105C, and 105D within the first substrate 100. Hereinafter, the component isolation film 110 is depicted or described as including only the first component isolation films to fourth component isolation films 110_A, 110_B, 110_C, and 110_D. However, the technical concept of this disclosure is not limited thereto.

[0056] Device isolation trenches 110t may be formed within a first substrate 100 to define a plurality of active regions 105A, 105B, 105C, and 105D. First to fourth device isolation films 110_A, 110_B, 110_C, and 110_D may respectively fill the corresponding device isolation trenches 110t. The first to fourth device isolation films 110_A, 110_B, 110_C, and 110_D may respectively surround the active regions 105A, 105B, 105C, and 105D. In some embodiments of this disclosure, the depth of the device isolation trenches 110t may be in the range of about 3000 Å to about 5000 Å. However, this is merely an example.

[0057] The first to fourth element isolation films 110_A, 110_B, 110_C, and 110_D can be spaced apart from each other. For example, the first element isolation film 110_A and the second element isolation film 110_B can be spaced apart from each other in a first direction X. Furthermore, for example, the first element isolation film 110_A and the third element isolation film 110_C can be spaced apart from each other in a second direction Y intersecting the first direction X. Figure 1 In the plan view, the element isolation films 110 can be arranged in a matrix.

[0058] exist Figures 2 to 5 In the illustration, the side surface of the element isolation film 110 is depicted as having an inclined angle. However, this is merely a feature of the process for forming the element isolation film 110. The technical concept of this disclosure is not limited thereto.

[0059] In some embodiments of this disclosure, the element isolation membrane 110 may be formed as a single membrane, such as Figures 2 to 5 As shown. However, the technical concept of this disclosure is not limited thereto. For example, the component isolation film 110 can be formed as a stack of multiple films. Specifically, the component isolation film 110 may include an insulating pad, an etch stop pad, and a gap-filling insulating film sequentially stacked within the component isolation trench 110t. The insulating pad may extend conformally along the contours of the side and bottom surfaces of the component isolation trench 110t. The etch stop pad may extend conformally along the contours of the insulating pad. The gap-filling insulating film may fill the area remaining in the component isolation trench 110t after the insulating pad and etch stop pad have been formed.

[0060] The element isolation film 110 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. However, embodiments of this disclosure are not limited thereto.

[0061] The first to fourth active regions 105A, 105B, 105C, and 105D may be surrounded by the first to fourth element isolation films 110_A, 110_B, 110_C, and 110_D, respectively. The first to fourth active regions 105A, 105B, 105C, and 105D may be isolated from each other via the first to fourth element isolation films 110_A, 110_B, 110_C, and 110_D, respectively. For example, the plurality of active regions 105A, 105B, 105C, and 105D may include a first active region 105A and a second active region 105B arranged along a first direction X. A portion of the first element isolation film 110_A and a portion of the second element isolation film 110_B disposed between the first active region 105A and the second active region 105B may extend in a second direction Y to isolate the first active region 105A and the second active region 105B from each other.

[0062] Furthermore, for example, the plurality of active regions 105A, 105B, 105C, and 105D may include a first active region 105A and a third active region 105C arranged along a second direction Y, and a second active region 105B and a fourth active region 105D arranged along the second direction Y. A portion of the first element isolation film 110_A and a portion of the third element isolation film 110_C disposed between the first active region 105A and the third active region 105C may extend in the first direction X to isolate the first active region 105A and the third active region 105C from each other. A portion of the second element isolation film 110_B and a portion of the fourth element isolation film 110_D disposed between the second active region 105B and the fourth active region 105D may extend in the first direction X to isolate the second active region 105B and the fourth active region 105D from each other.

[0063] Impurity region 150 may be disposed in the first substrate 100. Impurity region 150 may be disposed surrounding the device isolation film 110 and within the first substrate 100. Impurity region 150 may be disposed surrounding each of a plurality of active regions 105A, 105B, 105C and 105D and within the first substrate 100.

[0064] In some embodiments of this disclosure, the impurity region 150 may include a first impurity region 150X extending in a first direction X, a second impurity region 150Y extending in a second direction Y, and a third impurity region 150C being a region where the first impurity region 150X and the second impurity region 150Y intersect each other.

[0065] Impurity regions 150 can be disposed between adjacent element isolation films 110. Impurity regions 150 can also be disposed between adjacent element isolation trenches 110t. For example, a first impurity region 150X can be disposed between a first element isolation film 110_A and a third element isolation film 110_C, and can extend in a first direction X. Furthermore, for example, a second impurity region 150Y can be disposed between a first element isolation film 110_A and a second element isolation film 110_B, and can extend in a second direction Y.

[0066] Impurity region 150 may be doped with impurities of a first conductivity type. For example, when each of the first to fourth circuit elements TR1, TR2, TR3, and TR4 described below is an n-type transistor, impurity region 150 may contain p-type impurities. In some embodiments of this disclosure, the doping concentration of impurity region 150 may be higher than the doping concentration of the first substrate 100.

[0067] The second impurity region contact portion 156 may extend in the third direction Z to contact the impurity region 150. The second impurity region contact portion 156 may apply a ground voltage to the impurity region 150. In one example, the third direction Z may represent a direction substantially perpendicular to the first direction X and the second direction Y, and the first direction X and the second direction Y may be substantially orthogonal to each other.

[0068] The second impurity region contact portion 156 may include, but is not limited to, metals such as aluminum (Al), copper (Cu), or tungsten (W). Furthermore, Figures 1 to 3 The number and arrangement of the second impurity region contacts 156 shown are merely examples, and the technical concept of this disclosure is not limited thereto. For example, the second impurity region contacts 156 may also be provided on the first impurity region 150X.

[0069] The first to fourth circuit elements TR1, TR2, TR3, and TR4 can be disposed on active regions 105A, 105B, 105C, and 105D. For example, the first circuit element TR1, the second circuit element TR2, and the third circuit element TR3 can be disposed on the first active region 105A, and the fourth circuit element TR4 can be disposed on the second active region 105B. However, contrary to the illustration, instead of three circuit elements, two or four or more circuit elements can be disposed on each of the active regions 105A, 105B, 105C, and 105D. In this document, for ease of illustration, this description is based on three circuit elements arranged on each of the active regions 105A, 105B, 105C, and 105D.

[0070] The first circuit element TR1 may include a first gate dielectric film 132_1A, a first gate electrode 134_1A, a first source / drain region 120_1A, and a second source / drain region 120_2A. The first gate electrode 134_1A may be disposed on the first active region 105A and extend in one direction (e.g., a second direction Y). The first gate dielectric film 132_1A may be located between the first substrate 100 and the first gate electrode 134_1A.

[0071] The first source / drain region 120_1A can be disposed in the first active region 105A and on one side of the first gate electrode 134_1A. The second source / drain region 120_2A can be disposed in the first active region 105A and on the other side of the first gate electrode 134_1A. For example, the first gate electrode 134_1A can be disposed on the first active region 105A and extend in the second direction Y between the first source / drain region 120_1A and the second source / drain region 120_2A. Furthermore, for example, the second source / drain region 120_2A can be disposed on the first active region 105A and can be located between the first gate electrode 134_1A and the second gate electrode 134_2A.

[0072] The first source / drain region 120_1A may be adjacent to the first element isolation film 110_A in the first direction X. The first source / drain region 120_1A may also be in contact with the first element isolation film 110_A in the first direction X. For example, in the third direction Z, at least a portion of the first source / drain region 120_1A may overlap with the first element isolation film 110_A.

[0073] In some embodiments of this disclosure, the first source / drain region 120_1A may be the drain region of the first circuit element TR1, and the second source / drain region 120_2A may be the source region of the first circuit element TR1. For example, when the first circuit element TR1 is an n-type transistor, a higher voltage may be applied to the first source / drain region 120_1A than the voltage applied to the second source / drain region 120_2A. In one example, approximately 5V may be applied to the first source / drain region 120_1A, and 0V may be applied to the second source / drain region 120_2A. Conversely, when the first circuit element TR1 is a p-type transistor, a lower voltage may be applied to the first source / drain region 120_1A than the voltage applied to the second source / drain region 120_2A.

[0074] The second circuit element TR2 may include a second gate dielectric film 132_2A, a second gate electrode 134_2A, a second source / drain region 120_2A, and a third source / drain region 120_3A. The second gate electrode 134_2A may extend in one direction (e.g., a second direction Y) while being disposed on the first active region 105A. In one example, the second gate electrode 134_2A may extend parallel to the first gate electrode 134_1A. The second gate dielectric film 132_2A may be located between the first substrate 100 and the second gate electrode 134_2A.

[0075] The second source / drain region 120_2A can be disposed in the first active region 105A and on one side of the second gate electrode 134_2A. The third source / drain region 120_3A can be disposed in the first active region 105A and on the other side of the second gate electrode 134_2A. The second source / drain region 120_2A can be spaced apart from the first source / drain region 120_1A in the first direction X. The third source / drain region 120_3A can be spaced apart from the second source / drain region 120_2A in the first direction X.

[0076] In some embodiments of this disclosure, the first circuit element TR1 and the second circuit element TR2 may share the second source / drain region 120_2A. For example, the second source / drain region 120_2A may be the source region of the first circuit element TR1 and the source region of the second circuit element TR2.

[0077] In some embodiments of this disclosure, the second source / drain region 120_2A may be the source region of the second circuit element TR2, and the third source / drain region 120_3A may be the drain region of the second circuit element TR2. For example, when the second circuit element TR2 is an n-type transistor, a higher voltage may be applied to the third source / drain region 120_3A than the voltage applied to the second source / drain region 120_2A. In one example, approximately 5V may be applied to the third source / drain region 120_3A, and 0V may be applied to the second source / drain region 120_2A. Conversely, when the second circuit element TR2 is a p-type transistor, a lower voltage may be applied to the third source / drain region 120_3A than the voltage applied to the second source / drain region 120_2A.

[0078] The third circuit element TR3 may include a third gate dielectric film 132_3A, a third gate electrode 134_3A, a third source / drain region 120_3A, and a fourth source / drain region 120_4A. The third gate electrode 134_3A may extend in one direction (e.g., a second direction Y) while being disposed on the first active region 105A. In one example, the third gate electrode 134_3A may extend parallel to the first gate electrode 134_1A and the second gate electrode 134_2A. The third gate dielectric film 132_3A may be located between the first substrate 100 and the third gate electrode 134_3A.

[0079] The third source / drain region 120_3A can be disposed in the first active region 105A and on one side of the third gate electrode 134_3A. The fourth source / drain region 120_4A can be disposed in the first active region 105A and on the other side of the third gate electrode 134_3A. The fourth source / drain region 120_4A can be spaced apart from the third source / drain region 120_3A in the first direction X. For example, the third gate electrode 134_3A can be disposed in the first active region 105A and extend in the second direction Y between the third source / drain region 120_3A and the fourth source / drain region 120_4A.

[0080] The fourth source / drain region 120_4A may be adjacent to the first element isolation film 110_A in the first direction X. The fourth source / drain region 120_4A may also be in contact with the first element isolation film 110_A in the first direction X. For example, in the third direction Z, at least a portion of the fourth source / drain region 120_4A may overlap with the first element isolation film 110_A.

[0081] In some embodiments of this disclosure, the second circuit element TR2 and the third circuit element TR3 may share the third source / drain region 120_3A. For example, the third source / drain region 120_3A may be the drain region of the second circuit element TR2 and the drain region of the third circuit element TR3.

[0082] In some embodiments of this disclosure, the third source / drain region 120_3A may be the drain region of the third circuit element TR3, and the fourth source / drain region 120_4A may be the source region of the third circuit element TR3. For example, when the third circuit element TR3 is an n-type transistor, a higher voltage may be applied to the third source / drain region 120_3A than the voltage applied to the fourth source / drain region 120_4A. In one example, approximately 5V may be applied to the third source / drain region 120_3A, and 0V may be applied to the fourth source / drain region 120_4A. Conversely, when the third circuit element TR3 is a p-type transistor, a lower voltage may be applied to the third source / drain region 120_3A than the voltage applied to the fourth source / drain region 120_4A.

[0083] A fourth circuit element TR4 may be disposed on the second active region 105B. The fourth circuit element TR4 may include a first gate dielectric film 132_1B, a first gate electrode 134_1B, a first source / drain region 120_1B, and a second source / drain region 120_2B. The description of the fourth circuit element TR4 is similar to the description given above with reference to the first circuit element TR1. Therefore, its detailed description is omitted.

[0084] Each of the first gate dielectric films 132_1A and 132_1B, the second gate dielectric film 132_2A, and the third gate dielectric film 132_3A may include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, and high-k materials with a dielectric constant higher than that of silicon oxide. High-k materials may include, but are not limited to, at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0085] In some embodiments of this disclosure, each of the first to fourth circuit elements TR1, TR2, TR3, and TR4 may be a high-voltage transistor. For example, each of the first to fourth circuit elements TR1, TR2, TR3, and TR4 may include each of a first gate dielectric film 132_1A and 132_1B, a second gate dielectric film 132_2A, and a third gate dielectric film 132_3A having a thickness of about 200 Å or greater. However, this disclosure is not limited thereto.

[0086] Each of the first gate electrodes 134_1A and 134_1B, the second gate electrode 134_2A, and the third gate electrode 134_3A may include, but is not limited to, at least one of polycrystalline silicon (polySi), amorphous silicon (a-Si), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), tantalum carbonitride (TaCN), silicon tantalum nitride (TaSiN), tantalum (Ta), cobalt (Co), ruthenium (Ru), aluminum (Al), tungsten (W), and combinations thereof.

[0087] In some embodiments of this disclosure, each of the first to fourth circuit elements TR1, TR2, TR3, and TR4 may be a high-voltage transistor. For example, a high voltage of about 5V to about 100V may be applied to each of the first gate electrodes 134_1A and 134_1B, the second gate electrode 134_2A, and the third gate electrode 134_3A. However, embodiments of this disclosure are not limited thereto.

[0088] Each of the first source / drain regions 120_1A and 120_1B, the second source / drain regions 120_2A and 120_2B, the third source / drain region 120_3A, and the fourth source / drain region 120_4A may be doped with a second conductivity type impurity, different from the first conductivity type impurity. For example, each of the first source / drain regions 120_1A and 120_1B, the second source / drain regions 120_2A and 120_2B, the third source / drain region 120_3A, and the fourth source / drain region 120_4A may contain an n-type impurity.

[0089] In some embodiments of this disclosure, each of the first source / drain regions 120_1A and 120_1B, the second source / drain regions 120_2A and 120_2B, the third source / drain region 120_3A, and the fourth source / drain region 120_4A may include low-concentration impurity regions 122_1A, 122_2A, 122_3A, and 122_4A, and high-concentration impurity regions 124_1A, 124_2A, 124_3A, and 124_4A. The high-concentration impurity regions 124_1A, 124_2A, 124_3A, and 124_4A may be formed within the low-concentration impurity regions 122_1A, 122_2A, 122_3A, and 122_4A, respectively. The low-concentration impurity regions 122_1A, 122_2A, 122_3A and 122_4A can surround the high-concentration impurity regions 124_1A, 124_2A, 124_3A and 124_4A, respectively.

[0090] Each of the low-concentration impurity regions 122_1A, 122_2A, 122_3A, and 122_4A, and the high-concentration impurity regions 124_1A, 124_2A, 124_3A, and 124_4A, may be doped with an impurity of a second conductivity type. In this respect, the doping concentration of each of the high-concentration impurity regions 124_1A, 124_2A, 124_3A, and 124_4A may be higher than the doping concentration of each of the low-concentration impurity regions 122_1A, 122_2A, 122_3A, and 122_4A.

[0091] Although not shown, each of the first to fourth circuit elements TR1, TR2, TR3, and TR4 may further include a gate spacer covering the side surface of each of the first gate electrodes 134_1A and 134_1B, the second gate electrode 134_2A, and the third gate electrode 134_3A. Furthermore, although not shown, each of the first to fourth circuit elements TR1, TR2, TR3, and TR4 may further include a gate capping pattern covering the upper surface of each of the first gate electrodes 134_1A and 134_1B, the second gate electrode 134_2A, and the third gate electrode 134_3A. Furthermore, although not shown, each of the first to fourth circuit elements TR1, TR2, TR3 and TR4 may also include an etch stop film covering each of the first source / drain regions 120_1A and 120_1B, the second source / drain regions 120_2A and 120_2B, the third source / drain region 120_3A and the fourth source / drain region 120_4A, the gate spacer and the gate cap pattern.

[0092] The description of the second gate electrode 134_2B and the third gate electrode 134_3B disposed on the second active region 105B is similar to the description of the second gate electrode 134_2A and the third gate electrode 134_3A disposed on the first active region 105A, and is therefore omitted. The description of the first to third gate electrodes 134_1C, 134_2C and 134_3C disposed on the third active region 105C is similar to the description of the first to third gate electrodes 134_1A, 134_2A and 134_3A disposed on the third active region 105A, and is therefore omitted. Furthermore, the description of the first to third gate electrodes 134_1D, 134_2D and 134_3D disposed on the fourth active region 105D is similar to the description of the first to third gate electrodes 134_1A, 134_2A and 134_3A disposed on the first active region 105A, and is therefore omitted.

[0093] The first auxiliary electrode 138_1 and the second auxiliary electrode 138_2 may be disposed on the element isolation film 110. The first auxiliary electrode 138_1 and the second auxiliary electrode 138_2 may be disposed on the upper surface of the element isolation film 110. In some embodiments of this disclosure, the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2 may be disposed on the portion of the element isolation film 110 located between each of the active regions 105A, 105B, 105C, and 105D and the first impurity region 150X. The first auxiliary electrode 138_1 and the second auxiliary electrode 138_2 may not be disposed on the portion of the element isolation film 110 located between each of the active regions 105A, 105B, 105C, and 105D and the second impurity region 150Y.

[0094] A ground voltage can be applied to the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2. In some embodiments of this disclosure, the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2 can be connected to the impurity region 150 through the auxiliary electrode contact portion 146, the connection pattern 170, and the first impurity region contact portion 155 as described below, so that the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2 can be applied a ground voltage.

[0095] In some embodiments of this disclosure, the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2, as well as the first gate electrode to the third gate electrode 134_1A to 134_1D, 134_2A to 134_2D, and 134_3A to 134_3D, may be formed at the same height. Furthermore, the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2 may be formed at the same height. In this respect, "formed at the same height" can mean formed at the same step in the semiconductor device manufacturing process.

[0096] In some embodiments of this disclosure, each of the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2 may have the same material composition as each of the first to third gate electrodes 134_1A to 134_1D, 134_2A to 134_2D, and 134_3A to 134_3D. For example, each of the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2 may include, but is not limited to, at least one of polycrystalline silicon (polySi), amorphous silicon (a-Si), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), tantalum carbonitride (TaCN), silicon tantalum nitride (TaSiN), tantalum (Ta), cobalt (Co), ruthenium (Ru), aluminum (Al), tungsten (W), and combinations thereof.

[0097] In the plan view, each of the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2 is shown as having a rectangular or square shape. However, embodiments of this disclosure are not limited thereto. The first auxiliary electrode 138_1 and the second auxiliary electrode 138_2 may be spaced apart from each other in a first direction X, as described later.

[0098] In a plan view parallel to the upper surface of the first substrate 100, the first auxiliary electrode 138_1A disposed on the first element isolation film 110_A may overlap with the second source / drain region 120_2A in the second direction Y. In a plan view, the first auxiliary electrode 138_1A disposed on the first element isolation film 110_A may not overlap with the first source / drain region 120_1A in the second direction Y. In a plan view, the first auxiliary electrode 138_1A disposed on the first element isolation film 110_A may not overlap with the first source / drain region 120_1A in the first direction X. In a plan view, the first auxiliary electrode 138_1A disposed on the first element isolation film 110_A may be located between the first impurity region 150X and the second source / drain region 120_2A. Here, the plan view parallel to the upper surface of the first substrate 100 can represent the viewing angle from a plane substantially perpendicular to the third direction Z.

[0099] In other words, in the plan view, the first auxiliary electrode 138_1A disposed on the first element isolation film 110_A may not be disposed on the first portion of the first element isolation film 110_A located between the first source / drain region 120_1A and the first impurity region 150X. Furthermore, in the plan view, the first auxiliary electrode 138_1A disposed on the first element isolation film 110_A may not be disposed on the second portion of the first element isolation film 110_A located between the first portion and the second impurity region 150Y. Furthermore, in the plan view, the first auxiliary electrode 138_1A may not be disposed on the third portion of the first element isolation film 110_A located between the first source / drain region 120_1A and the second impurity region 150Y.

[0100] As semiconductor devices become increasingly integrated, the impact of leakage current becomes more significant. For example, characteristic degradation may occur due to the cutoff current in the off-state of a semiconductor device. Furthermore, as semiconductor devices become more integrated, the breakdown voltage may decrease, leading to further characteristic degradation.

[0101] As a semiconductor device, the multifinite transistor can have an increased electron concentration in the region between the gate electrodes and a relatively low electron concentration in the end region of the multifinite transistor.

[0102] In some embodiments of this disclosure, a first auxiliary electrode 138_1A with an applied ground voltage can be configured to overlap with a second source / drain region 120_2A in a second direction Y in a planar view. Therefore, when the first auxiliary electrode 138_1A with an applied ground voltage is disposed adjacent to the second source / drain region 120_2A, the electron concentration of the second source / drain region 120_2A can be appropriately reduced, thereby limiting and / or preventing characteristic degradation due to reduced cutoff current and increased breakdown voltage. Furthermore, since the first auxiliary electrode 138_1A is not disposed on the first, second, and third portions, characteristic degradation due to reduced electron concentration can be limited and / or prevented. Therefore, a semiconductor device with improved reliability and / or performance can be provided.

[0103] Since the description of each of the first auxiliary electrodes 138_1B, 138_1C, and 138_1D respectively disposed on the second to fourth element isolation films 110_B, 110_C, and 110_D is similar to the description of the first auxiliary electrode 138_1A disposed on the first element isolation film 110_A, its detailed description is omitted.

[0104] In the plan view, the second auxiliary electrode 138_2A disposed on the first element isolation film 110_A may overlap with the third source / drain region 120_3A in the second direction Y. In the plan view, the second auxiliary electrode 138_2A disposed on the first element isolation film 110_A may not overlap with the fourth source / drain region 120_4A in the second direction Y. In the plan view, the second auxiliary electrode 138_2A disposed on the first element isolation film 110_A may be located between the first impurity region 150X and the third source / drain region 120_3A. The second auxiliary electrode 138_2A disposed on the first element isolation film 110_A may be spaced apart from the first auxiliary electrode 138_1A disposed on the first element isolation film 110_A in the first direction X.

[0105] In other words, in the plan view, the second auxiliary electrode 138_2A disposed on the first element isolation film 110_A may not be disposed on the fourth portion of the first element isolation film 110_A located between the fourth source / drain region 120_4A and the first impurity region 150X. Furthermore, in the plan view, the second auxiliary electrode 138_2A disposed on the first element isolation film 110_A may not be disposed on the fifth portion of the first element isolation film 110_A located between the fourth portion and the second impurity region 150Y. Furthermore, the second auxiliary electrode 138_2A disposed on the first element isolation film 110_A may not be disposed on the sixth portion of the first element isolation film 110_A located between the fourth source / drain region 120_4A and the second impurity region 150Y.

[0106] In some embodiments of this disclosure, the second auxiliary electrode 138_2A, to which a ground voltage is applied, can be configured to overlap with the third source / drain region 120_3A in the second direction Y in a planar view. Therefore, when the second auxiliary electrode 138_2A, to which a ground voltage is applied, is disposed adjacent to the third source / drain region 120_3A, the electron concentration of the third source / drain region 120_3A can be appropriately reduced, thereby limiting and / or preventing characteristic degradation due to reduced cutoff current and increased breakdown voltage. Furthermore, since the second auxiliary electrode 138_2A is not disposed on the fourth, fifth, and sixth portions, characteristic degradation due to reduced electron concentration can be limited and / or prevented. Therefore, a semiconductor device with improved reliability and performance can be provided.

[0107] The description of the second auxiliary electrodes 138_2B, 138_2C, and 138_2D respectively disposed on the second to fourth element isolation films 110_B, 110_C, and 110_D is similar to the description of the second auxiliary electrode 138_2A disposed on the first element isolation film 110_A. Therefore, its detailed description is omitted.

[0108] exist Figure 6 In some embodiments of this disclosure, the second auxiliary electrode 138_2A disposed on the first element isolation film 110_A may not overlap with the second gate electrode 134_2A and the third gate electrode 134_3A in the first direction X. For example, in Figure 6 In the plan view, the shortest distance d3 from the first active region 105A to the second auxiliary electrode 138_2A in the second direction Y can be greater than the maximum distance d4 from the first active region 105A to the third gate electrode 134_3A in the second direction Y. In some embodiments of this disclosure, the shortest distance d3 from the first active region 105A to the second auxiliary electrode 138_2A in the second direction Y can be 0.3 μm. However, this is just an example.

[0109] Furthermore, in some embodiments of this disclosure, the second auxiliary electrode 138_2A disposed on the first element isolation film 110_A may not overlap with the second gate electrode 134_2A and the third gate electrode 134_3A in the second direction Y. For example, in Figure 6 In the planar view, the distance d1 from the second gate electrode 134_2A to the second auxiliary electrode 138_2A in the first direction X can be 0.2 μm. Furthermore, for example, in... Figure 6 In the planar diagram, the distance d2 from the second auxiliary electrode 138_2A to the third gate electrode 134_3A in the first direction X can be 0.2μm.

[0110] In some embodiments of this disclosure, the first auxiliary electrode 138_1A disposed on the first element isolation film 110_A may not overlap with the first gate electrode 134_1A and the second gate electrode 134_2A in the first direction X and the second direction Y. Since its description is similar to that for the second auxiliary electrode 138_2A, its detailed description is omitted. For example, the first auxiliary electrode 138_1A and the second auxiliary electrode 138_2A disposed on the first element isolation film 110_A may be spaced apart from each other in the first direction X.

[0111] The first auxiliary dielectric films 136_1A and 136_1B and the second auxiliary dielectric film 136_2A may be located between the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2 and the element isolation film 110. The first auxiliary dielectric films 136_1A and 136_1B and the second auxiliary dielectric film 136_2A may be formed at the same height as each of the first gate dielectric films 132_1A and 132_1B, the second gate dielectric film 132_2A and the third gate dielectric film 132_3AB.

[0112] For example, each of the first auxiliary dielectric films 136_1A and 136_1B and the second auxiliary dielectric film 136_2A may include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, and high-k materials with a dielectric constant higher than that of silicon oxide. High-k materials may include, but are not limited to, at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0113] Interlayer insulating film 160 may be formed on first substrate 100. Interlayer insulating film 160 may cover first substrate 100, element isolation film 110, and first to fourth circuit elements TR1, TR2, TR3 and TR4.

[0114] The interlayer insulating film 160 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material with a dielectric constant lower than that of silicon oxide. The low-k material may include, but is not limited to, at least one of FOX (flowable oxide), TOSZ (Toron silane), USG (undoped silicon glass), BSG (borosilicate glass), PSG (phosphorus quartz glass), BPSG (borophosphorus glass), PETEOS (plasma-enhanced tetraethyl orthosilicate), FSG (fluorosilicate glass), CDO (carbon-doped silicon dioxide), degelatin, aerogel, amorphous fluorinated carbon, OSG (organosilicon glass), parylene, BCB (bisbenzocyclobutene), SiLK, polyimide, porous polymer materials, and combinations thereof.

[0115] The gate contact 142 can contact each of the first to third gate electrodes 134_1A to 134_1D, 134_2A to 134_2D, and 134_3A to 134_3D. For example, the gate contact 142 can extend in the third direction Z to extend through the interlayer insulating film 160. The gate contact 142 can be electrically connected to each of the first to third gate electrodes 134_1A to 134_1D, 134_2A to 134_2D, and 134_3A to 134_3D, and apply a voltage to each of the first to third gate electrodes 134_1A to 134_1D, 134_2A to 134_2D, and 134_3A to 134_3D.

[0116] The gate contact 142 may be, but is not limited to, a metal such as aluminum (Al), copper (Cu) or tungsten (W).

[0117] The source / drain contact 144 can contact each of the first source / drain regions 120_1A and 120_1B, the second source / drain regions 120_2A and 120_2B, the third source / drain region 120_3A, and the fourth source / drain region 120_4A. For example, the source / drain contact 144 can extend in the third direction Z to extend through the interlayer insulating film 160. The source / drain contact 144 can be electrically connected to each of the first source / drain regions 120_1A and 120_1B, the second source / drain regions 120_2A and 120_2B, the third source / drain region 120_3A, and the fourth source / drain region 120_4A, and can apply a voltage to each of the first source / drain regions 120_1A and 120_1B, the second source / drain regions 120_2A and 120_2B, the third source / drain region 120_3A, and the fourth source / drain region 120_4A.

[0118] The source / drain contact 144 may include, but is not limited to, a metal such as aluminum (Al), copper (Cu), or tungsten (W). In some embodiments, the gate contact 142 and the source / drain contact 144 may be formed at the same height. For example, the gate contact 142 and the source / drain contact 144 may comprise the same material.

[0119] The auxiliary electrode contact 146 can contact each of the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2. For example, the auxiliary electrode contact 146 can extend in a third direction Z to extend through the interlayer insulating film 160. The auxiliary electrode contact 146 can be electrically connected to each of the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2, and a voltage can be applied to each of the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2.

[0120] The auxiliary electrode contact 146 may include, for example, a metal such as aluminum (Al), copper (Cu), or tungsten (W). However, embodiments of this disclosure are not limited thereto. In some embodiments of this disclosure, the auxiliary electrode contact 146, the gate contact 142, and the source / drain contact 144 may be formed at the same height.

[0121] The first impurity region contact 155 may contact the impurity region 150. The first impurity region contact 155 is shown in contact with the first impurity region 150X. However, embodiments of this disclosure are not limited thereto. For example, the first impurity region contact 155 may extend in the third direction Z to extend through the interlayer insulating film 160. The first impurity region contact 155 may be electrically connected to the impurity region 150 to apply a voltage to the impurity region 150.

[0122] The first impurity region contact 155 may be, but is not limited to, a metal such as aluminum (Al), copper (Cu), or tungsten (W). In some embodiments of this disclosure, the first impurity region contact 155, the auxiliary electrode contact 146, the gate contact 142, and the source / drain contact 144 may be formed at the same height.

[0123] exist Figure 4 In this configuration, connection pattern 170 connects the auxiliary electrode contact 146 and the first impurity region contact 155 to each other. Connection pattern 170 also connects the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2 to the impurity region 150. Through connection pattern 170, the impurity region 150, to which a ground voltage is applied, can be electrically connected to the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2, thereby allowing a ground voltage to be applied to both the first and second auxiliary electrodes 138_1 and 138_2. Therefore, the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2, to which a ground voltage is applied, can be positioned adjacent to the first to fourth source / drain regions 120_2A, 120_3A, and 120_2B, thereby providing a semiconductor device with improved performance and reliability.

[0124] The connecting pattern 170 may include, for example, a metal such as aluminum (Al), copper (Cu), or tungsten (W). However, embodiments of this disclosure are not limited thereto.

[0125] Figure 7 It is a layout diagram used to illustrate semiconductor devices according to some embodiments of the present disclosure. Figure 8 It is along Figure 7 A schematic cross-sectional view of line AA. For ease of description, a brief description has been referenced above. Figures 1 to 6 The description contains repeated content, or the description is omitted.

[0126] refer to Figure 7 and Figure 8 In the plan view, auxiliary electrodes 138_A, 138_B, 138_C, and 138_D can be connected in the second direction Y to the first to third gate electrodes 134_1A to 134_1D, 134_2A to 134_2D, and 134_3A to 134_3D, and the second source / drain region (see...). Figure 3 120_2A in the middle) and the third source / drain region (see ... Figure 3 The 120_3A in the middle overlaps.

[0127] In some embodiments of this disclosure, each of the auxiliary electrodes 138_A, 138_B, 138_C, and 138_D may not be divided into two auxiliary electrodes, but may be implemented as a single structure extending elongated in the first direction X, as described above. Figures 1 to 6 The embodiments described herein differ from those in the text.

[0128] In some embodiments of this disclosure, in a plan view, each of the auxiliary electrodes 138_A, 138_B, 138_C, and 138_D may be not adjacent to the first source / drain region in the second direction Y (see [reference]). Figure 3 120_1A) and the fourth source / drain region (see ... Figure 3 (120_4A) overlap.

[0129] Figure 9 It is a layout diagram used to illustrate semiconductor devices according to some embodiments of the present disclosure. Figure 10 It is along Figure 9 A schematic cross-sectional view of line AA. For ease of description, a brief description will be provided in conjunction with the above references. Figures 1 to 6 The description contains repeated content, or the description is omitted.

[0130] refer to Figure 9 and Figure 10 The semiconductor device according to some embodiments of the present disclosure may further include a first dummy auxiliary electrode 138DX and a second dummy auxiliary electrode 138DY.

[0131] In some embodiments of this disclosure, in a plan view, the first dummy auxiliary electrode 138DX may be located in the second direction Y, adjacent to the first source / drain region (see [reference]). Figure 3 120_1A) and the fourth source / drain region (see ... Figure 3 The second dummy auxiliary electrode 138DY overlaps with the first source / drain region 120_1A and the fourth source / drain region 120_4A in the first direction X. In the plan view, at least a portion of the second dummy auxiliary electrode 138DY may overlap with the first source / drain region 120_1A and the fourth source / drain region 120_4A in the first direction X.

[0132] In some embodiments of this disclosure, the first dummy auxiliary electrode 138DX and the second dummy auxiliary electrode 138DY can be formed at the same height as each of the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2. However, the first dummy auxiliary electrode 138DX and the second dummy auxiliary electrode 138DY may not be in contact with the auxiliary electrode contact portion 146. That is, no voltage may be applied to the first dummy auxiliary electrode 138DX and the second dummy auxiliary electrode 138DY. Therefore, even if the first dummy auxiliary electrode 138DX and the second dummy auxiliary electrode 138DY are provided, it is possible to achieve the desired effect. Figures 1 to 6 As with the embodiments shown, characteristic degradation can be prevented due to the reduction in cutoff current and the increase in breakdown voltage, thereby providing semiconductor devices with improved performance and reliability.

[0133] The number and arrangement of the first dummy auxiliary electrode 138DX and the second dummy auxiliary electrode 138DY are merely examples and are not limited to the number and arrangement shown. For example, the first dummy auxiliary electrode 138DX and the second dummy auxiliary electrode 138DY can be connected to each other.

[0134] Figure 11 It is a layout diagram used to illustrate semiconductor devices according to some embodiments of the present disclosure. Figure 12 It is along Figure 11 A schematic cross-sectional view of line AA. For ease of description, a brief description will be provided in conjunction with the above references. Figures 1 to 6 The description contains repeated content, or the description is omitted.

[0135] refer to Figure 11 and Figure 12 In some embodiments of this disclosure, the impurity region 150 may extend in the first direction X.

[0136] In some embodiments of this disclosure, with Figures 1 to 6 Unlike the embodiments described above, the impurity region 150 may not include a second impurity region extending in the second direction Y (see [reference]). Figure 1 (150Y). That is, the impurity region 150 may isolate the multiple active regions 105A, 105B, 105C and 105D from each other only in the second direction Y, but may not isolate the multiple active regions 105A, 105B, 105C and 105D from each other in the first direction X. However, the technical concept of this disclosure is not limited to this, for example, with Figure 11 As shown, impurity region 150 may extend in the second direction Y and may not be included in the first impurity region extending in the first direction X (see...). Figure 1 (150X in the middle).

[0137] The first impurity region contact portion 155 can contact the impurity region 150. Although not shown, the second impurity region contact portion (see...) Figure 1 156) can contact the impurity region 150.

[0138] Figure 13 This is a layout diagram illustrating semiconductor devices according to some embodiments of the present disclosure. For ease of description, a brief description has been referenced above. Figures 1 to 6 The description contains repeated content, or the description is omitted.

[0139] refer to Figure 13 In some embodiments of this disclosure, the impurity region 150 may include a plurality of sub-impurity regions spaced apart from each other.

[0140] In some embodiments of this disclosure, a sub-impurity region may be disposed between the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2. For example, the sub-impurity region may be disposed between the first auxiliary electrode 138_1A adjacent to the first active region 105A and the first auxiliary electrode 138_1C adjacent to the third active region 105C. The first impurity region contact portion 155 may contact the sub-impurity region.

[0141] Figure 14 This is a layout diagram illustrating semiconductor devices according to some embodiments of the present disclosure. For ease of description, a brief description has been referenced above. Figures 1 to 6 The description contains repeated content, or the description is omitted.

[0142] refer to Figure 14 Semiconductor devices according to some embodiments of this disclosure may not include impurity regions (see [link]). Figure 1 (150).

[0143] In some embodiments of this disclosure, the element isolation film 110 may isolate a plurality of active regions 105A, 105B, 105C, and 105D from each other in a first direction X and a second direction Y. A first auxiliary electrode 138_1 and a second auxiliary electrode 138_2 may be located between adjacent active regions among the plurality of active regions 105A, 105B, 105C, and 105D that are spaced apart from each other in the second direction Y.

[0144] In some embodiments of this disclosure, the auxiliary electrode contact 146 can contact the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2. A ground voltage can be applied to the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2 through the auxiliary electrode contact 146.

[0145] Figure 15 It is a layout diagram used to illustrate semiconductor devices according to some embodiments of the present disclosure. Figure 16 It shows Figure 15 A magnified view of the R2 region. For ease of description, a brief description has been referenced above. Figures 1 to 6 The description contains repeated content, or the description is omitted.

[0146] refer to Figure 15 and Figure 16 The first auxiliary electrode 138_1 and the second auxiliary electrode 138_2 may overlap with the first gate electrode to the third gate electrode 134_1A to 134_1D, 134_2A to 134_2D and 134_3A to 134_3D in the first direction X.

[0147] exist Figure 16 In the planar diagram, the shortest distance d7 from the first active region 105A to the second auxiliary electrode 138_2A can be less than the maximum distance d6 from the first active region 105A to the third source / drain region 134_3A. In this case, the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2 with applied ground voltage can achieve a reduction in cutoff current and an increase in breakdown voltage, thereby preventing characteristic degradation and providing a semiconductor device with improved performance and reliability.

[0148] In addition, Figure 16 In the planar diagram, the distance d5 from the second gate electrode 134_2A to the second auxiliary electrode 138_2A in the first direction X can be 0.2 μm. Furthermore, for example, in... Figure 16 In the planar diagram, the distance d6 from the second auxiliary electrode 138_2A to the third gate electrode 134_3A in the first direction X can be 0.2 μm. However, this is only an example, and the technical concept of this disclosure is not limited thereto.

[0149] Figure 17 It is a layout diagram used to illustrate semiconductor devices according to some embodiments of the present disclosure. Figure 18 It is along Figure 17 A schematic cross-sectional view of line AA. Figure 19 It is along Figure 17 A schematic cross-sectional view of line CC. For ease of description, a brief description will be provided in conjunction with the above references. Figures 1 to 6 The description contains repeated content, or the description is omitted.

[0150] refer to Figure 17 and Figure 19 The impurity isolation region 180 may surround the first to fourth active regions 105A, 105B, 105C and 105D. The impurity isolation region 180 may be disposed below the isolation film 110 of each element.

[0151] For example, a portion of the isolation impurity region 180 may extend in the second direction Y while being disposed between the first active region 105A and the second active region 105B. Furthermore, another portion of the isolation impurity region 180 may extend in the first direction X while being disposed between the first active region 105A and the third active region 105C.

[0152] The isolation impurity region 180 may be doped with impurities of a first conductivity type. For example, the isolation impurity region 180 may contain p-type impurities.

[0153] The impurity isolation region 180 may overlap at least a portion of each of the first auxiliary electrode 138_1 and the second auxiliary electrode 138_2 in the third direction Z. The impurity isolation region 180, the first auxiliary electrode 138_1, and the second auxiliary electrode 138_2 may be spaced apart from each other, and the element isolation film 110 is interposed therebetween.

[0154] Because the isolation impurity region 180 is located below the device isolation film 110, a decrease in breakdown voltage may occur. However, in semiconductor devices according to some embodiments of the present disclosure, a first auxiliary electrode 138_1 and a second auxiliary electrode 138_2 with a ground voltage applied are provided on the device isolation film 110, which prevents a decrease in breakdown voltage, thereby providing improved performance and reliability for the semiconductor device.

[0155] In the following text, reference will be made to Figures 1 to 25 Describes non-volatile storage devices according to some embodiments.

[0156] Figure 20 This is a schematic block diagram illustrating a non-volatile storage device according to some embodiments of the present disclosure. Figure 21 This is a schematic cross-sectional view used to illustrate a non-volatile storage device according to some embodiments of the present disclosure. Figure 22 and Figure 23 It shows Figure 21 Various magnified views of the R3 region. For ease of description, a brief description will be provided in conjunction with the above references. Figures 1 to 19 The description contains repeated content, or the description is omitted.

[0157] refer to Figure 20 According to some embodiments, a non-volatile storage device may include a first structure 1100F and a second structure 1100S disposed on the first structure 1100F.

[0158] In some embodiments, the first structure 1100F may be located adjacent to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure, which includes a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure, which includes a bit line BL, a common source line CSL, a word line WL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0159] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary depending on the embodiment.

[0160] In some embodiments, upper transistors UT1 and UT2 may include string select transistors, while lower transistors LT1 and LT2 may include ground select transistors. A first lower gate line LL1 and a second lower gate line LL2 may be the gate electrodes of lower transistors LT1 and LT2, respectively. Word lines WL may be the gate electrodes of memory cell transistors MCT, respectively. A first upper gate line UL1 and a second upper gate line UL2 may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0161] In some embodiments of this disclosure, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 can be used for an erase operation that uses the gate-sensed drain leakage (GIDL) phenomenon to erase data stored in the memory cell transistor MCT.

[0162] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first connection wiring 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second connection wiring 1125 extending from the first structure 1100F to the second structure 1100S.

[0163] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130.

[0164] refer to Figure 21 According to some embodiments, a non-volatile memory device may include a peripheral circuit area (PERI) and a cell area (CELL).

[0165] The peripheral circuit region PERI may include a first substrate 100, an interlayer insulating film 160, a plurality of circuit elements TR1, TR2, TR3, 220a and 220b formed on the first substrate 100, first metal layers 144, 156, 230a and 230b connected to each of the plurality of circuit elements TR1, TR2, TR3, 220a and 220b, and second metal layers 240, 240a and 240b formed on the first metal layers 144, 156, 230a and 230b.

[0166] In some embodiments, the first to third circuit elements TR1, TR2, and TR3 may provide decoder circuitry in the peripheral circuitry region PERI (e.g., Figure 20 (1110). In some embodiments, the fourth circuit element 230a may provide logic circuitry in the peripheral circuit region PERI (e.g., Figure 20 (1130). In some embodiments, the fifth circuit element 230b may provide a page buffer in the peripheral circuit region PERI (e.g., Figure 20 (1120).

[0167] In this document, only the first metal layers 144 and 156 (also shown as, for example) are shown and described. Figure 3 The source / drain contact 144 and the second impurity region contact 156, 230a and 230b, and the second metal layers 240, 240a and 240b are shown. However, embodiments of this disclosure are not limited thereto, and at least one or more metal layers may be further formed on the second metal layers 240, 240a and 240b. At least some of the one or more metal layers formed on the second metal layers 240, 240a and 240b may be made of aluminum or the like, which have a lower resistivity than copper, which constitutes the second metal layers 240, 240a and 240b.

[0168] In some embodiments, the first metal layers 144, 156, 230a and 230b may be made of tungsten, which has relatively high resistance, while the second metal layers 240, 240a and 240b may be made of copper, which has relatively low resistance.

[0169] An interlayer insulating film 160 may be disposed on a first substrate 100 to cover multiple circuit elements TR1, TR2, TR3, 220a and 220b, first metal layers 144, 156, 230a and 230b, and second metal layers 240, 240a and 240b.

[0170] A cell region (CELL) can provide at least one memory block. The cell region (CELL) may include a second substrate 310 and a common source line 320. Multiple word lines 331 to 338 (i.e., 330) may be stacked on the second substrate 310 along a vertical direction Z intersecting the upper surface of the second substrate 310. Serial select lines (e.g., ...) Figure 20 UL1 and UL2 in the middle) and ground selection line (e.g., Figure 20 LL1 and LL2 can be set at the top of word line 330 and below word line 330 respectively, and multiple word lines 330 can be set between serial select line and ground select line.

[0171] The channel structure CH can extend in the vertical direction Z to extend through word line 330, serial select line, and ground select line. For example... Figure 22 and Figure 23 As shown, the channel structure CH may include a semiconductor pattern 390 and an information storage film 392.

[0172] Semiconductor pattern 390 may extend in the Z direction. Semiconductor pattern 390 is shown as having a cup shape. However, this is only an example, and semiconductor pattern 390 may have various shapes such as a circular pillar shape, a square pillar shape, a solid pillar shape, etc. Semiconductor pattern 390 may include, but is not limited to, semiconductor materials such as monocrystalline silicon, polycrystalline silicon, organic semiconductor materials, and carbon nanostructures.

[0173] The information storage film 392 may be located between the semiconductor pattern 390 and the word line 330. For example, the information storage film 392 may extend along the side surface of the semiconductor pattern 390.

[0174] In some embodiments, the information storage film 392 may be formed as a stack of multiple films. For example, the information storage film 392 may include a tunnel insulating film 392a, a charge storage film 392b, and a barrier insulating film 392c sequentially stacked on a semiconductor pattern 390. The tunnel insulating film 392a may, for example, include silicon oxide or a high-k material with a dielectric constant higher than that of silicon oxide. The high-k material may, for example, include aluminum oxide (Al2O3) or hafnium oxide (HfO2). The charge storage film 392b may, for example, include silicon nitride. The barrier insulating film 392c may, for example, include silicon oxide or a high-k material with a dielectric constant higher than that of silicon oxide.

[0175] In some embodiments, the channel structure CH may further include a fill pattern 394. The fill pattern 394 may be formed to fill the interior of the semiconductor pattern 130 having a cup shape. The fill pattern 394 may include, but is not limited to, an insulating material, such as silicon oxide.

[0176] The common source line 320 can be formed as a semiconductor pattern 390 of the contact channel structure CH.

[0177] like Figure 22 As shown, in some embodiments, the channel structure CH may extend through the common source line 320 to be partially embedded in the second substrate 310. The common source line 320 may extend through a portion of the information storage film 392 to contact the side surface of the semiconductor pattern 390. The common source line 320 may include a source layer 321 and a source support layer 106.

[0178] like Figure 23 As shown, in some embodiments, at least a portion of the common source line 320 may be embedded in the second substrate 310. The common source line 320 may be formed from the second substrate 310, for example, in a selective epitaxial growth (SEG) process. The channel structure CH may extend through a portion of the information storage film 392 to contact the upper surface of the common source line 320.

[0179] The channel structure CH can be electrically connected to the first metal layer 350c and the second metal layer 360c. For example, the first metal layer 350c can be a bit line contact, and the second metal layer 360c can be a bit line (e.g., Figure 20 (BL). In some embodiments, bit line 360c may extend in a direction parallel to the upper surface of the second substrate 310 (e.g., the second direction Y). In some embodiments, bit line 360c may be electrically connected to a fifth circuit element 230b, which provides a page buffer (e.g., BL) in the peripheral circuit region PERI. Figure 20 (1120).

[0180] Word lines 330 may extend in a direction parallel to the upper surface of the second substrate 310 (e.g., a first direction X) and may be connected to a plurality of cell contact plugs 340. Word lines WL and cell contact plugs 340 may be connected to each other via pads formed by extending at least some of the word lines WL to different lengths. A first metal layer 350b and a second metal layer 360b may be sequentially stacked on the cell contact plugs 340 connected to the word lines 330 and may be connected to the top of the cell contact plugs 340.

[0181] In some embodiments of this disclosure, the unit contact plug 340 may be electrically connected to first to third circuit elements TR1, TR2, and TR3, which provide decoder circuitry in the peripheral circuitry area PERI (e.g., Figure 20 (1110). In one example, the first metal layer 350b connected to the cell contact plug 340 can be connected to the first metal layer 350d via the second metal layer 360b. The first metal layer 350d can be connected to the second metal layer 340 via the connection contact plug 345. Therefore, the first circuit elements to the third circuit elements TR1, TR2 and TR3 can be electrically connected to the word lines 330. For example, the first circuit element TR1 can be electrically connected to some of the word lines 330, the second circuit element TR2 can be electrically connected to the other word lines in the word lines 330, and the third circuit element TR3 can be electrically connected to the other word lines in the word lines 330.

[0182] In some embodiments of this disclosure, the operating voltage of each of the first to third circuit elements TR1, TR2, and TR3 may differ from that of the fifth circuit element 220b providing the page buffer (e.g., Figure 20 The operating voltage of the fifth circuit element 220b is greater than the operating voltage of each of the first to third circuit elements TR1, TR2 and TR3.

[0183] The common source contact plug 380 can be electrically connected to the common source line 320. The common source contact plug 380 can be made of a conductive material such as metal, metal compound or polysilicon, and a first metal layer 350a can be formed on top of the common source contact plug 380.

[0184] In some embodiments of this disclosure, a lower insulating film 201 covering the lower surface of the first substrate 100 may be formed below the first substrate 100. A first input / output pad 205 may be formed on the lower insulating film 201. The first input / output pad 205 may be connected via a first input / output contact plug 203 to at least one of a plurality of circuit elements TR1, TR2, TR3, 220a, and 220b disposed in the peripheral circuit area PERI, and may be isolated from the first substrate 100 via the lower insulating film 201. Furthermore, a side insulating film may be disposed between the first input / output contact plug 203 and the first substrate 100 to electrically insulate the first input / output contact plug 203 and the first substrate 100 from each other.

[0185] In some embodiments of this disclosure, an upper insulating film 301 covering the upper surface of the second substrate 310 may be formed on top of the second substrate 310, and a second input / output pad 305 may be disposed on the upper insulating film 301. The second input / output pad 305 may be connected via a second input / output contact plug 303 to at least one of a plurality of circuit elements TR1, TR2, TR3, 220a, and 220b disposed in the peripheral circuit area PERI.

[0186] In some embodiments of this disclosure, the second substrate 310 and the common source line 320 may not be provided in the region where the second input / output contact plug 303 is provided. Furthermore, the second input / output pad 305 may not overlap with the word line 330 in the vertical direction Z. The second input / output contact plug 303 may be isolated from the second substrate 310 in a direction parallel to the upper surface of the second substrate 310 (e.g., the first direction X), and may extend through the interlayer insulating film 315 of the cell region to connect to the second input / output pad 305.

[0187] In some embodiments, a first input / output pad 205 and a second input / output pad 305 may optionally be formed. In one example, a non-volatile memory device according to some embodiments may include only the first input / output pad 205 disposed on the first substrate 100, or may include only the second input / output pad 305 disposed on the second substrate 310. Alternatively, a non-volatile memory device according to some embodiments may include both the first input / output pad 205 and the second input / output pad 305.

[0188] In some embodiments of this disclosure, the second impurity region contact 156 may be electrically connected to the first input / output pad 205 or the second input / output pad 305 via the first input / output contact plug 203 or the second input / output contact plug 303. Therefore, a voltage can be applied to the second impurity region contact 156.

[0189] Figure 24 This is a schematic cross-sectional view used to illustrate a semiconductor device according to some embodiments of the present disclosure. Figure 25 yes Figure 24 A magnified view of the R3 region. For ease of description, a brief description has been referenced above. Figures 1 to 23 The description contains repeated content, or the description is omitted.

[0190] refer to Figure 24 According to some embodiments, non-volatile storage devices may have a C2C (chip-to-chip) structure.

[0191] In this respect, a C2C structure can refer to a structure in which at least one upper chip, including a memory cell area (CELL), is disposed on a first wafer, and a lower chip, including a peripheral circuit area (PERI), is disposed on a second wafer different from the first wafer, and the upper and lower chips are then connected to each other using a bonding scheme. In one example, the bonding scheme refers to a scheme for electrically connecting a first bonding metal formed in the uppermost metal layer of the upper chip and a second bonding metal formed in the uppermost metal layer of the lower chip to each other. For example, when each of the first and second bonding metals is made of copper (Cu), the bonding scheme can be embodied as a Cu-Cu bonding scheme. However, this is merely an example. In another example, each of the first and second bonding metals can be made of various other metals such as aluminum (Al) or tungsten (W).

[0192] In some embodiments, each of the peripheral circuit area PERI and the cell area CELL may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0193] A word line bonding area (WLBA) can be defined as an area in which multiple cell contact plugs 340, etc., are disposed. Lower bonding metals 271b and 272b can be formed on a second metal layer 240 of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 271b and 272b of the peripheral circuit area (PERI) can be electrically connected in a bonding manner to the upper bonding metals 371b and 372b of the cell area (CELL). Each of the lower bonding metals 271b and 272b and the upper bonding metals 371b and 372b can be made of aluminum, copper, or tungsten. In the word line bonding area WLBA, the cell contact plugs 340 can be connected to the peripheral circuit area (PERI) via the upper bonding metals 371b and 372b of the cell area (CELL) and the lower bonding metals 271b and 272b of the peripheral circuit area (PERI).

[0194] The bit line bonding area (BLBA) can be defined as the region in which a channel structure (CH) and a bit line 360c are disposed. The bit line 360c can be electrically connected to a fifth circuit element 220b in the bit line bonding area (BLBA). For example, the bit line 360c can be connected to upper bonding metals 371c and 372c in the peripheral circuit area (PERI). The upper bonding metals 371c and 372c can be connected to lower bonding metals 271c and 272c connected to the fifth circuit element 220b.

[0195] A common source line contact plug 380 can be disposed in the external pad bonding area PA. The common source line contact plug 380 can be made of a conductive material such as metal, metal compound, or polysilicon, and can be electrically connected to the common source line 320. A first metal layer 350a and a second metal layer 360a can be disposed on top of the common source line contact plug 380, and can be stacked sequentially. For example, the area where the common source line contact plug 380, the first metal layer 350a, and the second metal layer 360a are disposed can be defined as the external pad bonding area PA. Furthermore, input / output pads 205 and 305 can be disposed in the external pad bonding area PA.

[0196] The metal pattern of the topmost metal layer in each of the external pad bonding area (PA) and bit line bonding area (BLBA) included in the cell area (CELL) and peripheral circuit area (PERI) can exist as a dummy pattern. Alternatively, the topmost metal layer of each of the external pad bonding area (PA) and bit line bonding area (BLBA) included in the cell area (CELL) and peripheral circuit area (PERI) can be empty.

[0197] In a non-volatile memory device according to some embodiments, in the external pad bonding area PA, a lower metal pattern 273a with the same shape as the upper metal pattern 372a of the cell region CELL can be formed in the uppermost metal layer of the peripheral circuit region PERI in a manner corresponding to the formation of the upper metal pattern 372a in the uppermost metal layer of the cell region CELL. The lower metal pattern 273a formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a separate contact in the peripheral circuit region PERI. Similarly, in the external pad bonding area PA, an upper metal pattern with the same shape as the lower metal pattern of the peripheral circuit region PERI can be formed in the upper metal layer of the cell region CELL in a manner corresponding to the formation of the lower metal pattern in the uppermost metal layer of the peripheral circuit region PERI.

[0198] Furthermore, in the bit line bonding area BLBA, the upper metal pattern 372d, which has the same shape as the lower metal pattern 272d of the peripheral circuit area PERI, can be formed in the uppermost metal layer of the cell area CELL in a manner corresponding to the formation of the lower metal pattern 272d in the uppermost metal layer of the peripheral circuit area PERI. No contact portion may be formed on the upper metal pattern 372d formed in the uppermost metal layer of the cell area CELL.

[0199] In the following text, reference will be made to Figures 1 to 33 Methods for manufacturing semiconductor devices according to some embodiments of the present disclosure are described.

[0200] Figures 26 to 33This is a diagram of an intermediate structure corresponding to an intermediate step in a method for manufacturing a semiconductor device according to some embodiments of this disclosure. For ease of description, a brief description will be provided in conjunction with the above-referenced diagram. Figures 1 to 19 The description contains repeated content, or the description is omitted.

[0201] refer to Figure 26 and Figure 27 The element isolation trench 110t can be formed in the first substrate 100.

[0202] Specifically, the first active region 105A and the second active region 105B can be defined by the element isolation trench 110t.

[0203] refer to Figure 28 and Figure 29 The component isolation films 110_A and 110_B can fill the component isolation trench 110t.

[0204] Next, the first auxiliary dielectric films 136_1A and 136_1B, the second auxiliary dielectric film 136_2A, and the first auxiliary electrodes 138_1A and 138_1B, and the second auxiliary electrode 138_2A can be sequentially formed on the element isolation films 110_A and 110_B. At the same height, the first gate dielectric films 132_1A and 132_1B, the second gate dielectric film 132_2A and the third gate dielectric film 132_3A, and the first gate electrodes 134_1A and 134_1B, the second gate electrode 134_2A and the third gate electrode 134_3A are sequentially formed on the first active region 105A and the second active region 105B.

[0205] refer to Figure 30 and Figure 31 Impurity region 150 can be formed between element isolation films 110_A and 110_B, and first source / drain regions 120_1A and 120_1B, second source / drain regions 120_2A and 120_2B, third source / drain region 120_3A and fourth source / drain region 120_4A can be formed between element isolation films 110_A and 110_B and first gate electrodes 134_1A and 134_1B, second gate electrode 134_2A and third gate electrode 134_3A.

[0206] Specifically, the impurity region 150 and the first source / drain regions 120_1A and 120_1B, the second source / drain regions 120_2A and 120_2B, the third source / drain region 120_3A, and the fourth source / drain region 120_4A can be formed at the same height. However, the embodiments of this disclosure are not limited thereto. For example, the impurity region 150 can be formed first, and then the first source / drain regions 120_1A and 120_1B, the second source / drain regions 120_2A and 120_2B, the third source / drain region 120_3A, and the fourth source / drain region 120_4A can be formed. The impurity region 150 and the first source / drain regions 120_1A and 120_1B, the second source / drain regions 120_2A and 120_2B, the third source / drain region 120_3A, and the fourth source / drain region 120_4A can be doped with impurities of the same conductivity type. For example, impurity region 150 and first source / drain regions 120_1A and 120_1B, second source / drain regions 120_2A and 120_2B, third source / drain region 120_3A and fourth source / drain region 120_4A may be doped with n-type impurities.

[0207] refer to Figure 32 and Figure 33 The interlayer insulating film 160 may cover the element isolation films 110_A and 110_B, the first substrate 100, the first gate electrodes 134_1A and 134_1B, the second gate electrode 134_2A and the third gate electrode 134_3A, as well as the first auxiliary electrodes 138_1A and 138_1B and the second auxiliary electrode 138_2A.

[0208] Subsequently, gate contact hole 142t, source / drain contact hole 144t, auxiliary electrode contact hole 146t, and second impurity region contact hole 156t are formed. Gate contact hole 142t, source / drain contact hole 144t, auxiliary electrode contact hole 146t, and second impurity region contact hole 156t extend through interlayer insulating film 160 in the third direction Z.

[0209] Next, refer to Figures 1 to 3 The gate contact 142t, source / drain contact 144t, auxiliary electrode contact 146t, and second impurity region contact 156t are filled with conductive material, thereby forming the gate contact portion 142, source / drain contact portion 144, auxiliary electrode contact 146, and second impurity region contact portion 156. Therefore, it is possible to manufacture the above-described... Figures 1 to 6 Semiconductor devices according to some embodiments of the present disclosure are described.

[0210] In the following text, reference will be made to Figures 1 to 37 To describe an electronic system according to some embodiments of the present disclosure.

[0211] Figure 34This is an example block diagram illustrating an electronic system according to some embodiments of the present disclosure. Figure 35 This is an example perspective view used to illustrate an electronic system according to some embodiments of the present disclosure. Figure 36 and Figure 37 It is along Figure 35 Various schematic cross-sectional views of line I-I' are shown. For ease of description, a brief description is provided, referencing the above. Figures 1 to 33 The description contains repeated content, or the description is omitted.

[0212] refer to Figure 34 According to some embodiments, the electronic system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including the storage device. For example, the electronic system 1000 may be a solid-state drive (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0213] Semiconductor device 1100 may be a non-volatile memory device (e.g., a NAND flash memory device), and may be, for example, the one referenced above. Figures 20 to 24 The described non-volatile memory device. Semiconductor device 1100 can communicate with controller 1200 via input / output pads 1101 electrically connected to logic circuit 1130. Input / output pads 1101 can be electrically connected to logic circuit 1130 via input / output connection wiring 1135 extending from first structure 1100F to second structure 1100S.

[0214] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the electronic system 1000 may include a plurality of semiconductor devices 1100. In this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0215] Processor 1210 can control the overall operation of electronic system 1000, including controller 1200. Processor 1210 can operate according to desired and / or alternatively predetermined firmware, and can control NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 may include NAND interface 1221, which handles communication with semiconductor device 1100. Through NAND interface 1221, control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, data to be read from memory cell transistors (MCTs) of semiconductor device 1100, etc., can be sent. Host interface 1230 provides communication functionality between electronic system 1000 and external host. When a control command is received from external host via host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0216] refer to Figure 35 An electronic system according to some embodiments may include a main substrate 2001 (e.g., a motherboard), a main controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the main controller 2002 via a circuit pattern 2005 formed on the main substrate 2001.

[0217] The main substrate 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary based on the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may communicate with the external host using one of an interface such as USB (Universal Serial Bus), PCI Fast (Peripheral Component Interconnect High Speed ​​Interface), SATA (Serial Advanced Technology Attachment), or M-Phy for UFS (Universal Flash Memory). In some embodiments, the electronic system 2000 may operate using power supplied from the external host via the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the main controller 2002 and the semiconductor package 2003.

[0218] The main controller 2002 can write data to or read data from the semiconductor package 2003, and can improve the operating speed of the electronic system 2000.

[0219] DRAM 2004 can act as a buffer memory to reduce the speed difference between the semiconductor package 2003, which serves as data storage space, and the operating speed of the external host. The DRAM 2004 included in the electronic system 2000 can act as a cache memory and can provide space for temporary data storage during the control operation of the semiconductor package 2003. When DRAM 2004 is included in the electronic system 2000, in addition to the NAND controller for controlling the semiconductor package 2003, the main controller 2002 may also include a DRAM controller for controlling the DRAM 2004.

[0220] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be implemented as a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include: a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the bottom surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100 to each other, and a molding layer 2500 disposed on the package substrate 2100 and covering the semiconductor chips 2200 and the connection structure 2400.

[0221] The package substrate 2100 can be implemented as a printed circuit board including on-package pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to... Figure 34 The input / output pads 1101. Each semiconductor chip 2200 may include a memory block 3210 and a channel structure 3220. The memory block 3210 may correspond to... Figure 21 The storage block, and the channel structure 3220 can correspond to Figure 21 The channel structure CH. Each semiconductor chip 2200 may include the channel structure CH used above. Figures 20 to 24 Described non-volatile storage devices.

[0222] In some embodiments, the connection structure 2400 may be implemented as bonding wiring that electrically connects the input / output pads 2210 and the on-package pads 2130 to each other. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wiring scheme and may be electrically connected to the on-package pads 2130 of the package substrate 2100. In some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including through-silicon vias (TSVs) instead of the connection structure 2400 using a bonding wiring scheme.

[0223] In some embodiments, the main controller 2002 and the semiconductor chip 2200 may be included in a single package. In some embodiments, the main controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate different from the main substrate 2001, and the main controller 2002 and the semiconductor chip 2200 may be interconnected with each other via lines formed on the interposer substrate.

[0224] refer to Figure 36 In semiconductor packaging 2003, the packaging substrate 2100 can be a printed circuit board. The packaging substrate 2100 may include a packaging substrate body 2120 and a [missing information - likely a component or element] disposed on the upper surface of the packaging substrate body 2120. Figure 35 The package includes an upper pad 2130, a lower pad 2125 disposed on or exposed through the lower surface of the package substrate body 2120, and internal wiring 2135 disposed within the package substrate body 2120 to electrically connect the upper pad 2130 and the lower pad 2125 to each other. The upper pad 2130 can be electrically connected to a connection structure 2400. The lower pad 2125 can be connected via a conductive connection portion 2800 to a wiring pattern 2005 (e.g., a wiring pattern) of the main substrate 2010 of the electronic system 2000, such as... Figure 35 As shown.

[0225] Each of the semiconductor chips 2200 may include a semiconductor substrate 3010, and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The semiconductor substrate 3010 may correspond to... Figure 21 The first substrate 100. The first structure 3100 may correspond to... Figure 21 The peripheral circuit region PERI, and the second structure 3200 can correspond to Figure 21 Cells.

[0226] For example, the second structure 3200 may include a second substrate 310, multiple word lines 330, a channel structure CH, and multiple cell contact plugs 340. In some embodiments, as shown in the figures, the first structure 3100 may include a device isolation film 110, first auxiliary electrodes 138_1A and 138_1B, and a second auxiliary electrode 138_2A. Each semiconductor chip 2200 may also include components electrically connected to the first structure 3100. Figure 35 Input / output pad 2210.

[0227] refer to Figure 37 In semiconductor package 2003A, each semiconductor chip 2200 may include a first structure 3100 and a second structure 3200 bonded to each other by a wafer bonding scheme. For example, the first structure 3100 may correspond to Figure 24 The peripheral circuit region PERI, and the second structure 3200 can correspond to Figure 24 Cells.

[0228] Figure 36 and Figure 37 The semiconductor chip 2200 in the middle can be transmitted via Figure 35 The interconnected wiring-type connection structures 2400 are electrically connected to each other. However, in some embodiments, the semiconductor chip 2200 (e.g., within a single semiconductor package) is electrically connected to each other. Figure 36 and Figure 37 The semiconductor chips 2200 can be electrically connected to each other via interconnection structures including through silicon vias (TSVs).

[0229] One or more of the elements disclosed above may include or be implemented in processing circuitry (e.g., hardware including logic circuitry; hardware / software combination, such as a processor executing software; or a combination thereof). For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0230] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments and can be implemented in various different forms. Those skilled in the art will understand that the present disclosure can be implemented in other specific forms without changing the technical spirit or essential characteristics of the present disclosure. Therefore, it should be understood that the above embodiments are illustrative in all respects and are not limiting in any way.

Claims

1. A semiconductor device, comprising: Substrate; A component isolation film is provided on the substrate, wherein the component isolation film defines a first active region of the substrate, the first active region of the substrate including a first source / drain region and a second source / drain region within the first active region, the first source / drain region contacting the component isolation film in a first direction and having a first conductivity type, and the second source / drain region being spaced apart from the first source / drain region in the first direction and having the first conductivity type; A first gate electrode is located on the portion of the first active region between the first source / drain region and the second source / drain region, wherein the first gate electrode extends in a second direction, the second direction intersecting the first direction; A second gate electrode is located on the first active region and extends in the second direction, wherein the second source / drain region is located between the first gate electrode and the second gate electrode; and The first auxiliary electrode is located on the isolation film of the element. In the planar view, the first auxiliary electrode does not overlap with the first source / drain region in the second direction, and the first auxiliary electrode overlaps with the second source / drain region in the second direction.

2. The semiconductor device according to claim 1, wherein, The first auxiliary electrode is subjected to a ground voltage.

3. The semiconductor device according to claim 1, wherein, The substrate further includes impurity regions within the substrate, and the impurity regions surround the device isolation film. The impurity region contains impurities with a second conductivity type, and The second conductivity type is different from the first conductivity type.

4. The semiconductor device according to claim 3, wherein, In the plan view, The first auxiliary electrode is located between the second source / drain region and the impurity region.

5. The semiconductor device according to claim 3, further comprising: A connection pattern is used to connect the first auxiliary electrode and the impurity region to each other. The impurity region is subjected to a ground voltage.

6. The semiconductor device according to claim 3, wherein, The first conductivity type is n-type, and The second conductivity type is p-type.

7. The semiconductor device according to claim 1, wherein, The first gate electrode and the first auxiliary electrode do not overlap each other in the first direction.

8. The semiconductor device according to claim 1, wherein, The first gate electrode and the first auxiliary electrode do not overlap each other in the second direction.

9. The semiconductor device according to claim 1, wherein, The first gate electrode and the first auxiliary electrode are at the same height.

10. The semiconductor device according to claim 1, wherein, The first active region of the substrate further includes a third source / drain region within the first active region. The third source / drain region is in contact with the device isolation film in the first direction, and the third source / drain region has the first conductivity type. The second gate electrode is located on the portion of the first active region between the second source / drain region and the third source / drain region, and In the plan view, the first auxiliary electrode does not overlap with the third source / drain region in the second direction.

11. The semiconductor device according to claim 1, further comprising: Third gate electrode; as well as The second auxiliary electrode is located on the isolation film of the element, wherein, The first active region of the substrate further includes a third source / drain region and a fourth source / drain region within the first active region. The third source / drain region is spaced apart from the second source / drain region in the first direction, and the third source / drain region has the first conductivity type. The fourth source / drain region is spaced apart from the third source / drain region in the first direction. The fourth source / drain region contacts the device isolation film in the first direction, and the fourth source / drain region has the first conductivity type. The third gate electrode is located on the portion of the first active region between the third source / drain region and the fourth source / drain region. The third gate electrode extends in the second direction, and In the plan view, the second auxiliary electrode overlaps with the third source / drain region in the second direction, but does not overlap with the fourth source / drain region in the second direction.

12. The semiconductor device according to claim 11, wherein, The second auxiliary electrode is spaced apart from the first auxiliary electrode in the first direction.

13. The semiconductor device according to claim 11, wherein, The first auxiliary electrode and the second auxiliary electrode are at the same height.

14. The semiconductor device according to claim 1, further comprising: A unit substrate, wherein the unit substrate is spaced apart from the substrate in a vertical direction, and the vertical direction intersects the upper surface of the substrate; Multiple word lines are stacked sequentially on the unit substrate; A channel structure is provided on the cell substrate, and the channel structure intersects with the plurality of word lines. as well as Bit lines contact the channel structure. The first source / drain region is electrically connected to one of the plurality of word lines.

15. A semiconductor device, comprising: Substrate; A component isolation film is provided on the substrate, wherein the component isolation film defines a first active region of the substrate, the first active region of the substrate including a first source / drain region and a second source / drain region, the first source / drain region having a first conductivity type, and the second source / drain region being spaced apart from the first source / drain region in a first direction and having the first conductivity type. A first gate electrode is located on the portion of the first active region between the first source / drain region and the second source / drain region, wherein the first gate electrode extends in a second direction and the second direction intersects the first direction; Auxiliary electrode, on the insulating film of the element, wherein, The substrate includes an impurity region surrounding the isolation film of the element. The impurity region contains impurities with a second conductivity type. The second conductivity type is different from the first conductivity type, and The auxiliary electrode and the impurity region are electrically connected to each other.

16. The semiconductor device according to claim 15, wherein, Ground voltage is applied to the auxiliary electrode and the impurity region.

17. The semiconductor device of claim 15, further comprising: The second gate electrode, wherein... The first active region further includes a third source / drain region within the first active region, the third source / drain region being in contact with the device isolation film in the first direction, and the third source / drain region having the first conductivity type. The second gate electrode is located on the portion of the first active region between the second source / drain region and the third source / drain region. The second gate electrode extends in the second direction. In the plan view, the auxiliary electrode does not overlap with the third source / drain region in the second direction.

18. The semiconductor device according to claim 17, wherein, In the plan view, the auxiliary electrode is located between the second source / drain region and the impurity region.

19. The semiconductor device of claim 15, further comprising: A unit substrate, spaced apart from the substrate in a vertical direction, the vertical direction intersecting the upper surface of the substrate; Multiple word lines are stacked sequentially on the unit substrate; A channel structure is provided on the cell substrate and intersects with the plurality of word lines. as well as Bit lines contact the channel structure. The first source / drain region is electrically connected to one of the plurality of word lines.

20. An electronic system comprising: Main substrate; A semiconductor device, on the main substrate, the semiconductor device includes a first substrate having a peripheral circuit region and a second substrate having a cell region; as well as The main controller is located on the main substrate and is electrically connected to the semiconductor device, wherein, The semiconductor device includes: a device isolation film on a first substrate; a first gate electrode; a second gate electrode; an auxiliary electrode on the device isolation film; a plurality of word lines sequentially stacked on the second substrate; a channel structure on the second substrate and intersecting the plurality of word lines; and bit lines contacting the channel structure, wherein... The device isolation film defines a first active region in the substrate. The first active region includes a first source / drain region and a second source / drain region. The first source / drain region contacts the element isolation film in a first direction and has a first conductivity type. The second source / drain region is spaced apart from the first source / drain region in the first direction and has the first conductivity type. The first gate electrode is located on the portion of the first active region between the first source / drain region and the second source / drain region. The first gate electrode extends in a second direction, which intersects with the first direction. The second gate electrode is located on the first active region and extends in the second direction. The second source / drain region is located between the first gate electrode and the second gate electrode, and In the plan view, the auxiliary electrode does not overlap with the first source / drain region in the second direction, and the auxiliary electrode overlaps with the second source / drain region in the second direction.

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