High electron mobility transistor and preparation method thereof
By introducing a connected depletion layer into a high electron mobility transistor and using secondary epitaxy to prepare the connected depletion layer in the trench, the problem of high preparation difficulty in vertical utilization is solved, and the effective utilization in the vertical direction and the breakdown voltage capability are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BOE HUACAN OPTOELECTRONICS (GUANGDONG) CO LTD
- Filing Date
- 2025-12-23
- Publication Date
- 2026-05-08
AI Technical Summary
Existing high electron mobility transistors (HEMTs) are difficult to utilize in the vertical direction due to their high fabrication difficulty. In particular, the vertical gate structure requires high photolithography precision, with key dimensions below 0.1µm, which makes fabrication challenging.
By introducing a connected depletion layer in the epitaxial layer to form a vertical depletion region, a connected depletion layer is prepared in the trench using secondary epitaxy technology to achieve horizontal connectivity. Furthermore, electrons are depleted by applying a negative voltage through the gate structure to form a vertical depletion region, thus reducing the fabrication difficulty.
This technology enables the efficient use of high electron mobility transistors in the vertical direction, improves the gate voltage withstand capability, reduces fabrication difficulty, and decreases the dependence on photolithography precision.
Smart Images
Figure CN122002845A_ABST
Abstract
Description
Technical Field
[0001] This disclosure belongs to the field of semiconductor technology, and specifically relates to a high electron mobility transistor and its fabrication method. Background Technology
[0002] A high electron mobility transistor (HEMT) is a type of field-effect transistor, mainly including two types: depletion-mode and enhancement-mode.
[0003] In related technologies, depletion-mode high electron mobility transistors (HEMTs) are widely used due to their low on-resistance and high gate reliability. However, HEMTs are horizontal structures and cannot utilize the vertical dimension. Designing HEMTs by stacking multiple channels—that is, growing multiple cycles of channel and barrier layers to create multiple two-dimensional electron gases—would result in a deep two-dimensional electron gas that cannot be turned off using a horizontal gate structure. Furthermore, vertical gate structures or trench gate structures require very high photolithographic precision, with critical dimensions often below 0.1µm, leading to significant fabrication challenges. Summary of the Invention
[0004] This disclosure provides a high electron mobility transistor and its fabrication method, which enables the utilization of the vertical dimension with relatively low fabrication difficulty. The technical solution is as follows: On one hand, embodiments of this disclosure provide a high electron mobility transistor, including: an epitaxial layer, a gate structure, a source structure, and a drain structure; The epitaxial layer includes a first channel layer, a first barrier layer, a second channel layer, a second barrier layer, and a connecting depletion layer. The first channel layer, the first barrier layer, the second channel layer, and the second barrier layer are stacked sequentially. The second channel layer and the second barrier layer have a trench on one side. The trench extends from the second barrier layer to the first barrier layer. The connecting depletion layer is located in the trench and extends along the sidewall of the second barrier layer and the second channel layer to the first barrier layer. The orthogonal projection of the gate structure in the epitaxial growth direction covers the connected depletion layer, as well as at least a portion of the first barrier layer and the second barrier layer; The source structure is located within the trench, and the source structure penetrates the first barrier layer and is connected to the first channel layer. The drain structure penetrates the second barrier layer, the second channel layer, and the first barrier layer and is connected to the first channel layer.
[0005] In one implementation of this disclosure, the connectivity depletion layer is an N-type GaN layer; The thickness of the connected depletion layer is 10~25 nm parallel to the epitaxial growth direction.
[0006] In one implementation of this disclosure, the first channel layer is an unintentionally doped GaN layer, and the thickness of the first channel layer is 50~200nm; The first barrier layer is Al x Ga 1-x The N-layer has a first barrier layer with a thickness of 8~30nm and 0.1≤x≤0.4.
[0007] In one implementation of this disclosure, the second channel layer is an unintentionally doped GaN layer, and the thickness of the second channel layer is 50~200nm; The first barrier layer is Al x Ga 1-x The N-layer has a first barrier layer with a thickness of 8~30nm and 0.1≤x≤0.4.
[0008] In one implementation of this disclosure, the source structure includes an ohmic source and a source electrode; The first end of the ohmic source is located inside the first channel layer, and the second end of the ohmic source is located outside the first barrier layer. The source electrode is electrically connected to the second terminal of the ohmic source electrode.
[0009] In one implementation of this disclosure, the source structure further includes a source protection structure; The source protection structure is located between the ohmic source and the source electrode, and the material of the source protection structure is the same as that of the gate structure.
[0010] In one implementation of this disclosure, the drain structure includes an ohmic drain and a drain electrode; The first end of the ohmic drain is located inside the first channel layer, and the second end of the ohmic drain is located outside the second barrier layer; The drain electrode is electrically connected to the second terminal of the ohmic drain electrode.
[0011] In one implementation of this disclosure, the drain structure further includes a drain protection structure; The drain protection structure is located between the ohmic drain and the drain electrode, and the material of the drain protection structure is the same as that of the gate structure.
[0012] In one implementation of this disclosure, a gate dielectric layer is also included; The gate dielectric layer covers the first barrier layer, the connected depletion layer, and the second barrier layer, and at least a portion of the gate dielectric layer is located between the gate structure and the connected depletion layer.
[0013] On the other hand, embodiments of this disclosure provide a method for fabricating a high electron mobility transistor, comprising: The first channel layer, the first barrier layer, the second channel layer, and the second barrier layer are prepared sequentially. The second barrier layer and the second trench layer are photolithographically formed to create a trench extending from the second barrier layer to the first barrier layer; A connected depletion layer is prepared such that the connected depletion layer is located within the trench and extends along the sidewalls of the second barrier layer and the second channel layer to the first barrier layer; A gate structure, a source structure, and a drain structure are fabricated separately. The orthogonal projection of the gate structure in the epitaxial growth direction covers the connected depletion layer, as well as at least a portion of the first barrier layer and the second barrier layer. The source structure is located within the trench and penetrates the first barrier layer and is connected to the first channel layer. The drain structure penetrates the second barrier layer, the second channel layer, and the first barrier layer and is connected to the first channel layer.
[0014] The beneficial effects of the technical solutions provided in this disclosure are: The high electron mobility transistor provided in this disclosure includes an epitaxial layer, a gate structure, a source structure, and a drain structure. The epitaxial layer includes a first channel layer, a first barrier layer, a second channel layer, and a second barrier layer stacked sequentially. A first two-dimensional electron gas is formed at the first channel layer and the first barrier layer, thereby forming a first gate region. A second two-dimensional electron gas is formed at the second channel layer and the second barrier layer, thereby forming a second gate region. A trench is provided on one side of the second channel layer and the second barrier layer, extending from the second barrier layer to the first barrier layer. The trench provides fabrication space for secondary epitaxial fabrication of a connected depletion layer. The connected depletion layer is located within the trench and extends along the sidewalls of the second barrier layer and the second channel layer to the first barrier layer. In this way, horizontal connectivity between the first channel layer, the first barrier layer, the second channel layer, and the second barrier layer is achieved through the connected depletion layer. When a negative voltage is applied to the gate structure, the first gate region and the second gate region can be simultaneously turned off. Furthermore, this process depletes electrons in the connected depletion layer, forming a vertically oriented depletion region to bear the electric field, effectively improving the breakdown voltage of the first gate region. In addition, the vertically oriented depletion region is determined by the growth thickness of the connected depletion layer, rather than by the photolithography precision, thus significantly reducing the fabrication difficulty.
[0015] In other words, the high electron mobility transistor provided in this disclosure, by fabricating a connected depletion layer through secondary epitaxy, can achieve utilization of the vertical dimension with relatively low fabrication difficulty. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a front cross-sectional view of a high electron mobility transistor provided in an embodiment of this disclosure; Figure 2 This is a flowchart of a method for fabricating a high electron mobility transistor provided in an embodiment of this disclosure; Figure 3 This is a flowchart of another method for fabricating a high electron mobility transistor provided in this disclosure embodiment; Figure 4 This is a schematic diagram of the fabrication process of the high electron mobility transistor provided in the embodiments of this disclosure; Figure 5 This is a schematic diagram of the fabrication process of the high electron mobility transistor provided in the embodiments of this disclosure; Figure 6 This is a schematic diagram of the fabrication process of the high electron mobility transistor provided in the embodiments of this disclosure; Figure 7 This is a schematic diagram of the fabrication process of the high electron mobility transistor provided in the embodiments of this disclosure; Figure 8 This is a schematic diagram of the fabrication process of the high electron mobility transistor provided in the embodiments of this disclosure; Figure 9 This is a schematic diagram of the fabrication process of the high electron mobility transistor provided in the embodiments of this disclosure; Figure 10 This is a schematic diagram of the fabrication process of the high electron mobility transistor provided in the embodiments of this disclosure.
[0018] The symbols in the diagram represent the following meanings: 10. Epitaxial layer; 110, First channel layer; 120, First barrier layer; 130, Second channel layer; 140, Second barrier layer; 150, Connectivity depletion layer; 20. Gate structure; 30. Source structure; 310. Ohmic source electrode; 320. Source electrode; 330. Source protection structure; 40. Drain structure; 410 Ohmic drain electrode; 420 Drain electrode; 430 Drain protection structure; 50. Gate dielectric layer; 60. Substrate; 70. Buffer layer; 80. High-resistivity layer; 90. Dielectric layer; 100, First grid area; 200, Second grid area.
[0019] The accompanying drawings have illustrated specific embodiments of this disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.
[0021] This disclosure provides a high electron mobility transistor. Figure 1 For a front cross-sectional view of this high electron mobility transistor, see [link / reference]. Figure 1 In this embodiment, the high electron mobility transistor includes an epitaxial layer 10, a gate structure 20, a source structure 30, and a drain structure 40.
[0022] The epitaxial layer 10 includes a first channel layer 110, a first barrier layer 120, a second channel layer 130, a second barrier layer 140, and a connecting depletion layer 150. The first channel layer 110, the first barrier layer 120, the second channel layer 130, and the second barrier layer 140 are stacked sequentially. A trench is formed on one side of the second channel layer 130 and the second barrier layer 140, extending from the second barrier layer 140 to the first barrier layer 120. The connecting depletion layer 150 is located within the trench and extends along the sidewalls of the second barrier layer 140 and the second channel layer 130 to the first barrier layer 120. The gate structure 20, projected orthogonally in the epitaxial growth direction, covers the connecting depletion layer 150 and at least a portion of the first barrier layer 120 and the second barrier layer 140. The source structure 30 is located within the trench and penetrates the first barrier layer 120 and is connected to the first channel layer 110. The drain structure 40 penetrates the second barrier layer 140, the second channel layer 130, and the first barrier layer 120 and is connected to the first channel layer 110.
[0023] The high electron mobility transistor provided in this embodiment includes an epitaxial layer 10, a gate structure 20, a source structure 30, and a drain structure 40. The epitaxial layer 10 includes a first channel layer 110, a first barrier layer 120, a second channel layer 130, and a second barrier layer 140 stacked sequentially. A first two-dimensional electron gas is formed at the first channel layer 110 and the first barrier layer 120, thereby forming a first gate region 100. A second two-dimensional electron gas is formed at the second channel layer 130 and the second barrier layer 140, thereby forming a second gate region 200. A trench is provided on one side of the second channel layer 130 and the second barrier layer 140, extending from the second barrier layer 140 to the first barrier layer 120. The trench provides fabrication space for a secondary epitaxial layer 150 to be fabricated. The connected depletion layer 150 is located within the trench and extends along the sidewalls of the second barrier layer 140 and the second channel layer 130 to the first barrier layer 120. In this way, horizontal connectivity is achieved between the first channel layer 110, the first barrier layer 120, the second channel layer 130, and the second barrier layer 140 through the connected depletion layer 150. When a negative voltage is applied to the gate structure 20, the first gate region 100 and the second gate region 200 can be turned off simultaneously. Furthermore, during this process, electrons in the connected depletion layer 150 are depleted, thereby forming a vertical depletion region to fulfill the function of bearing the electric field, effectively improving the breakdown voltage capability of the first gate region 100. In addition, the vertical depletion region is determined by the growth thickness of the connected depletion layer 150, rather than by the photolithography precision, thus significantly reducing the fabrication difficulty.
[0024] In other words, the high electron mobility transistor provided in this disclosure, by fabricating the connected depletion layer 150 through secondary epitaxy, can achieve utilization of the vertical dimension with relatively low fabrication difficulty.
[0025] In this embodiment, the high electron mobility transistor includes a substrate 60.
[0026] For example, the substrate 60 is silicon, sapphire, silicon carbide, gallium nitride, etc., and this disclosure does not limit it.
[0027] In this embodiment, the epitaxial layer 10 further includes a buffer layer 70, which is located on one side of the substrate 60. The buffer layer 70 is made of AlN and Al. x Ga 1-x The N-layer structure has a thickness of 1~3µm.
[0028] In this embodiment, the epitaxial layer 10 further includes a high-resistivity layer 80, which is located on one side of the buffer layer 70. The high-resistivity layer 80 is carbon-doped gallium nitride.
[0029] In other embodiments, the doping source of the high-resistivity layer 80 may also be elements such as Zn and Mg.
[0030] See also Figure 1 In this embodiment, the first channel layer 110 is an unintentionally doped GaN layer, and the thickness of the first channel layer 110 is 50~200nm. The first barrier layer 120 is Al. x Ga 1-x The thickness of the N-layer, the first barrier layer 120, is 8~30nm, and 0.1≤x≤0.4.
[0031] In the above implementation, a first two-dimensional electron gas is formed at the first channel layer 110 and the first barrier layer 120, thereby forming the first gate region 100.
[0032] See also Figure 1 In this embodiment, the second channel layer 130 is an unintentionally doped GaN layer, and the thickness of the second channel layer 130 is 50~200nm. The first barrier layer 120 is Al. x Ga 1-x The thickness of the N-layer, the first barrier layer 120, is 8~30nm, and 0.1≤x≤0.4.
[0033] In the above implementation, a second two-dimensional electron gas is formed at the second channel layer 130 and the second barrier layer 140, thereby forming the second gate region 200.
[0034] In this embodiment, the connected depletion layer 150 is an N-type GaN layer, and the thickness of the connected depletion layer 150 is 10~25nm in parallel with the epitaxial growth direction.
[0035] For example, the N-type GaN layer is achieved by doping silicon atoms during gallium nitride growth, and the electron concentration of the N-type GaN layer is 1E17~1E18.
[0036] See also Figure 1 In this embodiment, the high electron mobility transistor further includes a gate dielectric layer 50. The gate dielectric layer 50 covers the first barrier layer 120, the interconnect depletion layer 150, and the second barrier layer 140, and at least a portion of the gate dielectric layer 50 is located between the gate structure 20 and the interconnect depletion layer 150.
[0037] For example, the gate dielectric layer 50 is made of aluminum oxide, silicon oxide, silicon nitride, etc., and the thickness of the gate dielectric layer 50 is 20~60nm.
[0038] The material and thickness of the gate dielectric layer 50 determine the magnitude of the gate turn-off voltage. In this embodiment, the gate dielectric layer 50 is silicon nitride, and the thickness of the gate dielectric layer 50 is 50 nm.
[0039] See also Figure 1 In this embodiment, the source structure 30 includes an ohmic source 310 and a source electrode 320.
[0040] The first end of the ohmic source 310 is located inside the first channel layer 110, and the second end of the ohmic source 310 is located outside the first barrier layer 120. The source electrode 320 is electrically connected to the second end of the ohmic source 310.
[0041] In the above implementation, the ohmic source 310 is used to achieve vertical interconnection, providing a reliable channel for efficient bidirectional electron flow. The source electrode 320 is located outside the first barrier layer 120 and is used to connect to external devices.
[0042] For example, the ohmic source 310 and the source electrode 320 are Al-based composite materials, such as a Ti / Al / Ti sandwich structure or a Ti / Al / Ni / Au stacked structure.
[0043] When it is a Ti / Al / Ti structure, the thicknesses of each layer are 30 / 200 / 60 respectively.
[0044] When the structure is Ti / Al / Ni / Au, the thicknesses of each layer are 15 / 300 / 100 / 50 mm, respectively.
[0045] In the above implementation, a non-rectified contact can be formed by combining low-barrier metals, which effectively realizes efficient bidirectional electron flow.
[0046] In this embodiment, the source structure 30 further includes a source protection structure 330. The source protection structure 330 is located between the ohmic source 310 and the source electrode 320, and the material of the source protection structure 330 is the same as that of the gate structure 20.
[0047] In the above implementation, the source protection structure 330 can protect the ohmic source 310 during the photolithography of the gate structure 20, thus preventing the ohmic source 310 from being damaged.
[0048] For example, the source protection structure 330 is a TiN / Al / TiN stacked structure.
[0049] See also Figure 1 In this embodiment, the drain structure 40 includes an ohmic drain 410 and a drain electrode 420.
[0050] The first end of the ohmic drain 410 is located inside the first channel layer 110, the second end of the ohmic drain 410 is located outside the second barrier layer 140, and the drain electrode 420 is electrically connected to the second end of the ohmic drain 410.
[0051] In the above implementation, the ohmic drain 410 is used to achieve vertical interconnection, providing a reliable channel for efficient bidirectional electron flow. The drain electrode 420 is located outside the second barrier layer 140 and is used to connect to external devices.
[0052] For example, the ohmic drain 410 and the drain electrode 420 are Al-based composite materials, such as a Ti / Al / Ti sandwich structure or a Ti / Al / Ni / Au stacked structure.
[0053] When it is a Ti / Al / Ti structure, the thicknesses of each layer are 30 / 200 / 60 respectively.
[0054] When the structure is Ti / Al / Ni / Au, the thicknesses of each layer are 15 / 300 / 100 / 50 mm, respectively.
[0055] In the above implementation, a non-rectified contact can be formed by combining low-barrier metals, which effectively realizes efficient bidirectional electron flow.
[0056] In this embodiment, the drain structure 40 further includes a drain protection structure 430. The drain protection structure 430 is located between the ohmic drain 410 and the drain electrode 420, and the material of the drain protection structure 430 is the same as that of the gate structure 20.
[0057] In the above implementation, the drain protection structure 430 can protect the ohmic drain 410 during the photolithography of the gate structure 20, thus preventing the ohmic drain 410 from being damaged.
[0058] For example, the drain protection structure 430 is a TiN / Al / TiN stacked structure.
[0059] See also Figure 1 In this embodiment, the high electron mobility transistor further includes a dielectric layer 90. The dielectric layer 90 covers the source protection structure 330, the gate dielectric layer 50, the gate structure 20, and the drain protection structure 430.
[0060] In the above implementation, the dielectric layer 90 can play a role in protection and isolation.
[0061] For example, the dielectric layer 90 is silicon nitride and silicon oxide, or a combination of both. The thickness of the dielectric layer 90 is 2~5µm.
[0062] Figure 2 A flowchart illustrating a method for fabricating a high electron mobility transistor, as provided in this disclosure, is presented in conjunction with... Figure 2 In this embodiment, the preparation method includes: Step 201: Sequentially prepare the first channel layer 110, the first barrier layer 120, the second channel layer 130, and the second barrier layer 140.
[0063] Step 202: Photolithography of the second barrier layer 140 and the second channel layer 130 to form a trench extending from the second barrier layer 140 to the first barrier layer 120.
[0064] Step 203: Prepare a connected depletion layer 150 such that the connected depletion layer 150 is located in the trench and extends along the sidewalls of the second barrier layer 140 and the second channel layer 130 to the first barrier layer 120.
[0065] Step 204: Prepare gate structure 20, source structure 30 and drain structure 40 respectively.
[0066] The gate structure 20 is projected onto the epitaxial growth direction and covers the depletion layer 150, as well as at least a portion of the first barrier layer 120 and the second barrier layer 140. The source structure 30 is located in the trench and penetrates the first barrier layer 120 and is connected to the first channel layer 110. The drain structure 40 penetrates the second barrier layer 140, the second channel layer 130, and the first barrier layer 120 and is connected to the first channel layer 110.
[0067] The high electron mobility transistor fabricated by the method provided in this embodiment includes an epitaxial layer 10 comprising a first channel layer 110, a first barrier layer 120, a second channel layer 130, and a second barrier layer 140 stacked sequentially. A first two-dimensional electron gas is formed at the first channel layer 110 and the first barrier layer 120, thereby forming a first gate region 100. A second two-dimensional electron gas is formed at the second channel layer 130 and the second barrier layer 140, thereby forming a second gate region 200. A trench is provided on one side of the second channel layer 130 and the second barrier layer 140, extending from the second barrier layer 140 to the first barrier layer 120. The trench provides fabrication space for secondary epitaxial fabrication of a connected depletion layer 150. The connected depletion layer 150 is located within the trench and extends along the sidewalls of the second barrier layer 140 and the second channel layer 130 to the first barrier layer 120. In this way, horizontal connectivity is achieved between the first channel layer 110, the first barrier layer 120, the second channel layer 130, and the second barrier layer 140 through the connected depletion layer 150. When a negative voltage is applied to the gate structure 20, the first gate region 100 and the second gate region 200 can be turned off simultaneously. Furthermore, during this process, electrons in the connected depletion layer 150 are depleted, thereby forming a vertical depletion region to fulfill the function of bearing the electric field, effectively improving the breakdown voltage capability of the first gate region 100. In addition, the vertical depletion region is determined by the growth thickness of the connected depletion layer 150, rather than by the photolithography precision, thus significantly reducing the fabrication difficulty.
[0068] In other words, the high electron mobility transistor prepared by the method provided in this disclosure can utilize the vertical dimension with relatively low preparation difficulty by preparing a connected depletion layer 150 through secondary epitaxy.
[0069] Figure 3A flowchart illustrating another method for fabricating a high electron mobility transistor provided in this disclosure, in conjunction with... Figure 3 In this embodiment, the preparation method includes: Step 301: Provide a substrate 60, and sequentially fabricate a buffer layer 70, a high-resistivity layer 80, a first channel layer 110, a first barrier layer 120, a second channel layer 130, and a second barrier layer 140 on one side of the substrate (see...). Figure 4 ).
[0070] For example, the growth method can be MOCVD (metal-organic chemical vapor deposition) or MBE (molecular beam epitaxy).
[0071] Step 301 completes the first epitaxial growth.
[0072] Step 302: Photolithography of the second barrier layer 140 and the second trench layer 130 to form a trench extending from the second barrier layer 140 to the first barrier layer 120 (see...) Figure 5 ).
[0073] After the trenches are etched, the recessed trenches form mesa structures at the second barrier layer 140 and the second channel layer 130. These mesa structures horizontally divide the epitaxial layer 10 into a first gate region 100 and a second gate region 200. The size of the first gate region 100 and the second gate region 200 depends on the application scenario of the device. For example, the device in this embodiment is suitable for consumer-grade 650V~700V products, with the horizontal length of the first gate region 100 being 3~7µm and the horizontal length of the second gate region 200 being 17~25µm.
[0074] Step 303: Prepare the connected depletion layer 150 (see...) Figure 6 ).
[0075] In this embodiment, step 303 includes: First, an N-type GaN layer is grown.
[0076] For example, N-type doping is achieved by incorporating silicon atoms, and the electron concentration of the N-type GaN layer is 1E17~1E18.
[0077] For example, the thickness of the N-type GaN layer is 20~50nm.
[0078] Then, the vertical N-type GaN layer is removed by etching back, while the N-type GaN layer located on the trench sidewall is retained, which is the vertical connected depletion layer 150.
[0079] Step 303 completes the second epitaxial growth.
[0080] Step 304: Prepare the gate dielectric layer 50 and form holes using photolithography (see...) Figure 7 ).
[0081] For example, the holes are located in the first grid region 100 and the second grid region 200, respectively, and the distance between the holes in the first grid region 100 and the holes in the second grid region 200 is 20~30µm.
[0082] Step 305: Fabrication of ohmic source 310 and ohmic drain 410 (see...) Figure 8 ).
[0083] In this embodiment, step 305 includes: First, an ohmic metal layer is deposited.
[0084] Then, the ohmic source 310 and ohmic drain 410 are prepared by photolithography or lift-off process.
[0085] Step 306: Fabricate gate structure 20, source protection structure 330, and drain protection structure 430 (see...) Figure 9 ).
[0086] In this embodiment, step 306 includes: First, a gate metal layer is deposited.
[0087] Then, the gate structure 20, the source protection structure 330, and the drain protection structure 430 are prepared by photolithography.
[0088] Step 307: Prepare dielectric layer 90 and form holes using photolithography (see...) Figure 10 ).
[0089] For example, a dielectric layer 90 of 2-5 µm is grown, and the surface of the dielectric layer 90 facing away from the epitaxial layer 10 is planarized by chemical mechanical polishing, which is beneficial to obtaining a better morphology in subsequent steps.
[0090] Step 308: Fabrication of source electrode 320 and drain electrode 420 (see...) Figure 1 ).
[0091] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described objects changes, the relative positional relationship may also change accordingly.
[0092] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.
Claims
1. A high electron mobility transistor, characterized in that, include: Epitaxial layer (10), gate structure (20), source structure (30) and drain structure (40); The epitaxial layer (10) includes a first channel layer (110), a first barrier layer (120), a second channel layer (130), a second barrier layer (140), and a connecting depletion layer (150). The first channel layer (110), the first barrier layer (120), the second channel layer (130), and the second barrier layer (140) are stacked sequentially. The second channel layer (130) and the second barrier layer (140) have a trench on one side. The trench extends from the second barrier layer (140) to the first barrier layer (120). The connecting depletion layer (150) is located in the trench and extends along the sidewalls of the second barrier layer (140) and the second channel layer (130) to the first barrier layer (120). The orthogonal projection of the gate structure (20) in the epitaxial growth direction covers the connected depletion layer (150), as well as at least a portion of the first barrier layer (120) and the second barrier layer (140). The source structure (30) is located in the trench, and the source structure (30) penetrates the first barrier layer (120) and is connected to the first channel layer (110); The drain structure (40) penetrates the second barrier layer (140), the second channel layer (130), and the first barrier layer (120) and is connected to the first channel layer (110).
2. The high electron mobility transistor according to claim 1, characterized in that, The connected depletion layer (150) is an N-type GaN layer; The thickness of the connected depletion layer (150) is 10~25 nm parallel to the epitaxial growth direction.
3. The high electron mobility transistor according to claim 1, characterized in that, The first channel layer (110) is an unintentionally doped GaN layer, and the thickness of the first channel layer (110) is 50~200nm; The first barrier layer (120) is Al x Ga 1-x The N-layer has a first barrier layer (120) with a thickness of 8~30nm and 0.1≤x≤0.
4.
4. The high electron mobility transistor according to claim 1, characterized in that, The second channel layer (130) is an unintentionally doped GaN layer, and the thickness of the second channel layer (130) is 50~200nm; The first barrier layer (120) is Al x Ga 1-x The N-layer has a first barrier layer (120) with a thickness of 8~30nm and 0.1≤x≤0.
4.
5. The high electron mobility transistor according to claim 1, characterized in that, The source structure (30) includes an ohmic source (310) and a source electrode (320). The first end of the ohmic source (310) is located inside the first channel layer (110), and the second end of the ohmic source (310) is located outside the first barrier layer (120). The source electrode (320) is electrically connected to the second end of the ohmic source electrode (310).
6. The high electron mobility transistor according to claim 5, characterized in that, The source structure (30) also includes a source protection structure (330). The source protection structure (330) is located between the ohmic source (310) and the source electrode (320), and the material of the source protection structure (330) is the same as that of the gate structure (20).
7. The high electron mobility transistor according to claim 1, characterized in that, The drain structure (40) includes an ohmic drain (410) and a drain electrode (420). The first end of the ohmic drain (410) is located inside the first channel layer (110), and the second end of the ohmic drain (410) is located outside the second barrier layer (140). The drain electrode (420) is electrically connected to the second terminal of the ohmic drain electrode (410).
8. The high electron mobility transistor according to claim 7, characterized in that, The drain structure (40) also includes a drain protection structure (430). The drain protection structure (430) is located between the ohmic drain (410) and the drain electrode (420), and the material of the drain protection structure (430) is the same as that of the gate structure (20).
9. The high electron mobility transistor according to claim 1, characterized in that, It also includes a gate dielectric layer (50); The gate dielectric layer (50) covers the first barrier layer (120), the connected depletion layer (150), and the second barrier layer (140), and at least a portion of the gate dielectric layer (50) is located between the gate structure (20) and the connected depletion layer (150).
10. A method for fabricating a high electron mobility transistor, characterized in that, include: The first channel layer (110), the first barrier layer (120), the second channel layer (130), and the second barrier layer (140) are prepared sequentially. The second barrier layer (140) and the second channel layer (130) are photolithographically formed to form a trench extending from the second barrier layer (140) to the first barrier layer (120); A connected depletion layer (150) is prepared such that the connected depletion layer (150) is located within the trench and extends along the sidewalls of the second barrier layer (140) and the second channel layer (130) to the first barrier layer (120). A gate structure (20), a source structure (30), and a drain structure (40) are fabricated respectively. The orthogonal projection of the gate structure (20) in the epitaxial growth direction covers the connected depletion layer (150), as well as at least a portion of the first barrier layer (120) and the second barrier layer (140). The source structure (30) is located in the trench and penetrates the first barrier layer (120) and is connected to the first channel layer (110). The drain structure (40) penetrates the second barrier layer (140), the second channel layer (130), and the first barrier layer (120) and is connected to the first channel layer (110).