Vertical annular channel three-dimensional transistor and preparation method thereof

Abstract

The invention relates to a vertical annular channel three-dimensional transistor and a preparation method, the vertical annular channel three-dimensional transistor comprises M stack layers, M is a positive integer, and each stack layer comprises a silicon nitride layer, a first doped polycrystalline silicon layer, an oxide layer and a second doped polycrystalline silicon layer which are deposited in sequence; the gate structure comprises a gate electrode, a channel region and a gate oxide, and the channel region and the gate oxide respectively correspond to each stack layer; the M source electrodes and the M drain electrodes are formed on the basis of contact steps, and the contact steps are formed on the M stacking layers through a stepped technology. According to the scheme, the density and the integration level of the transistor are improved, the capacity of the transistor is improved, and the processing capacity of the transistor is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a vertical annular channel three-dimensional transistor and its fabrication method. Background Technology

[0002] In the semiconductor manufacturing field, the device architecture in chips is shifting from 2D to 3D. 3D homogeneous integration and 3D heterogeneous integration are becoming active research directions in chip manufacturing. The problem that needs to be solved is how to improve the performance of system-on-chip (SoC) and memory chips, such as chip processing speed, bandwidth, capacity, and power consumption, while minimizing the overall chip area. Summary of the Invention

[0003] The purpose of this disclosure is to provide a vertical annular channel three-dimensional transistor and its fabrication method, which can improve the density and performance of the transistor.

[0004] To achieve the above objectives, in a first aspect, this disclosure provides a vertical annular channel three-dimensional transistor, comprising: M stacked layers, where M is a positive integer, each of the stacked layers includes a silicon nitride layer, a first doped polysilicon layer, an oxide layer and a second doped polysilicon layer deposited sequentially. A gate structure, wherein the gate structure includes a gate electrode and a channel region and a gate oxide corresponding to each of the stacked layers; M source electrodes and M drain electrodes are formed based on contact steps, wherein the contact steps are formed on the M stacked layers using a step-type process.

[0005] Optionally, when M is a positive integer greater than 1, the M stacking layers are stacked vertically in sequence.

[0006] Optionally, for each of the stacked layers, the source and drain corresponding to the stacked layer are respectively connected to different doped polysilicon layers in the stacked layer.

[0007] Optionally, the gate electrode extends through the M stacked layers in the vertical direction, and the material of the gate electrode is phosphorus-doped polycrystalline silicon.

[0008] Optionally, the channel region corresponding to the stacked layer is formed by depositing boron-doped polysilicon or phosphorus-doped polysilicon in two oxide trenches. The two oxide trenches are two horizontal trenches etched on the oxide layer in the stacked layer, and the two oxide trenches correspond to the two sides of the gate electrode.

[0009] Optionally, the gate oxide corresponding to the stacked layer is formed on both sides of the gate electrode and at positions corresponding to the first doped polysilicon layer, the oxide layer and the second doped polysilicon layer in the stacked layer.

[0010] In a second aspect, this disclosure provides a method for fabricating a vertical annular channel three-dimensional transistor, the method being used to fabricate the vertical annular channel three-dimensional transistor provided in the first aspect of this disclosure, the method comprising: M stacked layers are formed, where M is a positive integer. Each stacked layer includes a silicon nitride layer, a first doped polysilicon layer, an oxide layer, and a second doped polysilicon layer deposited sequentially. Photolithography and etching processes are used to etch the M stacked layers to form a channel hole that penetrates the M stacked layers in the vertical direction; The gate structure of the vertical annular channel three-dimensional transistor is formed based on the channel hole, wherein the gate structure includes a gate electrode and a channel region and a gate oxide corresponding to each of the stacked layers; Contact steps are formed on the M stacked layers using a stepped process; Using back-end processes, based on the contact steps, a source and drain corresponding to each of the stacked layers are formed, wherein the source and drain corresponding to each stacked layer are respectively connected to different doped polysilicon layers in the stacked layers.

[0011] Optionally, when M is a positive integer greater than 1, forming M stacked layers includes: Repeat the steps of depositing a silicon nitride layer, a first doped polysilicon layer, an oxide layer, and a second doped polysilicon layer in sequence until the M stacked layers are formed vertically.

[0012] Optionally, the formation of the gate structure of the vertical annular channel three-dimensional transistor based on the channel aperture includes: For each of the oxide layers in the stacked layers, a wet oxide etching process is used to etch two horizontal oxide grooves on the oxide layer to form a channel, wherein the two oxide grooves correspond to the two sides of the channel hole; Boron-doped polysilicon or phosphorus-doped polysilicon is deposited in each of the channels using low-pressure chemical vapor deposition. A wet polysilicon etching process is used to remove the boron-doped or phosphorus-doped polysilicon deposited at other locations outside the oxide trench, so as to form the channel region corresponding to each of the stacked layers. For each of the stacked layers, atomic layer deposition technology is used to deposit the gate oxide on both sides of the channel hole and at positions corresponding to the first doped polysilicon layer, oxide layer and second doped polysilicon layer of the stacked layer; Phosphorus-doped polycrystalline silicon is deposited in the channel holes using low-pressure chemical vapor deposition to form the gate electrode.

[0013] Optionally, forming the source and drain corresponding to each of the stacked layers based on the contact steps includes: A silicon nitride layer is deposited on the contact steps as an oxide etch stop layer; Using the back-end process, for each stacked layer, based on the contact steps, the source contact holes and drain contact holes corresponding to the stacked layer are photolithographically and etched. Tungsten metal is deposited in the source contact hole and the drain contact hole to form the source and drain corresponding to each of the stacked layers, and the tungsten metal on top of the silicon nitride layer deposited on the contact steps is removed by chemical mechanical planarization (CMP).

[0014] The above technical solution provides a vertical annular channel 3D transistor comprising M stacked layers. The number of stacked layers can be set as needed, and multiple stacked layers can be vertically stacked sequentially. This increases transistor density and capacity without increasing transistor area, thereby improving transistor processing power. Contact steps form the source and drain for each stacked layer. The channel region in the gate structure can be used to conduct the corresponding source and drain of the stacked layers, and the gate oxide isolates the current flow between the gate electrode and the channel region. In summary, this method improves transistor integration without occupying the transistor's front-end area.

[0015] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of a device structure of a three-layer stacked CAA field-effect transistor according to an exemplary embodiment.

[0017] Figure 2 This is an exemplary schematic diagram of the gate cross-section of a three-dimensional transistor with a vertical annular channel.

[0018] Figure 3This is a schematic diagram illustrating a single-layer CAA field-effect transistor device structure according to an exemplary embodiment.

[0019] Figure 4 This is a flowchart illustrating a method for fabricating a vertical annular channel three-dimensional transistor according to an exemplary embodiment. Detailed Implementation

[0020] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0021] The vertical annular channel CAA (Channel-All-Around) three-dimensional transistor, also known as a CAA field-effect transistor, disclosed herein may include M stacked layers, a gate structure, M sources and M drains formed based on contact steps, where M is a positive integer.

[0022] Each stacked layer comprises a silicon nitride layer, a first doped polysilicon layer, an oxide layer, and a second doped polysilicon layer deposited sequentially. The gate structure includes a gate electrode and a channel region and a gate oxide corresponding to each stacked layer. M sources and M drains are formed based on contact steps, meaning each stacked layer corresponds to one source and one drain. The contact steps are formed on the M stacked layers using a step-type process.

[0023] Figure 1 This is a schematic diagram of a device structure for a three-layer stacked CAA field-effect transistor according to an exemplary embodiment. Figure 1 As shown, the bottom layer is a substrate (e.g., a silicon substrate). An oxide layer can be formed on top of the substrate. It should be noted that the substrate and the oxide layer are optional structures, and the materials of the substrate and the oxide layer can be set as needed; this disclosure does not impose any limitations. Silicon nitride (SIN), doped polysilicon (Doped Poly), oxide, and doped polysilicon (Doped Poly) are sequentially deposited on the oxide layer to form a stacked layer L1. A stacked layer L2 can be formed on top of the stacked layer L1, and a stacked layer L3 can be formed on top of the stacked layer L2. Figure 1 The example shown includes three stacked layers and does not constitute a limitation on the embodiments of this disclosure. The number of stacked layers can be set as needed. Preferably, in order to improve the density and performance of transistors, the number of stacked layers can be 10 or more. Doped polycrystalline silicon refers to a material formed by adding a small amount of dopant (such as phosphorus, boron, etc.) to polycrystalline silicon to adjust its conductivity, resulting in different conductivity properties. The doped polycrystalline silicon involved in this disclosure can be highly doped polycrystalline silicon.

[0024] When M is a positive integer greater than 1, the M stacking layers are stacked vertically in sequence. For example... Figure 1 As shown, stacked layers L1, L2, and L3 are vertically stacked sequentially from bottom to top. This sequential vertical stacking of multiple layers allows for increased transistor density and integration without increasing transistor area, thereby improving transistor processing power. It should be noted that... Figure 1 The silicon nitride layer, oxide layer, and silicon nitride layer formed sequentially from bottom to top above the stacked layer L3 shown are optional structures. The number of layers and materials can be set as needed and do not constitute a limitation on the embodiments disclosed herein.

[0025] In this process, photolithography and etching techniques can be used to etch patterns onto stacked layers to form vertical channel holes. Photolithography is a process in integrated circuit manufacturing that uses optical-chemical reaction principles and chemical and physical etching methods to transfer circuit patterns onto a single crystal surface or dielectric layer, forming effective pattern windows or functional patterns. Etching, also known as photochemical etching, refers to the process of removing the protective film from the area to be etched after exposure and development, allowing the area to come into contact with a chemical solution during etching, achieving a dissolving and corroding effect to create raised or hollowed-out shapes.

[0026] like Figure 1 As shown, region 11 is the gate electrode (Poly Gate). Before the gate electrode material is deposited, region 11 is a channel hole. This channel hole penetrates the stacked layers L1, L2, L3, and the silicon nitride layer, oxide layer, and silicon nitride layer formed sequentially above L3. After forming the channel hole, the gate structure of a vertical annular channel three-dimensional transistor can be formed based on the channel hole.

[0027] In this disclosure, the channel region corresponding to the stacked layer is formed by depositing boron-doped or phosphorus-doped polysilicon within two oxide trenches. The two oxide trenches are horizontally oriented trenches etched onto the oxide layer in the stacked layer, corresponding to both sides of the gate electrode. The channel region can be used to conduct the source and drain corresponding to the stacked layer.

[0028] For example, for each oxide layer in the stack, two horizontal oxide recesses can be etched into the oxide layer to form a channel. The two oxide recesses correspond to the two sides of the channel aperture, that is, the two sides of the gate electrode. Figure 1As shown, region 12, before the deposition of channel region material, is an oxide groove located to the right of the channel aperture in stacked layer L1. Symmetrically opposite to region 12 is another oxide groove located to the left of the channel aperture. The oxide grooves in other stacked layers are similar. Subsequently, channel region material is deposited in each channel. The channel region material can be boron-doped polysilicon (B-Doped Poly) or phosphorus-doped polysilicon (Phos-Doped Poly). After the channel region material is deposited, region 12 becomes the channel region located to the right of the channel aperture in stacked layer L1.

[0029] In this disclosure, the gate oxide corresponding to the stacked layer is formed on both sides of the gate electrode and at positions corresponding to the first doped polysilicon layer, the oxide layer and the second doped polysilicon layer in the stacked layer.

[0030] After forming the channel region, the corresponding gate oxide can be formed for this stack. The gate oxide can be an ISSG (In-Situ-Steam-Generation) oxide, which refers to an oxide generated by an in-situ steam generation method, possessing good interface characteristics and electrical properties. For example... Figure 1 As shown, region 13 is located to the right of the via and corresponds to the first doped polysilicon layer, oxide layer, and second doped polysilicon layer in the stacked layer L1. After depositing the gate oxide at this location, region 13 becomes the gate oxide corresponding to the stacked layer L1 to the right of the via. There is also a region symmetrical to region 13 on the left side of the via, which is the gate oxide corresponding to the stacked layer L1 to the left of the via. Other stacked layers are similar. It should be noted that for the topmost stacked layer, in addition to depositing the gate oxide at the locations corresponding to the first doped polysilicon layer, oxide layer, and second doped polysilicon layer, a gate oxide can also be deposited at the location corresponding to the silicon nitride layer deposited above this stacked layer. For example... Figure 1 In the structure shown, a gate oxide can be deposited at the location corresponding to the silicon nitride layer deposited above the stacked layer L3. The gate oxide can isolate the current flow between the gate electrode and the channel region and prevent the transistor from short-circuiting.

[0031] In this disclosure, the gate electrode extends vertically through M stacked layers, and the material of the gate electrode can be phosphorus-doped polysilicon. The gate electrode can be used to form the gate contact of a vertical annular channel three-dimensional transistor.

[0032] After the gate oxide deposition is complete, phosphorus-doped polysilicon can be deposited in the channel holes as the gate electrode. Figure 1 Region 11 shown is the gate electrode.

[0033] Figure 2This is an exemplary schematic diagram of the gate cross-section of a three-dimensional transistor with a vertical annular channel, as shown below. Figure 2 As shown, the outermost layer is boron-doped or phosphorus-doped polysilicon in the channel region, the middle layer is gate oxide, and the innermost layer is phosphorus-doped polysilicon (i.e., the gate electrode). The thickness of each deposited material can be set as needed.

[0034] In this disclosure, for each stacked layer, the source and drain corresponding to the stacked layer are respectively connected to different doped polysilicon layers in the stacked layer.

[0035] In this configuration, the M stacked layers correspond one-to-one with the M sources and one-to-one with the M drains, as follows: Figure 1 As shown, there are three stacked layers, corresponding to three sources (source 1, source 2, and source 3) and three drains (drain 1, drain 2, and drain 3). Stacked layer L1 corresponds to source 1 and drain 1, stacked layer L2 corresponds to source 2 and drain 2, and stacked layer L3 corresponds to source 3 and drain 3. Figure 1 As shown, the source 1 of the stacked layer L1 is connected to the first doped polysilicon layer in L1, and the drain 1 is connected to the second doped polysilicon layer in L1. It should be noted that... Figure 1 The source and drain connections shown are for illustrative purposes only. For example, source 1 can be connected to the second doped polysilicon layer in L1, and drain 1 can be connected to the first doped polysilicon layer in L1. The source and drain connections for other stacked layers are similar.

[0036] This disclosure does not limit the number of stacked layers; there can be one or more. Figure 3 This is a schematic diagram of a single-layer CAA field-effect transistor device structure according to an exemplary embodiment, including a stacked layer L', wherein the source of the stacked layer L' is connected to a first doped polysilicon layer in L', and the drain is connected to a second doped polysilicon layer in L'. Figure 3 The silicon nitride layer and oxide layer shown are formed sequentially from bottom to top on the top layer of the stacked layers, which is an optional structure.

[0037] The above technical solution provides a vertical annular channel 3D transistor comprising M stacked layers. The number of stacked layers can be set as needed, and multiple stacked layers can be vertically stacked sequentially. This increases transistor density and capacity without increasing transistor area, thereby improving transistor processing power. Contact steps form the source and drain for each stacked layer. The channel region in the gate structure can be used to conduct the corresponding source and drain of the stacked layers, and the gate oxide isolates the current flow between the gate electrode and the channel region. In summary, this method improves transistor integration without occupying the transistor's front-end area.

[0038] Based on the same inventive concept, this disclosure also provides a method for fabricating a vertical annular channel three-dimensional transistor, used to fabricate the vertical annular channel three-dimensional transistor provided in any of the above embodiments. Figure 4 This is a flowchart illustrating a method for fabricating a vertical annular channel three-dimensional transistor according to an exemplary embodiment, such as... Figure 4 As shown, the method may include steps 41 to 45.

[0039] In step 41, M stacked layers are formed.

[0040] Where M is a positive integer greater than 1, forming M stacked layers includes: Repeat the steps of depositing a silicon nitride layer, a first doped polysilicon layer, an oxide layer, and a second doped polysilicon layer in sequence until M vertically stacked layers are formed.

[0041] In step 42, photolithography and etching processes are used to etch based on the M stacked layers to form a channel hole that penetrates the M stacked layers in the vertical direction.

[0042] In step 43, the gate structure of a vertical annular channel three-dimensional transistor is formed based on the channel hole.

[0043] Step 43 may include steps (a) through (e) below.

[0044] (a) For each stacked layer of oxide layer, a wet process oxide etching process is used to etch two horizontal oxide grooves on the oxide layer to form a channel, wherein the two oxide grooves correspond to the two sides of the channel hole.

[0045] Among them, wet etching uses chemical solutions to dissolve the material on the wafer surface to meet the requirements for manufacturing devices and circuits.

[0046] (b) Boron-doped polysilicon or phosphorus-doped polysilicon is deposited in each channel using low-pressure chemical vapor deposition.

[0047] Low-pressure chemical vapor deposition (LPCVD) is a technique that performs chemical vapor deposition at lower pressures. It involves heating the substrate material in a reaction chamber, causing it to react chemically with a gaseous precursor, thereby depositing the desired thin film material onto the substrate.

[0048] (c) A wet polysilicon etching process is used to remove boron-doped or phosphorus-doped polysilicon deposited in other locations outside the oxide trenches to form the channel regions corresponding to each stacked layer.

[0049] Because excess doped polysilicon may be deposited at other locations within the channel during the deposition of doped polysilicon within the channel, a wet process polysilicon etching is used, for example, to remove the doped polysilicon deposited at locations outside the oxide trench. This doped polysilicon can be boron-doped or phosphorus-doped polysilicon.

[0050] (d) For each stacked layer, atomic layer deposition technology is used to deposit gate oxide on both sides of the channel hole and at positions corresponding to the first doped polysilicon layer, oxide layer and second doped polysilicon layer of the stacked layer.

[0051] Atomic Layer Deposition (ALD) is a high-precision thin film deposition technology that deposits materials as single-atom films layer by layer onto the surface of a substrate based on a chemical vapor phase.

[0052] (e) Phosphorus-doped polysilicon is deposited in the channel hole using low-pressure chemical vapor deposition to form the gate electrode.

[0053] In step 44, contact steps are formed on the M stacked layers using a stepped process.

[0054] The staircase process refers to the process of forming different structural layers in semiconductor manufacturing by processing them layer by layer. This process typically involves gradually adding or removing material to form the desired circuit structure and connections layer by layer. The staircase process is used to form contact stairs on M stacked layers.

[0055] In step 45, using back-end processes, source and drain electrodes corresponding to each stacked layer are formed based on contact steps.

[0056] Step 45 may include: depositing a silicon nitride layer on the contact step as an oxide etch stop layer; Using back-end processes, for each stacked layer, based on contact steps, the source and drain contact holes corresponding to the stacked layer are photolithographically and etched. Tungsten metal is deposited in the source and drain contact holes to form the source and drain corresponding to each stacked layer, and the tungsten metal on top of the silicon nitride layer deposited on the contact steps is removed by chemical mechanical planarization (CMP).

[0057] Among them, a silicon nitride layer is deposited on the contact steps ( Figure 1(Not shown) serves as an oxide etch stop layer. Back-end processing (BEOL) refers to the interconnect and packaging steps performed after the front-end processes in semiconductor device manufacturing. Using BEOL, source and drain contact holes are formed by photolithography and etching based on contact steps. The number of source and drain contact holes is determined by the number of stacked layers and is the same as the number of stacked layers.

[0058] The above scheme can increase transistor density and capacity without increasing transistor area, thereby improving transistor processing power and achieving increased transistor integration without occupying transistor front-end area.

[0059] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0060] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0061] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A vertical annular channel three-dimensional transistor, characterized in that, include: M stacked layers, where M is a positive integer, each of the stacked layers includes a silicon nitride layer, a first doped polysilicon layer, an oxide layer and a second doped polysilicon layer deposited sequentially. A gate structure, wherein the gate structure includes a gate electrode and a channel region and a gate oxide corresponding to each of the stacked layers; M source electrodes and M drain electrodes are formed based on contact steps, wherein the contact steps are formed on the M stacked layers using a step-type process.

2. The vertical annular channel three-dimensional transistor according to claim 1, characterized in that, When M is a positive integer greater than 1, the M stacking layers are stacked vertically in sequence.

3. The vertical annular channel three-dimensional transistor according to claim 1, characterized in that, For each of the stacked layers, the source and drain of the stacked layer are respectively connected to different doped polysilicon layers in the stacked layer.

4. The vertical annular channel three-dimensional transistor according to claim 1, characterized in that, The gate electrode extends vertically through the M stacked layers, and the material of the gate electrode is phosphorus-doped polycrystalline silicon.

5. The vertical annular channel three-dimensional transistor according to claim 1, characterized in that, The channel region corresponding to the stacked layer is formed by depositing boron-doped polysilicon or phosphorus-doped polysilicon in two oxide trenches. The two oxide trenches are two horizontal trenches etched on the oxide layer in the stacked layer, and the two oxide trenches correspond to the two sides of the gate electrode.

6. The vertical annular channel three-dimensional transistor according to claim 1, characterized in that, The gate oxide corresponding to the stacked layer is formed on both sides of the gate electrode and at positions corresponding to the first doped polysilicon layer, the oxide layer and the second doped polysilicon layer in the stacked layer.

7. A method for fabricating a vertical annular channel three-dimensional transistor, characterized in that, The method is used to fabricate a vertical annular channel three-dimensional transistor according to any one of claims 1-6, the method comprising: M stacked layers are formed, where M is a positive integer. Each stacked layer includes a silicon nitride layer, a first doped polysilicon layer, an oxide layer, and a second doped polysilicon layer deposited sequentially. Photolithography and etching processes are used to etch the M stacked layers to form a channel hole that penetrates the M stacked layers in the vertical direction; The gate structure of the vertical annular channel three-dimensional transistor is formed based on the channel hole, wherein the gate structure includes a gate electrode and a channel region and a gate oxide corresponding to each of the stacked layers; Contact steps are formed on the M stacked layers using a stepped process; Using back-end processes, based on the contact steps, a source and drain corresponding to each of the stacked layers are formed, wherein the source and drain corresponding to each stacked layer are respectively connected to different doped polysilicon layers in the stacked layers.

8. The method according to claim 7, characterized in that, When M is a positive integer greater than 1, forming M stacked layers includes: Repeat the steps of depositing a silicon nitride layer, a first doped polysilicon layer, an oxide layer, and a second doped polysilicon layer in sequence until the M stacked layers are formed vertically.

9. The method according to claim 7, characterized in that, The gate structure of the vertical annular channel three-dimensional transistor formed based on the channel hole includes: For each of the oxide layers in the stacked layers, a wet oxide etching process is used to etch two horizontal oxide grooves on the oxide layer to form a channel, wherein the two oxide grooves correspond to the two sides of the channel hole; Boron-doped polysilicon or phosphorus-doped polysilicon is deposited in each of the channels using low-pressure chemical vapor deposition. A wet polysilicon etching process is used to remove the boron-doped or phosphorus-doped polysilicon deposited at other locations outside the oxide trench, so as to form the channel region corresponding to each of the stacked layers. For each of the stacked layers, atomic layer deposition technology is used to deposit the gate oxide on both sides of the channel hole and at positions corresponding to the first doped polysilicon layer, oxide layer and second doped polysilicon layer of the stacked layer; Phosphorus-doped polycrystalline silicon is deposited in the channel holes using low-pressure chemical vapor deposition to form the gate electrode.

10. The method according to claim 7, characterized in that, The process of forming the source and drain corresponding to each of the stacked layers based on the contact steps includes: A silicon nitride layer is deposited on the contact steps as an oxide etch stop layer; Using the back-end process, for each stacked layer, based on the contact steps, the source contact holes and drain contact holes corresponding to the stacked layer are photolithographically and etched. Tungsten metal is deposited in the source contact hole and the drain contact hole to form the source and drain corresponding to each of the stacked layers, and the tungsten metal on top of the silicon nitride layer deposited on the contact steps is removed by chemical mechanical planarization (CMP).

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