Transistor and manufacturing method thereof

Abstract

The invention provides a transistor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The transistor comprises a substrate, a heterojunction, an electrode assembly and a cap layer, the heterojunction comprises a channel layer and a barrier layer which are sequentially stacked on the substrate, the electrode assembly comprises a source electrode, a drain electrode and a grid electrode, the source electrode and the drain electrode are located on the two sides of the grid electrode, and the cap layer is located between the source electrode and the drain electrode. The grid electrode, the source electrode and the drain electrode are electrically connected with the heterojunction respectively; the cap layer is located on the side, away from the substrate, of the barrier layer and located on the side, close to the grid electrode, of the drain electrode, the cap layer makes contact with the drain electrode, and the cap layer and the grid electrode are arranged in a spaced mode. The transistor is small in on resistance and good in voltage resistance.

Description

Technical Field

[0001] This disclosure belongs to the field of semiconductor technology, and in particular relates to a transistor and a method for manufacturing the same. Background Technology

[0002] Transistors are a common type of semiconductor device that are widely used in various electronic devices.

[0003] In related technologies, a transistor includes a substrate, a channel layer, a barrier layer, and an electrode assembly. The channel layer and the barrier layer are sequentially stacked on the substrate. The electrode assembly includes a source, a drain, and a gate. The source and the drain are located on opposite sides of the gate, and the gate, the source, and the drain are respectively connected to the barrier layer.

[0004] The breakdown voltage of a transistor is positively correlated with the length of its drift region; that is, the longer the drift region, the better the breakdown voltage, but the greater the on-resistance. This creates a conflict between the breakdown voltage and on-resistance requirements of a transistor at the device physics level. Summary of the Invention

[0005] This disclosure provides a transistor and a method for manufacturing the same, which can improve the transistor's voltage withstand performance while maintaining a low on-resistance. The technical solution is as follows: This disclosure provides a transistor comprising: a substrate, a heterojunction, an electrode assembly, and a cap layer. The heterojunction includes a channel layer and a barrier layer sequentially stacked on the substrate. The electrode assembly includes a source, a drain, and a gate. The source and the drain are located on opposite sides of the gate, and the source, the drain, and the gate are electrically connected to the heterojunction. The cap layer is located on the side of the barrier layer away from the substrate and on the side of the drain closer to the gate. The cap layer is in contact with the drain and spaced apart from the gate.

[0006] In one possible implementation, the cap layer is a monolithic structure that extends from one side of the barrier layer to the other side in a direction perpendicular to the arrangement direction of the source and the drain.

[0007] Optionally, the entire surface of the cap layer near the substrate is connected to the barrier layer; or, the transistor further includes a spacer dielectric layer comprising a plurality of dielectric blocks spaced apart along a first direction intersecting the arrangement direction of the source and the drain, a portion of the cap layer being located between the plurality of dielectric blocks and connected to the barrier layer, and another portion of the cap layer being located on the surface of the plurality of dielectric blocks away from the substrate.

[0008] In another possible implementation, the cap layer includes a plurality of spaced-apart block structures, each of which is in contact with the drain electrode.

[0009] Optionally, the length of the orthographic projection of the cap layer onto the barrier layer is 2μm-15μm.

[0010] Optionally, the width of the orthographic projection of each block structure onto the barrier layer is 0.5 μm-3 μm, and the spacing between two adjacent block structures is 0.5 μm-3 μm.

[0011] Optionally, the cap layer is a GaN layer, a ScAlN layer, an InGaN layer, or an AlGaN layer.

[0012] Optionally, the barrier layer includes a first barrier layer and a second barrier layer stacked sequentially on the channel layer, and the transistor further includes: a first dielectric layer located between the first barrier layer and the second barrier layer; the gate penetrates the second barrier layer and is connected to the first dielectric layer.

[0013] Optionally, the distance between the orthographic projection of the contact surface between the gate and the first dielectric layer on the substrate and the orthographic projection of the contact surface between the drain and the first barrier layer on the substrate is 10μm-22μm.

[0014] This disclosure also provides a method for manufacturing a transistor. The method includes: sequentially forming a heterojunction and a cap layer on a substrate, the heterojunction including a channel layer and a barrier layer sequentially stacked on the substrate, the cap layer being located on the side of the barrier layer away from the substrate; fabricating an electrode assembly including a source, a gate, and a drain, wherein the source and the drain are located on opposite sides of the gate, and the source, the drain, and the gate are electrically connected to the heterojunction; wherein the cap layer is located on the side of the drain closer to the gate, the cap layer contacting the drain and spaced apart from the gate.

[0015] The beneficial effects of the technical solutions provided in this disclosure are: In this embodiment, a cap layer is provided on the side of the barrier layer away from the substrate. This cap layer is located on the drain side near the gate, contacting the drain but not the gate. Furthermore, the orthographic projection of the cap layer onto the surface of the substrate does not overlap with the orthographic projection of the gate onto the surface of the substrate. This cap layer can introduce an electric field component in the stacking direction of the barrier layer and the channel layer, forming a region with high electric field capacity on the drain side of the transistor drift region, optimizing the channel electric field, thereby improving the transistor's breakdown voltage performance while maintaining low on-resistance. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a cross-sectional structure of a transistor provided in an embodiment of this disclosure; Figure 2 yes Figure 1 A top view of the transistor structure; Figure 3 yes Figure 2 A schematic cross-sectional view of the transistor along line B-B'; Figure 4 yes Figure 1 Another top view of a transistor structure; Figure 5 yes Figure 4 A schematic cross-sectional view of the transistor along line C-C'. Figure 6 This is a schematic diagram of a cross-sectional structure of another transistor provided in an embodiment of this disclosure; Figure 7 This is a schematic flowchart of a transistor manufacturing method provided in an embodiment of this disclosure; Figure 8 This is a schematic flowchart of another transistor manufacturing method provided in this disclosure embodiment; Figures 9 to 14 This is a schematic diagram illustrating the manufacturing process of a transistor according to an embodiment of this disclosure. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0019] This disclosure provides a transistor. Figure 1 This is a schematic diagram of a transistor structure provided in an embodiment of this disclosure. Figure 1As shown, the transistor includes a substrate 10, a heterojunction, a cap layer 40, and an electrode assembly. The heterojunction includes a channel layer 20 and a barrier layer 30 sequentially stacked on the substrate 10. The electrode assembly includes a source 51, a drain 52, and a gate 53. The source 51 and drain 52 are located on opposite sides of the gate 53, and the source 51, drain 52, and gate 53 are electrically connected to the heterojunction. The cap layer 40 is located on the side of the barrier layer 30 away from the substrate 10 and on the side of the drain 52 closer to the gate 53. The cap layer 40 is in contact with the drain 52 and spaced apart from the gate 53, meaning the cap layer 40 is not in contact with the gate 53.

[0020] In this embodiment, a cap layer is provided on the side of the barrier layer away from the substrate, and this cap layer is located on the side of the drain near the gate, contacting the drain but not the gate. This cap layer can introduce an electric field component in the stacking direction of the barrier layer and the channel layer, forming a region with high electric field capacity on the drain side of the transistor drift region, optimizing the channel electric field, thereby improving the breakdown voltage performance of the transistor while keeping the on-resistance constant.

[0021] Figure 2 yes Figure 1 A top view of the transistor's structure. Figure 1 yes Figure 2 A schematic diagram of the cross-sectional structure of the transistor along line A-A'. (See diagram below.) Figure 2 As shown, the three dashed boxes from left to right represent the orthographic projection regions of the source 51, gate 53, and drain 52 onto the surface of the substrate 10, respectively, while the shaded area represents the orthographic projection region of the cap layer 40 onto the surface of the substrate 10. The orthographic projection of the cap layer 40 onto the surface of the substrate 10 does not overlap with the orthographic projection of the gate 53 onto the surface of the substrate 10. When the gate employs a gate field plate structure, if the orthographic projections of the cap layer and the gate overlap, it will adversely affect the electric field modulation effect of the gate field plate structure. Therefore, the orthographic projections of the cap layer and the gate can be set to not overlap.

[0022] Figure 3 yes Figure 2 A schematic diagram of the cross-sectional structure of the transistor along line B-B'. (Combined with...) Figures 1 to 3 The cap layer 40 is a monolithic structure that extends from one side of the barrier layer 30 to the other side in a direction perpendicular to the arrangement direction of the source electrode 51 and the drain electrode 52.

[0023] In this embodiment, the entire surface of the cap layer 40 near the substrate 10 is in contact with the barrier layer 30.

[0024] Optionally, the length L of the orthographic projection of the cap layer 40 onto the barrier layer 30 is 2μm-15μm. The lower limit of the cap layer length can be determined by the effect, and the upper limit is determined by the spacing between the source and drain.

[0025] For example, the length L of the cap layer 40 is 4μm-8μm. This length range ensures that the cap layer has a significant impact on improving the voltage withstand performance of the transistor, and also avoids the gate and the cap layer from not overlapping on the substrate surface.

[0026] Optionally, the sidewall of the cap 60 near the drain 53 has a stepped structure 42, and the drain 53 contacts the stepped surface of the stepped structure to ensure good contact between the cap 60 and the drain 53.

[0027] The stepped structure 42 includes a top surface, a bottom surface, and a side wall connecting the top and bottom surfaces. The distances between the top and bottom surfaces and the surfaces of the cap 40 that contact the barrier layer 30 are both greater than 0, and the distance between the top surface and the surface of the cap 40 that contacts the barrier layer 30 is greater than the distance between the bottom surface and the surface of the cap 40 that contacts the barrier layer 30.

[0028] In implementation, the size of the bottom surface of the step is 0.2μm-1μm in the arrangement direction of the source 51 and drain 53. For example, it is 0.6μm. The lower limit of the size range of the bottom surface of the step is determined by the alignment accuracy of the photolithography process; if it is too small, the alignment accuracy may not be met. The upper limit of the size range of the bottom surface of the step takes into account the chip area and the contact reliability between the drain and the barrier layer. While ensuring the contact between the drain and the barrier layer, the size of the bottom surface of the step is kept small to avoid sacrificing chip area.

[0029] Optionally, the cap layer 40 is a GaN layer, a ScAlN layer, an InGaN layer, or an AlGaN layer. Using these layers as the cap layer 40 can form a hole potential well between the barrier layer and the cap layer, and an electron potential well between the barrier layer and the channel layer. The hole potential well and the electron potential well form an equivalent PN junction, thereby generating a vertical electric field and optimizing the channel electric field.

[0030] In this embodiment, the cap layer 40 is an intrinsic GaN layer (i.e., an unintentionally doped GaN layer) or a p-type doped GaN layer. When the cap layer 40 is a p-type doped GaN layer, the doping element can be Mg, Zn, Ca, C, or Si. Using a GaN layer as the cap layer 40 is a mature process, and the required gas source is the same as that used when fabricating the communication layer 20, eliminating the need for an additional gas source and reducing costs. Furthermore, when the barrier layer is an AlGaN layer, using a GaN layer as the cap layer can increase the amount of interfacial polarization charge between the cap layer and the barrier layer, which is beneficial for improving the transistor's breakdown voltage performance.

[0031] Optionally, the thickness of the cap layer 40 is 5nm-30nm. The thickness of the cap layer determines the hole concentration at the interface between the cap layer and the barrier layer. If the cap layer is too thin, it is insufficient to form a hole well layer that affects the vertical electric field. If the cap layer is too thick, on the one hand, the hole concentration at the interface between the cap layer and the barrier layer will not increase further, and the breakdown voltage performance of the semiconductor device will not be further improved; on the other hand, it may affect the structural morphology of the drain region, increasing the difficulty of process optimization.

[0032] In one possible implementation, gate 53 includes a gate body and a gate field plate connected together. The gate body has a columnar structure, with one end in contact with the barrier layer and the other end connected to the gate field plate. The orthographic projection of the gate body onto the surface of the substrate is located inside the orthographic projection of the gate field plate onto the surface of the substrate.

[0033] This disclosure does not limit the number of gate field plates, which can be single or multiple. When the number of gate field plates is multiple, the multiple gate field plates are connected sequentially along the direction away from the gate body, and the orthographic projection of the nth-level gate field plate on the surface of the substrate is located inside the orthographic projection of the (n+1)th-level gate field plate on the surface of the substrate. The nth-level gate field plate is closer to the gate body than the (n+1)th-level gate field plate.

[0034] For example, in Figure 1 In this structure, the gate 53 includes a gate body 53a and three-stage gate field plates 53b, with the gate field plates 53b having three stages. The first, second, and third stage gate field plates 53b are connected sequentially in a direction away from the gate body 53a. The orthographic projection of the first stage gate field plate 53b onto the surface of the substrate 10 is located inside the orthographic projection of the second stage gate field plate 53b onto the surface of the substrate 10, and the orthographic projection of the second stage gate field plate 53b onto the surface of the substrate 10 is located inside the orthographic projection of the third stage gate field plate 53b onto the surface of the substrate 10.

[0035] In this embodiment, the gate field plate can disperse the electric field peak at the gate edge over a larger area, thereby improving the breakdown voltage. Furthermore, the multi-level gate field plate, through its stepped extension, can progressively adjust the electric field, resulting in a smoother and more uniform electric field distribution and avoiding localized electric field spikes.

[0036] In another possible implementation, the gate 53 is a columnar structure. The fabrication process of a columnar gate structure is simple.

[0037] Optionally, the channel layer 20 is a GaN layer with a thickness of 100nm-300nm.

[0038] Optionally, the barrier layer 30 includes a first barrier layer 31 and a second barrier layer 32 sequentially stacked on the channel layer 20. The gate 53 penetrates the first barrier layer 31, thereby forming a recessed gate structure. With a recessed gate structure, the thickness of the barrier layer between the gate and the channel layer is smaller, which can weaken its polarization field effect on the channel layer and reduce the two-dimensional electron gas concentration. This makes the transistor more easily depleted by the gate voltage, which is beneficial for controlling the transistor's threshold voltage. In the region outside the gate, the barrier layer is thicker, and the two-dimensional electron gas concentration is higher, which is beneficial for reducing the transistor's on-resistance.

[0039] Optionally, the first barrier layer 31 can be an AlGaN layer with a thickness of 10nm-25nm. The Al content in the first barrier layer 31 is greater than or equal to 0.15 and less than or equal to 0.25.

[0040] Optionally, the second barrier layer 32 can be an AlGaN layer with a thickness of 10nm-25nm. The Al content in the second barrier layer 32 is greater than or equal to 0.2 and less than or equal to 0.45.

[0041] When both the first barrier layer 31 and the second barrier layer 32 are AlGaN layers, the thicknesses of the first barrier layer 31 and the second barrier layer 32 may be the same or different, and the Al content in the first barrier layer 31 and the Al content in the second barrier layer 32 may be the same or different.

[0042] In some examples, the Al content in the first barrier layer 31 is lower than the Al content in the second barrier layer. The Al content in the first barrier layer 31 affects the threshold voltage of the transistor; therefore, the smaller content range described above can be used. The Al content in the second barrier layer 32 does not affect the threshold voltage, and a higher Al content in the second barrier layer 32 is beneficial for enhancing the polarization intensity of the transistor's drift region, thereby increasing the carrier concentration. Therefore, the Al content in the second barrier layer 32 can be set to a larger value within the corresponding range described above.

[0043] exist Figure 1 In the illustrated embodiment, the gate 53 is in contact with the second barrier layer 32. Since the gate is in contact with the second barrier layer, leakage current from the gate to the drain may occur through the second barrier layer; however, this leakage has a relatively small impact on transistor performance. In this case, to simplify the transistor fabrication process, the gate can be fabricated by creating a trench in the second barrier layer.

[0044] In other embodiments, the gate 53 may not be in contact with the second barrier layer 32, thus preventing leakage from the gate to the drain through the second dielectric layer. However, additional processing is required to make the gate in contact with the second barrier layer.

[0045] Optionally, the transistor further includes a first dielectric layer 61 located between a first barrier layer 31 and a second barrier layer 32. A gate 53 penetrates the second barrier layer 32 and is connected to the first dielectric layer 61.

[0046] The first dielectric layer is disposed between the gate and the second barrier layer. The first barrier layer is a monolithic structure. The interface between the gate and the first barrier layer will not undergo dry etching, thereby avoiding interface damage caused by dry etching. This results in good interface characteristics between the gate and the first barrier layer, which is beneficial to improving the stability and reliability of gate control.

[0047] Optionally, the dimension of the first dielectric layer 61 in the arrangement direction of the source 51 and the drain 53 is larger than the dimension of the contact surface between the gate 53 and the first dielectric layer 61 in that arrangement direction. That is, the first dielectric layer 61 extends a certain distance from the contact surface between the gate 53 and the first dielectric layer 61 toward the source 51 and the drain 53, respectively.

[0048] In this embodiment of the disclosure, the contact surface between the gate 53 and the first dielectric layer 61 has a first boundary near the source 51 and a second boundary near the drain 52, and the dimension of the contact surface between the gate 53 and the first dielectric layer 61 in this arrangement direction is the distance between the first boundary and the second boundary.

[0049] In implementation, the distance between the second boundary and the boundary of the first dielectric layer 61 near the drain 52 in the aforementioned arrangement direction is less than the length of the first-stage field plate. The length of the first-stage field plate refers to the length of the first-stage field plate extending towards the drain 52 relative to the columnar structure in the aforementioned arrangement direction. This allows the first-stage field plate to modulate the electric field spikes at the edge of the first dielectric layer.

[0050] In some examples, the dimension of the contact surface in the aforementioned arrangement direction is 0.4 μm-2 μm; the distance between the first boundary and the boundary of the first dielectric layer 61 near the source 51 in the aforementioned arrangement direction is 0.2 μm-2 μm; the distance between the second boundary and the boundary of the first dielectric layer 61 near the drain 52 in the aforementioned arrangement direction is 0.2 μm-5 μm. That is, Figure 1 In the process, the distance between the left and right boundaries of the contact surface is 0.4μm-2μm; the distance between the left boundary of the contact surface and the left boundary of the first dielectric layer is 0.2μm-2μm; and the distance between the right boundary of the contact surface and the right boundary of the first dielectric layer is 0.2μm-5μm.

[0051] In each of the above distance ranges, the lower limit is determined by the fabrication process precision, while the upper limit is determined by the device performance requirements. For example, the upper limit of the distance between the second boundary and the boundary of the first dielectric layer 61 near the drain 52 in the aforementioned arrangement direction is determined by the length of the first-stage field plate. The length of the first-stage field plate is typically no greater than 5 μm; therefore, the corresponding upper limit of the distance is 5 μm.

[0052] Optionally, the first dielectric layer 61 can be a SiN layer, a SiO2 layer, or an Al2O3 layer.

[0053] In this embodiment, the first dielectric layer 61 is a SiN layer, and SiN has good interface characteristics with group III-V materials (i.e., barrier layer materials).

[0054] The thickness of the first dielectric layer 61 is related to the dielectric constant of the material used to fabricate the first dielectric layer. A higher dielectric constant results in a thicker first dielectric layer. In practice, when the first dielectric layer 61 is a SiN layer, its thickness can be 30nm-70nm. For example, the thickness of the first dielectric layer 61 is 50nm.

[0055] Optionally, see Figure 1 The distance D between the orthographic projection of the contact surface between the gate 53 and the first dielectric layer 61 on the substrate 10 and the orthographic projection of the contact surface between the drain 52 and the first barrier layer 31 on the substrate 10 is 10μm-22μm.

[0056] The spacing D is the length of the drift region. When the drift region length is 10 μm, the voltage of the transistor is 650 V. When the drift region length is 22 μm, the voltage of the transistor is 1200 V.

[0057] Generally, the longer the drift region, the better the transistor's voltage withstand capability, but the higher the on-resistance. In the embodiments of this disclosure, since the cap layer can form a region with high electric field capacity on the gate side of the drift region, by setting the cap layer, the on-resistance of the transistor can be kept low while increasing the length of the drift region, thereby obtaining a transistor with high voltage withstand capability and low on-resistance.

[0058] For example, for a 650V transistor, without a cap layer, the length of the drift region is typically greater than or equal to 15μm, while in the embodiments of this disclosure, after a cap layer is provided, the length of the drift region can be reduced to 10μm.

[0059] Optionally, the substrate 10 can be a silicon substrate, a sapphire substrate, a gallium nitride substrate, or a silicon carbide substrate, etc.

[0060] Optionally, the transistor further includes a buffer layer 70. The buffer layer 70 is located between the channel layer 20 and the substrate 10. By providing the buffer layer 70, it is beneficial to improve the crystal quality of the channel layer and ensure that the two-dimensional electron gas has high electron mobility.

[0061] The material of the buffer layer 70 is determined by the materials of the substrate 10 and the channel layer 20. For example, for a sapphire substrate, the buffer layer 70 can be a GaN layer, an AlGaN layer, or a stacked structure composed of GaN and AlGaN layers.

[0062] Optionally, the thickness of the buffer layer 70 can be 0.5 μm-3 μm.

[0063] Optionally, the buffer layer 70 may be doped with C or Fe. Doping with C or Fe can transform the buffer layer from a conductive state to a high-resistivity semi-insulating state, which is beneficial for obtaining high-performance, high-voltage-resistant transistors.

[0064] Optionally, the transistor further includes a second dielectric layer 62 located on the side of the cap layer 40 away from the substrate 10, and covering the cap layer 40 and the barrier layer 30.

[0065] exist Figure 1 In the illustrated embodiment, the source 51 and drain 52 penetrate the second dielectric layer 62 and the barrier layer 30 and are in contact with the channel layer 20. In this case, the sidewalls of the source 51 and drain 52 are in contact with the barrier layer 30.

[0066] In other embodiments, the source 51 and drain 52 may not penetrate the barrier layer 30, but may instead contact the surface of the barrier layer 30 away from the substrate 10.

[0067] Optionally, the transistor further includes a third dielectric layer 63, which is located on the side of the second dielectric layer 62 away from the substrate 10 and covers the surface of the second dielectric layer 62. The gate 53 extends through the second dielectric layer 62, the third dielectric layer 63, and the second barrier layer 32.

[0068] In this embodiment of the disclosure, both the second dielectric layer 62 and the third dielectric layer 63 are made of insulating material. Exemplarily, the second dielectric layer 62 can be a SiN layer, a SiO2 layer, or a stacked structure composed of a SiN layer and a SiO2 layer; the third dielectric layer 63 can be a SiN layer, a SiO2 layer, or a stacked structure composed of a SiN layer and a SiO2 layer.

[0069] Optionally, the thickness of the second dielectric layer 62 can be 50nm-200nm; the thickness of the third dielectric layer 63 can be 100nm-500nm.

[0070] It should be noted that vias exposing the source and drain may be provided in the third dielectric layer 63. Figure 1 (not shown in the image) to facilitate electrical connection between the source and drain terminals and the external environment.

[0071] In this embodiment, a second dielectric layer and a third dielectric layer are provided to facilitate the formation of the aforementioned three-level gate field plate structure. When the gate only includes a columnar structure and does not include a gate field plate, it is not necessary to provide a second dielectric layer and a third dielectric layer.

[0072] Optionally, an etching stop layer may be inserted in the second dielectric layer 62, and / or an etching stop layer may be inserted in the third dielectric layer 63. This restricts the position of the stepped grooves when forming the stepped grooves for accommodating the gate field plate.

[0073] The etching stop layer can be an AlN layer or an Al2O3 layer, with a thickness of 5nm-10nm.

[0074] Optionally, the source 51, drain 52, and gate 53 are all made of metallic materials. Exemplarily, the source 51, drain 52, and gate 53 can be formed using an Al-based composite material, meaning that the source 51, drain 52, and gate 53 are all multilayer structures including an Al layer. Exemplarily, the multilayer structure including the Al layer can be a multilayer structure composed of a TiN layer, an Al layer, and a TiN layer, or a multilayer structure composed of a Ti layer, an Al layer, and a TiN layer. Since the source and drain are usually formed simultaneously, the layer structure of the source 51 and drain 52 is the same. The layer structure of the gate 53 can be the same as or different from the layer structure of the source 51 and drain 52. This disclosure does not limit the material of each electrode, as long as the electrode's conductivity function can be achieved.

[0075] The thicknesses of the source 51 and drain 52 depend on the thicknesses of the barrier layer 30, the cap layer 40, and the second dielectric layer 62. For example, the thicknesses of the source 51 and drain 52 are 100nm-200nm, such as 150nm.

[0076] The thickness of gate 52 depends on the thicknesses of the second barrier layer 32, the first dielectric layer 61, the second dielectric layer 62, and the third dielectric layer 63. For example, the thickness of gate 53 is 150nm-500nm.

[0077] Figure 4 yes Figure 1 Another top view of a transistor structure. Figure 5 yes Figure 4 A schematic cross-sectional view of the C-C' line in the transistor. Figure 2 and Figure 3 The difference in the transistors shown lies in the different structure of the cap layer 40.

[0078] Figure 4 and Figure 5 In the middle, the cap layer 40 includes a plurality of block structures 41, which are arranged at intervals, and each block structure 41 is in contact with the drain electrode 52.

[0079] Optionally, the width a of the orthographic projection of each block structure 41 onto the barrier layer 30 is 0.5μm-3μm; the spacing h between two adjacent block structures 41 is 0.5μm-3μm.

[0080] If the spacing between adjacent block structures is too large, it will be unable to regulate the electric field in the channel region between adjacent block structures when the transistor is in the off state. Conversely, if the spacing between adjacent block structures is too small, it will significantly affect the on-resistance when the transistor is on. Setting the size of the block structures and the spacing between adjacent block structures within this range is beneficial for better balancing the on-resistance and voltage withstand capability of the transistor.

[0081] In this embodiment, the number of block structures in the cap layer 40 can be determined based on the transistor size and the size of each block structure in the arrangement direction of the plurality of block structures. For example, Figure 4 In the middle, the cap layer 40 includes 3 block structures 41.

[0082] In this embodiment, there is a conductive path between adjacent block structures that is unaffected by the cap layer. When the transistor is in the on state, the concentration of two-dimensional electron gas at this conductive path is high, which is consistent with... Figure 2 and Figure 3 Compared to the illustrated embodiment, with all other structures except the cap layer remaining the same, the on-resistance can be further reduced. Even when the transistor is in the off-state, the cap layer can still introduce an electric field component in the vertical direction, thereby improving the transistor's breakdown voltage. Therefore, this embodiment allows for a trade-off between improving the device's breakdown voltage performance and reducing on-resistance, resulting in a transistor that meets the required performance requirements.

[0083] Figure 6 This is a schematic cross-sectional view of another transistor provided in this disclosure. Figure 2 and Figure 3 The difference in the transistor shown is that it also includes a spacer dielectric layer 64 located between the cap layer 40 and the barrier layer 30.

[0084] The spacer dielectric layer 64 includes a plurality of dielectric blocks 641 arranged at intervals. A portion of the cap layer 40 is located between the plurality of dielectric blocks 641 and connected to the barrier layer 30, and another portion of the cap layer 40 is located on the surface of the plurality of dielectric blocks 641 away from the substrate 10.

[0085] That is, in this embodiment, a portion of the surface of the cap layer 40 near the substrate 10 is in contact with the barrier layer 30, and another portion is in contact with the dielectric block 641.

[0086] The number of media blocks 641 can be set according to actual needs, such as two or three, and this embodiment does not limit this.

[0087] Optionally, the width of the orthographic projection of each dielectric block 641 onto the barrier layer 30 is 0.5μm-3μm; the spacing between two adjacent dielectric blocks 641 is 0.5μm-3μm.

[0088] In this embodiment, the cap layer 40, which is in contact with the barrier layer 30, can introduce an electric field component in the vertical direction when the transistor is in the off-state, thereby improving the transistor's breakdown voltage capability. Meanwhile, in the region where the dielectric block is located, there exists a conductive path unaffected by the cap layer. When the transistor is in the on-state, the concentration of two-dimensional electron gas at this conductive path is high, which is related to… Figure 2 and Figure 3 Compared to the embodiment shown, the on-resistance can be further reduced while keeping all other structures the same except for the cap layer.

[0089] Furthermore, in this embodiment, the pattern (i.e., dielectric block) in the spacer dielectric layer 64 can be formed using a wet etching process, while the cap layer 40 is formed using a dry etching process. In this way, the region of the second barrier layer 32 near the drain 53 is completely covered by the cap layer 40 and will not undergo dry etching, resulting in higher interface quality and better dynamic stability of the device under high voltage bias.

[0090] The transistors provided in this disclosure can be GaN HEMTs (High Electron Mobility Transistors), especially GaNHEMTs with high voltage resistance (voltage level greater than or equal to 650V).

[0091] Figure 7 This is a flowchart illustrating a method for manufacturing a transistor according to an embodiment of this disclosure, which can be used to manufacture any of the aforementioned transistors. Figure 7 As shown, the manufacturing method includes: In step 701, a heterojunction and a cap layer are sequentially formed on the substrate. The heterojunction includes a channel layer and a barrier layer sequentially stacked on the substrate, and the cap layer is located on the side of the barrier layer away from the substrate. In step 702, an electrode assembly is prepared, which includes a source, a gate, and a drain. The source and drain are located on opposite sides of the gate, and the source, drain, and gate are electrically connected to a heterojunction.

[0092] The cap layer is located on the side of the drain electrode closest to the gate, and the cap layer is in contact with the drain electrode and spaced apart from the gate electrode.

[0093] Figure 8 This is a flowchart illustrating another method for manufacturing a transistor according to an embodiment of this disclosure, which can be used to manufacture... Figures 1 to 5 The transistor shown. (As shown) Figure 8 As shown, the manufacturing method includes: In step 801, a buffer layer, a channel layer, and a first barrier layer are sequentially formed on the substrate.

[0094] The buffer layer, channel layer, and first barrier layer can all be formed using MOCVD (Metal-organic Chemical Vapor Deposition) or MBE (Molecular Beam Epitaxy) processes.

[0095] like Figure 9 As shown, the buffer layer 70, the channel layer 20, and the first barrier layer 31 are sequentially stacked on the substrate 10.

[0096] In step 802, a first dielectric layer is formed on the first barrier layer.

[0097] Step 802 may include: first forming a complete first dielectric material layer on the first barrier layer using processes such as MOCVD or MBE, and then etching the first dielectric material layer to obtain the first dielectric layer.

[0098] In step 803, a second barrier layer is formed on the first dielectric layer.

[0099] Optionally, the second barrier layer 32 can be formed using MOCVD or MBE processes.

[0100] like Figure 10 As shown, the first dielectric layer 61 is located on the side of the first barrier layer 31 away from the substrate 10 and covers a portion of the first barrier layer 31. The second barrier layer 32 covers the first dielectric layer 61 and the surface of the first barrier layer 31 not covered by the first dielectric layer 61.

[0101] In step 804, a cap layer is formed on the second barrier layer.

[0102] Step 804 may include: first forming a complete cap layer material layer on the first barrier layer using processes such as MOCVD or MBE, and then etching the cap layer material layer to obtain the cap layer.

[0103] like Figure 11 As shown, the cap layer 40 covers a portion of the second barrier layer 32 and is located on one side of the first dielectric layer 61.

[0104] In step 805, a second dielectric layer is formed on the cap layer.

[0105] Alternatively, the second dielectric layer can be formed using processes such as LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), or ALD (Atomic Layer Deposition).

[0106] like Figure 12 As shown, the second dielectric layer 62 covers the surface of the second barrier layer 32 that is not covered by the cap layer 40, as well as the surface of the cap layer 40.

[0107] In step 806, a source via and a drain via are formed in the second dielectric layer, the second barrier layer and the first barrier layer, and a source is formed in the source via and a drain is formed in the drain via.

[0108] Source vias and drain vias can be formed through photolithography and etching processes.

[0109] Forming a source in a source via and a drain in a drain via includes: forming a source / drain metal layer that covers the surface of a second dielectric layer away from the substrate and fills the source and drain vias; and patterning the source / drain metal layer to obtain the source and drain.

[0110] Optionally, after patterning the source and drain metal layers to obtain the source and drain, rapid annealing can be performed to obtain the source and drain with ohmic contact properties.

[0111] Alternatively, the rapid annealing temperature can be 800℃-900℃, for example 850℃.

[0112] like Figure 13 As shown, the source 51 and drain 53 penetrate the second dielectric layer 62, the second barrier layer 32 and the first barrier layer 31.

[0113] In step 807, a third dielectric layer is formed on the source, drain, and second dielectric layer.

[0114] like Figure 14 As shown, the third dielectric layer 63 covers the source 51, the drain 52, and the second dielectric layer 62.

[0115] In step 808, a gate via is formed in the third dielectric layer, the second dielectric layer, and the second barrier layer, and a gate is formed in the gate via.

[0116] The gate vias can be formed through photolithography and etching processes. It should be noted that when the gate includes a gate field plate, multiple photolithography and etching processes are required to form a stepped via that can accommodate the gate field plate.

[0117] Forming a gate in a gate via includes: forming a gate metal layer that covers the surface of a third dielectric layer away from the substrate and fills the gate via; and patterning the gate metal layer to obtain the gate.

[0118] At this point, we can obtain Figure 1 The transistor shown.

[0119] This disclosure also provides another method for manufacturing a transistor, for manufacturing... Figure 6 The transistor shown. This manufacturing method is similar to... Figure 8 Compared to the manufacturing method shown, this manufacturing method further includes: forming a spacer dielectric material layer after step 803 and before step 804, and performing patterning processing on the spacer dielectric material layer to obtain the spacer dielectric layer.

[0120] Alternatively, when patterning the spacer dielectric material layer, wet etching can be used to avoid dry etching damage to the surface of the second barrier layer.

[0121] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described objects changes, the relative positional relationship may also change accordingly.

[0122] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A transistor, characterized in that, include: Substrate (10), heterojunction, electrode assembly and cap layer (40). The heterojunction includes a channel layer (20) and a barrier layer (30) sequentially stacked on the substrate (10). The electrode assembly includes a source (51), a drain (52), and a gate (53). The source and the drain (52) are located on both sides of the gate (53), and the source (51), the drain (52), and the gate (53) are electrically connected to the heterojunction, respectively. The cap layer (40) is located on the side of the barrier layer (30) away from the substrate (10) and on the side of the drain (52) near the gate (53). The cap layer (40) is in contact with the drain (52) and spaced apart from the gate (53).

2. The transistor according to claim 1, characterized in that, The cap layer (40) is a monolithic structure that extends from one side of the barrier layer (30) to the other side in a direction perpendicular to the arrangement direction of the source (51) and the drain (52).

3. The transistor according to claim 2, characterized in that, The entire surface of the cap layer (40) near the substrate (10) is connected to the barrier layer (30); or, The transistor further includes a spacer dielectric layer (64) comprising a plurality of dielectric blocks (641) spaced apart along a first direction intersecting the arrangement direction of the source (51) and the drain (52), a portion of the cap layer (40) being located between the plurality of dielectric blocks (641) and connected to the barrier layer (30), and another portion of the cap layer (40) being located on the surface of the plurality of dielectric blocks (641) away from the substrate (10).

4. The transistor according to claim 1, characterized in that, The cap layer (40) includes a plurality of spaced block structures (41), each of which is in contact with the drain electrode (52).

5. The transistor according to claim 4, characterized in that, The width a of the orthographic projection of each block structure (41) onto the barrier layer (30) is 0.5μm-3μm; the spacing h between two adjacent block structures (41) is 0.5μm-3μm.

6. The transistor according to any one of claims 1 to 5, characterized in that, The length L of the orthogonal projection of the cap layer (40) onto the barrier layer (30) is 2μm-15μm.

7. The transistor according to any one of claims 1 to 5, characterized in that, The cap layer (40) is a GaN layer, a ScAlN layer, an InGaN layer, or an AlGaN layer.

8. The transistor according to any one of claims 1 to 5, characterized in that, The barrier layer (30) includes a first barrier layer (31) and a second barrier layer (32) stacked sequentially on the channel layer (20). The transistor further includes a first dielectric layer (61) located between the first barrier layer (31) and the second barrier layer (32). The gate (53) extends through the second barrier layer (32) and is connected to the first dielectric layer (61).

9. The transistor according to claim 8, characterized in that, The distance D between the orthographic projection of the contact surface between the gate (53) and the first dielectric layer (61) on the substrate (10) and the orthographic projection of the contact surface between the drain (52) and the first barrier layer (31) on the substrate (10) is 10μm-22μm.

10. A method for manufacturing a transistor, characterized in that, include: A heterojunction and a cap layer are sequentially formed on a substrate. The heterojunction includes a channel layer and a barrier layer sequentially stacked on the substrate, and the cap layer is located on the side of the barrier layer away from the substrate. An electrode assembly is fabricated, the electrode assembly including a source, a gate, and a drain, the source and the drain being located on opposite sides of the gate, and the source, the drain, and the gate being electrically connected to the heterojunction respectively; The cap layer is located on the side of the drain electrode closer to the gate electrode, and the cap layer is in contact with the drain electrode and spaced apart from the gate electrode.

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