Chip interconnection structure, chip and preparation method of chip interconnection structure
By forming interconnect interfaces on the die and directly connecting the internal bus using an interconnect intermediary layer, the design complexity and high cost of chip interconnect solutions are solved, achieving efficient, low-latency signal transmission and miniaturized design, thus reducing chip production costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING HUAFENG INTEGRATED ELECTRONICS CO LTD
- Filing Date
- 2025-12-29
- Publication Date
- 2026-05-08
AI Technical Summary
Existing chip interconnect solutions suffer from problems such as complex design, high cost, high latency and high power consumption, especially in large-size chips. Furthermore, complex protocol conversion increases additional latency and power consumption.
It adopts the method of forming interconnection interfaces on bare die and directly connecting the internal bus through interconnection interposer, eliminating the need for dedicated I/O circuits, and using micro-bump array and silicon bridge to achieve high-density, low-latency signal transmission.
It simplifies design, reduces costs, eliminates the need for protocol conversion in signal transmission paths, removes delays and power consumption introduced by dedicated I/O circuits, supports miniaturized design, and reduces design difficulty and cycle time.
Smart Images
Figure CN122003155A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor packaging technology, specifically to a chip interconnect structure, a chip, and a method for fabricating the chip interconnect structure. Background Technology
[0002] With the rapid development of applications such as high-performance computing and artificial intelligence, the number of functional modules integrated into System-on-a-Chip (SoC) is increasing, leading to a continuous increase in chip area. Larger chips not only incur high tape-out costs, but also experience a decrease in product yield as chip area increases, significantly raising production costs. To address this, existing solutions have proposed the Chiplet approach. A Chiplet is a technology that integrates dies from different process nodes using advanced packaging techniques to form a multifunctional modular chip. It can break down an on-chip system into multiple dies, enabling functional reuse and computing power expansion through heterogeneous combinations, thereby reducing design and manufacturing costs, shortening development cycles, and improving manufacturing yield. However, these solutions require interconnecting multiple dies. To achieve high-bandwidth, low-latency communication between different dies, current solutions typically integrate dedicated high-speed serializers / deserializers (SerDes), physical layer interfaces (PHYs, such as PCIe), or complex differential pair driver / receiver circuits into the I / O area of each die. The interconnection schemes with dedicated I / O circuits mentioned above have problems such as complex design and high cost. Furthermore, the complexity of protocol conversion will increase latency and power consumption. Summary of the Invention
[0003] This application aims to address one of the technical problems in related technologies to a certain extent. To this end, this application provides a chip interconnect structure, a chip, and a method for fabricating the chip interconnect structure.
[0004] To achieve the above objectives, this application adopts the following technical solution: a chip interconnect structure, comprising:
[0005] The first die has a first functional circuit and a first internal bus electrically connected to the first functional circuit, and the first die is provided with a first interconnection interface, and the signal lines of the first internal bus are directly connected to the first interconnection interface.
[0006] The second die has a second functional circuit and a second internal bus electrically connected to the second functional circuit, and the second die is provided with a second interconnect interface, wherein the signal lines of the second internal bus are directly connected to the second interconnect interface; and,
[0007] An interconnect intermediary layer is disposed between the first die and the second die, and the interconnect intermediary layer is used to electrically connect the first interconnect interface and the second interconnect interface so that the first internal bus and the second internal bus can communicate directly.
[0008] The application of this application has the following advantages: By forming a first interconnect interface and a second interconnect interface on a first die and a second die respectively, and directly connecting the first internal bus in the first die to the first interconnect interface and the second internal bus in the second die to the second interconnect interface, and then electrically connecting the first interconnect interface and the second interconnect interface using an interconnect interposer, direct communication between the first internal bus in the first die and the second internal bus in the second die can be achieved. This eliminates the need for dedicated high-speed serializers / deserializers (SerDes), physical layer interfaces (PHYs, such as PCIe), or complex differential pair driver / receiver circuits found in existing solutions, simplifying the design and reducing manufacturing costs. Furthermore, with the above structural design, the signal transmission path requires no protocol conversion or signal reshaping, eliminating the delay and power consumption introduced by dedicated I / O circuits. In addition, the inter-chip communication delay mainly depends on the physical length of the interconnect interposer, achieving performance close to that of intra-chip communication. Furthermore, this application can also support the splitting of a large-size chip (with large internal circuitry) into multiple dies that are easy to miniaturize. The miniaturized dies have the advantages of low design difficulty and short design cycle, which can reduce the design difficulty and shorten the design cycle of the entire chip product, thereby reducing the manufacturing cost of the entire chip product.
[0009] Optionally, the first die and the second die are manufactured using different semiconductor processes.
[0010] Optionally, the first interconnect interface includes a first micro-bump array, and the second interconnect interface includes a second micro-bump array, wherein the number of micro-bumps in the first micro-bump array is the same as the number of micro-bumps in the second micro-bump array and they correspond one-to-one.
[0011] Optionally, the first microbump array is formed on the edge region of the surface of the first die, and the second microbump array is formed on the edge region of the surface of the second die.
[0012] Optionally, the interconnect interposer is a silicon bridge, and interconnect wires are formed within the silicon bridge to connect the microbumps in the first microbump array to the microbumps in the second microbump array in a one-to-one correspondence.
[0013] Optionally, the chip interconnect structure further includes at least one supplementary die, the supplementary die having a third functional circuit and a third internal bus electrically connected to the third functional circuit, and the supplementary die being provided with a third interconnect interface, the signal lines of the third internal bus being directly connected to the third interconnect interface;
[0014] The interconnection intermediary layer is also used to electrically connect the third interconnection interface to the first interconnection interface and the second interconnection interface, so that the third internal bus can communicate directly with the first internal bus and the second internal bus.
[0015] Optionally, there may be multiple supplementary dies, each manufactured using a different semiconductor process.
[0016] In addition, this application also provides a chip, including a packaging substrate, the chip further including at least one chip interconnect structure as described in any one of the above technical solutions, the chip interconnect structure being disposed on the packaging substrate.
[0017] The reasoning process for the beneficial effects of the chip provided in this application and the aforementioned chip interconnect structure is similar, and will not be repeated here.
[0018] In addition, this application also provides a method for fabricating a chip interconnect structure, including:
[0019] A first die and a second die are provided. The first die has a first functional circuit and a first internal bus electrically connected to the first functional circuit. The second die has a second functional circuit and a second internal bus electrically connected to the second functional circuit.
[0020] A first interconnect interface is formed on the first die, and a second interconnect interface is formed on the second die;
[0021] Connect the signal lines of the first internal bus directly to the first interconnect interface, and connect the signal lines of the second internal bus directly to the second interconnect interface;
[0022] An interconnection intermediary layer is provided, which is used to electrically connect the first interconnection interface and the second interconnection interface.
[0023] The preparation method provided in this application is similar to the reasoning process of the beneficial effects of the aforementioned chip interconnect structure, and will not be repeated here.
[0024] These features and advantages of this application will be disclosed in detail in the following specific embodiments and accompanying drawings. The best embodiments or means of this application will be shown in detail in conjunction with the accompanying drawings, but are not intended to limit the technical solutions of this application. In addition, each of these features, elements and components appearing in the following text and drawings is multiple and is labeled with different symbols or numbers for convenience, but all represent parts with the same or similar structure or function. Attached Figure Description
[0025] The following description, in conjunction with the accompanying drawings, further illustrates this application:
[0026] Figure 1This is a schematic diagram of a chip interconnect structure provided in an embodiment of this application;
[0027] Figure 2 This is a schematic diagram of the first and second dies in the chip interconnect structure;
[0028] Figure 3 This is a schematic diagram of a silicon bridge in a chip interconnect structure;
[0029] Figure 4 This is a schematic diagram of a chip interconnect structure in another implementation method;
[0030] Figure 5 This is a schematic diagram of a chip using the chip interconnect structure provided in this embodiment; it includes two bare dies.
[0031] Figure 6 This is a schematic diagram of a chip in another implementation method;
[0032] Figure 7 This is a schematic diagram of a chip in another embodiment.
[0033] Among them, 1 is the first die; 10 is the first microbump array; 2 is the second die; 20 is the second microbump array; 3 is the interconnect interposer; 30 is the third microbump array; 31 is the fourth microbump array; 32 is the interconnect wire; 4 is the supplementary die; 5 is the packaging substrate; 6 is the first chip interconnect structure; 7 is the second chip interconnect structure; and 8 is the third chip interconnect structure. Detailed Implementation
[0034] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described are intended to explain this application and should not be construed as limiting it.
[0035] The terms "an embodiment," "example," or "example" used in this specification refer to a particular feature, structure, or characteristic described in connection with the embodiment itself that may be included in at least one embodiment disclosed in this application. The phrase "in an embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment.
[0036] In the description of this application, it should be understood that the terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In the description of this application, "a plurality of" means two or more, unless otherwise precisely specified.
[0037] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected," "linked," and "connected" should be interpreted broadly. For example, they can refer to a fixed connection, a connection through an intermediary, or a connection within two elements or an interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0038] This embodiment provides a chip interconnect structure, such as Figure 1 and Figure 2 As shown, the chip interconnect structure includes a first die 1, a second die 2, and an interconnect interposer 3. The first die 1 has a first functional circuit and a first internal bus electrically connected to the first functional circuit. The first die 1 also has a first interconnect interface, and the signal lines of the first internal bus are directly connected to the first interconnect interface. The second die 2 has a second functional circuit and a second internal bus electrically connected to the second functional circuit. The second die 2 also has a second interconnect interface, and the signal lines of the second internal bus are directly connected to the second interconnect interface. The interconnect interposer 3 is disposed between the first die 1 and the second die 2, and is used to electrically connect the first interconnect interface and the second interconnect interface, enabling direct communication between the first internal bus and the second internal bus.
[0039] By forming a first interconnect interface and a second interconnect interface on the first die 1 and the second die 2 respectively, and directly connecting the first internal bus in the first die 1 to the first interconnect interface, and directly connecting the second internal bus in the second die 2 to the second interconnect interface, and then electrically connecting the first interconnect interface and the second interconnect interface using an interconnect intermediary layer 3, direct communication can be achieved between the first internal bus in the first die 1 and the second internal bus in the second die 2. This eliminates the need for dedicated high-speed serializers / deserializers (SerDes), physical layer interfaces (PHYs, such as PCIe), or complex differential pair driver / receiver circuits found in existing solutions, simplifying the design and reducing manufacturing costs. Furthermore, with this structure, the signal transmission path requires no protocol conversion or signal reshaping, eliminating the delay and power consumption introduced by dedicated I / O circuits. In addition, the inter-chip communication delay mainly depends on the physical length of the interconnect intermediary layer 3, achieving performance close to that of intra-chip communication. In practical applications, the connection length between the pins in the first die 1 and the pins in the second die 2 in this embodiment can be controlled within 1mm, and the signal quality can reach the level of the on-chip bus.
[0040] Furthermore, this application can also support the splitting of a large-size chip (with large internal circuitry) into multiple dies that facilitate miniaturization design. Utilizing the advantages of miniaturized dies, such as lower design difficulty and shorter design cycles, can reduce the overall design complexity and shorten the overall chip product design cycle, thereby reducing the overall chip product manufacturing cost. For example, the final target chip can be designed and fabricated into multiple dies according to different functional units (such as arithmetic logic units, memory units, acceleration units, etc.). Any two dies connected by an interconnecting interposer layer 3 can be considered as the first die 1 and the second die 2 described in this embodiment.
[0041] In this embodiment, the first internal bus and the second internal bus are on-chip system buses based on the AXI bus protocol. Bus signals include read / write address signals, read / write valid signals, read / write data signals, acknowledge signals, etc. In other optional embodiments, the first internal bus and the second internal bus can also be on-chip system buses based on the AHB bus protocol, PLB bus protocol, or ACE bus protocol, or similar protocols. User-defined bus protocols can also be used.
[0042] In a preferred embodiment, the first die 1 and the second die 2 are manufactured using different semiconductor process technologies. For example, the first die 1 is a CPU chip, which has extremely high requirements for computing speed and energy efficiency, and can be manufactured using advanced process technologies such as the most advanced FinFET technology, such as 5nm or 4nm. The second die 2 is an I / O chip, which occupies a large circuit area but does not have high performance requirements, and can be manufactured using mature processes such as 12nm or 6nm. This balances the performance and cost of the final target chip. It is easy to understand that the first die 1 and the second die 2 can also be manufactured using the same semiconductor process technology.
[0043] Combination Figure 2 and Figure 3 As shown, in this embodiment, the first interconnect interface includes a first microbump array 10, and the second interconnect interface includes a second microbump array 20. The number of microbumps in the first microbump array 10 and the number of microbumps in the second microbump array 20 are the same and correspond one-to-one. The interconnect interposer layer 3 is a silicon bridge, and interconnect wires 32 are formed within the silicon bridge to connect the microbumps in the first microbump array 10 and the microbumps in the second microbump array 20 in a one-to-one correspondence. Specifically, a third microbump array 30 corresponding to the first microbump array 10 and a fourth microbump array 31 corresponding to the second microbump array 20 are formed on the silicon bridge. The term "correspondence" here means that the number of microbumps in the first microbump array 10 and the number of microbumps in the third microbump array 30 are the same, and their array arrangement is the same. This ensures that the interconnect wires 32 are of equal length and that the interconnect wires 32 do not interfere with each other during wiring.
[0044] Using a microbump array as the interconnect interface provides a high-density, high-reliability physical connection, which is beneficial for enabling parallel transmission of multiple signals and improving interconnect bandwidth. Using a silicon bridge as the interconnect interposer layer 3 enables high-density, low-latency interconnection between microbumps. Simultaneously, the silicon bridge exhibits good thermal stability and electrical performance, making it suitable for high-performance chip packaging.
[0045] Furthermore, in this embodiment, the first microbump array 10 is formed on the edge region of the surface of the first die 1, and the second microbump array 20 is formed on the edge region of the surface of the second die 2. Arranging the microbump array on the edge region of the die surface facilitates thermal management and facilitates alignment and bonding with the interconnect interposer layer 3, thereby improving packaging yield.
[0046] In this embodiment, the chip interconnect structure uses an interconnect interposer 3 to connect two dies, namely the first die 1 and the second die 2. In other optional embodiments, an interconnect interposer 3 can connect a larger number of dies simultaneously. Figure 4As shown, the chip interconnect structure in this case also includes two supplementary dies 4. Each supplementary die 4 has a third functional circuit and a third internal bus electrically connected to the third functional circuit. The supplementary dies 4 are also provided with a third interconnect interface, and the signal lines of the third internal bus are directly connected to the third interconnect interface. The interconnect interposer layer 3 is also used to electrically connect the third interconnect interface to the first interconnect interface and the second interconnect interface, so that the third internal bus can communicate directly with the first internal bus and the second internal bus.
[0047] The above structural design can support the integration of multiple bare dies in the same chip interconnect structure, thereby expanding the system's functionality and scale, increasing its applicability, such as making it more suitable for complex SoC or chip stacking scenarios, and improving system integration and flexibility.
[0048] Furthermore, the two supplementary dies 4 mentioned above are also manufactured using different semiconductor process technologies. This allows the four dies in the chip interconnect structure to be manufactured using different semiconductor process technologies, further supporting heterogeneous integration and modular design, which is beneficial for achieving high-performance, low-power, multi-functional chip systems. Of course, it is also possible to choose to manufacture multiple supplementary dies 4 using the same semiconductor process technology.
[0049] It should be noted that the number of supplementary wafers 4 can be selected and set as needed, or only one supplementary wafer 4 or more supplementary wafers 4 can be set.
[0050] like Figure 5 As shown, this application also provides a chip, including a packaging substrate 5 and the chip interconnect structure provided in this embodiment, wherein the chip interconnect structure is disposed on the packaging substrate 5. The chip uses the chip interconnect structure provided in this embodiment. As mentioned above, a large-size chip (with integrated large circuitry) is split into multiple dies that facilitate miniaturization design. Utilizing the advantages of miniaturized dies—low design difficulty and short design cycle—can reduce the overall design difficulty and shorten the overall chip product design cycle, thereby reducing the overall chip product manufacturing cost. Simultaneously, it eliminates the need for dedicated high-speed serializers / deserializers (SerDes), physical layer interfaces (PHYs, such as PCIe), or complex differential pair drive / receive circuits found in existing solutions. Furthermore, the signal transmission path requires no protocol conversion or signal reshaping, eliminating the delay and power consumption introduced by dedicated I / O circuits.
[0051] Furthermore, to illustrate the significant effects of this chip interconnect structure, this embodiment also provides two other chips that employ this chip interconnect structure, specifically as follows: Figure 6 and Figure 7As shown. For ease of distinction, the multiple chip interconnect structures are referred to as the first chip interconnect structure 6, the second chip interconnect structure 7, and the third chip interconnect structure 8, respectively.
[0052] Figure 5 The image shows a scenario where the chip includes a chip interconnect structure. Figure 6 and Figure 7 All examples illustrate a scenario where the chip comprises three interconnect structures, but the arrangement of these interconnect structures differs. For instance... Figure 6 As shown, the chip includes three chip interconnect structures. The die in the middle can be used as the first die 1, and the other three dies are used as second dies 2 to interconnect with the first die 1 in the middle. The three second dies 2 interconnect with the first die 1 in the middle respectively form the first chip interconnect structure 6, the second chip interconnect structure 7, and the third chip interconnect structure 8. Figure 7 As shown, four dies arranged horizontally in succession are interconnected sequentially through an interconnecting interposer 3. From left to right, the first and third dies can serve as the first die 1, and the second and fourth dies can serve as the second die 2, thereby forming the first chip interconnect structure 6, the second chip interconnect structure 7, and the third chip interconnect structure 8, respectively. Therefore, the chip interconnect structure provided according to this embodiment can be conveniently used to interconnect not only two or more dies, depending on design requirements.
[0053] The fabrication method for the chip interconnect structure provided in this embodiment is described below, and the fabrication method includes the following steps:
[0054] First, a first die 1 and a second die 2 are provided. The first die 1 has a first functional circuit and a first internal bus electrically connected to the first functional circuit. The second die 2 has a second functional circuit and a second internal bus electrically connected to the second functional circuit.
[0055] Secondly, a first interconnect interface is formed on the first die 1, and a second interconnect interface is formed on the second die 2. Specifically, a first microbump array 10 and a second microbump array 20 can be formed at the edges of the first die 1 and the second die 2 by photolithography, thin film deposition, electroplating and other processes.
[0056] Then, the signal lines of the first internal bus are directly connected to the first interconnect interface, and the signal lines of the second internal bus are directly connected to the second interconnect interface.
[0057] Finally, an interconnect interposer layer 3 is provided, which is used to electrically connect the first interconnect interface and the second interconnect interface. Specifically, the microbumps in the third microbump array 30 on the interconnect interposer layer 3 are flip-bonded one-to-one with the microbumps in the first microbump array 10, and the microbumps in the fourth microbump array 31 on the interconnect interposer layer 3 are flip-bonded one-to-one with the microbumps in the second microbump array 20.
[0058] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Those skilled in the art should understand that this application includes, but is not limited to, the contents described in the accompanying drawings and the specific embodiments above. Any modifications that do not depart from the functional and structural principles of this application will be included within the scope of the claims.
Claims
1. A chip interconnect structure, characterized in that, include: The first die has a first functional circuit and a first internal bus electrically connected to the first functional circuit, and the first die is provided with a first interconnection interface, and the signal lines of the first internal bus are directly connected to the first interconnection interface. The second die has a second functional circuit and a second internal bus electrically connected to the second functional circuit, and the second die is provided with a second interconnection interface, and the signal lines of the second internal bus are directly connected to the second interconnection interface; as well as, An interconnect intermediary layer is disposed between the first die and the second die, and the interconnect intermediary layer is used to electrically connect the first interconnect interface and the second interconnect interface so that the first internal bus and the second internal bus can communicate directly.
2. The chip interconnect structure as described in claim 1, characterized in that, The first die and the second die are manufactured using different semiconductor processes.
3. The chip interconnect structure as described in claim 1 or 2, characterized in that, The first interconnect interface includes a first microbump array, and the second interconnect interface includes a second microbump array. The number of microbumps in the first microbump array and the number of microbumps in the second microbump array are the same and correspond one-to-one.
4. The chip interconnect structure as described in claim 3, characterized in that, The first microbump array is formed on the edge region of the surface of the first die, and the second microbump array is formed on the edge region of the surface of the second die.
5. The chip interconnect structure as described in claim 3, characterized in that, The interconnecting interposer is a silicon bridge, and interconnecting wires are formed within the silicon bridge to connect the microbumps in the first microbump array to the microbumps in the second microbump array in a one-to-one correspondence.
6. The chip interconnect structure as described in claim 1, characterized in that, The chip interconnect structure further includes at least one supplementary die, which has a third functional circuit and a third internal bus electrically connected to the third functional circuit. The supplementary die is provided with a third interconnect interface, and the signal lines of the third internal bus are directly connected to the third interconnect interface. The interconnection intermediary layer is also used to electrically connect the third interconnection interface to the first interconnection interface and the second interconnection interface, so that the third internal bus can communicate directly with the first internal bus and the second internal bus.
7. The chip interconnect structure as described in claim 6, characterized in that, The supplementary die is multiple, and each of the multiple supplementary dies is manufactured using a different semiconductor process.
8. A chip, comprising a packaging substrate, characterized in that, The chip further includes at least one chip interconnect structure as described in any one of claims 1 to 7, the chip interconnect structure being disposed on the packaging substrate.
9. A method for fabricating a chip interconnect structure, characterized in that, include: A first die and a second die are provided. The first die has a first functional circuit and a first internal bus electrically connected to the first functional circuit. The second die has a second functional circuit and a second internal bus electrically connected to the second functional circuit. A first interconnect interface is formed on the first die, and a second interconnect interface is formed on the second die; Connect the signal lines of the first internal bus directly to the first interconnect interface, and connect the signal lines of the second internal bus directly to the second interconnect interface; An interconnection intermediary layer is provided, which is used to electrically connect the first interconnection interface and the second interconnection interface.