Multi-chip in-situ stacking structure, stacking method and system thereof, and chips

Abstract

The invention relates to the technical field of chip stacking, and provides a multi-chip in-situ stacking structure, a stacking method and system thereof, and chips, the multi-chip in-situ stacking structure takes an FOW film as a single connection bonding medium to replace a traditional DAF bottom layer chip film, the multi-chip in-situ stacking structure structurally comprises a substrate and multiple layers of chips stacked in sequence, each layer of chip is electrically connected with the substrate through a lead, and the FOW film is used as a single connection bonding medium to replace the traditional DAF bottom layer chip film. And the FOW film is connected with the substrate or other chips, the FOW film is heated to allow the lead to pass through, and stable bonding is realized after curing. According to the technology, an FOW film is attached to the back face of the chip in advance, the chip is stacked in sequence after being scribed, heating and curing are carried out after each layer of chip is stacked, and then lead bonding is carried out. By adopting the single FOW film, the process control elements are reduced, the production process is simplified, the production efficiency of products is effectively improved, and meanwhile, the chip stacking stability and the electrical connection reliability are guaranteed.

Description

Technical Field

[0001] This invention relates to the field of chip stacking technology, and more specifically, to a multi-chip in-situ stacking structure and its stacking method, system, and chip. Background Technology

[0002] The content in this section only provides background information related to this invention and may not constitute prior art.

[0003] Currently, memory chips are rapidly developing towards higher capacity, higher speed, higher frequency, lower power consumption, and miniaturization. To package more chips in a smaller volume, three-dimensional stacked packaging is becoming increasingly widely used in memory chip packaging structures. Compared to traditional two-dimensional packaging, three-dimensional stacked packaging can not only effectively reduce package volume, improve substrate utilization efficiency and storage density, but also shorten wiring length and signal transmission paths, reduce system latency and chip power consumption, and has superior technical characteristics and economic benefits.

[0004] However, current 3D stacking technologies using wire interconnection mainly have five typical structures, all of which have significant drawbacks. Specifically, these include: pyramid-shaped stacking structures (such as...) Figure 8 (As shown) Due to the area reduction effect, the total number of stacked layers is limited, usually not exceeding 5 layers. Furthermore, the varying lengths of the upper and lower chip leads can easily lead to timing inconsistencies and unstable delays. Length balancing is required at the substrate design level, which is quite challenging. Product performance is also limited by the longest lead, making it difficult to fully utilize the chip's optimal performance. Staggered stacking structures (such as...) Figure 9 The footprint of a staggered stack (as shown) is typically 125% of the bottom chip area. As the number of stacked layers increases, the staggered area further expands, hindering product miniaturization. Furthermore, since the pads must be positioned at the chip edge, after staggered stacking, the pads are often suspended at the bottom, requiring extra care to control the soldering pressure during wire bonding to avoid potential damage. Staggered stacking structures (such as...) Figure 10 The footprint of the stacked chip (as shown) reaches 150% of the bottom chip's area. Because the length and width of the upper and lower chips change in a cross pattern, its footprint is larger than that of the staggered stacking. Furthermore, the substrate pads typically need to be arranged around the perimeter, placing extremely high demands on the substrate wiring, and it also suffers from the problem of pads being suspended. The overhead layer stacking structure (such as...) Figure 11 Although the footprint of the DAF+FOW film-type same-size stacked structure is the same as that of a single chip, an additional intermediate spacer layer is required between each chip layer in the vertical direction. This adds an extra spacer placement step to the process flow, resulting in a higher overall product thickness than other types and lower vertical space utilization, often making it unsuitable for stacking scenarios with more than three layers. Figure 12The footprint of the chip shown is the same as that of a single chip. The bottom chip uses a die attach film (DAF) as the bottom adhesive, while the second chip and the next chip use a flow on wire (FOW) back film for stacking. This structure requires at least two types of die attach adhesives and two die bonding processes when stacking multiple chips, which not only increases the difficulty of process control but also prolongs the production process.

[0005] Therefore, there is an urgent need for a multi-chip in-situ stacking structure, its stacking method, system, and chip to simplify the production process of multi-chip in-situ stacking and improve product production efficiency. Summary of the Invention

[0006] The purpose of this invention is to provide a multi-chip in-situ stacking structure, its stacking method, system, and chip to improve the aforementioned problems. To achieve the above objective, the technical solution adopted by this invention is as follows: In a first aspect, this application provides a multi-chip in-situ stacked structure, including: substrate; At least two layers of chips, or multiple layers of chips, are stacked sequentially on a substrate, with each layer of chips electrically interconnected to the substrate via leads; In this process, any chip is connected to other chips or substrates via a FOW film; the FOW film allows leads to pass through after heating, and after curing, it achieves bonding and fixation between chips or between chips and substrates.

[0007] Furthermore, the projections of each chip layer onto the substrate completely overlap to achieve stacking of the same size.

[0008] Furthermore, the heating temperature of the FOW membrane is 115~125℃.

[0009] Secondly, this application also provides a multi-chip in-situ stacking method for manufacturing a multi-chip in-situ stacking structure as described in the first aspect, the method comprising: S101: Obtain the first wafer, thin the first wafer until it meets the required stacking height, and attach a FOW film to the back of the first wafer; S102: Divide the first wafer with the FOW film attached to it to obtain multiple independent first chips with the FOW film attached to the back; S103: Place the first chip at the designated position on the substrate with the FOW film attached to its back side facing the substrate; S104: The first chip placed on the substrate is heated and cured to fix the first chip to the substrate through the FOW film; S105: Perform wire bonding on the cured first chip to form an electrical connection with the substrate; S106: Obtain the second chip, with a FOW film attached to its back; place the second chip with the FOW film attached to its back facing the first chip, preheat the second chip to 115°C to 125°C, so that the FOW film can penetrate the leads of the first chip, and stack it on the first chip; S107: The stacked second chip is heated and cured, so that the second chip is fixed to the first chip through the FOW film; S108: Wire bonding is performed on the cured second chip to form an electrical connection with the substrate; S109: Repeat steps S106 to S108 to continue stacking subsequent chips with FOW film attached to the back side on the second chip in the same way until the preset number of stacking layers is reached.

[0010] Furthermore, the step of placing the first chip at a designated position on the substrate with the FOW film attached to its back side facing the substrate specifically includes: The bonding pressure, vertical direction, and downward pressure height of the bonding head and substrate of the die bonding equipment are calibrated. The control bonding head picks up the first chip and raises it to a safe height; The bonding head, carrying the first chip, is controlled to descend from a safe altitude to a release altitude at a first speed. The bonding head is controlled to descend from the release height to the bonding height at a second speed, so that the FOW film on the back of the first chip contacts the substrate; At the mounting height, a preset bonding pressure is applied to the first chip and maintained for a preset contact time. At the same time, a weak air blow is used to break the vacuum adsorption of the bonding head on the first chip, so as to release the first chip onto the substrate. The bonding head is controlled to rise from the patch height to the release height at a second speed; The control bond head is raised from the release height to the safe height at the first speed.

[0011] Furthermore, the step of heating and curing the first chip placed on the substrate specifically includes: The heating device is controlled to heat the first chip and its back FOW film according to a preset curing temperature curve; The preset curing temperature curve includes a first heating stage, a first holding stage, a second heating stage, a second holding stage, and a cooling stage, performed sequentially. The first heating stage involves raising the temperature from the initial temperature to the first temperature at a first preset rate within a first preset time. The first holding stage involves maintaining the first temperature for a second preset time to release air bubbles. The second heating stage involves raising the temperature to the second temperature at a second preset rate within a third preset time. The second holding stage involves maintaining the second temperature for a fourth preset time. The cooling stage involves lowering the temperature to the initial temperature at a third preset rate within a fifth preset time.

[0012] Furthermore, the second preset time is determined by the time required for the bubbles to be completely expelled.

[0013] Thirdly, this application also provides a multi-chip in-situ stacking system, comprising: The first wafer mounting module is used to acquire the first wafer, thin the first wafer until it meets the required stacking height, and mount a FOW film on the back of the first wafer. The dicing module is used to dice the first wafer with the FOW film attached to it to obtain multiple independent first chips with the FOW film attached to the back. A placement module is used to place the first chip at a designated position on the substrate with the FOW film attached to its back side facing the substrate. The first heating and curing module is used to heat and cure the first chip placed on the substrate, so that the first chip is fixed to the substrate through the FOW film; The first bonding module is used to perform wire bonding on the cured first chip to form an electrical connection with the substrate; A stacking module is used to acquire a second chip, the back of which is attached with a FOW film; the second chip is then stacked on top of the first chip with the FOW film on its back facing the first chip; The second heat curing module is used to heat and cure the stacked second chip, so that the second chip is fixed to the first chip through the FOW film; The second bonding module is used to perform wire bonding on the cured second chip to form an electrical connection with the substrate; The circulation module is used to repeatedly stack the module, the second heating and curing module, and the second bonding module, and continue to stack subsequent chips with FOW film attached to the back on the second chip in the same way until the preset number of stacking layers is reached.

[0014] Fourthly, this application also provides a memory chip, including a multi-chip in-situ stacking structure as described in the first aspect to achieve double-layer or multi-layer stacking, wherein all chips are of the same type, and FOW film is used between adjacent chips and between chips and substrate during the stacking process.

[0015] The beneficial effects of this invention are: This invention uses a FOW (Field-Oriented Wood) film as the sole connection and bonding medium, replacing the traditional DAF (Digital Adhesive Film) bottom-layer chip film. Through specific structural design and process flow, it achieves efficient in-situ stacking of multilayer chips. The structure mainly consists of a substrate and multiple layers of chips stacked sequentially on it. Each chip layer is electrically interconnected with the substrate via leads, and any chip can be connected to other chips or the substrate via the FOW film. The FOW film allows leads to pass through after heating and provides stable bonding after curing, meeting the dual requirements of wire bonding and structural fixation during the stacking process. In the corresponding stacking process, a FOW film is pre-attached to the back of each chip. After dicing, the chips are stacked sequentially on the substrate or upper-layer chips with the FOW film facing the connection target. Each stacked chip layer undergoes a heat curing process, firmly fixing the chip to the substrate or upper-layer chips via the FOW film. After curing, wire bonding is used to achieve electrical interconnection between the chip and the substrate. Subsequent chips are stacked in the same manner until a preset number of layers is reached. The technical solution of using a single FOW film as the bottom bonding film and the middle lead layer also using FOW film eliminates the need for multiple different types of process materials, reduces the core elements of process control, effectively simplifies the production process of multi-chip in-situ stacking, and thus significantly improves the production efficiency of the product. At the same time, the characteristics of FOW film ensure the stability of chip stacking and the reliability of electrical connection. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a multi-chip in-situ stacked structure provided by the present invention; Figure 2 A flowchart of a multi-chip in-situ stacking method provided by the present invention; Figure 3 This is a flowchart illustrating the placement of the first chip at a designated position on the substrate in this invention. Figure 4 This is a curing curve of the FOW film on the first chip in this invention; Figure 5 This is a schematic diagram of the first chip mounting operation logic in this invention; Figure 6 This is a schematic diagram illustrating the stacking principle and process in this invention; Figure 7 This is a schematic diagram of a multi-chip in-situ stacking system provided by the present invention; Figure 8 This is a schematic diagram of a pyramid-shaped stacking structure in the prior art; Figure 9 This is a schematic diagram of a staggered stacking structure in the prior art; Figure 10 This is a schematic diagram of an interleaved stacking structure in the prior art; Figure 11 This is a schematic diagram of an overhead stacking structure in the prior art; Figure 12 This is a schematic diagram of a DAF+FOW membrane-type stacked structure of the same size in the prior art.

[0017] In the figure: 1. Substrate; 2. FOW film; 3. First chip; 4. Second chip; 5. Lead wire; 6. DAF film; 7. Multi-chip in-situ stacking system; 701. First wafer mounting module; 702. Dicing module; 703. Placement module; 704. First heat curing module; 705. First bonding module; 706. Stacking module; 707. Second heat curing module; 708. Second bonding module; 709. Cycling module. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Example 1 like Figure 1 As shown, an embodiment of the present invention proposes a multi-chip in-situ stacked structure, including a substrate 1 and at least two layers of chips. The multi-layer chips are stacked sequentially on the substrate 1, and each layer of chips is electrically interconnected with the substrate 1 through a lead 5. In this embodiment, any chip is connected to other chips or the substrate 1 through a FOW film 2. After heating, the FOW film 2 allows the lead 5 to pass through, and after curing, it achieves bonding and fixation between chips or between chips and the substrate 1.

[0020] Specifically, substrate 1 serves as the foundation and core support component of the entire stacking system. Its principle lies in having stable mechanical strength and precise wiring capabilities, providing a stable mounting reference surface for multilayer chips. At the same time, it serves as a key carrier for electrical interconnection, constructing a signal transmission channel between the chip and external circuits.

[0021] The configuration of at least two chip layers aligns with the trend of memory chips moving towards higher capacity. By vertically stacking multiple chip layers, more chips can be integrated without increasing the horizontal footprint, significantly improving storage density and meeting market demand for high-capacity storage products. The multiple chip layers are stacked sequentially on substrate 1, following the precise positioning logic of in-situ stacking. High-precision calibration and operation control of the die-bonding equipment ensure the coaxiality and flatness of each chip layer, providing a solid foundation for subsequent wire bonding and film curing. Each chip layer is electrically interconnected to substrate 1 via wires 5, using wires 5 as the medium for electrical signal transmission. Wire bonding technology ensures a reliable connection between the chip's pads and the corresponding pads on substrate 1, enabling electrical signal conduction between the chip and substrate 1. This multi-layer chip stacking design overcomes the capacity limitations of traditional two-dimensional packaging, achieving greater storage capacity in a smaller volume. The sequential stacking method ensures the compactness of the stacked structure, and the wire interconnection shortens wiring length, reducing signal attenuation and interference during transmission, ensuring the stability and consistency of signal transmission across each chip layer.

[0022] In this design, any chip is connected to other chips or substrate 1 via FOW film 2 (Flow on Wire, lead 5 through-film). The principle behind this is that FOW film 2, as a special wafer back-end adhesive film, possesses unique thermal response characteristics. It exhibits extremely low viscosity and strong fluidity within a temperature range of 115~125℃, and can cure and significantly enhance rigidity upon continuous temperature increases. Furthermore, this film layer can adapt to the connection requirements between chips and between chips and substrate 1, eliminating the need for additional types of adhesive films. This replaces the traditional dual-film approach where the bottom layer chip uses DAF film 6 (Die Attach Film) and the top layer chip uses FOW film 2. The bonding requirements for the entire stack can be met using only a single type of FOW film 2, reducing the types of process materials and control factors, and lowering unnecessary cost losses. The FOW film 2 allows the leads 5 to pass through after heating. This is based on the low viscosity and high fluidity of the FOW film 2 at a specific temperature. During the bonding process of the leads 5, the leads 5 can smoothly penetrate the FOW film 2 in this state, forming an effective connection with the substrate 1 without adversely affecting the subsequent curing of the film layer. After curing, the FOW film 2 achieves bonding and fixation between chips or between chips and the substrate 1. The principle is that after the FOW film 2 is heated and cured, the molecular structure undergoes a cross-linking reaction, significantly increasing its stiffness and forming a cured layer with high bonding strength. This layer can resist the mechanical stress generated during chip stacking, the thermal stress caused by temperature changes, and the external force influence in subsequent process operations, achieving a stable bonding and fixation effect. This effectively avoids problems such as chip misalignment and tilting after stacking, ensuring the long-term mechanical stability and dimensional accuracy of the stacked structure.

[0023] Furthermore, the projections of each chip layer on substrate 1 completely overlap to achieve same-size stacking. This is achieved through precise positioning and stacking processes, ensuring that the geometric center of each chip layer is coaxial with a preset reference point on substrate 1. This guarantees that each chip layer is horizontally aligned without offset or misalignment, resulting in a same-size layout where the stacked area and the single-chip area (S1) are identical. This solves the problem of excessive horizontal area occupation in traditional staggered stacking (typically occupying 125% of the bottom chip area) and interleaved stacking (typically occupying 150% of the bottom chip area), significantly improving product miniaturization and aligning with the trend of memory chip miniaturization. Simultaneously, the completely overlapping projection layout eliminates the need for pads on substrate 1 to be designed around the perimeter to avoid chip misalignment areas, reducing the wiring difficulty and design complexity of substrate 1 and improving its wiring flexibility and utilization. Moreover, this same-size stacking design avoids the low vertical space utilization problem caused by adding spacer layers in traditional overhead stacking, eliminating the need for additional vertical clearance and resulting in higher space utilization.

[0024] Example 2 like Figure 2 As shown, based on the same inventive concept, this embodiment provides a multi-chip in-situ stacking method for manufacturing a multi-chip in-situ stacked structure as described in Embodiment 1. The stacking principle and process are as follows: Figure 6 As shown, the method specifically includes: S101: Obtain the first wafer, thin the first wafer until it meets the required stacking height, and attach FOW film 2 to the back of the first wafer.

[0025] Specifically, the first wafer is the basic substrate for fabricating the first chip 3. As the carrier of the chip, it possesses the core semiconductor structure required for chip fabrication and can provide the original blank for the subsequent molding of the first chip 3. The first wafer is thinned until it meets the required stacking height. The principle behind this is that multiple chips need to be stacked sequentially in the vertical direction. If the thickness of the first wafer is too large, the overall vertical height of the stacked chips will be too high, which will not meet the miniaturization requirements of the product. It will also affect the coaxiality and flatness of each chip layer and will not be conducive to the implementation of the subsequent bonding process of the lead 5. Therefore, the thickness of the thinning process needs to be precisely controlled to adapt to the process requirements of in-situ stacking. Then, FOW film 2 is mounted on the back of the first wafer. The principle is that FOW film 2 is a special back-mounted adhesive film for wafers with unique thermal response characteristics. After heating, it allows the lead wire 5 to pass through, and after curing, it enables bonding and fixation between chips or between chips and substrate 1. It can also adapt to the connection requirements between chips and substrate 1 without the need to use other types of adhesive films. By pre-mounting FOW film 2 on the back of the first wafer, the first chip 3 after subsequent dicing can directly have the basis for bonding with substrate 1. This replaces the traditional dual-film combination mode in which the bottom chip uses DAF film 6 and the top chip uses FOW film 2. The bonding requirements between the bottom chip and substrate 1 can be completed with only a single type of FOW film 2, reducing the types of process materials and control factors, and reducing unnecessary cost losses.

[0026] S102: Divide the first wafer with FOW film 2 attached to it to obtain multiple independent first chips 3 with FOW film 2 attached to their back sides.

[0027] Specifically, the first wafer is initially in a monolithic wafer form and cannot be directly used for stacking individual chips in a multi-chip in-situ stacking process. It needs to be divided into multiple independent chip units, i.e., first chips 3, by a dicing process. The dicing process can divide the first wafer with FOW film 2 into multiple independent chip units, i.e., first chips 3, according to the preset chip size dicing path. Since FOW film 2 has been pre-attached to the back of the first wafer, the FOW film 2 on the back of the first wafer will be divided accordingly during the dicing process. This ensures that the back of each independent first chip 3 formed after division can be completely attached with FOW film 2, ensuring that each first chip 3 has the adhesive medium foundation required to connect with the subsequent substrate 1 or upper layer chips. This process is consistent with the design logic of FOW film 2 as a single adhesive film to replace the traditional dual-film combination mode mentioned above, ensuring the continuity and uniformity of the process.

[0028] S103: Place the first chip 3 with the FOW film 2 attached to its back facing the substrate 1 at the designated position on the substrate 1; Specifically, such as Figure 3 As shown, the placement process specifically includes the following steps: S201 calibrates the bonding pressure, vertical direction, and pressing height of the bonding head and substrate 1 of the die bonding equipment. The principle is that the bonding head of the die bonding equipment is the core component for picking up and placing the first chip 3. The bonding pressure, vertical direction, and pressing height of the substrate 1 directly affect the flatness, coaxiality, and initial contact state between the first chip 3 and the FOW film 2 and the substrate 1. Calibration eliminates the mechanical errors and positioning deviations of the die bonding equipment itself, ensuring that the movement trajectory of the bonding head, the applied bonding pressure, and all height parameters meet the precise requirements of multi-chip in-situ stacking. This ensures the accuracy of the operating parameters of the die bonding equipment, providing equipment-level support for the precise picking up and stable placement of the first chip 3, and preventing the first chip 3 from shifting or tilting, or uneven contact between the FOW film 2 and the substrate 1, due to deviations in equipment parameters.

[0029] S202, control the bonding head to pick up the first chip 3 and raise the first chip 3 to a safe height. The principle is that the bonding head can reliably pick up the first chip 3 through vacuum adsorption, which can prevent the first chip 3 from falling off or being damaged during the picking process. The safe height is a preset height higher than the substrate 1 and other components of the equipment. This height setting can avoid collisions between the bonding head and the substrate 1 or other components of the equipment during the movement of the first chip 3, thereby causing damage to the first chip 3, the substrate 1 or the equipment components.

[0030] S203, the control bonding head carrying the first chip 3 descends from a safe altitude to a release altitude at a first speed. The principle behind this is that the first speed is a preset, relatively fast descent speed (i.e.,...). Figure 5 The rapid descent phase (in the process) utilizes this speed to improve process efficiency and reduce the overall stacking process time; the slow-release height is a transition height between the safety height and the placement height. Setting this transition height buffers the bonding head from rapid descent to slow descent, preventing excessive impact force on the bonding head due to a direct rapid descent to the placement height, which could damage the first chip 3 or cause unnecessary deformation of the FOW film 2. While ensuring process efficiency, a smooth transition during the descent process is achieved, reducing the impact force on the first chip 3 and FOW film 2, ensuring the structural integrity of the first chip 3 and FOW film 2, and preventing component damage from affecting subsequent processes.

[0031] S204, the bonding head is controlled to descend from the release height to the bonding height at a second speed, so that the FOW film 2 on the back of the first chip 3 contacts the substrate 1. The principle is that the second speed is a preset, relatively slow descent speed (i.e., Figure 5The first chip 3 is placed stably at a designated position on the substrate 1. The second speed is lower than the first speed. This speed allows for precise control of the descent accuracy of the bonding head, ensuring that the first chip 3 can be placed stably at the designated position on the substrate 1. The mounting height is a preset height that makes the FOW film 2 on the back of the first chip 3 just contact the surface of the substrate 1. This height setting ensures that the FOW film 2 and the substrate 1 form effective contact, providing a basis for subsequent heat curing, and also avoids applying excessive pressure, which could cause the FOW film 2 to deform prematurely and affect the subsequent bonding effect, thereby achieving the stable placement of the first chip 3.

[0032] S205, at the bonding height, a preset bonding pressure is applied to the first chip 3 and a preset contact time is maintained. At the same time, a weak air blowing is used to break the vacuum adsorption of the bonding head on the first chip 3, so as to release the first chip 3 onto the substrate 1. The principle is that the preset bonding pressure is a reasonable pressure value determined by experiments. This pressure can make the FOW film 2 and the substrate 1 form a tight contact without damaging the first chip 3 and the FOW film 2. Maintaining the preset contact time can make sufficient contact between the FOW film 2 and the substrate 1, expelling the air between the contact surfaces and avoiding the generation of air bubbles due to air residue during the subsequent heating and curing process, which would affect the bonding strength of the FOW film 2. The pressure of the weak air blowing is controlled within the range that does not damage the first chip 3 and can effectively break the vacuum adsorption. By breaking the vacuum adsorption state between the bonding head and the first chip 3, the first chip 3 can be smoothly released and attached to the designated position on the substrate 1, avoiding the first chip 3 from shifting during the release process. Its beneficial effects are to further ensure the tightness of the contact between the FOW film 2 and the substrate 1, reduce the air residue on the contact surface, reduce the probability of air bubbles generated after subsequent heating and curing, and improve the bonding reliability; at the same time, it can achieve the smooth release of the first chip 3, ensuring that the first chip 3 can still remain in the designated position on the substrate 1 after release, and avoid the effect of accurate positioning in the early stage due to the displacement during the release process.

[0033] S206, control the bonding head to rise from the patch height to the release height at a second speed (e.g., ... Figure 5 The principle behind the slow lifting of the bonding head (from the bonding height) is that the slow lifting at the second speed avoids airflow disturbances or mechanical impacts during the lifting process, preventing the first chip 3, which has just been released from the substrate 1, from shifting or tilting, and ensuring that the first chip 3 can be stably bonded to the designated position on the substrate 1. The slow-release height serves as a transition height, allowing the bonding head to smoothly transition from the bonding height to a safe height, avoiding instability caused by rapid lifting. This ensures that the first chip 3 can be stably bonded to the designated position on the substrate 1 after release, preventing the first chip 3 from shifting due to interference caused by the lifting of the bonding head.

[0034] S207, control the keyway head to rise from the release height to the safe height at a first speed (e.g., ... Figure 5The principle behind the rapid return to a safe height is that the relatively fast initial lift can improve the reset efficiency of the bonding head, reduce the processing time, and improve the overall stacking efficiency. After the bonding head is reset to a safe height, it can move away from the substrate 1 and the first chip 3, avoiding interference with the heating and curing process in the subsequent step S104, and preparing for the subsequent picking and placing of other first chips 3.

[0035] Specifically, the parameters corresponding to the placement steps are shown in Table 1 below: Table 1 S104: The first chip 3 placed on the substrate 1 is heated and cured so that the first chip 3 is fixed to the substrate 1 through the FOW film 2.

[0036] Specifically, the heating device is controlled according to a preset curing temperature curve, such as... Figure 4 As shown, the first chip 3 and its back FOW film 2 are heated. The principle is that the preset curing temperature curve is designed for the thermal response characteristics and curing reaction law of the FOW film 2. The heating device provides a stable energy input for the implementation of the temperature curve and can accurately control the temperature change during the heating process. Through the cooperation of the heating device and the preset curing temperature curve, the curing reaction of the FOW film 2 is ensured to proceed in an orderly manner according to the preset path, avoiding insufficient curing or abnormal performance of the FOW film 2 due to uncontrolled heating parameters, and ensuring the consistency of the curing effect.

[0037] The preset curing temperature profile includes a first heating stage performed sequentially (i.e., Figure 4 The slow heating phase), the first heat preservation phase (i.e.) Figure 4 (medium-stage slow-release emission), the second heating stage (i.e., Figure 4 The rapid heating phase and the second heat preservation phase (i.e.) Figure 4 Intermediate curing insulation) and cooling stage (i.e. Figure 4 The principle of cooling in the furnace is that the curing process of FOW film 2 requires a gradual change in temperature and a physical and chemical transformation. The staged temperature control can adapt to the transformation requirements of FOW film 2 from the initial state to the flow state and then to the cured state. Each stage is connected in sequence to form a complete curing process. It avoids curing defects caused by single temperature or continuous temperature rise, and provides process guarantee for the full curing of FOW film 2, the removal of air bubbles, and the improvement of bonding strength, so as to ensure that the performance of FOW film 2 after curing meets the stacking requirements.

[0038] The first heating stage involves raising the temperature from the initial temperature to a first temperature (85°C) at a first preset rate within a first preset time. The principle behind this is that the first preset rate and time are determined based on the thermal conductivity and initial state of the FOW film 2. This avoids excessively rapid heating that could cause uneven local temperatures in the FOW film 2, while simultaneously achieving rapid temperature increases to improve process efficiency. It also ensures that the FOW film 2, the first chip 3, and the substrate 1 are heated synchronously, guaranteeing a uniform overall temperature distribution across the film layer. This creates conditions for bubble release during the subsequent heat preservation stage, preventing inconsistent curing results due to localized temperature differences. The first heat preservation stage involves maintaining the first temperature for a second preset time (30 minutes) to release bubbles. The principle behind this is that the first temperature is the temperature at which residual air between the FOW film 2 and the substrate 1 forms bubbles and overflows. The second preset time is determined by the time required for complete bubble expulsion, ensuring sufficient air removal between the contact surfaces. This effectively reduces voids and residual bubbles between the FOW film 2 and the substrate 1, improving the contact tightness between them and preventing insufficient bonding strength or bonding failure during subsequent use due to bubbles. The second heating stage involves increasing the temperature to the second temperature (175 degrees Celsius) at a second preset rate within a third preset time. The principle behind this is that the second preset rate is adapted to the state of the FOW film 2 after the first heat treatment, gradually increasing the temperature to the critical response temperature of the FOW film 2. This allows the FOW film 2 to flow fully, filling any tiny gaps that may exist between the first chip 3 and the substrate 1, further optimizing the adhesion between the film layer and the contact surface, and laying the foundation for high bonding strength after subsequent curing. The second heat treatment stage involves maintaining the second temperature for a fourth preset time (120 minutes). The principle behind this is that the fluidity and reactivity of the FOW film 2 are at an appropriate level at the second temperature. The fourth preset time is the time required to ensure that the FOW film 2 completes the full curing reaction, allowing the molecular structure of the film layer to fully cross-link; achieving complete curing of the FOW film 2, significantly enhancing the rigidity and bonding strength of the film layer, ensuring long-term stable bonding between the first chip 3 and the substrate 1, and resisting the influence of external forces in subsequent processes. The cooling stage involves reducing the temperature to the initial temperature at a third preset rate within a fifth preset time period. The principle behind this is that the third preset rate is determined based on the thermal stability of the cured FOW film 2 and the thermal expansion and contraction characteristics of the first chip 3 and the substrate 1. This avoids excessively rapid cooling, which could cause internal stress between the film layer and the chip / substrate 1 due to differences in thermal expansion and contraction. It also reduces the internal stress between the cured FOW film 2 and the first chip 3 and the substrate 1, preventing the film layer from cracking or the adhesion from loosening, ensuring the dimensional accuracy and mechanical stability of the stacked structure, and providing a good structural foundation for the subsequent lead bonding process.

[0039] S105: The first chip 3 after curing is bonded with wires 5 to form an electrical connection with the substrate 1.

[0040] Specifically, after the first chip 3 is heated and cured by the FOW film 2, the FOW film 2 forms a high-rigidity cured layer, which enables the first chip 3 to be mechanically fixed to the substrate 1, and obtains a flat and stable bonding reference surface. This reference surface can resist the mechanical stress applied during the bonding process of the lead wire 5, and prevent the first chip 3 from shifting or tilting during the bonding operation. The lead wire 5 bonding process is the core implementation method of lead wire 5 interconnection. It relies on a dedicated bonding equipment to reliably connect the lead wire 5 to the pads of the first chip 3 and the corresponding pads of the substrate 1. The lead wire 5 serves as a medium for electrical signal transmission. Its material and structure are adapted to the signal transmission requirements between the chip and the substrate 1, and can realize the effective conduction of electrical signals, thereby forming an electrical connection with the substrate 1.

[0041] S106: Obtain the second chip 4, with FOW film 2 attached to the back of the second chip 4; align the second chip 4 with the FOW film 2 attached to its back facing the first chip 3, and preheat the second chip 4 to 115°C to 125°C, so that the FOW film 2 can penetrate the leads of the first chip 3 and be stacked on the first chip 3.

[0042] Specifically, the second chip 4, although it also has a FOW film 2 attached to its back (the material and characteristics of the FOW film 2 attached to the first chip 3 are the same), the core difference between it and the first chip 3 is that the second chip 4 does not need to go through the wafer thinning and dicing process corresponding to the first chip 3. It is directly used for stacking in the form of a finished chip with a FOW film 2 attached to its back. The core purpose of attaching the FOW film 2 is to adapt to the bonding requirements of the lower first chip 3, rather than to the bonding with the substrate 1 (the core purpose of attaching the FOW film 2 to the first chip 3 is to bond with the substrate 1).

[0043] Unlike the operation of placing the first chip 3 with the FOW film 2 facing the substrate 1, the second chip 4 needs to place the FOW film 2 attached to its back side facing the first chip 3 and stack it on the first chip 3, which has been cured and bonded with the leads 5. The stacking of the second chip 4 is used to expand the number of chip layers in the vertical direction (the stacking of the first chip 3 is used to build the underlying foundation), further improving the storage density. Its stacking positioning needs to meet the requirement of stacking of the same size with the projection of each chip layer completely overlapping. It uses the first chip 3 as the reference to achieve precise positioning, rather than using the substrate 1 as the reference. At the same time, it provides a basis for subsequent curing and bonding with the chip and bonding with its own leads 5. It continues the bonding logic of the single FOW film 2 and does not require the addition of other bonding films.

[0044] S107: The stacked second chip 4 is heated and cured so that the second chip 4 is fixed to the first chip 3 through the FOW film 2.

[0045] Specifically, during the heating process, when the temperature first rises to the range of 115~125℃, the FOW film 2 exhibits extremely low viscosity and extremely strong fluidity, which can fully fill the tiny gap between the second chip 4 and the first chip 3 and expel the air remaining between the contact surfaces; after the temperature continues to rise, the FOW film 2 undergoes a molecular structure cross-linking reaction, its stiffness is significantly enhanced, and the curing transformation is completed.

[0046] S108: The cured second chip 4 is bonded with wires 5 to form an electrical connection with the substrate 1. Specifically, after being cured by heat, the second chip 4 is firmly fixed to the lower first chip 3 by the FOW film 2. Its bonding reference surface is provided by the cured connection structure between the first chip 3 and the second chip 4, rather than directly relying on the substrate 1. During the wire bonding process, the second chip 4 leads out wires 5 from above and directly connects to the substrate 1 to realize the conduction of electrical signals.

[0047] S109: Repeat steps S106 to S108, continuing to stack subsequent chips with FOW film 2 attached to the back side on the second chip 4 in the same manner until the preset number of stacked layers is reached. Specifically, continuing the single FOW film 2 bonding logic, in-situ precise stacking logic, and lead wire 5 interconnection logic established above, relying on the already established underlying chip stacking foundation, through standardized and repetitive process operations, the orderly stacking of multiple layers of chips is achieved, thereby meeting the preset storage capacity and structural requirements.

[0048] Example 3 like Figure 7 As shown, based on the same inventive concept, this embodiment provides a multi-chip in-situ stacking system 7, including: The first wafer mounting module 701 is used to acquire the first wafer, thin the first wafer until it meets the required stacking height, and mount the FOW film 2 on the back of the first wafer; The dicing module 702 is used to dice the first wafer on which the FOW film 2 is mounted to obtain multiple independent first chips 3 with the FOW film 2 attached to their back sides; The placement module 703 is used to place the first chip 3 with the FOW film 2 attached to its back side facing the substrate 1 at a designated position on the substrate 1; The first heating and curing module 704 is used to heat and cure the first chip 3 placed on the substrate 1, so that the first chip 3 is fixed to the substrate 1 through the FOW film 2; The first bonding module 705 is used to bond the cured first chip 3 with wires 5 to form an electrical connection with the substrate 1; The stacking module 706 is used to obtain the second chip 4, the back of which is attached with a FOW film 2; and to stack the second chip 4 on the first chip 3 with the FOW film 2 attached to its back facing the first chip 3. The second heat curing module 707 is used to heat and cure the stacked second chip 4, so that the second chip 4 is fixed to the first chip 3 through the FOW film 2; The second bonding module 708 is used to bond the cured second chip 4 with wires 5 to form an electrical connection with the substrate 1; The circulation module 709 is used to repeatedly stack the stacking module, the second heating curing module, and the second bonding module, and continue to stack subsequent chips with FOW film 2 attached to the back side on the second chip 4 in the same way until the preset number of stacking layers is reached.

[0049] Based on the same inventive concept, this embodiment provides a memory chip that uses the multi-chip in-situ stacking structure in Embodiment 1 to achieve double-layer or multi-layer stacking, wherein all chips are of the same model, and FOW film 2 is used between adjacent chips and between chips and substrate during the stacking process.

[0050] It should be noted that the specific methods by which each module performs operations in the system described in the above embodiments have been described in detail in the embodiments related to the method, and will not be elaborated here.

[0051] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A multi-chip in-situ stacked structure, characterized in that... ,include: substrate; At least two layers of chips, and multiple layers of the chips are stacked sequentially on the substrate, with each layer of chips electrically interconnected to the substrate via leads; In this embodiment, any one of the chips is connected to other chips or the substrate via a FOW film; the FOW film allows leads to pass through after heating, and achieves bonding and fixation between chips or between chips and the substrate after curing.

2. The multi-chip in-situ stacking structure according to claim 1, characterized in that... The projections of the chips in each layer onto the substrate completely overlap to achieve stacking of the same size.

3. The multi-chip in-situ stacking structure according to claim 1, characterized in that... The heating temperature of the FOW film is 115~125℃.

4. A method for in-situ stacking of multiple chips, characterized in that... The method for manufacturing a multi-chip in-situ stacked structure as described in any one of claims 1 to 3, the method comprising: S101: Obtain the first wafer, thin the first wafer until it meets the required stacking height, and attach a FOW film to the back of the first wafer; S102: The first wafer with the FOW film attached is diced to obtain multiple independent first chips with the FOW film attached to the back; S103: Place the first chip at a designated position on the substrate with the FOW film attached to its back side facing the substrate; S104: The first chip placed on the substrate is heated and cured to fix the first chip to the substrate through the FOW film; S105: Perform wire bonding on the cured first chip to form an electrical connection with the substrate; S106: Obtain a second chip with a FOW film attached to its back side; preheat the second chip to 115°C to 125°C with the FOW film on its back side facing the first chip, so that the FOW film can penetrate the leads of the first chip and be stacked on the first chip; S107: The stacked second chip is heated and cured to fix the second chip onto the first chip through the FOW film; S108: Wire bonding is performed on the cured second chip to form an electrical connection with the substrate; S109: Repeat steps S106 to S108 to continue stacking subsequent chips with FOW film attached to the back side on the second chip in the same way until the preset number of stacking layers is reached.

5. A multi-chip in-situ stacking method according to claim 4, characterized in that... The step of placing the first chip at a designated position on the substrate with the FOW film attached to its back side facing the substrate specifically includes: The bonding pressure, vertical direction, and downward pressure height of the bonding head of the die bonding equipment and the substrate are calibrated. The bonding head is controlled to pick up the first chip and raise it to a safe height. The bonding head is controlled to descend from the safe height to the release height at a first speed, carrying the first chip; The bonding head is controlled to descend from the release height to the bonding height at a second speed, so that the FOW film on the back of the first chip contacts the substrate; At the patch height, a preset bonding pressure is applied to the first chip and maintained for a preset contact time. At the same time, a weak air blow is used to break the vacuum adsorption of the bonding head on the first chip, so as to release the first chip onto the substrate. The bonding head is controlled to rise from the patch height to the release height at a second speed; The bonding head is controlled to rise from the release height to the safety height at a first speed.

6. A multi-chip in-situ stacking method according to any one of claims 4 or 5, characterized in that... The step of heating and curing the first chip placed on the substrate specifically includes: The heating device is controlled to heat the first chip and its back FOW film according to a preset curing temperature curve; The preset curing temperature curve includes a first heating stage, a first holding stage, a second heating stage, a second holding stage, and a cooling stage performed sequentially. The first heating stage involves raising the temperature from the initial temperature to the first temperature at a first preset rate within a first preset time. The first holding stage involves maintaining the first temperature for a second preset time to release air bubbles. The second heating stage involves raising the temperature to the second temperature at a second preset rate within a third preset time. The second holding stage involves maintaining the second temperature for a fourth preset time. The cooling stage involves lowering the temperature to the initial temperature at a third preset rate within a fifth preset time.

7. A multi-chip in-situ stacking method according to claim 6, characterized in that... The second preset time is determined by the time it takes for the bubbles to be completely expelled.

8. A multi-chip in-situ stacking system, characterized in that... The system includes: The first wafer mounting module is used to acquire the first wafer, thin the first wafer until it meets the required stacking height, and mount a FOW film on the back of the first wafer; The dicing module is used to dice the first wafer with the FOW film attached to it to obtain multiple independent first chips with the FOW film attached to the back. A placement module is used to place the first chip at a designated position on the substrate with the FOW film attached to its back side facing the substrate. The first heat curing module is used to heat and cure the first chip placed on the substrate, so that the first chip is fixed to the substrate through the FOW film; The first bonding module is used to perform wire bonding on the cured first chip to form an electrical connection with the substrate; A stacking module is used to acquire a second chip, the back of which is attached with a FOW film; the second chip is then stacked on top of the first chip with the FOW film on its back facing the first chip; The second heat curing module is used to heat and cure the stacked second chips, so that the second chips are fixed to the first chips through the FOW film; The second bonding module is used to perform wire bonding on the cured second chip to form an electrical connection with the substrate; The circulation module is used to repeat the stacking module, the second heat curing module and the second bonding module to continue stacking subsequent chips with FOW film attached to the back side on the second chip in the same way until the preset number of stacking layers is reached.

9. A memory chip, characterized in that... The multi-chip in-situ stacking structure described in claim 1 or 2 is used to achieve double-layer or multi-layer stacking, wherein all chips are of the same type, and FOW film is used between adjacent chips and between chips and substrate during the stacking process.

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