Double-sided PCB optimized structure based on local pin header connection and manufacturing method thereof

Abstract

The invention relates to the technical field of PCB manufacturing, and discloses a double-sided PCB optimized structure based on local pin header connection and a manufacturing method thereof, and the method comprises the steps: carrying out the partition circuit design of a double-sided PCB substrate, and obtaining a circuit layout of the double-sided PCB substrate; drilling the double-sided PCB substrate to obtain a target PCB substrate; the method comprises the following steps of: pressing a brass conductive needle into a needle position hole of an insulating base to manufacture a pin header connecting assembly, inserting the pin header connecting assembly into a mechanical through hole of a target PCB substrate to obtain a preassembly body, and performing wave soldering to obtain a double-sided PCB finished product. The interconnection nodes of the top layer and the bottom layer of the double-sided PCB are divided into a pin header connecting area and a signal transmission area; and only the via holes in the signal transmission area are metalized, so that the number of the via holes needing three high-cost processes of glue residue removal, chemical copper deposition and copper electroplating is reduced, the consumption of copper electroplating materials and the consumption of chemical liquid medicine are reduced, and meanwhile, the production period is shortened.

Description

Technical Field

[0001] This invention relates to the field of PCB manufacturing technology, and in particular to an optimized double-sided PCB structure based on local pin header connections and its manufacturing method. Background Technology

[0002] As the core carrier of electronic products, the cost and reliability of printed circuit boards (PCBs) directly affect the market competitiveness of consumer electronics. Double-sided PCBs, due to their simple structure and wide application, have long been the mainstream choice for low- to mid-range electronic products. However, with increasingly stringent requirements for product cost control, the inherent high-cost structural problems in traditional double-sided PCB manufacturing processes are becoming increasingly prominent, necessitating breakthroughs at the process route level.

[0003] Traditional double-sided PCBs use plated vias (PTH) to interconnect the top and bottom layers. This process requires multiple costly steps, including drilling, desmearing, chemical copper plating, and electroplating, for all interconnect nodes. Drilling accounts for a significant portion of the production cycle time, electroplating consumes a large proportion of the material cost, and the chemical copper plating process generates a large amount of wastewater containing heavy metals, further increasing treatment costs. When the via density is high, the risk of board warping and short circuits increases, limiting overall production yield. Existing alternatives all have significant limitations: jumper soldering is labor-intensive and inconsistent; conductive adhesive connections have unstable contact resistance; and flexible circuit transitions add extra costs. Current technologies cannot effectively reduce manufacturing costs while ensuring the electrical reliability of interlayer interconnects. Therefore, it is necessary to propose a new double-sided PCB interconnection method to solve these problems. Summary of the Invention

[0004] This invention provides an optimized double-sided PCB structure and its manufacturing method based on local pin header connections. By dividing the top and bottom interconnection nodes of the double-sided PCB into a pin header connection area and a signal transmission area, and performing PTH metallization on the vias in the signal transmission area, this invention reduces the number of vias that need to undergo three high-cost processes: desmearing, chemical copper plating, and electroplating. This reduces the consumption of electroplating copper materials and chemical solutions, while also shortening the production cycle.

[0005] In a first aspect, the present invention provides a method for manufacturing a double-sided PCB based on partial pin header connections, the method comprising: The circuit layout of the double-sided PCB substrate is obtained by partitioning the circuit board. Based on the circuit layout, holes are drilled in the double-sided PCB substrate, and only the vias in the signal transmission area are subjected to desmearing, chemical copper plating and electroplating to obtain the target PCB substrate. A pin header connection assembly is made by pressing brass conductive pins into the pin holes of an insulating base, and the pin header connection assembly is inserted into the mechanical through holes of the target PCB substrate to obtain a pre-assembled body. Wave soldering is performed on the pre-assembled assembly to obtain a double-sided PCB finished product.

[0006] In conjunction with the first aspect, in a first implementation of the first aspect of the present invention, the step of performing partitioned circuit design on the double-sided PCB substrate to obtain the circuit layout of the double-sided PCB substrate includes: The top and bottom interconnect nodes of the pin header connection area in the double-sided PCB substrate are arranged in an array to obtain the pin header connection area hole layout. Based on the pin header connection area hole layout, power lines and ground lines are routed together in the pin header connection area, signal lines are routed in the signal transmission area, and via holes for PTH metallization are planned at each interconnect node in the signal transmission area to obtain the circuit layout of the double-sided PCB substrate.

[0007] In conjunction with the first aspect, in a second implementation of the first aspect of the present invention, the step of arraying the top and bottom interconnect nodes of the pin header connection area in the double-sided PCB substrate to obtain the pin header connection area hole layout includes: Arrange the top and bottom interconnect nodes in the pin connection area of ​​the double-sided PCB substrate in an array according to the standard pin spacing, and determine the center position of the top and bottom pads at each interconnect node. Based on the center position of the pad, the mechanical via diameter and pin header pad size that match the conductive pin diameter are planned at each interconnect node to obtain the pin header connection area hole layout.

[0008] In conjunction with the first aspect, in a third implementation of the first aspect of the present invention, the step of drilling holes in the double-sided PCB substrate based on the circuit layout, and performing desmearing, chemical copper plating, and electroplating copper treatment only on the vias within the signal transmission area to obtain the target PCB substrate, includes: Based on the circuit layout of the double-sided PCB substrate, holes are drilled in the pin header connection area and the signal transmission area of ​​the double-sided PCB substrate to obtain mechanical through holes in the pin header connection area and holes to be plated in the signal transmission area. The signal transmission area to be plated is sequentially subjected to desmearing, chemical copper plating, and electroplating copper treatments to form a metallized copper layer on the hole wall, thereby obtaining the target PCB substrate.

[0009] In conjunction with the first aspect, in a fourth implementation of the first aspect of the present invention, the step of sequentially performing desmearing, chemical copper plating, and electroplating copper treatments on the signal transmission area to be plated holes, thereby forming a metallized copper layer on the hole walls of the signal transmission area to be plated holes, to obtain the target PCB substrate, includes: The signal transmission area hole wall to be plated is treated with a descaling agent to remove adhesive residue, resulting in a signal transmission area hole with exposed copper ring on the hole wall. The signal transmission area to be plated, with exposed copper rings on the hole wall, is subjected to chemical copper deposition and electroplating in sequence. This process first deposits a chemical copper layer on the hole wall, and then electroplats a copper layer on the surface of the chemical copper layer to obtain the target PCB substrate. The pin header connection area of ​​the target PCB substrate contains mechanical through-holes, and the signal transmission area contains metallized vias.

[0010] In conjunction with the first aspect, in a fifth implementation of the first aspect of the present invention, the step of pressing brass conductive pins into the pin holes of an insulating base to form a pin header connection assembly, and inserting the pin header connection assembly into a mechanical through-hole of the target PCB substrate to obtain a pre-assembled body, includes: The surface of the brass conductive pins is sequentially plated with nickel and then with gold. The surface-treated brass conductive pins are then pressed one by one into the pin holes of the insulating base to obtain the pin header connection assembly. Align each conductive pin of the pin header connection assembly with each mechanical through hole in the pin header connection area of ​​the target PCB substrate, and insert the conductive pin into the mechanical through hole until the bottom surface of the insulating base is in close contact with the top surface of the target PCB substrate and the bottom end of the conductive pin extends out from the bottom layer of the target PCB substrate to obtain a pre-assembled body.

[0011] In conjunction with the first aspect, in the sixth implementation of the first aspect of the present invention, the surface of the brass conductive pins is sequentially subjected to nickel plating and gold plating, and then the surface-treated brass conductive pins are pressed one by one into the pin holes of the insulating base to obtain a pin header connection assembly, comprising: Nickel plating and gold plating are performed sequentially on the surface of the brass conductive needle to form a nickel layer as a barrier layer and a gold layer as a conductive surface layer on the outside of the nickel layer, resulting in a nickel-gold plated brass conductive needle. The nickel-gold plated brass conductive pins are pressed one by one into the pin holes of the insulating base, so that the outer wall of the nickel-gold plated brass conductive pins forms an interference fit with the hole wall of the insulating base, thus obtaining the pin header connection assembly.

[0012] In conjunction with the first aspect, in the seventh implementation of the first aspect of the present invention, the step of performing wave soldering on the pre-assembled body to obtain a double-sided PCB finished product includes: The pre-assembled body is wave-welded sequentially according to the preheating zone temperature, the peak temperature of the reflow zone, and the cooling rate to obtain a welded body. Online testing of contact resistance and insulation resistance is performed on each solder joint in the pin connection area of ​​the welded body to confirm that the solder connection between the conductive pin body and the top and bottom pads meets the electrical conductivity requirements, thus obtaining a double-sided PCB product.

[0013] In conjunction with the first aspect, in the eighth implementation of the first aspect of the present invention, the online detection of contact resistance and insulation resistance of each solder joint in the pin connection area of ​​the solder body to confirm that the solder connection between the conductive pin body and the top and bottom pads meets the electrical conductivity requirements, thereby obtaining a double-sided PCB finished product, includes: Contact resistance detection is performed sequentially on the solder connection points between each conductive pin body and the top and bottom pads in the solder body pin connection area to obtain the contact resistance value of each solder point. Based on the contact resistance value of each solder joint, insulation resistance testing is performed between adjacent conductive pins in the pin header connection area of ​​the solder body to confirm that the solder connection between the conductive pin and the top and bottom pads meets the electrical conductivity requirements, thus obtaining a double-sided PCB product with the conductive pin as the electrical path between the top and bottom layers of the pin header connection area.

[0014] Secondly, the present invention provides an optimized double-sided PCB structure based on local pin header connections, wherein the optimized double-sided PCB structure based on local pin header connections is manufactured using a double-sided PCB manufacturing method based on local pin header connections.

[0015] The technical solution provided by this invention divides the top and bottom interconnect nodes of a double-sided PCB into a pin header connection area and a signal transmission area. PTH metallization is performed only on vias within the signal transmission area, reducing the number of vias requiring three high-cost processes: desmearing, chemical copper plating, and electroplating. This reduces the consumption of electroplating copper materials and chemicals, while also shortening the production cycle. For the pin header connection area, this invention uses brass conductive pins that penetrate the PCB board and are wave soldered to the top and bottom pads to form solder connections. The conductive pin body directly serves as the electrical path between the top and bottom layers of the pin header connection area, completely replacing the reliance on the PTH hole wall electroplated copper layer in this area. This eliminates the need for a drilling metallization process in the pin header connection area from a process route perspective. Because the conductive cross-sectional area of ​​the conductive pin body is much larger than the effective conductive cross-section of the traditional PTH hole wall electroplated copper layer, the conductivity reliability of the interlayer electrical path in the pin header connection area is improved, resulting in lower contact resistance and better stability. Furthermore, the mechanical through-holes in the pin header connection area eliminate the need to control precise hole diameter tolerances and hole wall roughness, significantly improving drilling yield compared to traditional small-diameter PTH processes, thus increasing overall production yield. The insulating base, made of high-temperature resistant PA6T material, maintains structural stability at wave soldering peak temperatures, ensuring the positional accuracy of the pin header array. This allows the assembly and soldering of the pin header connection components to be completed in the same wave soldering process as other through-hole components, eliminating the need for dedicated soldering steps and simplifying the overall production flow.

[0016] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of an embodiment of the double-sided PCB manufacturing method based on local pin header connections in this invention. Figure 2 This is a schematic diagram of drilling in an embodiment of the present invention; Figure 3 This is a schematic diagram of the cross-section of chemically deposited copper PTH in an embodiment of the present invention; Figure 4 This is a schematic diagram of the full-plate electroplating cross-section in an embodiment of the present invention; Figure 5 This is a schematic cross-sectional view of the exposure process in an embodiment of the present invention; Figure 6 This is a schematic diagram of the secondary copper plating cross-section in an embodiment of the present invention; Figure 7 This is a top view of the pin header connection assembly in an embodiment of the present invention; Figure 8 This is a front view of the pin header connection assembly in an embodiment of the present invention; Figure 9 This is a schematic diagram of the PCB pin header pad dimensions in an embodiment of the present invention; Figure 10 This is a side view of the pin header connection assembly inserted into the PCB substrate in an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] The terms "comprising" and "having," and any variations thereof, used in the embodiments of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0021] To facilitate understanding of this embodiment, a detailed description of a double-sided PCB manufacturing method based on partial pin header connections disclosed in this embodiment of the invention will be provided first. For example... Figure 1 As shown, this method includes the following steps: 101. Perform partitioned circuit design on the double-sided PCB substrate to obtain the circuit layout of the double-sided PCB substrate; 102. Drill holes in a double-sided PCB substrate based on the circuit layout, and perform desmearing, chemical copper plating and copper electroplating only on the vias in the signal transmission area to obtain the target PCB substrate. 103. Press the brass conductive pins into the pin holes of the insulating base to form a pin header connection assembly, and insert the pin header connection assembly into the mechanical through hole of the target PCB substrate to obtain a pre-assembled body; 104. Perform wave soldering on the pre-assembled parts to obtain a double-sided PCB finished product.

[0022] In one specific embodiment, a partitioned circuit design is performed on the double-sided PCB substrate to obtain the circuit layout of the double-sided PCB substrate, including: The top and bottom interconnect nodes of the pin header connection area in the double-sided PCB substrate are arranged in an array to obtain the pin header connection area hole layout. Based on the pin header connection area hole layout, power lines and ground lines are routed together in the pin header connection area, signal lines are routed in the signal transmission area, and via holes for PTH metallization are planned at each interconnect node in the signal transmission area to obtain the circuit layout of the double-sided PCB substrate.

[0023] Specifically, when establishing the circuit layout of a double-sided PCB substrate, interconnection attribute identification is performed on all nodes to be connected between the top and bottom layers. Interconnection nodes used for power input, power distribution, and ground return are identified as high-current interconnection nodes and grouped into the pin header connection area. Interconnection nodes used for control signal transmission, data signal transmission, or functional status transmission are grouped into the signal transmission area. This allows the interlayer interconnection objects of the double-sided PCB substrate to be separated into regions according to current carrying characteristics and transmission purposes during the layout planning stage. After the region separation is completed, the top and bottom layer connection positions corresponding to the high-current interconnection nodes are arranged vertically according to standard array rules within the pin header connection area. This creates a regular hole array in the plane coordinates that allows for the overall insertion of local pin header connection components. For example, the array pitch is 2.54mm, the array form is a 4×4 matrix, and the geometric center of the pad corresponding to each group of interconnection nodes is used as the center coordinate of the hole position. Around the center coordinates of each hole, the top and bottom pads are coaxially designed. The mechanical via parameters are determined based on the insertion dimensions and soldering requirements of the brass conductive pins, resulting in a mechanical via diameter of 0.5mm and a pad diameter of 0.8mm. This ensures that each group of top and bottom pads and mechanical vias forms an integrated through-mount position. The coordinate parameters, hole diameter parameters, and array parameters corresponding to all through-mount positions are then summarized to form the pin header connection area hole layout. Based on the pin header connection area hole layout, a partitioned routing design is implemented on the double-sided PCB substrate. Power and ground lines are concentrated in the pin header connection area. This is not simply a change in routing position, but rather a way to ensure that the interlayer interconnect paths carrying larger current-carrying tasks correspond to the physical metal conductivity of the local pin header connection structure. Because power and ground lines carry significant current during operation, using conventional small-diameter PTH metallized vias for the main interlayer conduction would not only increase the number of vias but also subject the copper layer on the via walls to prolonged high current density, negatively impacting conduction stability, temperature rise control, and manufacturing costs. Therefore, in the layout design, the main power and ground lines are concentrated in the pin header connection area and connected to corresponding interconnect nodes in the pin header connection array. The brass conductive pins inserted into the mechanical vias serve as the main high-current conductor between the top and bottom layers, with the brass conductive pins and double-sided solder joints forming a low-impedance interlayer connection path. Correspondingly, the signal transmission area accommodates control signal lines, data signal lines, and other low-power transmission lines, allowing these signal lines to be routed away from the high-current interconnect structure of the pin header connection area. This reduces the coupling impact on signal integrity caused by the concentrated arrangement of power and ground loops and reserves continuous routing space for high-density signal routing.After completing the signal routing layout in the signal transmission area, vias for PTH metallization are planned at each interconnection node within the signal transmission area. These vias are then used solely for inter-layer switching and general signal conduction within the signal transmission area, rather than for inter-layer interconnection of power and ground lines in the pin header connection area. Specifically, the center coordinates of the PTH vias are set based on the intersection of top and bottom layer signal lines, layer switching requirements, and safety clearance requirements. The via diameter and spacing are determined by considering manufacturing precision and short-circuit risk control requirements. For example, the PTH via diameter in the signal transmission area is 0.2mm, and the via spacing is controlled to be no less than 1.0mm. This satisfies the signal interconnection density while reducing the processing offset and bridging risks caused by small-pitch via clusters. After the mechanical via parameters in the pin header connection area, the top and bottom pad pattern parameters in the pin header connection area, the signal transmission area circuit pattern parameters, and the PTH via parameters in the signal transmission area are unified and correlated, the circuit layout of the double-sided PCB substrate is generated. In the circuit layout of a double-sided PCB substrate, the pin header connection area corresponds to the mechanical through-hole plus local pin header connection method, and the signal transmission area corresponds to the PTH metallized via connection method. This enables the double-sided PCB substrate to establish a partitioned interconnection structure in the design stage, in which "power lines and ground lines achieve interlayer conduction through local pin header connection, and signal lines achieve interlayer conduction through PTH metallized vias".

[0024] In one specific embodiment, the top and bottom interconnect nodes of the pin header connection area in a double-sided PCB substrate are arranged in an array to obtain a pin header connection area hole layout, including: Arrange the top and bottom interconnect nodes in the pin connection area of ​​the double-sided PCB substrate in an array according to the standard pin spacing, and determine the center position of the top and bottom pads at each interconnect node. Based on the center position of the pad, the diameter of the mechanical via and the size of the pin header pad at each interconnect node are planned to match the diameter of the conductive pin, thus obtaining the pin header connection area hole layout.

[0025] Specifically, when planning the hole positions in the pin header connection area, based on the key interconnect nodes in the double-sided PCB substrate that require local pin header connections to achieve interlayer conductivity, a one-to-one interconnection relationship is established between the top and bottom layers. These interconnect nodes are then confined within the pin header connection area and arranged in a regular array. The standard pin pitch is used as the positioning reference during array arrangement, with an implementation parameter of 2.54mm. The pin hole arrangement on the insulating base is kept consistent with the planned pin header connection point coordinates. For each interconnect node within the pin header connection area, the geometric centers of the top and bottom pads are used as the positioning reference along the same through-mount axis, ensuring that the centers of the top pad, mechanical via, and bottom pad are vertically aligned. This transforms each interconnect node into a standard mounting position for conductive pins to pass through. When multiple mounting positions are evenly distributed horizontally or in an array direction according to the standard pin pitch, the center positions of the top and bottom pads at each interconnect node are obtained. Based on the center position of the pads, the diameter of the mechanical vias and the size of the pin header pads at each interconnect node are matched and planned. The matching objects must correspond to the diameter of the conductive pins and the soldering fixation requirements. The diameter of the conductive pins is 0.4±0.01mm, and the diameter of the mechanical vias in the pin header connection area is 0.5mm. Therefore, when planning the mechanical vias, the diameter of the mechanical vias is slightly larger than the diameter of the conductive pins, so as to provide the necessary assembly clearance for the insertion of the conductive pins. This allows the conductive pins to pass smoothly through the PCB board during the insertion process without causing significant skew due to excessively large hole diameters. At the same time, the pad size must cover the perimeter of the mechanical vias and reserve sufficient soldering area to form stable solder joints during wave soldering. In the pad parameters, the center-to-center spacing between adjacent pads is 1.27mm, the pad width is 0.70mm, the pad length is 2.40mm, and the center-to-center distance between double-row pads is 6.00mm. This means that after determining the center coordinates of the pads, the pad outline can be unfolded around each coordinate point along the arrangement direction and perpendicular to the arrangement direction, so that the length direction of the pad is consistent with the pin arrangement direction, and the width direction of the pad meets the requirements for solder wetting and solder ring retention. This forms a pin header pad pattern that simultaneously adapts to conductive pin insertion, pad alignment, and subsequent soldering fixation. After matching is completed, the center coordinates of the pads, the diameter of the mechanical via, the pad width, the pad length, and the double-row arrangement spacing corresponding to each interconnect node are uniformly packaged to obtain the pin header connection area hole layout.

[0026] Figure 2 This is a cross-sectional structural diagram of the drilling process, including the cross-sectional layer structure when drilling multiple PCB substrates stacked together. The aluminum cover plate is located at the top layer, below which are multiple layers of PCB boards stacked together. The gray layer is the substrate layer, and the red layer is the copper foil layer. The drill bit penetrates each layer of the board from top to bottom. At the bottom is a pad plate, which serves to support and protect the worktable.

[0027] In one specific embodiment, drilling is performed on a double-sided PCB substrate based on the circuit layout, and only the vias in the signal transmission area are subjected to desmearing, chemical copper plating, and electroplating to obtain the target PCB substrate, including: Based on the circuit layout of the double-sided PCB substrate, holes are drilled in the pin header connection area and the signal transmission area of ​​the double-sided PCB substrate to obtain mechanical through holes in the pin header connection area and holes to be plated in the signal transmission area. The signal transmission area to be plated is sequentially treated with desmearing, chemical copper plating, and electroplating to form a metallized copper layer on the hole wall, thus obtaining the target PCB substrate.

[0028] Specifically, the circuit layout of the double-sided PCB substrate is used as the direct input for the selective via machining program, and corresponding drilling paths are executed for the pin header connection area and the signal transmission area respectively. The substrate uses FR-4 standard board material with a thickness of 1.6mm and an outer copper thickness of 1oz. Before drilling, the substrate is cut, edged, rounded, and baked to reduce the moisture content to a level suitable for mechanical drilling and subsequent electroplating, thus avoiding scratches from burrs on the board edge and preventing the risk of delamination caused by excessive moisture absorption of the substrate. After preprocessing, the double-sided PCB substrates are stacked according to process requirements. For example, each stack consists of two to three PCBs. An aluminum cover plate is placed on the top layer of the stack to improve drill bit positioning stability and assist in heat dissipation, while reducing the risk of pressure foot damage to the board surface. A composite material pad is placed on the bottom layer of the stack to protect the drilling table, suppress burr formation at the exit, reduce drill bit temperature rise, and clean adhesive residue from the drill bit grooves. The PCB substrate in the middle is positioned and fixed by pins, thereby ensuring consistency between the program coordinates and the actual drilling coordinates. During the drilling execution phase, the CNC drilling machine is driven by the circuit layout file of the double-sided PCB substrate to mechanically drill two types of areas, where the pin connection area corresponds to the through holes in area A, and the signal transmission area corresponds to the PTH holes in area B. The through-holes in the pin header connection area are used for the insertion of conductive pins in local pin header connection components. Therefore, they are machined with a hole diameter of 0.5mm to ensure a proper fit with the subsequent 0.4±0.01mm brass conductive pins. The through-holes in the signal transmission area are used for traditional PTH metallization interlayer interconnection, and are machined with a hole diameter of 0.2mm to meet the conductivity density required for signal line layer switching. After processing, the pin header connection area becomes a mechanical through-hole, and the signal transmission area becomes a hole to be plated. Although both types of holes penetrate the double-sided PCB substrate, the mechanical through-holes in the pin header connection area only serve as insertion guides and soldering positions, while the holes to be plated in the signal transmission area require further metallization of the hole walls to establish a conductive path between the upper and lower layers. Since the previous partitioning design has concentrated power and ground lines in the pin header connection area and signal lines in the signal transmission area, the holes to be plated in the signal transmission area are further metallized in this step, without needing to repeat the high-cost PTH process on the mechanical through-holes in the pin header connection area. After the holes to be plated in the signal transmission area are formed, the holes are sequentially treated with desmearing, chemical copper plating, and electroplating to create a continuous copper metallized layer on the hole walls. The desmearing process uses a desmearing agent to remove the resin coating and processing debris remaining on the hole walls during drilling, exposing the previously resin-covered copper rings and providing an adhesion interface for copper plating. After the copper rings are exposed, chemical copper plating is performed on the holes in the signal transmission area, forming a continuous chemical copper layer on the hole walls. This chemical copper layer transforms the originally non-conductive hole wall surface into an initial conductive interface that allows current to pass through.Electroplating is performed on the surface of the chemical copper layer, allowing the electroplated copper layer to grow superimposed on the outside of the chemical copper layer, thereby gradually increasing the thickness of the copper layer on the hole wall and forming a metallized copper layer on the hole wall that can stably carry the signal interlayer interconnection. After all the processing is completed, the target PCB substrate is obtained. The structural characteristics of the target PCB substrate are that the pin connection area contains mechanical through holes and the signal transmission area contains metallized vias. That is, two different interlayer interconnection preparation forms are retained on the same double-sided PCB substrate: one is a mechanical through hole for brass conductive pins to pass through and form an electrical connection through wave soldering, and the other is a metallized via whose hole wall has been directly completed by the desmearing, chemical copper plating and electroplating processes.

[0029] Figure 3 This is a schematic diagram of the PCB cross-section structure after the PTH (Potentially Hidden Thoroughfare) process of chemical copper plating. It shows the layered structure of the gray substrate layer and the orange copper foil layer, the structure of the chemical copper layer formed on the via walls after the chemical copper plating treatment, and includes PTH, indicating the location of the chemical copper layer on the via walls.

[0030] In one specific embodiment, the signal transmission area to be plated holes undergoes sequential processes of desmearing, chemical copper plating, and electroplating to form a metallized copper layer on the hole walls, thereby obtaining the target PCB substrate, including: The signal transmission area hole wall to be plated is treated with a descaling agent to remove adhesive residue, resulting in a signal transmission area hole with exposed copper ring on the hole wall. The signal transmission area to be plated, with exposed copper rings on the hole wall, is subjected to chemical copper deposition and electroplating copper treatment in sequence. This process first deposits a chemical copper layer on the hole wall, and then electroplats a copper layer on the surface of the chemical copper layer to obtain the target PCB substrate. The pin header connection area of ​​the target PCB substrate contains mechanical through holes, and the signal transmission area contains metallized vias.

[0031] Specifically, after mechanical drilling is completed in the signal transmission area, the hole walls still retain a resin coating layer and residual adhesive residue formed during the drilling process due to localized temperature rise. Although the basic hole shape is exposed on the inner side of the hole wall, the copper rings are not yet in a clean state suitable for direct copper plating. Therefore, a descaling agent is first used to remove the adhesive residue from the hole walls in the signal transmission area, exposing the copper rings and improving the microstructure of the hole wall surface through expansion. After the descaling treatment, the signal transmission area changes from a resin-covered state to a state with exposed copper rings on the hole walls, thus meeting the prerequisites for entering the hole wall metallization process. After the copper rings are exposed, the signal transmission area undergoes chemical copper plating and electroplating treatments sequentially. The chemical copper plating process involves forming a continuous chemical copper layer on the surface of the hole wall, which originally lacked stable conductivity, thus giving the hole wall initial conductivity. For example, the thickness of the chemical copper plating layer is controlled to be 0.2–0.5 μm, allowing the electroplating current to be evenly distributed along the hole wall. After chemical copper plating, electroplating copper is performed on the surface of the chemical copper layer, allowing primary copper to continue to grow on the outside of the chemical copper layer. For example, the thickness of the electroplated copper layer is controlled to be 5–10 μm, forming a metallized copper layer on the hole wall that has both continuity and mechanical strength. After this process, the hole wall structure of the hole to be plated in the signal transmission area is composed of "substrate hole wall—chemical copper layer—electroplated copper layer" layer by layer. A stable conductive path can be established between the top and bottom layers of the circuitry through the metallized copper layer on the hole wall. At the same time, the pin header connection area does not enter the above chemical treatment path, but continues to retain the mechanical through-hole state formed by mechanical drilling, so that the pin header connection area and the signal transmission area are clearly distinguished in terms of hole structure. The pin header connection area is used for conductive pin insertion and soldering fixation, while the signal transmission area is used to achieve interlayer conduction of the signal through the metallization of the hole wall. After continuous processing of descaling, chemical copper plating, and electroplating, the target PCB substrate is obtained. The target PCB substrate has a structure in which the pin connection area contains mechanical vias and the signal transmission area contains metallized vias. Thus, two different interlayer connection preparation forms are preserved on the same double-sided PCB substrate.

[0032] In one specific embodiment, a pin header assembly is formed by pressing brass conductive pins into pin holes in an insulating base, and then inserting the pin header assembly into a mechanical through-hole on a target PCB substrate to obtain a pre-assembled body, comprising: The surface of the brass conductive pins is sequentially plated with nickel and then with gold. The surface-treated brass conductive pins are then pressed one by one into the pin holes of the insulating base to obtain the pin header connection assembly. Align each conductive pin of the pin header connection assembly with each mechanical through hole in the pin header connection area of ​​the target PCB substrate, and insert the conductive pin into the mechanical through hole until the bottom surface of the insulating base is in close contact with the top surface of the target PCB substrate and the bottom end of the conductive pin extends out from the bottom of the target PCB substrate to obtain a pre-assembled body.

[0033] Specifically, based on the through-hole dimensions of the pin header connection area and subsequent welding and fixing requirements, the brass conductive pins undergo forming, surface functionalization, and array press-fit assembly. H62 brass strip is selected as the raw material for the conductive pins, and a precision stamping process is used to form the pin body structure, controlling the pin diameter to 0.4±0.01mm. This ensures the conductive pin size maintains an insertion-matching relationship with the 0.5mm diameter of the mechanical through-holes in the pin header connection area. Simultaneously, considering the 1.6mm thickness of the double-sided PCB substrate and the welding height requirements of the top and bottom pads, the total length of the conductive pin is determined, ensuring sufficient welding protrusion on both the top and bottom sides after the conductive pin passes through the target PCB substrate. After the conductive pins are formed, nickel plating and gold plating are sequentially performed on the surface of the brass conductive pins. This results in a nickel layer first forming on the outer surface of the brass conductive pin, followed by a gold layer on the outside of the nickel layer. The nickel plating layer acts as a barrier layer to inhibit the outward diffusion of copper from the brass substrate, preventing interface instability. The gold plating layer acts as a conductive surface layer, reducing contact resistance and improving surface oxidation resistance. For example, with a nickel plating thickness of 2μm and a gold plating thickness of 0.05μm, after surface treatment, a stable layered structure of "brass substrate—nickel layer—gold layer" is formed on the surface of the brass conductive pin, thus obtaining a nickel-gold plated brass conductive pin. The contact resistance of the conductive pin can be controlled within 20mΩ, the insulation resistance is not less than 1000MΩ, the rated current is 1A AC / DC, the withstand voltage is 550V AC / min, and the single pin insertion and extraction force is 3N±0.5N. The surface-treated brass conductive pins are pressed one by one into the pin holes of the insulating base, transforming the scattered individual conductive pins into an array of connecting components with a uniform pitch, direction, and exposure height. The insulating base is injection molded from high-temperature resistant engineering plastic. For example, the pin holes on the insulating base are arranged according to a standard pin pitch of 2.54mm and are consistent with the pre-planned 4×4 array hole coordinates of the pin header connection area, forming a 16-hole mounting array that completely corresponds to the pin header connection area of ​​the target PCB substrate. During the press-fit process, an automatic pin insertion device is used to feed nickel-gold plated brass conductive pins one by one into the corresponding pin positions. A pressing force is applied along the pin body axis to create an interference fit between the outer wall of the conductive pin and the wall of the pin position hole in the insulating base. After the interference fit is formed, each conductive pin achieves stable vertical positioning within the insulating base, preventing axial misalignment or relative loosening during handling, alignment, and insertion. Simultaneously, the insulating base maintains all conductive pins within the same array pitch relationship as the pin header connection area, thus forming the pin header connection assembly. The heat resistance of the insulating base material is higher than the peak temperature of wave soldering, thus maintaining the positional accuracy and structural integrity of the pin header array during soldering, preventing thermal deformation of the base from affecting the alignment relationship between the conductive pins and the pads. The conductive pins of the pin header connection assembly are aligned with the mechanical through-holes in the pin header connection area of ​​the target PCB substrate and inserted into their positions to form a pre-assembled assembly.For example, the target PCB substrate is fixed on the assembly platform with the pin header connection area facing upwards and exposed. The pin header connection assembly is then moved as a whole above the target PCB substrate, and the mounting reference edge of the insulating base is aligned with the assembly reference edge of the target PCB substrate. Since the pin hole array of the insulating base, the conductive pin array, and the mechanical through-hole array of the pin header connection area of ​​the target PCB substrate all originate from the same set of hole coordinate data, after the reference edge is aligned, each conductive pin can establish a one-to-one correspondence with its corresponding mechanical through-hole. Subsequently, an overall insertion force is applied downwards in a direction perpendicular to the surface of the target PCB substrate, causing each conductive pin to simultaneously enter each mechanical through-hole and continue to insert until the bottom surface of the insulating base is in close contact with the top surface of the target PCB substrate. As the insertion action is completed, each conductive pin penetrates the target PCB substrate and extends from the bottom layer of the target PCB substrate, so that the top side of the conductive pin corresponds to the top layer pad and the bottom side aligns with the bottom layer pad, thereby forming a through-layer connection foundation of "top layer pad - conductive pin - bottom layer pad" at each pin header connection node. Because the interlayer interconnect is provided directly by the conductive pin body, rather than by the metallized copper layer of the mechanical via wall, the pin header connection area can complete the preparation of critical node interlayer interconnects without relying on the conductivity of traditional PTH via walls. After insertion, the pin header connection assembly and the target PCB substrate form a pre-assembled assembly.

[0034] Figure 4 This is a schematic diagram of the PCB cross-section structure after the full-board electroplating process is completed. It includes the coverage of the electroplated copper layer on the entire copper surface and hole walls, and the layer structure of the hole walls after the primary copper layer is superimposed on the outside of the chemical copper layer. The term "primary copper" indicates the location of the electroplated copper layer formed by the full-board electroplating.

[0035] In one specific embodiment, the surface of the brass conductive pins is sequentially plated with nickel and then with gold. The surface-treated brass conductive pins are then pressed one by one into the pin holes of the insulating base to obtain a pin header connection assembly, comprising: Nickel plating and gold plating are performed sequentially on the surface of the brass conductive needle to form a nickel layer as a barrier layer and a gold layer as a conductive surface layer on the outside of the nickel layer, resulting in a nickel-gold plated brass conductive needle. Nickel-gold plated brass conductive pins are pressed one by one into the pin holes of the insulating base, so that the outer wall of the nickel-gold plated brass conductive pins forms an interference fit with the pin hole wall of the insulating base, thus obtaining the pin header connection assembly.

[0036] Specifically, a continuous electroplating process is performed on the surface of the brass conductive pin to give it both a stable interface structure and low contact resistance. H62 brass strip is selected and precision-stamped to form the conductive pin body, with the pin diameter controlled at 0.4±0.01mm. The surface of the brass conductive pin is first nickel-plated, then gold-plated, forming a structure on the outer surface of the brass conductive pin consisting of a brass substrate, a nickel layer, and a gold layer distributed sequentially from the inside out. The nickel layer formed by the nickel plating process acts as a barrier layer on the outside of the brass substrate, inhibiting copper migration from the brass substrate to the surface and preventing interfacial diffusion instability during welding heating and long-term service. After the nickel layer is formed, gold plating is performed, placing the gold layer outside the nickel layer and serving as a conductive surface layer, thereby improving the oxidation resistance and conductivity stability of the conductive pin surface and reducing the contact interface resistance. For example, a nickel plating thickness of 2μm and a gold plating thickness of 0.05μm are used to obtain nickel-gold plated brass conductive pins. These brass conductive pins achieve a contact resistance of no more than 20mΩ, an insulation resistance of no less than 1000MΩ, a rated current of 1A AC / DC, a withstand voltage of 550V AC / min, and a single-pin insertion / extraction force of 3N±0.5N. The nickel-gold plated brass conductive pins are pressed one by one into the pin positions of the insulating base to form a pin header assembly. The insulating base can be made of high-temperature resistant engineering plastic through injection molding, ensuring that the pin positions on the insulating base are arranged according to a standard pin pitch of 2.54mm and consistent with the array of holes in the pin header connection area. The pin positions form a 4×4 array of 16 mounting holes, ensuring that all conductive pins have a uniform pitch and orientation after installation. During press-fitting, an automatic pin insertion device is used to feed nickel-gold plated brass conductive pins one by one into the corresponding pin positions. A pressing force is applied along the axial direction of the brass conductive pins, creating an interference fit between the outer wall of the brass conductive pin and the wall of the pin position hole in the insulating base. The interference fit utilizes the slight difference between the outer diameter of the pin and the size of the pin position hole to provide a stable frictional locking effect after the brass conductive pin is pressed in, thereby maintaining a vertical positioning state and preventing the brass conductive pin from skewing, loosening, or drifting along its axis during handling, alignment, and insertion. At the same time, the insulating base integrates the originally scattered individual brass conductive pins into a regular array structure, ensuring that the center distance, exposed height, and arrangement direction of each brass conductive pin are consistent, resulting in a pin array connection assembly.

[0037] In one specific embodiment, wave soldering is performed on the pre-assembled assembly to obtain a double-sided PCB finished product, including: Wave soldering was performed on the pre-assembled body according to the preheating zone temperature, the peak temperature of the reflow zone and the cooling rate to obtain the welded body. Online testing of contact resistance and insulation resistance was performed on each solder joint in the pin connection area of ​​the welded body to confirm that the solder connection between the conductive pin body and the top and bottom pads met the electrical conductivity requirements, thus obtaining a double-sided PCB product.

[0038] Specifically, the pre-assembled component is fed into the wave soldering station for welding and fixation, forming a permanent solder connection between each conductive pin in the pin header connection area and the top and bottom pads. Soldering is performed continuously according to a three-stage temperature profile consisting of the preheating zone temperature, the reflow zone peak temperature, and the cooling rate. The preheating zone ensures uniform heating of the pre-assembled component; the reflow zone ensures the solder fully melts and wets the connection; and the cooling zone controls the solder joint solidification process and suppresses thermal stress cracking. The preheating zone temperature is set at 150°C for 60 seconds. During the preheating stage, the PCB board surface, conductive pins, and the insulating base of the pin header connection assembly are heated synchronously. This fully activates the flux on the pad surface and removes the oxide layer from the conductive pins and pads. Simultaneously, the FR-4 substrate gradually transitions from room temperature to a high temperature, thereby reducing the instantaneous thermal shock when entering the high-temperature soldering zone and preventing delamination or blistering of the substrate due to sudden temperature changes. Since the pin header connectors in the pre-assembled assembly are already inserted, the bottom surface of the insulating base is in close contact with the top layer of the target PCB substrate, and each conductive pin has penetrated its corresponding mechanical via and formed a spatial correspondence with the top and bottom pads. After preheating, the pre-assembled assembly continues into the reflow zone, i.e., the wave soldering zone. In this stage, the peak temperature is controlled at 245°C, and the pre-assembled assembly is held at this peak temperature for 5 seconds to allow the solder to fully melt. After melting, under the combined action of capillary action and wetting, the solder simultaneously spreads to the contact interfaces between the conductive pin and the top pad, and between the conductive pin and the bottom pad, forming a fully filled solder joint between the pin tip and the top pad, and simultaneously forming a continuous solder joint between the pin bottom and the bottom pad. After processing, each interconnect node in the pin header connection area no longer relies on the traditional PTH hole wall metallized copper layer for interlayer conduction. Instead, a permanent electrical path is formed by "top pad - solder joint - conductive pin body - solder joint - bottom pad". Because the insulating base is made of PA6T high-temperature resistant engineering plastic, and the glass transition temperature of the insulating base material is higher than the 245℃ peak temperature of wave soldering, the insulating base can maintain structural stability during reflow soldering, without softening or deformation. This ensures that the positional accuracy of each conductive pin in the pin header connection area array does not become unstable due to soldering thermal shock, and guarantees the consistency of each solder joint formation. After the solder joints are formed in the reflow zone, the solder body enters the cooling zone and is cooled at a controlled rate of 3℃ / second, gradually transforming the molten solder from a liquid state to a stable solid connection structure. The cooling rate needs to be controlled to avoid internal stress concentration caused by uneven thermal contraction under rapid cooling conditions, which could lead to microcracks, cold solder joints, or solder joint embrittlement. By controlling the cooling rate at 3℃ / second, each solder joint in the pin header connection area can complete solidification and shrinkage under a relatively gentle thermal gradient, so that the conductive pin body and the top and bottom pads form a solder connection with a complete structure and continuous interface, thus obtaining a welded body.After the solder joint is formed, each conductive pin in the pin header connection area is permanently fixed to the target PCB substrate by solder. The conductive pin body, as a through conductor between the top and bottom layers, is stably retained, while the signal transmission area continues to rely on the previously formed metallized vias for inter-layer signal connection. Therefore, the entire board structurally completes a composite interconnect configuration of "partial pin header conduction in the pin header connection area and metallized via conduction in the signal transmission area." After the solder joint is formed, online electrical performance testing is performed on each solder joint in the pin header connection area to confirm that the solder connection between the conductive pin body and the top and bottom pads meets the electrical conductivity requirements. Contact resistance testing is then performed sequentially on the solder connection points between each conductive pin body and the top and bottom pads in the pin header connection area to obtain the contact resistance value of each solder joint. The purpose of contact resistance testing is to confirm whether the solder joint forms a continuous, low-resistance conductive interface. If individual solder joints have insufficient wetting, solder voids, or insufficient interface contact, the contact resistance value will deviate from the normal range. In the implementation parameters related to conductive pins, the contact resistance control target is no more than 20mΩ. Therefore, during online testing, this can be used to determine whether the solder joint continuity meets the requirements. After the resistance of each solder joint path meets the preset limit, insulation resistance testing is performed between adjacent conductive pins in the pin header connection area to confirm that there is no insulation failure caused by solder bridging, spatter short circuits, or residual conductive contamination between adjacent connection paths. The insulation resistance index is no less than 1000MΩ. Therefore, when the insulation resistance between adjacent conductive pin bodies reaches this index, and the contact resistance of each solder joint meets the limit requirement, it is confirmed that the solder connection between the conductive pin body and the top and bottom pads meets the electrical continuity requirements. After all the above online tests are qualified, a double-sided PCB product is obtained. In the double-sided PCB product, the pin header connection area consists of the conductive pin body and the solder joints at both ends, forming the electrical path between the top and bottom layers. The signal transmission area consists of metallized vias, forming the signal interlayer path. The two respectively undertake the tasks of high-current interconnection and conventional signal interconnection, thereby reducing the number of PTH metallized vias while maintaining the stability and reliability of the overall board interlayer interconnection.

[0039] In one specific embodiment, online detection of contact resistance and insulation resistance is performed on each solder joint in the pin connection area of ​​the solder body to confirm that the solder connection between the conductive pin body and the top and bottom pads meets the electrical conductivity requirements, thereby obtaining a double-sided PCB finished product, including: Contact resistance tests were performed sequentially on the solder connection points between each conductive pin in the pin header connection area and the top and bottom pads to obtain the contact resistance value of each solder point. Based on the contact resistance value of each solder joint, insulation resistance testing is performed between adjacent conductive pins in the pin header connection area of ​​the solder body to confirm that the solder connection between the conductive pin and the top and bottom pads meets the electrical conductivity requirements, thus obtaining a double-sided PCB product with the conductive pin as the electrical path between the top and bottom layers of the pin header connection area.

[0040] Specifically, after the solder body completes wave soldering and cools to set, each conductive pin in the pin header connection area has formed a fixed connection with the top and bottom pads through the solder joints at its upper and lower ends. However, a qualified solder joint appearance does not necessarily equate to a qualified electrical connection. Therefore, online electrical performance testing is performed on the pin header connection area of ​​the solder body to confirm whether each solder joint has truly established low-resistance conduction and maintains sufficient insulation between them. Contact resistance testing is performed sequentially on the solder joints between each conductive pin in the pin header connection area and the top and bottom pads. The testing sequence follows the arrangement of the array holes in the pin header connection area, ensuring that the upper and lower solder joints corresponding to each interconnect node enter the same testing process. During the testing process, the test probes are contacted with the test terminals on the top and bottom pads respectively, so that the test current forms a complete loop through the top pad, the upper solder joint, the conductive pin, the lower solder joint, and the bottom pad. The contact resistance value of the corresponding solder joint path is then calculated based on the loop voltage drop. Further assessment is needed to determine whether a stable, continuous, and low-resistance metal-metal contact relationship has been formed at the solder joint interface. If a solder joint has problems such as insufficient wetting, cold solder joint, voids, interface contamination, or insufficient solder filling, even if it is still partially conductive, the contact resistance value will be significantly higher. The contact resistance control target is no more than 20mΩ. Therefore, during online testing, the contact resistance value of each solder joint is compared with the 20mΩ limit. When the contact resistance value is not higher than 20mΩ, it is confirmed that a solder connection path that meets the low-resistance conductivity requirement has been formed between the corresponding conductive pin body and the top and bottom pads. Based on the contact resistance value of each solder joint, insulation resistance testing is performed between adjacent conductive pin bodies in the solder header connection area. The results of the previous test are used as a preliminary screening condition for insulation testing. Priority is given to confirming inter-pin insulation between conductive pin paths where the contact resistance meets the conductivity requirement, in order to avoid interference with subsequent insulation test results due to a single solder joint not being firmly soldered or the circuit not being truly established. During insulation resistance testing, two adjacent conductive pins within the pin header connection area are selected as a group of adjacent test objects. A test voltage is applied between the corresponding circuits of the two adjacent conductive pins to detect whether there are abnormal leakage paths formed by solder bridging, metal spatter, flux residue carbonization, or contamination residue between the two adjacent conductive paths. If local bridging or insulation failure occurs between adjacent conductive pins, the insulation resistance value will be lower than the normal range. The insulation resistance specification of the finished conductive pins is not less than 1000MΩ. Therefore, when the insulation resistance between adjacent conductive pin bodies is not less than 1000MΩ, it is confirmed that sufficient electrical isolation is maintained between each adjacent interconnection path within the pin header connection area, and there is no risk of inter-pin short circuit that would affect normal operation.Contact resistance testing and insulation resistance testing together form a closed-loop judgment relationship. The former is used to confirm whether a single "top pad - solder joint - conductive pin body - solder joint - bottom pad" path has low resistance continuity, while the latter is used to confirm whether multiple adjacent paths are insulated from each other. Therefore, only when the contact resistance of each solder joint meets the requirement of not exceeding 20mΩ and the insulation resistance between adjacent conductive pins meets the requirement of not less than 1000MΩ can it be confirmed that the solder connection between the conductive pin body and the top and bottom pads meets the electrical continuity requirements. After all the above tests pass, a double-sided PCB product is obtained.

[0041] Figure 5 This is a cross-sectional structural diagram of the Exposure process for outer layer circuitry. It includes a three-layer structure: a UV light source, a film, and a dry film. UV light shines through the white transparent area of ​​the film from below, irradiating the dry film and causing a polymerization reaction in the corresponding areas of the dry film to form a cured pattern. The black opaque area of ​​the film blocks the UV light, and the corresponding areas of the dry film do not undergo a polymerization reaction and can be washed away by the developer.

[0042] Figure 6 This is a schematic diagram of the PCB cross-sectional structure after the secondary copper plating process in the pattern electroplating process. It includes the layered structure of the exposed circuit area copper surface after development and thickening by secondary copper plating. Dry film covers both sides of the non-circuit area copper surface, and the secondary copper plating layer is above the circuit area copper surface. "Dry film" and "secondary copper" indicate the positional relationship between the dry film and the secondary copper plating layer, respectively.

[0043] Figure 7 This is a top-view schematic diagram of the pin header connection assembly, including the overall layout of the dual-row pin hole array. The total width of the assembly is 5.00mm, the center-to-center distance between the pin holes on both sides of the insulating base is 1.27mm, and the width of the base body is 3.40mm. PIN1 indicates the position of the lower row pin hole, and PIN2 indicates the position of the upper row pin hole. The two rows of pin holes are evenly arranged along the length of the base.

[0044] Figure 8 This is a front sectional view of the pin header assembly, showing the assembly relationship and key dimensions of the conductive pins and the insulating base. Dimensions include the total width of the assembly (A), the width of the pin hole area on the base (B), the cross-sectional dimension of the conductive pin (SQ = 0.40 mm, i.e., the side length of the pin cross-section is 0.40 mm), the height of the pin tip extending beyond the top surface of the base (1.27 ± 0.10 mm), and the height of the base body (2 - 1.00 mm). The dashed boxes in the figure indicate the arrangement areas of adjacent conductive pins.

[0045] Figure 9This is a schematic diagram of the planar dimensions of the PCB pin header connection area pads, including the arrangement spacing and pad size parameters of the double-row pads. The center-to-center distance between adjacent pads is 1.27mm, the pad width is 0.70mm, the pad length is 2.40mm, the center-to-center distance between rows of pads is 6.00mm, and the upper and lower rows of pads are evenly arranged horizontally. Each pad is indicated by a diagonal line.

[0046] Figure 10 This is a side cross-sectional view of the pin header connector assembly after it has been inserted into a PCB substrate. It shows the protrusion dimensions of the top and bottom ends of the conductive pin after penetrating the PCB board, and the mating relationship between the insulating base and the PCB surface. The dimensions include: a top width of 4.00 mm; a height of 3.70 mm for the top of the conductive pin extending beyond the top surface of the insulating base; a distance of 5.00 ± 0.20 mm from the top of the conductive pin to the bottom surface of the insulating base after insertion into the PCB substrate; a height of 8.50 ± 0.20 mm for the bottom end of the conductive pin extending from the bottom layer of the PCB substrate; a bottom pad height of 1.50 mm; and a total width of 5.50 ± 0.25 mm for the bottom pad area.

[0047] The optimized double-sided PCB structure based on local pin header connection in this embodiment of the invention is manufactured using a double-sided PCB manufacturing method based on local pin header connection.

[0048] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0049] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device, such as a personal computer, server, or network device, to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0050] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a double-sided PCB based on local pin header connections, characterized in that, include: The circuit layout of the double-sided PCB substrate is obtained by partitioning the circuit board. Based on the circuit layout, holes are drilled in the double-sided PCB substrate, and only the vias in the signal transmission area are subjected to desmearing, chemical copper plating and electroplating to obtain the target PCB substrate. A pin header connection assembly is made by pressing brass conductive pins into the pin holes of an insulating base, and the pin header connection assembly is inserted into the mechanical through holes of the target PCB substrate to obtain a pre-assembled body. Wave soldering is performed on the pre-assembled assembly to obtain a double-sided PCB finished product.

2. The double-sided PCB manufacturing method based on partial pin header connection according to claim 1, characterized in that, The step of partitioning the circuit board on a double-sided PCB substrate to obtain the circuit layout of the double-sided PCB substrate includes: The top and bottom interconnect nodes of the pin header connection area in the double-sided PCB substrate are arranged in an array to obtain the pin header connection area hole layout. Based on the pin header connection area hole layout, power lines and ground lines are routed together in the pin header connection area, signal lines are routed in the signal transmission area, and via holes for PTH metallization are planned at each interconnect node in the signal transmission area to obtain the circuit layout of the double-sided PCB substrate.

3. The double-sided PCB manufacturing method based on partial pin header connection according to claim 2, characterized in that, The step of arraying the top and bottom interconnect nodes of the pin header connection area in the double-sided PCB substrate to obtain the pin header connection area hole layout includes: Arrange the top and bottom interconnect nodes in the pin connection area of ​​the double-sided PCB substrate in an array according to the standard pin spacing, and determine the center position of the top and bottom pads at each interconnect node. Based on the center position of the pad, the mechanical via diameter and pin header pad size that match the conductive pin diameter are planned at each interconnect node to obtain the pin header connection area hole layout.

4. The double-sided PCB manufacturing method based on partial pin header connection according to claim 3, characterized in that, The process of drilling holes in the double-sided PCB substrate based on the circuit layout, and performing desmearing, chemical copper plating, and electroplating on vias only in the signal transmission area to obtain the target PCB substrate, includes: Based on the circuit layout of the double-sided PCB substrate, holes are drilled in the pin header connection area and the signal transmission area of ​​the double-sided PCB substrate to obtain mechanical through holes in the pin header connection area and holes to be plated in the signal transmission area. The signal transmission area to be plated is sequentially subjected to desmearing, chemical copper plating, and electroplating copper treatments to form a metallized copper layer on the hole wall, thereby obtaining the target PCB substrate.

5. The double-sided PCB manufacturing method based on partial pin header connection according to claim 4, characterized in that, The process of sequentially performing desmearing, chemical copper plating, and electroplating on the holes in the signal transmission area to form a metallized copper layer on the hole walls, thereby obtaining the target PCB substrate, includes: The signal transmission area hole wall to be plated is treated with a descaling agent to remove adhesive residue, resulting in a signal transmission area hole with exposed copper ring on the hole wall. The signal transmission area to be plated, with exposed copper rings on the hole wall, is subjected to chemical copper deposition and electroplating in sequence. This process first deposits a chemical copper layer on the hole wall, and then electroplats a copper layer on the surface of the chemical copper layer to obtain the target PCB substrate. The pin header connection area of ​​the target PCB substrate contains mechanical through-holes, and the signal transmission area contains metallized vias.

6. The double-sided PCB manufacturing method based on partial pin header connection according to claim 5, characterized in that, The process of pressing brass conductive pins into the pin holes of an insulating base to form a pin header connection assembly, and inserting the pin header connection assembly into the mechanical through-holes of the target PCB substrate to obtain a pre-assembled body, includes: The surface of the brass conductive pins is sequentially plated with nickel and then with gold. The surface-treated brass conductive pins are then pressed one by one into the pin holes of the insulating base to obtain the pin header connection assembly. Align each conductive pin of the pin header connection assembly with each mechanical through hole in the pin header connection area of ​​the target PCB substrate, and insert the conductive pin into the mechanical through hole until the bottom surface of the insulating base is in close contact with the top surface of the target PCB substrate and the bottom end of the conductive pin extends out from the bottom layer of the target PCB substrate to obtain a pre-assembled body.

7. The double-sided PCB manufacturing method based on partial pin header connection according to claim 6, characterized in that, The surface of the brass conductive pins is sequentially plated with nickel and then with gold. The surface-treated brass conductive pins are then pressed one by one into the pin holes of the insulating base to obtain a pin header connection assembly, comprising: Nickel plating and gold plating are performed sequentially on the surface of the brass conductive needle to form a nickel layer as a barrier layer and a gold layer as a conductive surface layer on the outside of the nickel layer, resulting in a nickel-gold plated brass conductive needle. The nickel-gold plated brass conductive pins are pressed one by one into the pin holes of the insulating base, so that the outer wall of the nickel-gold plated brass conductive pins forms an interference fit with the hole wall of the insulating base, thus obtaining the pin header connection assembly.

8. The double-sided PCB manufacturing method based on partial pin header connection according to claim 7, characterized in that, The wave soldering of the pre-assembled body to obtain a double-sided PCB product includes: The pre-assembled body is wave-welded sequentially according to the preheating zone temperature, the peak temperature of the reflow zone, and the cooling rate to obtain a welded body. Online testing of contact resistance and insulation resistance is performed on each solder joint in the pin connection area of ​​the welded body to confirm that the solder connection between the conductive pin body and the top and bottom pads meets the electrical conductivity requirements, thus obtaining a double-sided PCB product.

9. The double-sided PCB manufacturing method based on partial pin header connection according to claim 8, characterized in that, The online detection of contact resistance and insulation resistance of each solder joint in the pin connection area of ​​the welded body is performed to confirm that the solder connection between the conductive pin body and the top and bottom pads meets the electrical conductivity requirements, resulting in a double-sided PCB finished product, including: Contact resistance detection is performed sequentially on the solder connection points between each conductive pin body and the top and bottom pads in the solder body pin connection area to obtain the contact resistance value of each solder point. Based on the contact resistance value of each solder joint, insulation resistance testing is performed between adjacent conductive pins in the pin header connection area of ​​the solder body to confirm that the solder connection between the conductive pin and the top and bottom pads meets the electrical conductivity requirements, thus obtaining a double-sided PCB product with the conductive pin as the electrical path between the top and bottom layers of the pin header connection area.

10. An optimized double-sided PCB structure based on local pin header connections, characterized in that, It is manufactured using the double-sided PCB manufacturing method based on local pin header connection as described in any one of claims 1-9.

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