Circuit board and packaging method thereof
By using a metal layer instead of an organic layer as a carrier in circuit board packaging and embedding power devices within the cavity, the problems of cost and damage associated with temporary carriers in traditional technologies are solved, enabling packaging of ultra-thin substrates, simplifying operations and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENNAN CIRCUITS
- Filing Date
- 2026-03-04
- Publication Date
- 2026-05-12
AI Technical Summary
Traditional ECP technology is difficult to meet the requirements of miniaturized, thinner, and more integrated packaging, and the use of temporary carriers increases costs and the risk of damage.
By using a metal layer instead of an organic layer as a carrier, and by setting an insulating layer on the metal layer and embedding power devices in the cavity, and using dielectric material to fill and fix it, an ultra-thin substrate is formed, avoiding the use of temporary carriers and mechanical peeling damage.
It simplifies the operation process, reduces costs, improves the strength and stability of the substrate, and meets the packaging requirements for thinner and lighter designs.
Smart Images
Figure CN122028323A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit packaging technology, and more specifically, to a circuit board and its packaging method. Background Technology
[0002] With the rapid development of AI, 5G, electric vehicles, and portable mobile devices, miniaturized, thinner, and more integrated packaging technologies are gradually becoming the mainstream development direction. In traditional forms, ECP (Electronic Chip Packaging) technology can no longer meet application requirements, necessitating further reductions in package thickness.
[0003] In related technologies, the ETS (Electronic Tolerancing) process is commonly used to reduce the thickness of the package. ETS is a coreless packaging substrate process where dielectric and circuit layers are fabricated layer by layer on a temporary carrier using a stacking method. After all circuit layers are fabricated, the temporary carrier is peeled off, resulting in an ultra-thin substrate. However, the temporary carrier requires a depaneling machine for peeling, and the peeling process can easily tear the material, damaging the structure and reducing yield. Furthermore, the temporary carrier is a disposable material, resulting in high usage costs.
[0004] Therefore, there is a need in the art for a circuit board and a packaging method thereof to solve the above problems. Summary of the Invention
[0005] This application aims to at least partially address one of the technical problems in the related art. To this end, embodiments of this application propose a circuit board and its packaging method, which uses a metal layer to replace the existing organic layer as a carrier, thereby avoiding the use of a temporary carrier while forming an ultra-thin substrate. This avoids the damage to the substrate material caused by peeling off the temporary carrier with mechanical force, simplifies the operation steps, protects the substrate material, and reduces the cost of use.
[0006] The circuit board packaging method of this application embodiment includes: A core board is provided, the core board comprising a metal layer and an insulating layer disposed on at least one side of the metal layer; A cavity is formed in the core board, the cavity penetrating the metal layer and the insulating layer; Power devices are embedded in the cavity; A dielectric material is used to fill the cavity to form a filling layer to fix the power device.
[0007] In some embodiments, providing the core board includes: A metal layer is provided, and the metal layer is subjected to a browning treatment to form a browning film on the surface of the metal layer; The insulating layer is provided on both sides of the metal layer, and the insulating layer is bonded to the browning film.
[0008] In some embodiments, the thickness t1 of the insulating layer is ≤30μm.
[0009] In some embodiments, the cavity includes a first cavity and a cutting channel, the first cavity being used to embed power devices. The method of creating a cavity in the core board, the cavity penetrating the metal layer and the insulating layer, includes: The location of the first cavity to be created is determined on the core plate; According to the location of the first cavity to be opened, a first opening is provided on the insulating layer on both sides of the metal layer; According to the first opening position, a first slot is formed on the metal layer, and the first slot communicates with the first opening to form the first cavity.
[0010] In some embodiments, the insulating layer is burned off using a laser drill to form the first opening, and the metal layer is etched using an etching solution to form the first groove.
[0011] In some embodiments, the step of creating a cavity on the core board, the cavity penetrating the metal layer and the insulating layer, further includes: The location of the cutting groove to be opened is determined on the core plate; According to the location of the cutting path to be opened, a second opening is provided on the insulating layer on one side of the metal layer; According to the second opening position, a second slot is provided on the metal layer, the second slot is connected to the second opening and forms the cutting channel.
[0012] In some embodiments, before filling the cavity with a dielectric material to form a filling layer to fix the power device, the method further includes: bonding the power device to the metal layer with adhesive tape.
[0013] In some embodiments, the encapsulation method further includes: The power device is fan-out processed.
[0014] The circuit board of this application embodiment is made by the packaging method described in any of the above embodiments. The circuit board includes a core board, the core board includes a metal layer and an insulating layer disposed on at least one side of the metal layer, the core board has a cavity, the cavity penetrates the metal layer and the insulating layer, and a power device is embedded in the cavity.
[0015] In some embodiments, the core board has a filling layer that fills the cavity to fix the power device.
[0016] The circuit board packaging method of this application replaces the organic layer in related technologies with a metal layer, thereby increasing strength and improving the support effect on the core board, which can be used as a carrier. Then, a cavity is formed within the core board, and power devices are embedded within the cavity, ultimately forming an ultra-thin substrate. This packaging method avoids the use of temporary carriers, thus avoiding damage to the substrate material caused by mechanically peeling off temporary carriers. It reduces operation steps, simplifies operation, protects the substrate material, and avoids the introduction of temporary carriers, reducing usage costs. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic flowchart of a circuit board packaging method according to an embodiment of this application.
[0019] Figure 2 This is a schematic diagram of the structure for forming a metal layer in the packaging method of this application embodiment.
[0020] Figure 3 This is a schematic diagram of the encapsulation method of this application, in which a browning film is formed on a metal layer.
[0021] Figure 4 This is a schematic diagram of the structure of the core board formed by the packaging method of this application embodiment.
[0022] Figure 5 This is a schematic diagram of the packaging method of this application, which forms a first opening and a second opening on the core board.
[0023] Figure 6 This is a schematic diagram of the structure of forming a cavity on the core board in the packaging method of this application embodiment.
[0024] Figure 7 This is a schematic diagram of the packaging method of this application, in which a power device is embedded in a cavity to form a filling layer.
[0025] Figure 8 This is a schematic diagram of the structure of forming copper pillars and copper conductor layers on the core board in the packaging method of this application embodiment.
[0026] Figure label: 1000, Circuit board; 100. Core board; 10. Metal layer; 11. Brown coating; 12. Copper pillar; 13. Copper conductor layer; 20. Insulation layer; 30. Cavity; 31. First cavity; 311. First opening; 312. First slot; 32. Cutting channel; 321. Second opening; 322. Second slot; 40. Power devices; 41. Copper pillars; 42. Copper conductor layers; 50. Filler layer. Detailed Implementation
[0027] The embodiments of this application are described in detail below, with examples of these embodiments illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.
[0028] The following is combined Figures 1 to 8 This application describes a circuit board and its packaging method according to embodiments of the present application.
[0029] refer to Figures 1 to 8 This application proposes a packaging method for a circuit board 1000, which can modify the internal structure of the original core board 100. Using a metal layer 10 as a carrier, power devices 40 are embedded in the cavity 30 of the core board 100, ultimately forming an ultra-thin substrate. This packaging method avoids the use of temporary carriers and the damage to the substrate material caused by mechanically peeling off temporary carriers. It reduces the number of operation steps, simplifies the operation, protects the substrate material, and reduces the cost of using temporary carriers.
[0030] refer to Figures 1 to 8 The packaging method for circuit board 1000 includes the following steps: S1. A core board 100 is provided, the core board 100 including a metal layer 10 and an insulating layer 20 disposed on at least one side of the metal layer 10.
[0031] The metal layer 10 is typically made of metals such as copper or aluminum. Compared to traditional organic layers made of epoxy resin and glass fiber, the metal layer 10 has better strength and ductility, and can be used as a support for the core board 100, serving as a carrier. In this embodiment, the thickness t2 of the metal layer 10 is ≤80μm. As a preferred embodiment, the thickness t2 of the metal layer 10 can be 80μm.
[0032] In order to improve the rigidity of the metal layer 10 and ensure the stability of the core board 100 during processing, an insulating layer 20 is provided on the surface of the metal layer 10. The insulating layer 20 is made of epoxy resin glass fiber and can improve the rigidity of the metal layer 10 after being combined with the metal layer 10.
[0033] S2. A cavity 30 is formed on the core board 100, and the cavity 30 penetrates the metal layer 10 and the insulating layer 20.
[0034] The cavity 30 can be fabricated by laser ablation, mechanical cutting, chemical etching, or other methods. A portion of the cavity 30 is a through groove extending along the thickness direction of the core plate 100, used to embed the power device 40.
[0035] S3. Embed the power device 40 inside the cavity 30.
[0036] In this example, the power device 40 can be a chip. In other examples, the power device 40 can also be a capacitor, resistor, etc.
[0037] S4. A dielectric material is used to fill the cavity 30 to form a filling layer 50 to fix the power device 40.
[0038] The dielectric material constituting the filling layer 50 can be a semi-cured sheet with good fluidity. The semi-cured sheet is composed of resin and fiberglass cloth, and after curing, it can bond the power device 40 into the cavity 30.
[0039] The packaging method for the circuit board 1000 in this embodiment replaces the organic layer in related technologies with a metal layer 10, thereby increasing strength and improving the support effect on the core board 100, which can be used as a carrier. Then, a cavity 30 is formed within the core board 100, and power devices 40 are embedded within the cavity 30, ultimately forming an ultra-thin substrate. This packaging method avoids the use of temporary carriers, thus avoiding damage to the substrate material caused by mechanically peeling off temporary carriers. It reduces operation steps, simplifies operation, protects the substrate material, and avoids the introduction of temporary carriers, reducing usage costs.
[0040] refer to Figures 2 to 4 In some embodiments, a core board 100 is provided, including the following steps: A metal layer 10 is provided, and the metal layer 10 is subjected to a browning treatment to form a browning film 11 on the surface of the metal layer 10.
[0041] Browning is a chemical oxidation process that enhances the bond between the metal layer 10 and the insulating layer 20 by increasing the roughness of the metal surface and forming a uniform oxide layer (browning film 11) on the metal surface.
[0042] An insulating layer 20 is provided on both sides of the metal layer 10, and the insulating layer 20 is bonded to the browning film 11.
[0043] The insulating layer 20 is provided on both sides of the metal layer 10, that is, there are two insulating layers 20, which can further improve the rigidity of the metal layer 10 and ensure the stability of the core board 100.
[0044] refer to Figure 4 In some embodiments, the thickness t1 of the insulating layer 20 is ≤30μm.
[0045] In one preferred example, the thickness t1 of the insulating layer 20 can be 30 μm. In this way, the insulating layer 20 is relatively thin and is located on both sides of the metal layer 10. This can ensure the rigidity of the metal layer 10 and limit the overall thickness of the core board 100, thus avoiding the core board 100 being too thick and unable to meet the requirements of thinness and lightness.
[0046] Continue to refer to Figure 5 and Figure 6 In some embodiments, the cavity 30 includes a first cavity 31 and a cutting channel 32, the first cavity 31 being used to embed the power device 40.
[0047] A cavity 30 is formed in the core board 100, the cavity 30 penetrating the metal layer 10 and the insulating layer 20, including the following steps: Determine the position of the first cavity 31 to be opened on the core board 100; According to the position of the first cavity 31 to be opened, a first opening 311 is provided on the insulating layer 20 on both sides of the metal layer 10; According to the position of the first opening 311, a first slot 312 is provided on the metal layer 10. The first slot 312 is connected to the first opening 311 and forms a first cavity 31.
[0048] The above method steps can sequentially create spaces in the insulating layer 20 and the metal layer 10, thereby forming a first cavity 31 that extends through the thickness direction of the core board 100. The through first cavity 31 facilitates the subsequent placement of the power device 40. In this embodiment, the number of first cavities 31 is not limited and can be one, two, three, four, etc. If there are multiple first cavities 31, the multiple first cavities 31 are spaced apart from each other along the surface of the core board 100.
[0049] Continue to refer to Figure 5 and Figure 6 In some embodiments, a laser drill is used to burn off the insulating layer 20 to form the first opening 311, and an etching solution is used to etch the metal layer 10 to form the first groove 312.
[0050] In this method, the metal layer 10 is etched from both sides using an etching solution. The side etching phenomenon during etching can be reduced by setting a compensation value through pattern exposure.
[0051] To address the different material properties of the insulating layer 20 and the metal layer 10, different process methods, such as laser drilling and etching, are employed to achieve the formation of the first opening 311 and the first groove 312.
[0052] Continue to refer to Figure 5 and Figure 6 In some embodiments, a cavity 30 is formed in the core board 100, the cavity 30 penetrating the metal layer 10 and the insulating layer 20, and the method further includes the following steps: Determine the position of the cutting track 32 to be opened on the core board 100; According to the position of the cutting channel 32 to be opened, a second opening 321 is provided on the insulating layer 20 on one side of the metal layer 10; According to the position of the second opening 321, a second slot 322 is provided on the metal layer 10. The second slot 322 is connected to the second opening 321 and forms a cutting channel 32.
[0053] The process involves using a laser drill to burn away the insulating layer 20 to form the second opening 321, and using an etching solution to etch the metal layer 10 to form the second groove 322. Specifically, the etching solution is used to etch the metal layer 10 from the side adjacent to the second opening 321 until the metal layer 10 is etched through. Side etching during etching can be reduced by setting a compensation value for pattern exposure.
[0054] Understandably, the insulating layer 20 on the other side of the metal layer 10 was not etched by the etching solution; in other words, no second opening 321 was provided on the insulating layer 20 on the other side of the metal layer 10. This ensures the continuity of the insulating layer 20 on the other side of the metal layer 10, guaranteeing the rigidity of the circuit board 1000 during subsequent processing and preventing deformation. Furthermore, after processing, the insulating layer 20 on the other side of the metal layer 10 can be easily cut along the cutting path 32 using a cutting machine or similar equipment, achieving the separation of the various units of the circuit board 1000. This ensures both stability during processing and ease of separation.
[0055] In some embodiments, before filling the cavity 30 with a dielectric material to form a filling layer 50 to fix the power device 40, the method further includes the step of bonding the power device 40 to the metal layer 10 with adhesive tape.
[0056] The power device 40 is bonded to the metal layer 10 with adhesive tape, which initially fixes the power device 40 in the first cavity 31 and prevents the power device 40 from falling out. After curing, the subsequent filler layer 50 can completely wrap the power device 40 and fix the power device 40 in the first cavity 31.
[0057] Key reference Figure 7 and Figure 8 In some embodiments, the encapsulation method further includes the following steps: Fan-out processing is applied to power device 40.
[0058] Among them, continue to refer to Figure 8 Copper pillars 41 can be generated on the pads of the power device 40 by vacuum sputtering and electroplating. The copper pillars 41 extend vertically to the outside of the filler layer 50. At the end of the copper pillar 41 located outside the filler layer 50, a copper conductor layer 42 parallel to the surface of the core board 100 is provided, thereby realizing the fan-out of the power device 40.
[0059] In another embodiment, a blind hole corresponding to the pad of the power device 40 can be formed by laser ablation on the fill layer 50. Copper is electroplated in the blind hole to form a copper pillar 41 connected to the pad of the power device 40. At the end of the copper pillar 41 located outside the fill layer 50, a copper conductor layer 42 parallel to the surface of the core board 100 is provided, thereby realizing the fan-out of the power device 40.
[0060] Continue to refer to Figure 8 In some embodiments, laser etching can be used to ablate vias corresponding to and connected to the metal layer 10 on the filler layer 50 and the insulating layer 20. Copper layers are electroplated inside the vias to form copper pillars 12 connected to the metal layer 10. At the end of the copper pillar 12 located outside the filler layer 50, a copper conductor layer 13 parallel to the surface of the core board 100 is provided. This enables the core board 100 to be electrically conductive along the thickness direction and also facilitates the electrical connection between the metal layer 10 and the outside.
[0061] refer to Figures 2 to 7 This application also proposes a circuit board 1000, which is manufactured by the packaging method in any of the above embodiments. The circuit board 1000 includes a core board 100, the core board 100 includes a metal layer 10 and an insulating layer 20 disposed on at least one side of the metal layer 10, the core board 100 is provided with a cavity 30, the cavity 30 penetrates the metal layer 10 and the insulating layer 20, and a power device 40 is embedded in the cavity 30.
[0062] The insulating layer 20 can be made of epoxy resin and glass fiber, and is applied to the surface of the metal layer 10 by lamination. The power device 40 can be a chip, resistor, capacitor, etc.
[0063] Other technical advantages of the circuit board 1000 in this application embodiment are the same as the technical advantages of the packaging method of the circuit board 1000 described above, and will not be repeated here.
[0064] refer to Figures 6 to 8 In some embodiments, the core board 100 is provided with a filling layer 50 that fills the cavity 30 to fix the power device 40.
[0065] The filling layer 50 is composed of a dielectric material, specifically a prepreg. The prepreg is made of resin and fiberglass cloth and can be configured to have good fluidity, facilitating its flow and filling of the cavity 30. After curing, the prepreg can bond the power device 40 to the cavity 30. Understandably, the prepreg fills the cavity 30 of the core board 100 using a pressing method.
[0066] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0067] In this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0068] Although the above embodiments have been shown and described, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application. Any changes, modifications, substitutions and variations made to the above embodiments by those skilled in the art are within the protection scope of the present application.
Claims
1. A method for packaging a circuit board, characterized in that, include: A core board is provided, the core board comprising a metal layer and an insulating layer disposed on at least one side of the metal layer; A cavity is formed in the core board, the cavity penetrating the metal layer and the insulating layer; Power devices are embedded in the cavity; A dielectric material is used to fill the cavity to form a filling layer to fix the power device.
2. The packaging method according to claim 1, characterized in that, The provided core board includes: A metal layer is provided, and the metal layer is subjected to a browning treatment to form a browning film on the surface of the metal layer; The insulating layer is provided on both sides of the metal layer, and the insulating layer is bonded to the browning film.
3. The packaging method according to claim 1 or 2, characterized in that, The thickness t1 of the insulating layer is ≤30μm.
4. The packaging method according to claim 2, characterized in that, The cavity includes a first cavity and a cutting channel, wherein the first cavity is used to embed power devices. The method of creating a cavity in the core board, the cavity penetrating the metal layer and the insulating layer, includes: The location of the first cavity to be created is determined on the core plate; According to the location of the first cavity to be opened, a first opening is provided on the insulating layer on both sides of the metal layer; According to the first opening position, a first slot is formed on the metal layer, and the first slot communicates with the first opening to form the first cavity.
5. The packaging method according to claim 4, characterized in that, The insulating layer is burned off using a laser drill to form the first opening, and the metal layer is etched using an etching solution to form the first groove.
6. The packaging method according to claim 4, characterized in that, The method of creating a cavity in the core board, the cavity penetrating the metal layer and the insulating layer, further includes: The location of the cutting groove to be opened is determined on the core plate; According to the location of the cutting path to be opened, a second opening is provided on the insulating layer on one side of the metal layer; According to the second opening position, a second slot is provided on the metal layer, the second slot is connected to the second opening and forms the cutting channel.
7. The packaging method according to claim 1, characterized in that, Before filling the cavity with a dielectric material to form a filling layer to fix the power device, the method further includes: using adhesive tape to bond the power device to the metal layer.
8. The packaging method according to claim 1, characterized in that, The encapsulation method further includes: The power device is fan-out processed.
9. A circuit board, characterized in that, The circuit board, manufactured by the packaging method according to any one of claims 1 to 8, includes a core board, the core board including a metal layer and an insulating layer disposed on at least one side of the metal layer, the core board having a cavity penetrating the metal layer and the insulating layer, and a power device being embedded in the cavity.
10. The circuit board according to claim 9, characterized in that, The core board has a filling layer that fills the cavity to fix the power device.