Gallium nitride device

Abstract

The invention provides a gallium nitride device. The gallium nitride device comprises a substrate layer; the GaN channel layer is positioned on the surface of the substrate layer; the barrier layer is positioned on the surface of the GaN channel layer; the source electrode metal and the drain electrode metal are located at the two ends of the barrier layer respectively; the P-GaN region is located on the barrier layer and located between the source electrode metal and the drain electrode metal, the P-GaN region is formed by stacking at least two P-GaN layers, and the sides, close to the drain electrode metal, of the adjacent P-GaN layers are in a step shape; the field plate is located between the P-GaN region and the drain electrode metal, and the field plate is located on the barrier layer and extends to the position above the bottommost P-GaN layer of the P-GaN region; and the gate metal is positioned on the P-GaN layer on the topmost layer of the P-GaN region.

Description

Technical Field

[0001] This invention belongs to the field of gallium nitride device technology, and specifically relates to a gallium nitride device. Background Technology

[0002] With the continuous development of semiconductor process technology, gallium nitride (GaN) HEMTs (High Electron Mobility Transistors) have made significant progress in high-power microwave applications. GaN HEMTs are typically depletion-mode devices, meaning they are in the on-state when the threshold voltage Vth < 0V and the gate voltage Vg = 0V. To ensure circuit safety and simplify circuitry, normally-off devices, i.e., enhancement-mode devices, are preferred in practical applications. GaN devices using P-GaN cap technology have easily controllable threshold voltages, good breakdown characteristics, and high device stability, making them the mainstream technology for enhancement-mode GaN devices in the market. However, GaN devices using conventional P-GaN cap technology still suffer from concentrated electric field lines on the gate electrode side and high electric field spikes at the channel, affecting the device's breakdown characteristics and causing current collapse problems. Summary of the Invention

[0003] In view of this, the object of the present invention is to provide a gallium nitride device to improve the voltage withstand level of gallium nitride devices.

[0004] This invention provides a gallium nitride device, comprising:

[0005] basal layer;

[0006] A GaN channel layer located above the substrate layer;

[0007] A barrier layer located above the GaN channel layer;

[0008] The source metal and drain metal are located at opposite ends of the barrier layer, respectively;

[0009] The P-GaN region is located above the barrier layer and between the source metal and the drain metal. The P-GaN region is composed of at least two stacked P-GaN layers. On the side closer to the drain metal, the adjacent P-GaN layers are stepped.

[0010] The gate metal located above the topmost P-GaN layer in the P-GaN region;

[0011] A field plate is located between the P-GaN region and the drain metal. The field plate is located above the barrier layer and extends above the bottommost P-GaN layer of the P-GaN region. The field plate is isolated from the P-GaN region and the barrier layer by a first dielectric layer.

[0012] Furthermore, it also includes a first etch barrier layer located between adjacent P-GaN layers.

[0013] Furthermore, the material of the first etch barrier layer is AlGaN or AlN.

[0014] Furthermore, it also includes a second etch barrier layer located between the P-GaN region and the barrier layer.

[0015] Furthermore, the material of the second etch barrier layer is AlGaN or AlN.

[0016] Furthermore, the material of the first dielectric layer is silicon nitride.

[0017] Furthermore, the gate metal extends to one side of the drain metal onto the bottommost P-GaN layer of the P-GaN region.

[0018] Furthermore, a second dielectric layer is provided between the gate metal and the bottommost P-GaN layer of the P-GaN region.

[0019] Furthermore, the material of the second dielectric layer is silicon nitride or aluminum oxide.

[0020] Furthermore, the P-GaN region is located on the side near the source metal, and the adjacent P-GaN layers are stepped; the gate metal extends towards the source metal to the bottommost P-GaN layer of the P-GaN region.

[0021] The gallium nitride device of the present invention, firstly, the P-GaN region is composed of at least two stacked P-GaN layers in a stepped shape, resulting in a longer current channel length and making it difficult for the source and drain to cross-connect; secondly, a first etch barrier layer is provided between adjacent P-GaN layers, which can precisely control the thickness of each P-GaN layer and accurately control the shape of the formed step; thirdly, the gate metal extends towards the drain metal side to the bottom P-GaN layer of the P-GaN region as a gate field plate, which can reduce the peak electric field at the edge of the P-GaN region near the drain metal side and improve the breakdown voltage of the gallium nitride device; finally, the field plate structure can reduce the peak electric field at the edge of the P-GaN region near the drain metal side, further improving the breakdown voltage of the gallium nitride device. Attached Figure Description

[0022] Figure 1 This is a cross-sectional structural schematic diagram of the first embodiment of the gallium nitride device provided by the present invention;

[0023] Figure 2 This is a cross-sectional structural schematic diagram of the second embodiment of the gallium nitride device provided by the present invention;

[0024] Figure 3 This is a cross-sectional structural schematic diagram of the third embodiment of the gallium nitride device provided by the present invention;

[0025] Figure 4 This is a cross-sectional structural schematic diagram of the fourth embodiment of the gallium nitride device provided by the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention are within the scope of protection of the present invention.

[0027] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an" or "a" and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "connected" or "linked" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up," "down," "left," "right," etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship also changes accordingly.

[0028] Figure 1 This is a cross-sectional structural schematic diagram of an embodiment of a gallium nitride device provided by the present invention, as shown below. Figure 1 As shown, the gallium nitride device of the present invention includes a substrate layer 101, which typically includes a substrate layer such as silicon or silicon carbide, an AlN nucleation layer, an AlGaN buffer layer, etc. A channel layer 102 is located above the substrate layer 101, and the material of the channel layer 102 is typically GaN. A barrier layer 103 is located above the channel layer 102, and the material of the barrier layer 103 is typically AlGaN. A source metal 104 and a drain metal 105 are located at opposite ends of the barrier layer 103, i.e., the source metal 104 is located at one end of the barrier layer 103, and the drain metal 105 is located at the other end of the barrier layer 103.

[0029] A P-GaN region 106 is located above the barrier layer 103 and between the source metal 104 and the drain metal 105. The P-GaN region 106 is composed of at least two stacked P-GaN layers. In this embodiment, the P-GaN region 106 is composed of a first P-GaN layer 106a and a second P-GaN layer 106b. Adjacent P-GaN layers are stepped on the side near the drain metal 105, that is, the first P-GaN layer 106a and the second P-GaN layer 106b are stepped on the side near the drain metal 105. In other words, the extension length of the second P-GaN layer 106b is greater than the extension length of the first P-GaN layer 106a. The second P-GaN layer 106b is closer to the drain metal 105 than the first P-GaN layer 106a. A gate metal 108 is provided above the topmost P-GaN layer (i.e., the first P-GaN layer 106a) of the P-GaN region 106.

[0030] A first etch barrier layer 107a is provided between adjacent P-GaN layers in the P-GaN region 106. Specifically, a first etch barrier layer 107a is provided between the first P-GaN layer 106a and the second P-GaN layer 106b. The material of the first etch barrier layer 107a is preferably AlGaN or AlN, and its thickness is preferably 2-10 nanometers. By providing the first etch barrier layer 107a between adjacent P-GaN layers, the thickness of each P-GaN layer can be precisely controlled through the growth process. Furthermore, when etching the first P-GaN layer 106a, etching stops at the first etch barrier layer 107a, which protects the underlying P-GaN layer from being etched, thereby accurately controlling the shape of the formed step. At the same time, since the first etch barrier layer 107a is made of a III-V group material and is relatively thin, it does not affect the gate control capability of the gallium nitride device.

[0031] A second etch barrier layer 107b is provided between the P-GaN region 106 and the barrier layer 103. The material of the second etch barrier layer 107b is preferably AlGaN or AlN, and its thickness is preferably 2-10 nanometers. By providing the second etch barrier layer 107b, the barrier layer 103 can be prevented from being etched when the P-GaN region 106 is etched.

[0032] A field plate 110 is further disposed between the P-GaN region 106 and the drain metal 105. The field plate 110 is located above the barrier layer 103 and extends above the bottommost P-GaN layer (i.e., the second P-GaN layer 106b) of the P-GaN region 106. The field plate 110 is isolated from the P-GaN region 106 and the barrier layer 103 by a first dielectric layer 111, which is typically made of silicon nitride. The field plate 110 is electrically connected to the source metal 104, which can reduce the peak electric field at the edge of the P-GaN region 106 near the drain metal 105 and improve the breakdown voltage of the gallium nitride device.

[0033] Figure 2 This is a cross-sectional structural schematic diagram of a second embodiment of a gallium nitride device provided by the present invention, as shown below. Figure 2 As shown, the gallium nitride device of the present invention includes a substrate layer 201, a channel layer 202, a barrier layer 203, a source metal 204, a drain metal 205, a P-GaN region 206 (including a first P-GaN layer 206a and a second P-GaN layer 206b), a first etch stop layer 207a, a second etch stop layer 207b, a field plate 210, and a first dielectric layer 211. Figure 1 The difference between the gallium nitride device structure shown is that... Figure 2 The gate metal 208 of the gallium nitride device shown extends from the topmost P-GaN layer (i.e., the first P-GaN layer 206a) of the P-GaN region 206 to the bottommost P-GaN layer (i.e., the second P-GaN layer 206b) of the P-GaN region 206, towards the drain metal 205. In this way, the gate metal 208 extends to the second P-GaN layer 206b as a gate field plate, which can reduce the peak electric field at the edge of the P-GaN region 206 near the drain metal 205 and improve the breakdown voltage of the gallium nitride device.

[0034] Figure 3 This is a cross-sectional structural schematic diagram of a gallium nitride device according to a third embodiment of the present invention, as shown below. Figure 3 As shown, the gallium nitride device of the present invention includes a substrate layer 301, a channel layer 302, a barrier layer 303, a source metal 304, a drain metal 305, a P-GaN region 306 (including a first P-GaN layer 306a and a second P-GaN layer 306b), a first etch stop layer 307a, a second etch stop layer 307b, a field plate 310, and a first dielectric layer 311. Figure 2 The difference between the gallium nitride device structure shown is that... Figure 3The gate metal 308 of the gallium nitride device shown extends to the drain metal 305 and then onto the second P-GaN layer 306b. A dielectric layer 309 is provided between the gate metal 308 and the bottommost P-GaN layer (i.e., the second P-GaN layer 306b) of the P-GaN region 306. The material of the dielectric layer 309 is usually silicon nitride or aluminum oxide, which can reduce the gate leakage current and increase the gate breakdown voltage.

[0035] Figure 4 This is a cross-sectional structural schematic diagram of a gallium nitride device according to Embodiment 4 of the present invention, as shown below. Figure 4 As shown, the gallium nitride device of the present invention includes a substrate layer 401, a channel layer 402, a barrier layer 403, a source metal 404, a drain metal 405, a P-GaN region 406 (including a first P-GaN layer 406a and a second P-GaN layer 406b), a first etch stop layer 407a, a second etch stop layer 407b, a field plate 410, and a first dielectric layer 411. Figure 3 The difference between the gallium nitride device structure shown is that... Figure 4 In the gallium nitride device shown, the adjacent P-GaN layers (i.e., the first P-GaN layer 406a and the second P-GaN layer 406b) of the P-GaN region 406 also have a stepped shape on the side near the source metal 404. That is, the second P-GaN layer 406b is closer to the source metal 404 than the first P-GaN layer 406. The gate metal 408 extends towards the source metal 404 onto the bottommost P-GaN layer (i.e., the second P-GaN layer 406b) of the P-GaN region 406, which can reduce the on-resistance of the gallium nitride device.

[0036] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A gallium nitride device, characterized in that, include: basal layer; A GaN channel layer located above the substrate layer; A barrier layer located above the GaN channel layer; The source metal and drain metal are located at opposite ends of the barrier layer, respectively; The P-GaN region is located above the barrier layer and between the source metal and the drain metal. The P-GaN region is composed of at least two stacked P-GaN layers. On the side closer to the drain metal, the adjacent P-GaN layers are stepped. The gate metal located above the topmost P-GaN layer in the P-GaN region; A field plate is located between the P-GaN region and the drain metal. The field plate is located above the barrier layer and extends above the bottommost P-GaN layer of the P-GaN region. The field plate is isolated from the P-GaN region and the barrier layer by a first dielectric layer.

2. The gallium nitride device according to claim 1, characterized in that, It also includes a first etch barrier layer located between adjacent P-GaN layers.

3. The gallium nitride device according to claim 2, characterized in that, The material of the first etching barrier layer is AlGaN or AlN.

4. The gallium nitride device according to claim 1, characterized in that, It also includes a second etch barrier layer located between the P-GaN region and the barrier layer.

5. The gallium nitride device according to claim 4, characterized in that, The materials of the second etching barrier layer are AlGaN or AlN.

6. The gallium nitride device according to claim 1, characterized in that, The material of the first dielectric layer is silicon nitride.

7. The gallium nitride device according to claim 1, characterized in that, The gate metal extends to one side of the drain metal onto the bottommost P-GaN layer of the P-GaN region.

8. The gallium nitride device according to claim 7, characterized in that, A second dielectric layer is provided between the gate metal and the bottommost P-GaN layer of the P-GaN region.

9. The gallium nitride device according to claim 8, characterized in that, The material of the second dielectric layer is silicon nitride or aluminum oxide.

10. The gallium nitride device according to claim 1, characterized in that, The P-GaN region is located on the side closest to the source metal, with adjacent P-GaN layers forming a stepped structure. The gate metal extends towards the source metal to the bottommost P-GaN layer of the P-GaN region.

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