Approximate calculation method for signal processing and related device
By determining the approximate number of bits P in the optical fiber communication system, generating an approximate partial product array and adding compensation values, the problem of low efficiency in traditional fixed-point multiplication is solved, achieving efficient approximate calculation and improving the accuracy and energy efficiency of signal processing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUAWEI TECH CO LTD
- Filing Date
- 2024-11-13
- Publication Date
- 2026-05-15
AI Technical Summary
In existing fiber optic communication systems, the energy efficiency of digital signal processors is costly to achieve. Traditional fixed-point multiplication is inefficient due to the need for approximation after calculation. Existing approximation calculation techniques suffer from low accuracy and are difficult to apply in engineering.
By obtaining the first and second multipliers, the approximate number of bits P is determined based on the signal processing error, an approximate partial product array is generated, and partial product calculation is performed based on Booth coding. Low-weight partial products are omitted, and compensation values are added to improve calculation accuracy and efficiency.
It improves the accuracy and efficiency of approximate calculations, reduces the demand for computing resources, optimizes the utilization of hardware resources, and achieves gains in performance, power consumption, and area.
Smart Images
Figure CN122044512A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of digital signal processing technology, and in particular to an approximate calculation method and related apparatus for signal processing. Background Technology
[0002] Digital signal processing (DSP) plays a crucial role in modern fiber optic communication systems. With the increasing demands for data transmission, key parameters such as modulation depth and baud rate are rising, leading to stronger linear and nonlinear effects introduced by fiber optic channels and optoelectronic devices. This places ever-increasing demands on the processing power of DSPs, and consequently, increases the cost of implementing them. Achieving these DSP requirements with high energy efficiency is one of the major challenges currently facing optical communication chips.
[0003] In optical digital signal processing (oDSP) systems, each signal processing module is essentially a combination of mathematical formulas. Since the bandwidth of fiber optic communication systems is much greater than the chip's clock frequency, these mathematical formulas often need to be instantiated hundreds of times. Therefore, implementing an oDSP chip with high energy efficiency essentially means implementing dozens of mathematical formulas (mainly multiplication and addition) with high energy efficiency. Approximate computation is a very effective means of implementing high-efficiency multiplication and addition circuits. Taking multiplication circuits as an example, traditional fixed-point multiplication truncates the product after the multiplication operation to prevent bit width expansion. This process is essentially an approximation of the exact multiplication result. That is, traditional fixed-point multiplication incurs the cost of exact multiplication but obtains an approximate multiplication result. Unlike traditional fixed-point multiplication, approximate computation advances the approximation process to the multiplication calculation process, thus obtaining an approximate multiplication result at a lower cost than exact multiplication, thereby gaining performance power area (PPA) benefits. Currently, many approximate computation-related technical solutions exist, but they often suffer from low efficiency and low accuracy, making them difficult to apply in engineering. Summary of the Invention
[0004] This application provides an approximate calculation method and related apparatus for signal processing, which can improve the efficiency and accuracy of approximate calculation.
[0005] The first aspect of this application provides an approximate calculation method for signal processing, including:
[0006] Obtain the first and second multipliers;
[0007] Based on the signal processing error, the approximate number of bits P is determined, where P is an integer greater than 0;
[0008] Based on the approximate number of bits, the first and second multipliers are partially multiplied by Booth coding to generate an approximate partial product array. The number of bits in the partial product array is not less than P.
[0009] The approximate partial product array is summed bit by bit to obtain the calculation result.
[0010] The approximate calculation method for signal processing provided in this application first determines an approximate bit depth based on the signal processing error. This approximate bit depth reflects the allowable error level of the current signal processing; the larger the approximate bit depth, the larger the allowable error. Selecting a reasonable approximate bit depth based on the signal processing error ensures the accuracy of the approximate calculation. Then, an approximate partial product array is generated based on the approximate bit depth. The number of bits in each partial product in the approximate partial product array is not less than the approximate bit depth, thus saving computational resources during the generation of the partial product array. At the same time, when performing addition operations on the approximate partial product array, since the partial products in the approximate partial product array are reduced by a portion compared to the complete partial product array, computational resources are further saved, thereby improving computational efficiency.
[0011] In one possible implementation, before performing bit-by-bit addition on the approximate partial product array to obtain the calculation result, the following is also included:
[0012] The compensation value is determined based on the approximate number of digits;
[0013] Add the compensation value to the approximate partial product array.
[0014] In one possible implementation, the approximate partial product array is a complete partial product array that does not compute the low-weight partial product. The complete partial product array is generated by the first and second multipliers based on Booth coding. The low-weight partial product is the partial product in the first K rows of the complete partial product array with a number of bits not greater than P, where K is the largest integer not greater than P / 2.
[0015] In one possible implementation, the compensation value is specifically added to the P-th bit in the approximate partial product array.
[0016] In one possible implementation, there are K compensation values, all of which are added to the Pth bit of the approximate partial product array. The compensation values are specifically obtained by performing logical operations based on the bit values of the first multiplier corresponding to the low-weight partial product.
[0017] In one possible implementation, the first compensation value is a logical OR and logical AND of the first and second bits of the first multiplier;
[0018] The i-th compensation value Cp(i) is a logical OR-OR-AND of x(2i+1), x(2i), and x(2i-1), where x(i) indicates the i-th bit in the first multiplier, and i is an integer greater than 1. In one possible implementation,
[0019] Both the first multiplier and the second multiplier are complex numbers. The first multiplier includes the first real part coefficient and the first imaginary part coefficient, and the second multiplier includes the second real part coefficient and the second imaginary part coefficient.
[0020] Based on the approximate number of bits, a partial product calculation based on Booth coding is performed on the first and second multipliers to generate an approximate partial product array, including:
[0021] Based on the approximate number of bits, partial product calculation based on Booth coding is performed on the first and second multipliers to generate a first approximate partial product array corresponding to the first real part coefficient and the second real part coefficient, a second approximate partial product array corresponding to the first imaginary part coefficient and the second imaginary part coefficient, a third approximate partial product array corresponding to the first real part coefficient and the second imaginary part coefficient, and a fourth approximate partial product array corresponding to the second real part coefficient and the second imaginary part coefficient. The first approximate partial product array, the second approximate partial product array, the third approximate partial product array, and the fourth approximate partial product array belong to the approximate partial product array.
[0022] The partial product in the second approximate partial product array is calculated by inverting the first and second imaginary coefficients.
[0023] By performing bitwise summation on the approximate partial product array, the calculation results are obtained, including:
[0024] The real part coefficients of the calculation result are obtained by adding the first approximate partial product array and the second approximate partial product array bit by bit.
[0025] The imaginary coefficients of the calculated result are obtained by adding the third and fourth approximate partial product arrays bit by bit.
[0026] In one possible implementation, the first multiplier includes N first sub-multipliers, and the second multiplier includes N second sub-multipliers;
[0027] Based on the approximate number of bits, a partial product calculation based on Booth coding is performed on the first and second multipliers to generate an approximate partial product array, including:
[0028] Based on the approximate number of bits, perform partial product calculation based on Booth coding for N first multipliers and their corresponding N second sub-multipliers to generate N approximate sub-partial product arrays. The N approximate sub-partial product arrays belong to the approximate partial product array.
[0029] By performing bitwise summation on the approximate partial product array, the calculation results are obtained, including:
[0030] The result is obtained by adding the N approximate sub-partial arrays bit by bit.
[0031] A second aspect of this application provides an approximate multiplier, comprising:
[0032] The acquisition module is used to obtain the first and second multipliers;
[0033] An approximation module is used to determine the approximate number of bits P based on the signal processing error, where P is an integer greater than 0;
[0034] The encoding module is used to perform partial product calculation based on Booth coding on the first and second multipliers based on the approximate number of bits, and generate an approximate partial product array, wherein the number of bits of the partial product in the approximate partial product array is not less than P;
[0035] The adder module is used to add the approximate partial product array bit by bit to obtain the calculation result.
[0036] One possible implementation also includes: a compensation module for determining a compensation value based on the approximate number of digits; and adding the compensation value to the approximate partial product array.
[0037] In one possible implementation, the approximate partial product array is a partial product array that does not compute the low-weight partial product. The partial product array is generated by the first and second multipliers based on Booth coding. The low-weight partial product is the partial product located in the first K rows of the partial product array, with a bit length not exceeding P, where K is the largest integer not greater than P / 2. In another possible implementation, the compensation value is specifically added to the P-th bit of the approximate partial product array.
[0038] In one possible implementation, there are K compensation values, all of which are added to the Pth bit of the approximate partial product array. The compensation values are specifically obtained by performing logical operations based on the bit values of the first multiplier corresponding to the low-weight partial product.
[0039] In one possible implementation,
[0040] The first compensation value is a logical OR and logical AND of the first and second bits of the first multiplier;
[0041] The i-th compensation value Cp(i) is a logical OR-OR-logical AND of x(2i+1), x(2i), and x(2i-1), where x(i) indicates the i-th bit in the first multiplier, and i is an integer greater than 1 and not greater than K.
[0042] In one possible implementation,
[0043] Both the first multiplier and the second multiplier are complex numbers. The first multiplier includes the first real part coefficient and the first imaginary part coefficient, and the second multiplier includes the second real part coefficient and the second imaginary part coefficient.
[0044] Based on the approximate number of bits, a partial product calculation based on Booth coding is performed on the first and second multipliers to generate an approximate partial product array, including:
[0045] Based on the approximate number of bits, partial product calculation based on Booth coding is performed on the first and second multipliers to generate a first approximate partial product array corresponding to the first real part coefficient and the second real part coefficient, a second approximate partial product array corresponding to the first imaginary part coefficient and the second imaginary part coefficient, a third approximate partial product array corresponding to the first real part coefficient and the second imaginary part coefficient, and a fourth approximate partial product array corresponding to the second real part coefficient and the second imaginary part coefficient. The first approximate partial product array, the second approximate partial product array, the third approximate partial product array, and the fourth approximate partial product array belong to the approximate partial product array.
[0046] The partial product in the second approximate partial product array is calculated by inverting the first and second imaginary coefficients.
[0047] By performing bitwise summation on the approximate partial product array, the calculation results are obtained, including:
[0048] The real part coefficients of the calculation result are obtained by adding the first approximate partial product array and the second approximate partial product array bit by bit.
[0049] The imaginary coefficients of the calculated result are obtained by adding the third and fourth approximate partial product arrays bit by bit.
[0050] In one possible implementation,
[0051] The first multiplier consists of N first sub-multipliers, and the second multiplier consists of N second sub-multipliers;
[0052] Based on the approximate number of bits, a partial product calculation based on Booth coding is performed on the first and second multipliers to generate an approximate partial product array, including:
[0053] Based on the approximate number of bits, perform partial product calculation based on Booth coding for N first multipliers and their corresponding N second sub-multipliers to generate N approximate sub-partial product arrays. The N approximate sub-partial product arrays belong to the approximate partial product array.
[0054] By performing bitwise summation on the approximate partial product array, the calculation results are obtained, including:
[0055] The result is obtained by adding the N approximate sub-partial arrays bit by bit.
[0056] A third aspect of this application provides a computing device, including a processor;
[0057] The processor is used to execute computer programs or computer instructions in memory to perform the methods described in the first aspect above.
[0058] In one possible implementation, memory is also included.
[0059] The fourth aspect of this application provides a computer program product containing instructions that, when executed on a computer, cause the computer to perform the implementation as described in the first aspect.
[0060] The fifth aspect of this application provides a computer-readable storage medium including computer instructions that, when executed on a computer, cause the computer to perform the implementation as described in the first aspect.
[0061] The beneficial effects of the technical solutions provided in the second to fifth aspects above can be referred to the beneficial effects of the technical solutions in the first aspect, and will not be repeated here. Attached Figure Description
[0062] Figure 1 This is a flowchart of the approximate calculation method for signal processing provided in the embodiments of this application;
[0063] Figure 2 This is a flowchart of the approximate calculation method for signal processing provided in the embodiments of this application;
[0064] Figures 3 to 6 This is a schematic diagram of a partial product array with different approximate bit depths, provided in an embodiment of this application.
[0065] Figure 7 This is a schematic diagram of a partial product array of the real part in complex multiplication provided in an embodiment of this application;
[0066] Figure 8 This is a schematic diagram of a partial product array of the imaginary part in complex multiplication provided in an embodiment of this application;
[0067] Figure 9 This is a schematic diagram of a partial product array of multiple products added together, provided in an embodiment of this application.
[0068] Figure 10 This is a schematic diagram of the structure of the approximate multiplier provided in the embodiments of this application;
[0069] Figure 11 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation
[0070] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application are described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Those skilled in the art will understand that with the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.
[0071] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules is not necessarily limited to those explicitly listed, but may include other steps or modules not explicitly listed or inherent to such processes, methods, products, or devices. The naming or numbering of steps appearing in this application does not imply that the steps in the method flow must be performed in the chronological / logical order indicated by the naming or numbering. The execution order of named or numbered process steps can be changed according to the desired technical purpose, as long as the same or similar technical effect is achieved. The division of units in this application is a logical division. In practical applications, there may be other division methods. For example, multiple units may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the shown or discussed mutual coupling, direct coupling, or communication connection may be through some interface, and the indirect coupling or communication connection between units may be electrical or other similar forms, none of which are limited in this application. Furthermore, the units or sub-units described as separate components may or may not be physically separated, may or may not be physical units, or may be distributed among multiple circuit units. Some or all of the units can be selected to achieve the purpose of the solution in this application according to actual needs.
[0072] Digital signal processing (DSP) plays a crucial role in modern fiber optic communication systems. With the increasing demands for data transmission, key parameters such as modulation depth and baud rate are rising, leading to stronger linear and nonlinear effects introduced by fiber optic channels and optoelectronic devices. This places greater demands on the processing power of DSPs, while simultaneously increasing the cost of implementing them. Achieving these DSP requirements with high energy efficiency is one of the main challenges currently facing optical communication chips.
[0073] In an oDSP system, each signal processing module is essentially a combination of a series of mathematical formulas. Since the bandwidth of an optical fiber communication system is much greater than the chip's clock frequency, these mathematical formulas often need to be instantiated hundreds of times. Therefore, implementing an oDSP chip with high energy efficiency essentially means implementing dozens of mathematical formulas (mainly multiply-accumulate) with high energy efficiency. Approximate calculation is a very effective means of implementing high-efficiency multiply-accumulate circuits.
[0074] Broadly speaking, the DSP field encompasses numerous complex and sophisticated operations, including many approximation methods. These approximation operations include, but are not limited to, quantizing analog signals into fixed-point numbers with finite bit widths, and truncating decimals during fixed-point arithmetic operations. The emergence of these approximation techniques often stems from hardware resource constraints and the pursuit of computational efficiency. Therefore, approximation processing is ubiquitous in engineering applications, and its existence is inevitable. The key to approximation processing is whether the approximate result meets the system's performance requirements.
[0075] Taking multiplication circuits as an example, in traditional fixed-point multiplication, after the multiplication operation is completed, in order to prevent the bit width of the result from expanding indefinitely, the low-order bits of the product are usually truncated. This process is essentially an approximation of the exact multiplication result. That is, traditional fixed-point multiplication pays the price of exact multiplication, but the final result is an approximation, without improving computational efficiency.
[0076] Unlike traditional fixed-point multiplication, approximation computation incorporates the approximation process into the multiplication calculation process. Instead of performing the approximation after the multiplication operation is complete, it integrates the approximation process into the multiplication calculation itself. This approximation method not only significantly improves computational efficiency and reduces power consumption but also optimizes the utilization of hardware resources to a certain extent, thereby achieving benefits in performance, power consumption, and area (PPA benefits).
[0077] To improve the efficiency and accuracy of approximate calculations, embodiments of this application provide an approximate calculation method and related apparatus for signal processing. By deleting low-weight partial products and determining compensation values based on the deleted low-weight partial products and adding them to the partial product array, the amount of data that needs to be calculated is reduced, thereby improving the calculation efficiency. At the same time, the deleted calculation data is compensated, so the calculation results have high accuracy.
[0078] The approximate calculation method for signal processing provided in the embodiments of this application will now be described with reference to the accompanying drawings. Figure 1 , Figure 1 A flowchart of the approximate calculation method for signal processing provided in this application embodiment includes:
[0079] 101. Obtain the first and second multipliers.
[0080] It is understood that the scenario applied in this application embodiment is an approximate multiplication calculation scenario. Therefore, it is first necessary to obtain two numbers to be multiplied, namely the first multiplier and the second multiplier. It is understood that one of the first and second multipliers is the multiplier, and the other is the multiplicand. In approximate calculations in the field of signal processing, the multiplier and multiplicand can be various types of data. For example, the multiplier and multiplicand can be the values of discrete-time signals. In filtering operations, the filter coefficients (multipliers) are multiplied by samples of the input signal (multiplicand). In DSPs, continuous-time signals are typically sampled to convert them into discrete-time signals. These sampled values can be used as multipliers and multiplicands for approximate calculations. In signal processing applications, signals are represented as complex numbers in the frequency domain; therefore, the multiplier and multiplicand can be complex numbers used to implement operations such as Fourier transforms, filtering, and modulation. In adaptive filtering, neural networks, and machine learning algorithms, the multiplier may represent filter coefficients, neural network weights, or model parameters, while the multiplicand may be the input signal or feature values, etc.
[0081] 102. Based on signal processing error, determine the approximate number of bits P, where P is an integer greater than 0.
[0082] Understandably, the acceptable approximate multiplication error varies across different signal processing scenarios. Scenarios with higher precision requirements tolerate smaller errors, while those with lower precision requirements can accommodate larger errors. Therefore, based on the specific application and the system's error requirements, the acceptable error range for the current scenario can be determined, thus establishing an approximate number of bits.
[0083] 103. Calculate the partial product of the first and second multipliers based on Booth coding based on the approximate number of bits, and generate an approximate partial product array. The number of bits of the partial product in the approximate partial product array is not less than P.
[0084] Booth coding is an optimization algorithm for multiplication operations, designed to reduce the number of partial products in multiplication, thereby speeding up the multiplication process and potentially reducing the required hardware resources. Specifically, the core idea of Booth coding is to reduce the number of partial products that must be calculated in multiplication operations by converting the multiplicand into a specific encoded form.
[0085] A partial product array is an intermediate result representation in a Booth-coded multiplier. In a Booth-coded multiplier, the multiplier is encoded and multiplied by the multiplicand to generate a series of partial products. These partial products are arranged in a two-dimensional array according to their positions in the original multiplier. For example, suppose we have an 8-bit multiplier X and an 8-bit multiplicand Y (in practical applications, the multiplier may be extended with higher bits to have an even number of bits). After Booth coding, we might obtain a series of partial products. These partial products will be arranged in an M×N / 2 or M×(N / 2+1) partial product array according to their positions in the multiplier, where N is the number of bits in the multiplier (adding 1 when the multiplier is odd introduces extra partial products based on Booth coding); and M is the number of bits in the multiplicand plus 1.
[0086] In this embodiment of the application, the number of bits in the partial product in the generated approximate partial product array is not less than the number of approximate bits P. That is, when generating each partial product in the partial product array, only the partial product with an approximate number of bits greater than or equal to P is calculated.
[0087] Understandably, in conventional techniques, the partial product array generated based on Booth coding is a complete partial product array, meaning that the calculation of the first and second multipliers requires bit-by-bit computation. However, in this embodiment, the generated partial product array is an approximate partial product array, meaning that the partial products with lower bit depths (below the approximate bit depth P) do not need to be calculated, thus saving computational resources. Furthermore, since the approximate bit depth is determined based on signal processing errors, reasonably selecting the approximate bit depth according to the signal processing errors will not affect the accuracy of the approximate calculation.
[0088] 104. The approximate partial product array is summed bit by bit to obtain the calculation result.
[0089] It is understandable that performing a conventional bitwise addition step on the approximate partial product array yields the final calculation result, which is the approximate calculation result of the first and second multipliers in this embodiment of the application.
[0090] The approximate calculation method for signal processing provided in this application first determines an approximate bit depth based on the signal processing error. This approximate bit depth reflects the allowable error level of the current signal processing; the larger the approximate bit depth, the larger the allowable error. Selecting a reasonable approximate bit depth based on the signal processing error ensures the accuracy of the approximate calculation. Then, an approximate partial product array is generated based on the approximate bit depth. The number of bits in each partial product in the approximate partial product array is not less than the approximate bit depth, thus saving computational resources during the generation of the partial product array. At the same time, when performing addition operations on the approximate partial product array, since the partial products in the approximate partial product array are reduced by a portion compared to the complete partial product array, computational resources are further saved, thereby improving computational efficiency.
[0091] In one possible implementation, please refer to Figure 2 , Figure 2 A flowchart of the approximate calculation method for signal processing provided in this application embodiment includes:
[0092] 201. Obtain the first and second multipliers;
[0093] 202. Based on signal processing error, determine the approximate number of bits P, where P is an integer greater than 0;
[0094] 203. Calculate the partial product of the first and second multipliers based on Booth coding based on the approximate number of bits, and generate an approximate partial product array. The number of bits of the partial product in the approximate partial product array is not less than P.
[0095] It is understood that steps 201 to 203 above correspond to this application. Figure 1 For a detailed description of steps 101 to 103 in the corresponding embodiments, please refer to the above text, which will not be repeated here.
[0096] 204. Determine the compensation value based on the approximate number of digits;
[0097] 205. Add the compensation value to the approximate partial product array.
[0098] It is understood that, in this embodiment of the application, in order to further ensure the accuracy of the approximate calculation, a compensation value can be added to the approximate partial product array to compensate for the partial products in the approximate partial product array that were omitted from the calculation relative to the complete partial product array. It is understood that, since the partial products in the approximate partial product array are all partial products with a number of digits not less than P, the compensation value can be specifically determined based on the partial products omitted by approximating the number of digits.
[0099] In one possible implementation, the approximate partial product array is a complete partial product array that does not compute the low-weight partial product. The complete partial product array is generated by the first and second multipliers based on Booth coding. The low-weight partial product is the partial product in the first K rows of the complete partial product array with a number of bits not greater than P, where K is the largest integer not greater than P / 2.
[0100] For easier understanding, please refer to Figures 3 to 6 , Figures 3 to 6 This is a schematic diagram of a partial product array with different approximate bit depths, as provided in the embodiments of this application.
[0101] exist Figures 3 to 6 In the example of a multiplier with 8 bits and a multiplicand with 9 bits, the complete partial product array obtained after Booth coding has 4 rows, with s1 to s3 being error correction bits.
[0102] like Figure 3 As shown, if the approximate number of bits P = 4, then in this complete partial product array, the partial product with no more than 4 bits is the low-weight partial product, which is... Figure 3 The partial product is represented by a black background. Similarly, as... Figure 5 As shown, if the approximate number of digits P = 6, then the partial product with no more than 6 digits is the low-weight partial product. Similarly, in... Figure 5 The partial product array is represented by a black background. Therefore, an approximate partial product array is a partial product array in which the partial products represented by the black background are omitted from a complete partial product array.
[0103] Furthermore, since the partial product array in this embodiment is generated based on Booth coding, two bits need to be offset between adjacent rows of the partial product array. Therefore, for a partial product array with an approximate odd number of bits, when the number of partial products in each row is less than 2 and the number of bits is not greater than P, it is not determined as a low-weight partial product.
[0104] In this embodiment of the application, the low-weight partial product is further restricted, requiring it not only to satisfy that the approximate number of digits is no greater than P, but also to satisfy that it is located in the first K rows, where K is P / 2 rounded down.
[0105] like Figure 4 As shown, given an approximate number of bits P = 5, then in this partial product array, the first K rows refer to... The partial product that simultaneously satisfies the condition of being located in the first two rows and having no more than 5 digits is the low-weight partial product, which is... Figure 4 The partial product is represented by a black background. Similarly, Figures 3 to 6 The low-weight partial products in the model all satisfy this requirement, which will not be elaborated here.
[0106] In one possible implementation, the compensation value can be added to the position in the partial product array corresponding to the approximate number of bits P, in place of all low-weight partial products for subsequent addition calculations.
[0107] Furthermore, when the low-weight partial product is a partial product located in the first K rows of the partial product array and with no more than P bits, the compensation value can specifically include K values. All K compensation values are added to the Pth bit in the approximate partial product array, specifically located in the Pth bit of the first K rows of the partial product array. The compensation value is obtained by performing logical operations based on the bit value of the multiplier corresponding to the low-weight partial product. The multiplier can be the first multiplier or the second multiplier.
[0108] The first compensation value is a logical OR and logical AND of the first and second bits of the multiplier.
[0109] The i-th compensation value Cp(i) is a logical OR or logical AND of x(2i+1), x(2i), and x(2i-1), where x(i) indicates the i-th bit in the multiplier, i is an integer greater than 0. Similarly, the multiplier includes the first multiplier and the second multiplier.
[0110] In this embodiment, the specific method for determining the compensation value is described. Specifically, when the number of compensation values corresponds to the number of rows containing the low-weight partial product, multiple compensation values can be divided into multiple rows containing the low-weight partial product, and the value of each row can be determined using an AND gate or an OR gate.
[0111] The compensation value in the first row can be a logical OR or logical AND operation between the first and second bits of the multiplier, i.e., ... Figure 3 For example, the compensation value CP0 in the first row can be either CP0 = x0|x1 or CP0 = x0 & x1.
[0112] Except for the first row, the compensation value CP(i) of the other rows is a logical OR or logical AND of x(2i+1), x(2i), and x(2i-1), that is: the compensation value CP(i) can be CP(i) = x(2i+1)|x(2i)|x(2i-1), or CP(i) = x(2i+1)&x(2i)&x(2i-1). Figure 3 For example, the compensation value CP1 in the second row can be CP1 = x3|x2|x1 or CP1 = x3&x2&x1, and the compensation value CP2 in the third row can be CP2 = x5|x4|x3 or CP2 = x5&x4&x3.
[0113] 206. The approximate partial product array is summed bit by bit to obtain the calculation result.
[0114] In one possible implementation, both the first multiplier and the second multiplier are complex numbers. The first multiplier includes a first real part coefficient and a first imaginary part coefficient, and the second multiplier includes a second real part coefficient and a second imaginary part coefficient.
[0115] At this point, step 203 specifically includes:
[0116] Based on the approximate number of bits, partial product calculation based on Booth coding is performed on the first and second multipliers to generate a first approximate partial product array corresponding to the first real part coefficient and the second real part coefficient, a second approximate partial product array corresponding to the first imaginary part coefficient and the second imaginary part coefficient, a third approximate partial product array corresponding to the first real part coefficient and the second imaginary part coefficient, and a fourth approximate partial product array corresponding to the second real part coefficient and the second imaginary part coefficient. The first approximate partial product array, the second approximate partial product array, the third approximate partial product array, and the fourth approximate partial product array belong to the approximate partial product array.
[0117] Correspondingly, step 206 specifically includes:
[0118] The real part coefficients of the calculation result are obtained by adding the first approximate partial product array and the second approximate partial product array bit by bit.
[0119] The imaginary coefficients of the calculated result are obtained by adding the third and fourth approximate partial product arrays bit by bit.
[0120] Understandably, in coherent oDSP, signal processing is often done in the frequency domain, so complex multiplication accounts for the vast majority. The approximate calculation of complex multiplication follows similar steps to real multiplication, the difference being the generation of partial products. Assume the complex multiplication expression is (xi + kxj) * (yi + kyj) = xiyi - xjyj + k(xiyj + xjyi), where k is the imaginary unit. That is, complex multiplication is divided into real part operations (the difference between the two multiplications) and imaginary part operations (the sum of the two multiplications).
[0121] Please see Figure 7 and Figure 8 , Figure 7 This is a schematic diagram of a partial product array of the real part in complex number multiplication provided in an embodiment of this application. Figure 8 This is a schematic diagram of a partial product array of the imaginary part in complex multiplication provided in an embodiment of this application.
[0122] The principle is explained using an example where the multiplier has 8 bits, the multiplicand has 9 bits, and the approximate number of bits is 5. In practical applications, complex multiplication is approximate and applicable to any first or second multiplier with any number of bits and any approximate number of bits.
[0123] like Figure 7As shown, the partial product array of the real part of complex multiplication consists of the partial products of two real number multiplications. Here, `mii` represents the first partial product array composed of the partial products of `xi` and `yi`, and `mjj` represents the second partial product array composed of the partial products of `xj` and `yj`. It can be understood that the real part of complex multiplication is the difference between the two multiplications, requiring the partial products of `xj` and `yj` to be inverted. Therefore, the partial products of `xj` and `yj` are directly inverted, and appropriate compensation values are added to ensure the correctness of the output result. In this partial product array, the black background represents the low-weight partial product, which is omitted during the calculation of the approximate partial product array; the gray background represents the compensation value, which needs to be added to the approximate partial product array for subsequent addition calculations.
[0124] like Figure 8 As shown, the partial product array of the imaginary part of complex multiplication is similar to that of the partial product array of the real part of complex multiplication. Here, mij represents the third partial product array composed of the partial products of xi and yj, and mji represents the fourth partial product array composed of the partial products of xj and yi. Similarly, in this partial product array, the black background represents the low-weight partial products, which are omitted during the calculation of the approximate partial product array; the gray background represents the compensation values, which need to be added to the approximate partial product array for subsequent calculations.
[0125] The real part is obtained by combining the first and second approximate partial products and adding them digit by digit. The imaginary part is obtained by combining the third and fourth approximate partial products and adding them digit by digit.
[0126] In one possible implementation, the first multiplier includes N first sub-multipliers, and the second multiplier includes N second sub-multipliers;
[0127] At this point, step 203 specifically includes:
[0128] Based on the approximate number of bits, a partial product calculation based on Booth coding is performed on the first and second multipliers to generate an approximate partial product array, including:
[0129] Based on the approximate number of bits, perform partial product calculation based on Booth coding for N first multipliers and their corresponding N second sub-multipliers to generate N approximate sub-partial product arrays. The N approximate sub-partial product arrays belong to the approximate partial product array.
[0130] Correspondingly, step 206 specifically includes:
[0131] By performing bitwise summation on the approximate partial product array, the calculation results are obtained, including:
[0132] The result is obtained by adding the N approximate sub-partial arrays bit by bit.
[0133] Understandably, for short-range incoherent direct-modulation and direct-detection DSP systems, signal processing is often performed in the time domain, primarily involving time-domain finite impulse response (FIR) filtering. The output of an FIR filter is the convolution of the input signal and the filter's impulse response. The filter's impulse response consists of a series of coefficients (i.e., tap coefficients), which are multiplied by different delayed versions of the input signal and then summed to obtain the filter's output. The mathematical formula for an FIR filter can be viewed as the sum of multiple products: out = x0y0 + x1y1 + ... + xnyn. The approximate calculation of an FIR filter is similar to that of real number multiplication, the difference lying in the generation of partial products.
[0134] Please see Figure 9 , Figure 9 This is a schematic diagram of a partial product array of multiple products added together, provided in an embodiment of this application.
[0135] Taking an 8-bit multiplier, a 9-bit multiplicand, and an approximation bit depth of 5 as an example, where m0 represents the partial product of the data and coefficients at the 0th tap, and mn represents the partial product of the data and coefficients at the nth tap. In practical applications, approximate FIR is suitable for arbitrary bit widths, arbitrary approximation bit depths, and arbitrary number of taps.
[0136] Understandable, Figure 9 Each 4 rows in the array form a sub-partial product array, and the complete array consists of n sub-partial product arrays. In the generation of the corresponding approximate partial product array, the low-weight partial products (represented by a black background) are omitted.
[0137] The approximate calculation method for signal processing provided in this application does not approximate the partial products other than the low-weight partial product, and is therefore accurate. The low-weight partial product is determined based on the number of approximation bits selected according to system performance. Furthermore, adaptive compensation is applied to the approximate partial product array obtained after omitting the low-weight partial product, further reducing calculation errors. Therefore, from the perspective of computational accuracy, the approximation scheme provided in this application achieves computational accuracy comparable to the baseline fixed-point version, without compromising system performance.
[0138] In practical applications, in a DSP system, after replacing some complex multiplications with the approximate multiplications provided in the embodiments of this application, the performance fluctuation is between -0.01 and 0.01. Since the simulation system itself has certain performance fluctuations, the performance can be considered to remain unchanged after replacing the approximate calculations.
[0139] Furthermore, the approximate calculation method for signal processing provided in this application embodiment does not require generating low-weight partial products, and therefore does not require compression of low-weight partial products, resulting in benefits in area, timing, and power consumption. Since low-weight partial products do not need to be generated, the load on related data and coefficient registers is reduced, thereby improving timing and reducing power consumption. At the same time, regarding the selection of compensation values, only one 2-input AND gate or OR gate is needed for the first row, and only one 3-input AND gate or OR gate is needed for the non-first rows, resulting in low compensation cost.
[0140] In practical applications, taking complex number multiplication with 8 bits for the multiplier and 9 bits for the multiplicand, and an approximate number of 5 bits as an example, the area gain is ~31% and the power consumption gain is ~28%.
[0141] This application also provides an approximate multiplier; please refer to [link to relevant documentation]. Figure 10 , Figure 10 A schematic diagram of the structure of the approximate multiplier provided in the embodiments of this application includes:
[0142] Module 1001 is used to obtain the first multiplier and the second multiplier;
[0143] Approximation module 1002 is used to determine the approximate number of bits P based on the signal processing error, where P is an integer greater than 0;
[0144] The encoding module 1003 is used to perform partial product calculation based on Booth coding on the first multiplier and the second multiplier based on the approximate number of bits, and generate an approximate partial product array, wherein the number of bits of the partial product in the approximate partial product array is not less than P;
[0145] Adder module 1004 is used to add the approximate partial product array bit by bit to obtain the calculation result.
[0146] The approximate multiplier provided in this application first determines an approximate number of bits based on the signal processing error. This approximate number of bits reflects the allowable error level of the current signal processing; the larger the approximate number of bits, the larger the allowable error. Selecting a reasonable approximate number of bits based on the signal processing error ensures the accuracy of the approximate calculation. Then, an approximate partial product array is generated based on the approximate number of bits. The number of bits in each partial product in the approximate partial product array is not less than the approximate number of bits, thus saving computational resources during the generation of the partial product array. At the same time, when performing addition operations on the approximate partial product array, since the partial products in the approximate partial product array are reduced by a portion compared to the complete partial product array, computational resources are further saved, thereby improving computational efficiency.
[0147] One possible implementation also includes:
[0148] The compensation module 1005 is used to determine the compensation value based on the approximate number of digits and add the compensation value to the approximate partial product array.
[0149] In one possible implementation, the approximate partial product array is a partial product array that does not compute the low-weight partial product. The partial product array is generated by the first and second multipliers based on Booth coding. The low-weight partial product is the partial product located in the first K rows of the partial product array, with a bit length not exceeding P, where K is the largest integer not greater than P / 2. In another possible implementation, the compensation value is specifically added to the P-th bit of the approximate partial product array.
[0150] In one possible implementation, there are K compensation values, all of which are added to the Pth bit of the approximate partial product array. The compensation values are specifically obtained by performing logical operations based on the bit values of the first multiplier corresponding to the low-weight partial product.
[0151] In one possible implementation,
[0152] The first compensation value is a logical OR and logical AND of the first and second bits of the first multiplier;
[0153] The i-th compensation value Cp(i) is a logical OR-OR-logical AND of x(2i+1), x(2i), and x(2i-1), where x(i) indicates the i-th bit in the first multiplier, and i is an integer greater than 1 and not greater than K.
[0154] In one possible implementation,
[0155] Both the first multiplier and the second multiplier are complex numbers. The first multiplier includes the first real part coefficient and the first imaginary part coefficient, and the second multiplier includes the second real part coefficient and the second imaginary part coefficient.
[0156] The encoding module 1003 is specifically used to perform partial product calculation based on Booth coding on the first multiplier and the second multiplier based on the approximate number of bits, and generate a first approximate partial product array corresponding to the first real part coefficient and the second real part coefficient, a second approximate partial product array corresponding to the first imaginary part coefficient and the second imaginary part coefficient, a third approximate partial product array corresponding to the first real part coefficient and the second imaginary part coefficient, and a fourth approximate partial product array corresponding to the second real part coefficient and the second imaginary part coefficient. The first approximate partial product array, the second approximate partial product array, the third approximate partial product array, and the fourth approximate partial product array belong to the approximate partial product array.
[0157] Adder module 1004 is specifically used to add the first approximate partial product array and the second approximate partial product array bit by bit to obtain the real part coefficients of the calculation result; and to add the third approximate partial product array and the fourth approximate partial product array bit by bit to obtain the imaginary part coefficients of the calculation result.
[0158] In one possible implementation, the first multiplier includes N first sub-multipliers, and the second multiplier includes N second sub-multipliers;
[0159] The encoding module 1003 is specifically used to perform partial product calculation based on Booth coding based on N first multipliers and corresponding N second sub-multipliers, respectively, to generate N approximate sub-partial product arrays, and the N approximate sub-partial product arrays belong to the approximate partial product array;
[0160] Adder module 1004 is specifically used to add N approximate sub-partial arrays bit by bit to obtain the calculation result.
[0161] This application also provides a computing device; please refer to [link / reference]. Figure 11 , Figure 11 This is a schematic diagram of a computing device provided in an embodiment of this application. The computing device can be used to execute computer programs or computer instructions stored in memory to perform... Figure 1 or Figure 2 The methods in the illustrated embodiments can be referred to the relevant descriptions in the above method embodiments.
[0162] The communication device includes a processor 1301. Optionally, the communication device may also include a memory 1302 and a transceiver 1303.
[0163] This application also provides a computer program product including instructions that, when run on a computer, cause the computer to perform the above-described actions. Figure 1 or Figure 2 The illustrated embodiment is an approximate calculation method for signal processing.
[0164] This application also provides a computer-readable storage medium, including computer instructions that, when executed on a computer, cause the computer to perform the actions described above. Figure 1 or Figure 2 The method of the embodiment shown.
[0165] This application also provides a chip device, including a processor for connecting to a memory and calling a program stored in the memory, so that the processor executes the above-described... Figure 1 or Figure 2 The method of the embodiment shown.
[0166] The processor mentioned above can be a general-purpose central processing unit, a microprocessor, an application-specific integrated circuit (ASIC), or one or more devices used to control the above. Figure 1 or Figure 2The illustrated embodiment is an integrated circuit for program execution of the method. The memory mentioned above may be read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, such as random access memory (RAM).
[0167] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0168] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.
[0169] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0170] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0171] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
Claims
1. An approximate calculation method for signal processing, characterized in that, include: Obtain the first and second multipliers; Based on the signal processing error, the approximate number of bits P is determined, where P is an integer greater than 0; Based on the approximate number of bits, a partial product based on Booth coding is calculated on the first multiplier and the second multiplier to generate an approximate partial product array, wherein the number of bits of the partial product in the approximate partial product array is not less than P; The approximate partial product array is summed bitwise to obtain the calculation result.
2. The method according to claim 1, characterized in that, Before performing bit-wise addition on the approximate partial product array to obtain the calculation result, the method further includes: The compensation value is determined based on the approximate number of digits; The compensation value is added to the approximate partial product array.
3. The method according to claim 2, characterized in that, The approximate partial product array is a complete partial product array that does not compute the low-weight partial product. The complete partial product array is generated by the first multiplier and the second multiplier based on Booth coding. The low-weight partial product is the partial product located in the first K rows of the complete partial product array and whose number of bits is no greater than P, where K is the largest integer no greater than P / 2.
4. The method according to claim 2 or 3, characterized in that, The compensation value is specifically added to the P-th bit in the approximate partial product array.
5. The method according to claim 3, characterized in that, The compensation value includes K values, and all K compensation values are added to the Pth bit of the approximate partial product array; the compensation value is specifically obtained by performing logical operations based on the bit value of the first multiplier corresponding to the low-weight partial product.
6. The method according to claim 5, characterized in that, The first compensation value is a logical OR and logical AND of the first and second bits of the first multiplier. The i-th compensation value Cp(i) is a logical OR or logical AND of x(2i+1), x(2i), and x(2i-1), where x(i) indicates the i-th bit in the first multiplier, and i is an integer greater than 1 and not greater than K.
7. The method according to any one of claims 1 to 6, characterized in that, Both the first multiplier and the second multiplier are complex numbers. The first multiplier includes a first real part coefficient and a first imaginary part coefficient, and the second multiplier includes a second real part coefficient and a second imaginary part coefficient. The step of performing a partial product calculation based on Booth coding on the first multiplier and the second multiplier based on the approximate number of bits to generate an approximate partial product array includes: Based on the approximate number of bits, a partial product calculation based on Booth coding is performed on the first multiplier and the second multiplier to generate a first approximate partial product array corresponding to the first real part coefficient and the second real part coefficient, a second approximate partial product array corresponding to the first imaginary part coefficient and the second imaginary part coefficient, a third approximate partial product array corresponding to the first real part coefficient and the second imaginary part coefficient, and a fourth approximate partial product array corresponding to the second real part coefficient and the second imaginary part coefficient. The first approximate partial product array, the second approximate partial product array, the third approximate partial product array, and the fourth approximate partial product array belong to the approximate partial product array. Wherein, the partial product in the second approximate partial product array is calculated by inverting the first imaginary coefficient and the second imaginary coefficient; The step of adding the approximate partial product array bit-by-bit to obtain the calculation result includes: The real part coefficients of the calculation result are obtained by adding the first approximate partial product array and the second approximate partial product array bit by bit. The imaginary coefficients of the calculation result are obtained by adding the third approximate partial product array and the fourth approximate partial product array bit by bit.
8. The method according to any one of claims 1 to 6, characterized in that, The first multiplier includes N first sub-multipliers, and the second multiplier includes N second sub-multipliers; The step of performing a partial product calculation based on Booth coding on the first multiplier and the second multiplier based on the approximate number of bits to generate an approximate partial product array includes: Based on the approximate number of bits, partial product calculation based on Booth coding is performed on the N first multipliers and the corresponding N second sub-multipliers to generate N approximate sub-partial product arrays, and the N approximate sub-partial product arrays belong to the approximate partial product array; The step of adding the approximate partial product array bit-by-bit to obtain the calculation result includes: The calculation result is obtained by adding the N approximate sub-partial product arrays bit by bit.
9. An approximate multiplier, characterized in that, include: The acquisition module is used to obtain the first and second multipliers; An approximation module is used to determine the approximate number of bits P based on the signal processing error, where P is an integer greater than 0; The encoding module is used to perform a partial product calculation based on Booth coding on the first multiplier and the second multiplier based on the approximate number of bits, and generate an approximate partial product array, wherein the number of bits of the partial product in the approximate partial product array is not less than P; The adder module is used to add the approximate partial product array bit by bit to obtain the calculation result.
10. The approximate multiplier according to claim 9, characterized in that, Also includes: The compensation module is used to determine a compensation value based on the approximate number of digits and to add the compensation value to the approximate partial product array.
11. A computing device, characterized in that, Including the processor; The processor is configured to execute computer programs or computer instructions stored in memory to perform the method as described in any one of claims 1 to 8.
12. The computing device according to claim 11, characterized in that, It also includes the memory.
13. A computer program product containing instructions, characterized in that, When the instructions are executed by the computing device, the computing device performs the method as described in any one of claims 1 to 8.
14. A computer-readable storage medium, characterized in that, It includes computer program instructions, which, when executed by a computing device, cause the computing device to perform the method as described in any one of claims 1 to 8.