Circuit design method and system based on genetic optimization

Abstract

The invention discloses a circuit design method and system based on genetic optimization. The method comprises the following steps: constructing a hybrid coding model of circuit topology and parameters and generating an initial population; extracting circuit device characteristics, and obtaining population individual sequences under different constraint conditions according to target requirements; recording topological connection, device matching and performance response characteristics, and constructing an evolution duration map to track characteristic evolution; generating individual scores by weighting the features and combining the deviation degree between the centroid of the features and the centroid of the population, judging abnormal optimization individuals after sorting, and summarizing to obtain a suspected inferior circuit area; high-quality individuals are screened after the region is verified, and the characteristics of the high-quality individuals are fused to output an optimal circuit scheme; according to the method, collaborative optimization of topology and parameters is realized through hybrid coding, the search direction is accurately guided by utilizing constraint classification and an evolution graph, and inferior region identification and multi-working-condition verification are combined, so that the circuit design efficiency is greatly improved, the circuit performance is optimized, and the design cost and the iteration risk are reduced.

Description

Technical Field

[0001] This invention relates to the field of circuit design technology, and in particular to a circuit design method and system based on genetic optimization. Background Technology

[0002] As the scale and performance requirements of integrated circuits continue to increase, traditional circuit design methods based on human experience suffer from long iteration cycles, low optimization efficiency, and difficulty in simultaneously optimizing topology and device parameters. Intelligent optimization methods such as genetic algorithms, due to their global search capabilities, are increasingly being applied to automated circuit design. However, existing genetic optimization-based circuit design methods still have significant shortcomings.

[0003] Most existing technologies employ single-parameter encoding or fixed topology optimization methods, which cannot achieve joint search of circuit topology and device parameters, easily getting trapped in local optima and limiting design flexibility and innovation. Furthermore, the optimization process lacks hierarchical constraint management mechanisms, fails to form differentiated constraint sequences based on different design requirements, and suffers from chaotic selection of individuals in the population, resulting in unclear optimization direction and slow convergence speed.

[0004] During the evolutionary process, existing methods struggle to uniformly extract and effectively track key features such as circuit topology connectivity, device matching, and performance response. They cannot record the generation, evolution, and extinction patterns of features during iterations, and lack visualization and quantitative analysis tools for the circuit evolution process. Furthermore, due to the lack of in-depth mining of the evolutionary trajectory and distribution characteristics of topological features, it is difficult to objectively and accurately evaluate the quality of individual populations, and it is impossible to effectively identify abnormal individuals and inferior circuit regions, which can easily lead to poor reliability of optimization results and low engineering applicability.

[0005] Therefore, in response to the problems mentioned above, this invention proposes a circuit design method and system based on genetic optimization. Summary of the Invention

[0006] To overcome the problems of single encoding methods, lack of targeted constraint sorting and feature tracking in the optimization process, and difficulty in analyzing topology changes in traditional circuit optimization, this invention proposes a circuit design method and system based on genetic optimization.

[0007] The technical solution of this invention is: a circuit design method based on genetic optimization, comprising: S1. Based on the type and design specifications of the circuit to be optimized, a hybrid coding model of circuit parameters and topology is constructed to uniformly encode individual circuits and generate an initial population.

[0008] S2, extract the circuit device features of each circuit individual in the initial population, and obtain the population individual sequence under different constraints according to the target design requirements.

[0009] S3: In different population individual sequences, the topological connectivity features, device matching features, and performance response features of circuit individuals are recorded as circuit features. Based on the generation and extinction process of circuit features during the iteration process, the corresponding evolutionary persistence map is constructed.

[0010] S4. Weight different circuit features, combine the deviation of the centroid of the circuit feature from the overall population center to generate individual circuit scores, sort all population individuals, determine whether they are abnormally optimized individuals, and summarize to obtain suspected inferior circuit regions.

[0011] S5 verifies suspected substandard circuit areas, identifies high-quality circuits, and outputs the optimal circuit solution that meets the target design requirements based on the characteristics of the corresponding circuit components.

[0012] Preferably, the steps for constructing the hybrid coding model include: A1. Based on the type and design specifications of the circuit to be optimized, determine the optimized topology elements as the topology coding dimension and the optimized device parameters as the parameter coding dimension.

[0013] A2 employs a two-level coding structure of topology layer and parameter layer, encoding the topology coding dimension and parameter coding dimension of each individual circuit into a hybrid coding string.

[0014] A3, through preset encoding parsing rules, parses the mixed encoded string from the topology layer encoding and parameter layer encoding to obtain the circuit netlist.

[0015] A4 verifies the randomized number of mixed encoding strings in terms of completeness, effectiveness, and adjustability, and outputs the model that meets the conditions as the mixed encoding model.

[0016] Preferably, the steps for extracting features of circuit devices include: B1 splits the hybrid encoding string of the current circuit individual into topology encoding segments and parameter encoding segments, and identifies the number of devices and the connection relationship between devices based on the topology encoding segments.

[0017] B2: Read the parameters and structural features of each device according to the parameter encoding segment, and supplement the process-related features of each device with the process library information to obtain the circuit device features.

[0018] Preferably, the steps for obtaining population individual sequences under different constraints include: C1 determines the performance targets, constraints, and priorities as target indicators based on the target design requirements, and divides the target indicators into different levels of constraint sets according to different requirements.

[0019] C2 establishes evaluation rules for each set of constraints, evaluates each individual circuit to obtain multiple sets of individuals, and sorts each set of individuals from high to low performance to generate a corresponding list of individuals.

[0020] C3 sorts all the individual lists according to the level of the constraint set to obtain the population individual sequence under different constraint conditions.

[0021] Preferably, the steps for obtaining the circuit features include: D1. Feature extraction criteria are determined based on device classification standards, topological connectivity judgment criteria, and simulation parameters of performance response.

[0022] D2. Based on the feature extraction criteria, locate the circuit individuals in the sequence of each population as the individuals to be extracted, and perform parsing and reconstruction to obtain the corresponding circuit netlist to be extracted.

[0023] D3: Filter all circuit nodes and devices based on the circuit netlist to be extracted, assign unique numbers, construct a connectivity graph based on the port connection of each device, and extract topological connectivity features from the connectivity graph.

[0024] D4. Classify all devices of the current circuit individual to be extracted according to their functions, screen matching device groups, calculate the matching degree using the normalized deviation method, and define the matching device groups according to the preset matching degree threshold to obtain device matching characteristics.

[0025] D5 simulates the individual circuit to be extracted and obtains static performance indicators, performance compliance, fluctuation range, sensitivity, and robustness as performance response characteristics.

[0026] D6. Establish the correlation between topological connectivity features, device matching features, and performance response features, and classify and organize them according to the individual sequence of the population to obtain circuit features.

[0027] As a preferred approach, the steps for constructing an evolutionary persistence map include: E1 records the topological features of the circuit structure in the population individuals corresponding to different iteration generations. The topological features include connected paths, loop structures, port matching relationships, and parasitic sensitive regions.

[0028] E2 records the generation and disappearance algebras of each topological feature, and tracks the generation and disappearance process of each topological feature along the iterative algebra sequence.

[0029] E3 marks the spatial location and device composition of topological features in different populations and matches the topological features in adjacent iterations to form the evolutionary trajectory of topological features.

[0030] E4 subtracts the number of generations of each topological feature from the number of generations of its generation to obtain the evolutionary lifetime of the topological feature. Based on the type of topological feature, the evolutionary lifetime of the topological feature, and its spatial distribution, an evolutionary persistence map is constructed for each individual circuit.

[0031] Preferably, the steps for generating individual circuit scores include: F1 calculates the centroid coordinates for each topological feature in the evolutionary persistence graph, and uses the weighted average of the device and node coordinates corresponding to the topological feature as the centroid of the topological feature.

[0032] F2 uses the weighted average coordinates of the feature vectors of all individual circuits in the entire population as the overall centroid of the population, and the Euclidean distance between the topological feature centroid and the overall centroid of the population is used as the degree of deviation.

[0033] F3 sets corresponding weights as topology feature weights based on the degree of influence of topology features on circuit performance.

[0034] F4 calculates a weighted cumulative score for each circuit individual by weighting the evolutionary lifetime of topological features, the weight of topological features, and the degree of deviation.

[0035] Preferably, the steps for obtaining the suspected defective circuit region include: G1 uses the min-max normalization method to normalize the scores of individual circuits, determines the correlation logic between individual circuit scores and circuit quality, sorts all individuals in the population in descending order, and generates a quality ranking table.

[0036] G2 combines target design requirements and engineering experience to set dual judgment thresholds, traverses the quality degree ranking table, and obtains abnormal optimization individuals.

[0037] G3 constructs a mapping and coding rule between the physical regions of the circuit and the individuals in the population, binds the unique identifier of each abnormally optimized individual to the corresponding circuit region, counts the number of abnormally optimized individuals and the average standardized score in the region, and generates a regional anomaly statistics table.

[0038] G4 divides the circuit area into three levels of degradation risk: high, medium, and low, based on the regional anomaly statistics table, and selects circuit areas with high and medium degradation risk as suspected defective circuit areas.

[0039] As a preferred option, the steps to obtain the optimal circuit scheme include: H1 performs cross-validation on suspected substandard circuit regions from the data, simulation, and physical levels to screen for a high-quality candidate set within the region.

[0040] H2 uses the performance indicators of circuit design as a benchmark to select a set of high-quality candidates, obtains the selected individuals, sets the candidate weights according to the target design requirements, and calculates the comprehensive score of the selected individuals.

[0041] H3, sorted by comprehensive score from high to low, selects the first preset proportion of individuals as the initial high-quality individuals.

[0042] H4 takes the initially selected high-quality individuals and puts them into different working conditions for simulation testing. Individuals that consistently meet the standards and show no significant performance degradation under all working conditions are selected as high-quality circuit individuals.

[0043] H5 extracts the circuit device features of high-quality circuit individuals as a high-quality device feature set, and filters and retains high-quality feature individuals in combination with the target design requirements.

[0044] H6 employs a feature fusion algorithm to fuse complementary high-quality features from different high-quality individuals to construct the optimal circuit scheme.

[0045] This invention provides a circuit design system based on genetic optimization, comprising: The coding model construction module is used to construct a hybrid coding model of circuit parameters and topology based on the type and design specifications of the circuit to be optimized, to uniformly encode individual circuits, and to generate an initial population. The feature population extraction module is used to extract the circuit device features of each circuit individual in the initial population, and obtain the population individual sequence under different constraints according to the target design requirements; The graph construction module is used to record the topological connectivity features, device matching features, and performance response features of circuit individuals in different population sequences as circuit features, and to construct the corresponding evolutionary persistence graph based on the generation and extinction process of the circuit features during the iteration process. The circuit region filtering module is used to weight different circuit features, combine the deviation of the centroid of the circuit feature from the overall center of the population, generate individual circuit scores, sort all population individuals, determine whether they are abnormally optimized individuals, and summarize to obtain suspected inferior circuit regions. The circuit scheme generation module is used to verify the suspected inferior circuit areas, identify high-quality circuit individuals, and output the optimal circuit scheme that meets the target design requirements by combining the characteristics of the corresponding circuit devices.

[0046] The beneficial effects of this invention are: 1. This invention constructs a hybrid coding model of circuit parameters and topology to uniformly encode individual circuits. It adopts a two-level coding structure of topology layer and parameter layer to encode the topology coding dimension and parameter coding dimension of each individual circuit into a hybrid coding string, thereby realizing the unified coding and optimization of circuit topology and device parameters.

[0047] 2. This invention extracts the circuit device features, topological connectivity features, device matching features, and performance response features of individual circuits to construct an evolutionary continuous graph, tracking the generation and disappearance of circuit features during the iteration process. The automated circuit feature extraction and analysis reduces manual intervention and design time, improves circuit design efficiency, and optimizes the circuit's topology and device parameters, thereby improving the circuit's performance and reliability.

[0048] 3. Construct an evolutionary continuous graph to help designers better understand the evolution process of circuits and optimization directions.

[0049] 4. Automated circuit design processes reduce the cost of manual design and testing. The selection and verification of high-quality individual circuits improves the success rate and reliability of circuit design and reduces circuit design costs. Attached Figure Description

[0050] Figure 1 The diagram shown is a flowchart of a circuit design method based on genetic optimization according to the present invention. Figure 2 The diagram illustrates the process of obtaining circuit features in a genetic optimization-based circuit design method according to the present invention. Figure 3 The diagram shown is a schematic of a circuit design system based on genetic optimization according to the present invention. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] Please see Figure 1 and Figure 2 The present invention provides an embodiment: Based on the type and design specifications of the circuit to be optimized, a hybrid coding model of circuit parameters and topology is constructed to uniformly encode individual circuits and generate an initial population.

[0053] The specific steps for constructing a hybrid coding model are as follows: Based on the type and design specifications of the circuit to be optimized, the topology elements to be optimized are determined as the topology coding dimension, and the device parameters to be optimized are determined as the parameter coding dimension.

[0054] A two-level coding structure of topology layer and parameter layer is adopted to encode the topology coding dimension and parameter coding dimension of each individual circuit into a hybrid coding string.

[0055] The following is an example, using a common-source amplifier: Coding level Encoded content Encoding type Range of values Encoding length Topology layer Device type + connection relationship binary 0 = No device present / 1 = Device present. 00 = Source connected to power supply / 01 = Source grounded. 20bit Parameter layer MOSFET W / L + Resistor R + Capacitor C real numbers W / L: 10~1000. R: 1kΩ~100kΩ. C: 1pF~100pF 15 bits (5 bits per parameter) Topology layer coding rules: Use binary bits to represent "whether a certain device exists" and "the connection method between devices". For example, bits 1-5 indicate whether the input stage contains MOS transistor M1, and bits 6-10 indicate the connection object of the source of M1.

[0056] Parameter layer encoding rules: Continuous parameter values ​​are converted into discrete real number codes through linear mapping. For example, W / L∈[10,1000] is mapped to a normalized value of 0~1, and then converted into a 5-bit binary real number code to ensure that the parameter precision matches the code length.

[0057] By using preset encoding and parsing rules, the mixed encoded string is parsed from the topology layer encoding and parameter layer encoding to obtain the circuit netlist.

[0058] Parse the topology layer code: Parse the binary code bit by bit to generate the netlist framework of the circuit topology, such as "M1 drain gate source NMOSW / L=xxx".

[0059] Parse the parameter layer encoding: denormalize the real number encoding to restore the actual device parameter values ​​and fill them into the netlist frame.

[0060] Automatically supplement process models, such as BSIM4 models, and simulation stimuli, such as input voltage sources and AC sweep ranges, to generate complete netlist files that can be directly called for SPICE simulation.

[0061] The randomly generated preset number of hybrid encoding strings are verified in terms of completeness, effectiveness, and adjustability. Models that meet the conditions are output as hybrid encoding models.

[0062] Integrity: Check whether all encoded strings can be parsed into a valid circuit netlist, with no topology errors or parameter errors.

[0063] Validity: The circuit simulator is used to simulate the analyzed netlist to verify whether the circuit has basic functions, such as the amplifier having gain and the filter having frequency selectivity.

[0064] Adjustability: Fine-tune the parameter layer encoding values ​​to verify whether the circuit performance shows a continuous and optimizable trend as the parameters change, ensuring that the encoding model can cover the effective design space.

[0065] Extract the circuit device features of each individual circuit in the initial population, and obtain the population individual sequence under different constraints according to the target design requirements.

[0066] The specific steps for extracting features from circuit devices are as follows: The hybrid encoding string of the current circuit individual is split into topology encoding segment and parameter encoding segment. The number of devices and the connection relationship between devices are identified based on the topology encoding segment.

[0067] The number of components can include MOSFETs, resistors, capacitors, inductors, bias transistors, etc., and each component should be labeled with a number. The connection relationships include where each component's input, output, and control terminals are connected—whether to power supply, ground, or other components.

[0068] The parameters and structural features of each device are read from the parameter encoding segment, and the process-related features of each device are supplemented by the process library information to obtain the circuit device features.

[0069] Device parameters and structural characteristics may include: MOSFET: width W, length L, width-to-length ratio W / L. Resistor: resistance value R. Capacitor: capacitance value C. Structural characteristics: whether the device is a single transistor, cascode transistor, diode connection, or differential pair. Whether the devices are connected in series, parallel, or feedback structure. Whether it is a matched device or a symmetrical device. Process-related characteristics may include: whether it meets minimum size requirements. Approximate order of parasitic capacitance and parasitic resistance. Whether it operates in the saturation region, linear region, or cutoff region.

[0070] The specific steps for obtaining the population individual sequences under different constraints are as follows: Based on the target design requirements, performance targets, constraints, and priorities are determined as target indicators. According to different requirements, the target indicators are divided into different levels of constraint sets.

[0071] Performance targets: gain, bandwidth, power consumption, noise, phase margin, swing, etc.

[0072] Constraints include: voltage range, upper current limit, temperature range, process angle, minimum size, and maximum area.

[0073] Priority: Which are mandatory (hard constraints), and which are optimizations (soft objectives).

[0074] A set of constraints, for example: Constraint 1: Relaxed constraint, only basic functions are satisfied.

[0075] Constraint 2: Moderate constraint, meeting typical indicators.

[0076] Constraint 3: Strict constraints to meet all industrial-grade indicators.

[0077] An evaluation rule is established for each set of constraints. Each individual circuit is evaluated to obtain multiple sets of individuals. Each set of individuals is sorted from high to low performance to generate a corresponding list of individuals.

[0078] For each set of constraints, clearly define: which parameters cannot be exceeded, which performance characteristics must meet, which structures are permitted, and which are illegal. For example: Relaxed constraints: only require the circuit to function, without interruption or short circuit. Medium constraints: gain > 20dB, bandwidth > 100MHz. Strict constraints: gain > 20dB, bandwidth > 100MHz, phase margin > 60°, power consumption < 10mW.

[0079] For each individual circuit, perform the following: parse the circuit code into a simulable circuit, and simulate / calculate its performance under the first set of constraints. Determine if it meets these constraints. If it does, add it to the eligible circuit under those constraints. If it doesn't, exclude it. Re-evaluate it using the second set of constraints. Then evaluate it again using the third, more stringent set of constraints. Continue this process until all constraints have been exhausted, resulting in multiple sets of individual circuits.

[0080] Sort all the individual lists according to the level of the constraint set to obtain the population individual sequence under different constraint conditions.

[0081] In different population sequences, the topological connectivity features, device matching features, and performance response features of individual circuits are recorded as circuit features. Based on the generation and extinction of circuit features during the iteration process, a corresponding evolutionary persistence map is constructed.

[0082] The specific steps for obtaining circuit characteristics are as follows: Feature extraction criteria are determined based on device classification standards, topological connectivity criteria, and simulation parameters of performance response.

[0083] Based on the feature extraction criteria, the circuit individuals in the sequence of each population are located as the individuals to be extracted, and the corresponding circuit netlist to be extracted is obtained by parsing and restoring.

[0084] All circuit nodes and devices are filtered according to the circuit netlist to be extracted, and assigned unique numbers. A connectivity path graph is constructed based on the port connection of each device, and topological connectivity features are extracted from the connectivity path graph.

[0085] Topological connectivity characteristics may include: the number of connected components, the number of independent current paths in the circuit, such as a single-stage amplifier typically having one connected component, while a multi-stage amplifier may have multiple connected components, but it must be ensured that all components have a power / ground connection.

[0086] Loop structure: whether there is a feedback loop or an oscillation loop; record the components and path length of the loop. For example, the feedback loop of a common-source amplifier consists of a resistor Rf and a MOSFET M1, with a path length of 3 nodes.

[0087] Node connectivity refers to the number of connected devices at each node, such as the number of devices connected to a power node and the number of dangling nodes. A valid connection is defined as having zero dangling nodes.

[0088] Redundancy of connected paths: whether there are redundant connected paths, such as redundant paths formed by two resistors in parallel. Record the device type and length of redundant paths for simplifying the circuit during subsequent optimization.

[0089] Port connectivity matching: Check whether the input / output ports are smoothly connected to the internal circuitry. For example, check if there are impedance mismatches in the connection between the input port and the amplifier stage. Record the parameters of the matching nodes.

[0090] Parasitic sensitive connected regions are recorded, and connected paths that are susceptible to parasitic parameters are identified. For example, in high-frequency circuits, long-distance connected paths are prone to generating parasitic inductance. The nodes and devices of this path are marked.

[0091] All devices of the current circuit to be extracted are classified according to function, matching device groups are screened, the matching degree is calculated using the normalized deviation method, and the matching device groups are defined according to the preset matching degree threshold to obtain device matching characteristics.

[0092] Device matching features can include devices with abnormal matching. Devices with a matching degree lower than a preset threshold, such as resistors with a matching degree <0.8, are marked as abnormal and the causes of the abnormality are analyzed: parameter deviation, structural asymmetry.

[0093] Check for redundancy in the matching process. Are there any redundant matching devices? For example, if redundant capacitors are added to improve the matching degree, record the number and parameters of the redundant devices.

[0094] Matching stability refers to the change in the degree of matching under different constraints. For example, under strict constraints, whether the fluctuation of the degree of matching is less than 0.05. The smaller the fluctuation, the better the stability.

[0095] Simulate the individual circuit to be extracted to obtain static performance indicators, performance compliance, fluctuation range, sensitivity and robustness as performance response characteristics.

[0096] The correlation between topological connectivity features, device matching features, and performance response features is established, and the circuit features are obtained by classifying and organizing them according to the individual sequence of the population.

[0097] Relationships such as: feedback loops in topological connectivity lead to improved phase margin in performance response; insufficient differential pair matching in device matching leads to decreased common-mode rejection ratio in performance response; individuals within the same sequence are sorted from high to low fitness, and the characteristic differences of each individual are labeled, such as individuals with higher fitness having higher matching degree and greater performance redundancy.

[0098] The specific steps for constructing an evolutionary persistence map are as follows: In the population individuals corresponding to different iteration generations, the topological features of the circuit structure are recorded. The topological features include connected paths, loop structures, port matching relationships, and parasitic sensitive regions.

[0099] The connectivity path is used to reflect the electrical conduction relationship between devices, the loop structure is used to characterize the feedback loop and the signal transmission path, the port matching relationship is used to reflect the connection effectiveness between the input / output ports and the internal circuit, and the parasitic sensitive region is used to identify weak structural segments that are susceptible to parasitic parameters, thereby comprehensively covering the key changes in circuit topology during the evolution process.

[0100] Record the generation and disappearance algebras of each topological feature, and track the generation and disappearance process of each topological feature in the order of iteration algebras.

[0101] Starting from the initial population, the topological features are scanned generation by generation in ascending order of iteration generations. The generation number at which each topological feature first appears is recorded as the generation number. This process continues until the topological feature completely disappears from the entire population, which is recorded as the disappearance generation. Through continuous generational tracking, the complete process of each topological feature from its appearance to its disappearance is fully recorded, clarifying its existence period and patterns of change during evolution.

[0102] The spatial location and device composition of topological features in different populations are marked, and the topological features in adjacent iterations are matched to form the evolutionary trajectory of topological features.

[0103] For each topological feature, its functional region, node location, and physical distribution within the corresponding circuit are marked. Simultaneously, the specific device type, device number, and connection method constituting the topological feature are recorded. Between adjacent iterations, similarity matching is performed on the type, location, device composition, and structural morphology of the topological features to confirm the continuation, variation, or splitting of the same topological feature in previous and subsequent generations. This links together the same continuously existing, evolutionarily related topological features, forming a traceable and complete evolutionary trajectory.

[0104] Subtracting the number of generations of each topological feature from its number of generations of generation yields the evolutionary lifetime of the topological feature. Based on the type of topological feature, its evolutionary lifetime, and its spatial distribution, an evolutionary persistence map is constructed for each individual circuit.

[0105] Subtracting the generation number from the disappearance number yields the number of generations a topological feature persists in the population evolution process; this is the evolutionary lifetime of the topological feature, which directly reflects its stability and quality. By combining the type weight of the topological feature itself, the length of its evolutionary lifetime during iteration, and its spatial distribution and frequency of occurrence within individual circuits, this information is unified, integrated, and visualized to ultimately form an evolutionary persistence map that intuitively reflects the rise, fall, continuation, and change patterns of topological features within each individual circuit. This map is then used for subsequent anomaly assessment and optimization decisions.

[0106] Different circuit features are weighted, and the deviation between the centroid of the circuit feature and the overall population center is combined to generate individual circuit scores. All individuals in the population are sorted and it is determined whether they are abnormally optimized individuals. Suspected poor-quality circuit regions are then obtained.

[0107] The specific steps for generating individual circuit scores are as follows: For each topological feature in the evolutionary persistence graph, the centroid coordinates are calculated, and the weighted average of the device and node coordinates corresponding to the topological feature is used as the centroid of the topological feature.

[0108] For each type of topological feature recorded in the evolutionary persistence map, a corresponding two-dimensional or three-dimensional coordinate system is constructed based on the device location, circuit node number, and spatial distribution information of the topological feature in the circuit individual. The coordinate values ​​of each device and node included in the topological feature are weighted according to their electrical importance, and a weighted average is calculated. The coordinate point corresponding to the weighted average is defined as the centroid of the topological feature, which is used to characterize the concentrated distribution location of the topological feature in the circuit structure.

[0109] The weighted average coordinates of the feature vectors of all individual circuits in the entire population are used as the overall centroid of the population, and the degree of deviation is determined by the Euclidean distance between the topological feature centroid and the overall centroid of the population.

[0110] Feature vectors of all individual circuits within the current iterative population are extracted. The coordinates corresponding to all individual feature vectors are normalized, and a weighted average coordinate is calculated. This weighted average coordinate is used as the overall centroid of the population, reflecting the center of the overall population distribution. The spatial distance between the centroid of the topological feature and the overall centroid of the population is calculated using the Euclidean distance formula. This distance characterizes the degree of deviation of the topological feature from the overall population distribution; a larger distance indicates a more significant difference between the topological feature and the mainstream structure of the population.

[0111] Based on the degree of influence of topological features on circuit performance, corresponding weights are set as topological feature weights.

[0112] Differential weights are assigned to various topological features based on their impact on key performance indicators such as circuit gain, bandwidth, power consumption, noise, and stability. Core topological features that play a decisive role in circuit performance are given higher weights, while auxiliary structures or local features with less impact on circuit performance are given lower weights. The weights reflect the importance and contribution of topological features in the evolutionary process.

[0113] The topological feature evolution lifetime, topological feature weight, and deviation degree are weighted and accumulated to generate a circuit individual score for each circuit individual.

[0114] Using topological feature evolutionary lifetime, topological feature weight, and the degree of deviation of topological features from the population centroid as calculation variables, a weighted summation and accumulation calculation is performed according to preset weighting coefficients to comprehensively reflect the rationality, stability, and degree of anomaly of the internal topological features of the individual circuit. The final calculation result is used as the circuit score for the corresponding individual circuit. The higher the score, the more obvious the topological anomaly of the individual circuit and the worse the optimization effect, thus realizing a quantitative evaluation of the quality of the individual circuit.

[0115] The specific steps for identifying suspected defective circuit regions are as follows: The min-max normalization method is used to normalize the individual circuit scores, determine the correlation logic between individual circuit scores and circuit quality, sort all individuals in descending order, and generate a quality ranking table.

[0116] By combining target design requirements and engineering experience, dual judgment thresholds are set, and the quality level ranking table is traversed to obtain abnormal optimization individuals.

[0117] A mapping and coding rule is constructed between the physical regions of the circuit and the individuals in the population. The unique identifier of each anomalous optimized individual is bound to its corresponding circuit region. The number of anomalous optimized individuals and their average standardized scores within each region are counted, generating a regional anomaly statistics table. The fields in the regional anomaly statistics table include: region code, region name, number of anomalous individuals, average score of anomalous individuals, total number of individuals within the region, and percentage of anomalous individuals.

[0118] Based on the regional anomaly statistics table, the circuit areas are divided into three levels of degradation risk: high, medium, and low. Circuit areas with high and medium degradation risk are selected as suspected defective circuit areas.

[0119] High risk of degradation: Abnormal percentage ≥ 30% and average score ≥ 0.7. Medium risk of degradation: 10% ≤ abnormal percentage < 30% or 0.5 ≤ average score < 0.7. Low risk of degradation: Abnormal percentage < 10% and average score < 0.5.

[0120] The regions are sorted in descending order of their degradation risk level. The criteria for anomaly determination, core issues, risk level, and scope of impact for each region are clearly defined. The physical coordinates of each region and the corresponding population list are also marked, providing accurate location and analysis basis for subsequent circuit optimization and fault diagnosis.

[0121] Verify suspected substandard circuit areas, identify high-quality circuits, and, based on the characteristics of the corresponding circuit components, output the optimal circuit solution that meets the target design requirements.

[0122] Cross-validation of suspected substandard circuit regions is performed at the data, simulation, and physical levels to screen a set of high-quality candidate individuals within the region.

[0123] Data-level review: Retrieve the original score data and data acquisition logs of all individual circuits within the suspected substandard area to verify whether there are score anomalies caused by non-circuit quality issues such as test environment interference, data acquisition errors, or encoding mapping errors. For individuals misjudged as substandard due to data issues, recalibrate their scores and classify them as normal. If the proportion of substandard individuals in the area decreases to the low degradation risk standard as a result, the suspected substandard label for that area is removed.

[0124] Simulation-level verification: For the retained real suspected defective areas, a circuit simulation model (such as SPICE or ADS) is built. The circuit parameters of all individuals within the area are substituted to simulate actual operating conditions. The model verifies whether the core indicators such as individual performance loss, failure probability, and signal transmission efficiency are consistent with the scoring results. If the simulation results show that the individual indicators meet the standards, contradicting the scoring results, the individual scores are corrected and the area's degradation level is reassessed.

[0125] Physical verification: For areas still identified as substandard after simulation verification, the physical characteristics of the area, such as component layout, routing planning, and interface connections, are checked in conjunction with the circuit physical design drawings to confirm whether there are physical factors such as design redundancy, layout conflicts, or process limitations that lead to individual quality degradation. Simultaneously, circuits that meet both simulation and measured performance standards within the area are recorded as candidates for high-quality circuits in that area.

[0126] Based on the performance indicators of circuit design, a high-quality candidate set is selected to obtain the selected individuals. The candidate weights are set according to the target design requirements, and the comprehensive score of the selected individuals is calculated.

[0127] Individuals are sorted from highest to lowest based on their overall scores, and a predetermined percentage of those selected are chosen as high-quality individuals for the initial screening.

[0128] The initially selected high-quality individuals are subjected to simulation tests under different working conditions. Individuals that consistently meet the performance standards and show no significant performance degradation under all working conditions are selected as high-quality circuit individuals.

[0129] A high-quality circuit includes a unique identifier, corresponding circuit area, comprehensive score, performance indicators under various operating conditions, and encoded string information.

[0130] The circuit device features of high-quality circuit individuals are extracted as a high-quality device feature set, and high-quality feature individuals are selected and retained in combination with the target design requirements.

[0131] A feature fusion algorithm is used to fuse the complementary high-quality features of different high-quality individuals to construct the optimal circuit scheme.

[0132] Please see Figure 3 This invention provides an embodiment of a circuit design system based on genetic optimization, comprising: The coding model construction module is used to construct a hybrid coding model of circuit parameters and topology based on the type and design specifications of the circuit to be optimized, and to uniformly encode individual circuits to generate an initial population.

[0133] The feature population extraction module is used to extract the circuit device features of each individual circuit in the initial population and obtain the population individual sequence under different constraints according to the target design requirements.

[0134] The graph construction module is used to record the topological connectivity features, device matching features, and performance response features of circuit individuals in different population sequences as circuit features. Based on the generation and extinction process of circuit features during the iteration process, the corresponding evolutionary persistence graph is constructed.

[0135] The circuit region filtering module is used to weight different circuit features, combine the deviation of the centroid of the circuit feature from the overall population center, generate individual circuit scores, sort all population individuals, determine whether they are abnormally optimized individuals, and summarize to obtain suspected inferior circuit regions.

[0136] The circuit scheme generation module is used to verify suspected inferior circuit areas, identify high-quality circuit individuals, and output the optimal circuit scheme that meets the target design requirements by combining the characteristics of the corresponding circuit components.

[0137] In summary, this embodiment provides a circuit design method and system based on genetic optimization. By constructing a hybrid encoding model of circuit parameters and topology, it uniformly encodes individual circuits to generate an initial population. The encoded strings are then parsed into a circuit netlist using preset parsing rules. The encoding model is verified in terms of completeness, effectiveness, and adjustability, achieving collaborative optimization of topology and device parameters. It comprehensively extracts three categories of features from circuit devices: basic parameters, topological associations, and process constraints, ensuring the completeness and engineering practicality of the features. It establishes a correlation between device features and process requirements, preventing extracted features from deviating from actual manufacturing needs. Based on the target design requirements, performance targets, constraints, and priorities are divided to form constraint sets of different levels. Evaluation rules are established for each constraint set. After evaluating individual circuits, they are sorted by performance and then integrated into a population sequence according to constraint level, achieving hierarchical control of constraints to adapt to different design scenarios. A unified feature extraction standard ensures the comparability of features among different circuit individuals. It achieves collaborative extraction and association of topology, matching, and performance features, comprehensively reflecting the rationality of the circuit structure, device stability, and functional effectiveness, avoiding the one-sidedness of single-feature evaluation. It can improve optimization efficiency, automation and accuracy, ensure optimization quality, and enhance the practicality of engineering.

[0138] This invention provides Embodiment 1: This example focuses on the optimized design of a two-stage operational transconductance amplifier, aiming to create an operational transconductance amplifier suitable for low-power and high-gain applications. Specific design specifications are as follows: Performance targets: Low-frequency open-loop gain > 80dB, unity-gain bandwidth (GBW) > 10MHz, phase margin > 60°, quiescent power < 0.5mW.

[0139] Constraints: 0.18μm CMOS process, power supply voltage of 1.8V, and load capacitance of 2pF.

[0140] Priority: Power consumption and gain are the highest priority hard constraints, while bandwidth and phase margin are secondary optimization objectives.

[0141] (1) Based on the design specifications, construct a hybrid coding model of topology and parameters.

[0142] The topology coding dimension includes the number of amplifier stages, input stage structure, load type, output stage structure, and compensation network type. The parameter coding dimension includes the channel width (W) and length (L) of each MOSFET, the current value of the bias current source, and the values ​​of the compensation capacitor (Cc) and resistor (Rc).

[0143] The two-level coding structure adopts a hybrid coding string of "topology layer (binary coding) + parameter layer (real number coding)". The topology layer uses 20-bit binary code to represent the circuit structure selection, and the parameter layer maps continuous parameters such as W / L (range 1μm~100μm) and Cc (0.1pF~5pF) to discrete real number codes.

[0144] The model randomly generates 1000 hybrid coding strings, converts them into a SPICE netlist using parsing rules, and performs DC working point checks. The validation pass rate is approximately 92%. Illegal individuals that cannot establish correct DC working points are removed, ultimately forming an effective hybrid coding model.

[0145] (2) Based on the verified encoding model, an initial population (P0) containing 200 individual circuits is randomly generated. For each individual, its encoding string is parsed to extract the number of MOS transistors, connection relationships and aspect ratio, etc., and combined with the 0.18μm CMOS process library, the process characteristics such as the threshold voltage and capacitance per unit area of ​​the device are supplemented.

[0146] (3) Based on the target design requirements, divide the constraint sets into three levels and generate the corresponding population individual sequences: Sequence S1 (relaxed constraints): The circuit can establish the correct DC operating point without open circuits or short circuits.

[0147] Sequence S2 (Medium Constraints): Satisfies S1, with gain > 60dB and power consumption < 0.8mW.

[0148] Sequence S3 (strict constraints): Satisfies S2, and has a gain > 80dB, GBW > 10MHz, phase margin > 55°, and power consumption < 0.5mW.

[0149] Substitute all individuals in P0 into S1, S2, and S3 for evaluation in sequence to obtain a set of individuals that satisfy each constraint. Then, sort the individuals in the set according to their performance to form three progressive population sequences: S1, S2, and S3.

[0150] (4) During the genetic evolution process (a total of 200 generations), the population state is recorded every 10 generations, specifically: For individuals in sequence S3, their topological connectivity features, device matching features, and performance response features are extracted. Taking the "Miller compensation structure" topological feature as an example, it is recorded that it first appeared in generation 5, became stable in superior individuals starting in generation 15, and persisted until generation 200, with an evolutionary lifespan of 195 generations. The spatial location and device composition of this feature in different individuals are also recorded. The evolutionary process of all features is integrated to form an evolutionary persistence map for each individual.

[0151] (5) Perform individual circuit score calculations and identify suspected defective areas, specifically: The final population of the 200th generation is calculated. Taking the "Miller compensation structure" as an example, its centroid coordinates are calculated. The centroid of the population is obtained by averaging the feature vectors of all individuals in this generation. The Euclidean distance between this centroid and the population centroid is calculated as the "degree of deviation". Combining the evolutionary lifespan of this feature (195 generations), the preset weight (the compensation structure contributes significantly to stability, so it is set to 0.8), and the degree of deviation, a weighted score is calculated to obtain the score of individuals containing this feature.

[0152] After normalizing all individual scores, they are sorted. Based on engineering experience, a dual threshold is set: individuals with scores below 0.3 and performance metrics below 80% of the target value are marked as "abnormal optimization individuals." The chip layout is divided into several grid regions, and the number of abnormal individuals falling into each grid is counted. For example, in grid region A12, the number of abnormal individuals accounts for 35% of the total number of individuals in that region, and the average normalized score is 0.25, which is judged as a "high degradation risk region," i.e., a suspected area of ​​poor-quality circuitry.

[0153] (6) Generate the optimal circuit scheme, specifically: All individuals within region A12 underwent data verification to eliminate those misjudged due to simulation convergence errors. The remaining suspected substandard individuals were then subjected to more refined Monte Carlo simulations to confirm that their large performance fluctuations indeed stemmed from the device layout in this region. Simultaneously, individuals with excellent simulation performance were selected as candidates from within region A12.

[0154] Based on the design metrics, a comprehensive score is calculated for each candidate individual (gain weight 0.4, power consumption weight 0.3, bandwidth weight 0.2, phase margin weight 0.1). The top 10% of individuals with the comprehensive scores are selected as the initial high-quality individuals.

[0155] The initially selected high-quality individual circuits were simulated at typical process corners (TT), slow process corners (SS), and fast process corners (FF), and at temperatures of -40°C, 27°C, and 125°C. Those circuits with a gain >75dB, GBW >8MHz, and phase margin >55° under all operating conditions were selected as the final high-quality circuit circuits.

[0156] The features of the best individual components are extracted. For example, component A has excellent gain characteristics, and component B has ultra-low power consumption, but their compensation structures are slightly different. A feature fusion algorithm is used to combine the input stage structure of component A and the output stage bias structure of component B to generate a new encoding string that combines the advantages of both. The final circuit scheme derived from this encoding string, after simulation verification, achieves excellent performance of 85dB gain, 12MHz GBW, 62° phase margin, and 0.45mA power consumption, fully meeting and partially exceeding the design specifications.

[0157] Comparative Example 1 provided by the present invention: The comparative example uses a traditional genetic algorithm with a fixed topology, optimizing only device parameters, to optimize the same two-stage OTA. The algorithm parameters are consistent with the example, but techniques such as hybrid encoding, constraint hierarchies, feature tracking, and poor-quality region identification are not employed.

[0158] In the early stages of optimization, the population quickly converged to the vicinity of a few locally optimal topologies. Unable to explore new topologies, the optimization process stalled. Throughout this process, it was difficult to pinpoint the critical circuit regions causing poor performance. After 200 iterations, the optimal circuit scheme achieved a gain of 78dB, a GBW of 9.5MHz, a phase margin of 58°, and a power consumption of 0.52mW. The two hard constraints of gain and power consumption were not met, resulting in overall performance inferior to that obtained in Example 1, as detailed in the table below: Comparison items Example 1 Comparative Example 1 Low-frequency open-loop gain (dB) 85 78 Unity-gain bandwidth (MHz) 12 9.5 Phase margin (°) 62 58 Static power consumption (mW) 0.45 0.52 Design an iterative convergent algebra Approximately 120 generations The 200s generation still hasn't fully met the standards. Optimization scheme engineering applicability High stability (verified under multiple operating conditions) Low (meets standards only under typical operating conditions) By comparing the above embodiments with comparative examples, it can be concluded that the present invention achieves coordinated optimization of topology and parameters through hybrid encoding, achieves accurate search through constraint hierarchy, accurately locates inferior regions through feature tracking and centroid deviation analysis, and ensures design robustness through multi-condition verification. Compared with traditional methods, the present invention can significantly improve the efficiency and performance of circuit design and reduce costs, outputting a better and more reliable circuit design solution.

[0159] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments that can be applied to other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A circuit design method based on genetic optimization, characterized in that, Includes the following steps: S1. Based on the type and design specifications of the circuit to be optimized, a hybrid coding model of circuit parameters and topology is constructed to uniformly encode individual circuits and generate an initial population. S2, extract the circuit device features of each circuit individual in the initial population, and obtain the population individual sequence under different constraints according to the target design requirements; S3, In different population individual sequences, record the topological connectivity features, device matching features and performance response features of circuit individuals as circuit features, and construct the corresponding evolutionary persistence map based on the generation and extinction process of the circuit features in the iteration process; S4. Weight different circuit features, combine the deviation of the centroid of the circuit feature from the overall population center to generate individual circuit scores, sort all population individuals, determine whether they are abnormally optimized individuals, and summarize to obtain suspected inferior circuit regions. S5. Verify the suspected inferior circuit area, confirm the high-quality circuit individuals, and output the optimal circuit solution that meets the target design requirements based on the characteristics of the corresponding circuit devices.

2. The circuit design method based on genetic optimization according to claim 1, characterized in that, The steps for constructing the hybrid coding model include: A1. Based on the type and design specifications of the circuit to be optimized, determine the optimized topology elements as the topology coding dimension and the optimized device parameters as the parameter coding dimension. A2 employs a two-level coding structure of topology layer and parameter layer, encoding the topology coding dimension and parameter coding dimension of each individual circuit into a hybrid coding string; A3, using preset encoding parsing rules, the hybrid encoded string is parsed from the topology layer encoding and parameter layer encoding to obtain the circuit netlist; A4 verifies the randomized preset number of mixed encoding strings in terms of completeness, validity, and adjustability, and outputs the model that meets the conditions as the mixed encoding model.

3. The circuit design method based on genetic optimization according to claim 1, characterized in that, The steps for extracting the features of the circuit device include: B1, split the hybrid encoding string of the current circuit individual into topology encoding segment and parameter encoding segment, and identify the number of devices and the connection relationship between devices based on the topology encoding segment; B2. Based on the parameter encoding segment, read the parameters and structural features of each device, and supplement the process-related features of each device with the process library information to obtain the circuit device features.

4. The circuit design method based on genetic optimization according to claim 1, characterized in that, The steps to obtain the population individual sequences under different constraints include: C1, based on the target design requirements, determine the performance targets, constraints, and priorities as target indicators, and divide the target indicators into different levels of constraint sets according to different requirements; C2, establish evaluation rules for each set of constraints, evaluate each individual circuit to obtain multiple sets of individuals, and sort each set of individuals from high to low performance to generate a corresponding list of individuals; C3 sorts all the individual lists according to the level of the constraint set to obtain the population individual sequence under different constraint conditions.

5. The circuit design method based on genetic optimization according to claim 1, characterized in that, The steps for obtaining the circuit features include: D1. Feature extraction criteria are determined based on device classification standards, topological connectivity judgment criteria, and simulation parameters of performance response. D2, based on the feature extraction criteria, locate the circuit individuals in the sequence of each population as individuals to be extracted, and perform parsing and reconstruction to obtain the corresponding circuit netlist to be extracted; D3. Filter all circuit nodes and devices according to the circuit netlist to be extracted, assign unique numbers, construct a connectivity path graph according to the port connection of each device, and extract topological connectivity features from the connectivity path graph. D4. Classify all devices of the current circuit individual to be extracted according to their functions, screen matching device groups, calculate the matching degree using the normalized deviation method, and define the matching device group according to the preset matching degree threshold to obtain the device matching characteristics. D5, simulate the individual circuit to be extracted, and obtain static performance indicators, performance compliance, fluctuation range, sensitivity and robustness as the performance response characteristics; D6. Establish the correlation between the topological connectivity features, device matching features, and performance response features, and classify and organize them according to the individual sequence of the population to obtain the circuit features.

6. The circuit design method based on genetic optimization according to claim 1, characterized in that, The steps for constructing the evolutionary persistence map include: E1, in the population individuals corresponding to different iteration generations, record the topological features of the circuit structure, including connected paths, loop structures, port matching relationships and parasitic sensitive regions; E2 records the generation and disappearance algebras of each topological feature, and tracks the generation and disappearance process of each topological feature along the iterative algebra sequence; E3, mark the spatial location and device composition of the topological features in different populations, and match the topological features in adjacent iterations to form the evolutionary trajectory of the topological features; E4. Subtract the number of generations of each topological feature from the number of generations of its generation to obtain the evolutionary lifetime of the topological feature. Based on the type of the topological feature, the evolutionary lifetime of the topological feature, and its spatial distribution, construct the evolutionary persistence map of each individual circuit.

7. The circuit design method based on genetic optimization according to claim 1, characterized in that, The steps for generating the individual scores of the circuit include: F1, for each topological feature in the evolutionary persistence graph, calculate the centroid coordinates, and take the weighted average of the device and node coordinates corresponding to the topological feature as the centroid of the topological feature; F2, the weighted average coordinates of the feature vectors of all individual circuits in the entire population are taken as the overall centroid of the population, and the Euclidean distance between the topological feature centroid and the overall centroid of the population is taken as the degree of deviation. F3, based on the degree of influence of the topological features on circuit performance, set the corresponding weights as topological feature weights; F4 calculates and accumulates the evolutionary lifetime of the topological feature, the weight of the topological feature, and the degree of deviation to generate a circuit score for each circuit individual.

8. The circuit design method based on genetic optimization according to claim 1, characterized in that, The steps for obtaining the suspected defective circuit region include: G1 uses the min-max normalization method to normalize the scores of individual circuits, determines the correlation logic between the scores of individual circuits and circuit quality, sorts all individuals in descending order, and generates a quality ranking table. G2, combining the target design requirements and engineering experience to set dual judgment thresholds, traversing the quality degree ranking table to obtain the abnormal optimization individuals; G3 constructs a mapping and coding rule between the physical regions of the circuit and the individuals in the population, binds the unique identifier of each abnormally optimized individual to the corresponding circuit region, counts the number of abnormally optimized individuals and the average standardized score in the region, and generates a regional anomaly statistics table. G4. Based on the regional anomaly statistics table, the circuit region is divided into three levels of degradation risk: high, medium, and low. Circuit regions with high and medium degradation risk are selected as the suspected defective circuit regions.

9. The circuit design method based on genetic optimization according to claim 1, characterized in that, The steps to obtain the optimal circuit scheme include: H1, cross-validate the suspected substandard circuit region from the data level, simulation level and physical level, and screen the candidate set of high-quality individuals in the region; H2, the high-quality candidate set is screened based on the performance indicators of circuit design to obtain screened individuals, the candidate weights are set according to the target design requirements, and the comprehensive score of the screened individuals is calculated. H3, sort individuals from high to low according to the comprehensive score, and select the first preset proportion of individuals as the initial high-quality individuals; H4. The initially selected high-quality individuals are subjected to simulation tests under different working conditions. Individuals whose indicators are stable and meet the standards under all working conditions and have no obvious performance degradation are selected as the high-quality circuit individuals. H5, extract the circuit device features of the high-quality circuit individuals as a high-quality device feature set, and filter and retain high-quality feature individuals in combination with the target design requirements; H6 uses a feature fusion algorithm to fuse the complementary high-quality features of different high-quality individuals to construct the optimal circuit scheme.

10. A circuit design system based on genetic optimization, employing a circuit design method based on genetic optimization as described in any one of claims 1-9, characterized in that, include: The coding model construction module is used to construct a hybrid coding model of circuit parameters and topology based on the type and design specifications of the circuit to be optimized, to uniformly encode individual circuits, and to generate an initial population. The feature population extraction module is used to extract the circuit device features of each circuit individual in the initial population, and obtain the population individual sequence under different constraints according to the target design requirements; The graph construction module is used to record the topological connectivity features, device matching features, and performance response features of circuit individuals in different population sequences as circuit features, and to construct the corresponding evolutionary persistence graph based on the generation and extinction process of the circuit features during the iteration process. The circuit region filtering module is used to weight different circuit features, combine the deviation of the centroid of the circuit feature from the overall center of the population, generate individual circuit scores, sort all population individuals, determine whether they are abnormally optimized individuals, and summarize to obtain suspected inferior circuit regions. The circuit scheme generation module is used to verify the suspected inferior circuit areas, identify high-quality circuit individuals, and output the optimal circuit scheme that meets the target design requirements by combining the characteristics of the corresponding circuit devices.

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