Method and device for manufacturing PCB (printed circuit board) of server mainboard

Abstract

The invention relates to a method and a device for manufacturing a PCB (Printed Circuit Board) of a server mainboard, which solve the problem of copper thickness difference in a BGA (Ball Grid Array) area through a step of enabling the copper thickness to be uniform, effectively reduce the copper thickness difference in the BGA area, and avoid surface depression, thereby preventing excessive accumulation of resin and film pressing bubbles, and improving the product yield and reliability.

Description

Technical Field

[0001] This invention relates to the field of PCB manufacturing technology, specifically to a method and apparatus for manufacturing a server motherboard PCB. Background Technology

[0002] With the increasing multifunctionality and miniaturization of electronic information products, the integration level of integrated circuits is constantly improving, and their packaging forms are becoming increasingly complex. BGA (Ball Grid Array) packaging technology, as a chip packaging carrier, has become the mainstream packaging form in high-density interconnect structures due to its short pins, numerous leads, small size, and excellent electrical performance. However, with the increasing demand for ultra-high computing power, the design size of the BGA area carrying the chip is constantly increasing, and its design requirements are becoming increasingly stringent. In particular, the density of vias (PTH vias) in this area continues to rise, posing a severe challenge to the manufacturing process of printed circuit boards.

[0003] In the PCB electroplating process, the BGA area, due to its extremely dense via distribution, experiences a significant interplay between the copper deposition thickness within the vias and the surface copper thickness. In actual production, it has been observed that after electroplating, the surface copper thickness in the BGA area is often significantly lower than in other areas of the board, with a typical difference of 5 to 15 micrometers or even greater. While this difference is related to the electroplating equipment and chemicals, its regularity indicates that the structural characteristics of this area are the primary cause of the thinner surface copper. This thickness difference directly leads to the formation of micro-depressions on the BGA surface.

[0004] This depression caused a chain reaction of problems in the subsequent resin plugging process. Due to the low-lying nature of the depression area, resin tends to accumulate excessively during the filling and curing process, making it impossible to completely remove during the grinding process. This often necessitates 100% manual grinding for remediation, severely impacting production efficiency. Even after manually removing the surface resin, the depression's morphology remains fundamentally unchanged. In the subsequent capping electroplating and pre-contact molding dry film pressing process, the significant height difference prevents the dry film from fully adhering to the copper surface at the depression, resulting in incomplete filling or insufficient adhesion, leading to film bubbles. These bubbles severely interfere with the subsequent circuit exposure and etching accuracy, easily causing open-circuit defects and ultimately leading to circuit fabrication failure, significantly reducing product yield and reliability. Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention provide a method and apparatus for manufacturing server motherboard PCBs, which solves the problem that the height difference in the BGA area seriously interferes with the subsequent circuit exposure and etching accuracy, easily causing open circuit defects and ultimately leading to circuit manufacturing failure.

[0006] According to one aspect of the present invention, a method for manufacturing a server motherboard PCB is provided, the method comprising:

[0007] S11, multiple inner layer boards are pressed together to form a first multilayer board, a first hole is drilled in the first multilayer board and a plasma desmearing treatment is performed on the first multilayer board, a first electroplating is performed on the first multilayer board to form a first copper plating layer on the surface of the first multilayer board and the first hole, and a hole plating treatment or a first copper reduction treatment is performed on the first multilayer board to make the copper thickness of the first copper plating layer uniform. S12, a first outer layer is pressed onto the surface of the first multilayer board to form a second multilayer board; S13, after executing step S12 multiple times, a second outer layer is pressed onto the surface of the second multilayer board, and the second multilayer board is subjected to outer layer material processing to form the target multilayer board.

[0008] In some optional embodiments, the hole plating process includes: S21, a dry film treatment is performed on the first electroplating layer to form a first dry film pattern on the first electroplating layer, and a dry film window is made in the first drilling area of ​​the first electroplating layer, wherein the first drilling area is the area extending outward from the first drilling position by a first preset value. S22, The copper thickness of the first drilled area is increased by plating copper in the first drilled area; S23, the first dry film pattern of the first electroplated layer is removed by a film-removing solution.

[0009] In some optional embodiments, the first copper reduction process includes: S32, perform dry film treatment on the first electroplating layer to form a second dry film pattern on the first electroplating layer, and perform dry film windowing in the BGA area of ​​the first electroplating layer. S32, by reducing the copper in the BGA area, the copper thickness of the BGA area is reduced; S33, the second dry film pattern of the first electroplated layer is removed by a film-removing solution.

[0010] In some alternative embodiments, prior to performing a dry film treatment on the first electroplated layer to form a second dry film pattern on the first electroplated layer, the method further includes: The copper thickness of the first electroplated layer is measured to obtain the BGA area of ​​the first electroplated layer, and the copper thickness difference between the BGA area and other areas of the first electroplated layer is calculated; the copper thickness difference of the BGA area is removed by the first copper reduction process.

[0011] In some optional embodiments, after step S11 and before step S12, the method further includes: The first drilled hole is subjected to resin plugging treatment, dry film sealing treatment, second copper reduction treatment, resin grinding treatment, capping electroplating treatment, outer layer circuit fabrication, and outer layer AOI inspection in sequence.

[0012] In some optional embodiments, step S12, in which the first outer layer is pressed onto the surface of the first multilayer board, further includes: The second multilayer board is sequentially subjected to edge forming treatment, LDD browning treatment, laser blind via fabrication treatment, plasma adhesive removal treatment, browning removal treatment, blind via AOI treatment, via filling electroplating treatment, outer layer circuit fabrication, and outer layer AOI inspection.

[0013] In some optional embodiments, the outer layer processing of the second multilayer board specifically includes: The second multilayer board is subjected to the following processes in sequence: LDD browning treatment, laser treatment, plasma desmearing treatment, browning removal treatment, blind via AOI treatment, via filling electroplating treatment, third copper reduction treatment, drilling treatment, baking treatment, PLASMA treatment, second electroplating treatment, resin via plugging treatment, drilling treatment, baking treatment, dry film sealing treatment, copper reduction treatment, film removal treatment, resin grinding treatment, via capping electroplating treatment, outer layer circuit treatment, external inspection AOI treatment, solder mask treatment, first text processing, second text processing, IR treatment, impedance testing treatment, electroless gold treatment, molding treatment, electrical testing treatment, withstand voltage testing treatment, FQC treatment, OQC treatment and packaging treatment to produce the target multilayer board.

[0014] In some alternative embodiments, the target multilayer board has 24 inner layers, 8 first outer layers, and 2 second outer layers.

[0015] In some optional embodiments, the first multilayer board is browned before step S12; and the second multilayer board is browned before step S13.

[0016] According to another aspect of the present invention, a server motherboard PCB manufacturing apparatus is provided, the apparatus being used in the above-described server motherboard PCB manufacturing method.

[0017] The present invention discloses a server motherboard PCB manufacturing method and apparatus, the beneficial effects of which are as follows: the present invention solves the problem of copper thickness difference in the BGA area by including a step of making the copper thickness uniform, effectively reducing the copper thickness difference in the BGA area, avoiding surface depression, thereby preventing excessive resin accumulation and molding bubbles, and improving product yield and reliability.

[0018] The above description is merely an overview of the technical solutions of the embodiments of the present invention. In order to better understand the technical means of the embodiments of the present invention and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0019] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 A flowchart illustrating the server motherboard PCB manufacturing method according to Embodiment 1 of the present invention is shown. Figure 2 A schematic diagram of the hole plating process of Embodiment 1 provided by the present invention is shown; Figure 3 A schematic diagram of the first copper reduction process of Embodiment 1 provided by the present invention is shown. Detailed Implementation

[0020] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0021] Example 1 Figure 1 This invention illustrates a first embodiment of a server motherboard PCB manufacturing method, addressing the problem that height differences in the BGA area severely interfere with subsequent circuit exposure and etching accuracy, easily causing open-circuit defects and ultimately leading to circuit manufacturing failure. The method includes: In step S11, multiple inner layer boards are laminated to form a first multilayer board. A first hole is drilled in the first multilayer board to form a first drilled hole, and the first multilayer board undergoes plasma desmearing. A first electroplating process is performed on the first multilayer board to form a first copper plating layer on the surface of the first multilayer board and in the first drilled hole. A hole-plating process or a first copper reduction process is then performed on the first multilayer board to ensure uniform copper thickness in the first copper plating layer. In step S11, the inner layer boards constitute the basic unit of the conductive layer inside the multilayer board. The first multilayer board is an intermediate structure formed by bonding multiple inner layer boards together. The first drilled hole forms a hole in the first multilayer board to achieve interlayer electrical connection. The plasma desmearing process uses plasma to remove resin residue from the drilled hole walls, ensuring effective bonding between the electroplated layer and the hole walls. The first electroplating deposits a copper layer on the surface of the first multilayer board and inside the first drilled hole. The first copper plating layer is formed by the first electroplating on the surface of the first multilayer board and inside the first drilled hole. The hole-plating process selectively thickens the copper layer in specific areas of the first copper plating layer. The first copper reduction process selectively thins the copper layer in specific areas of the first copper plating layer.

[0022] Multiple inner layers are laminated to form a first multilayer board. This lamination process can be performed using a hot press, where temperature, pressure, and time are controlled to ensure thorough bonding between the inner layers and with the prepreg. Subsequently, holes are drilled into the first multilayer board to form the first drilled holes. This drilling can be performed using mechanical drilling equipment, where the desired through-holes or blind holes are formed by setting the drilling coordinates and depth. After drilling, the first multilayer board undergoes plasma desmearing. This treatment utilizes plasma cleaning equipment to remove resin residue from the drilled hole walls through plasma bombardment, improving the roughness and cleanliness of the hole walls and providing an adhesion base for subsequent electroplating. Next, the first multilayer board undergoes its first electroplating to form a first copper plating layer on its surface and within the first drilled holes. This electroplating process can employ direct current electroplating or pulse electroplating, where the copper layer deposition is uniform by adjusting the electroplating solution composition, current density, and plating time. To ensure uniform copper thickness in the first copper plating layer, the first multilayer board can undergo a hole plating process or a first copper reduction process. For example, the plated hole treatment can be a secondary electroplating process on the entire board surface to increase the copper thickness; or, the first copper reduction treatment can be an overall etching process on the entire board surface to reduce the copper thickness.

[0023] S12, a first outer layer is pressed onto the surface of a first multilayer board to form a second multilayer board; in step S12, the first outer layer is pressed onto the surface of the first multilayer board to form the outer conductive layer of the second multilayer board. The second multilayer board forms a complex multilayer board structure after the first outer layer is pressed onto the surface of the first multilayer board.

[0024] A first outer layer is laminated onto the surface of the first multilayer board to form a second multilayer board. This lamination process is similar to that of the inner layer board, and it also requires control of process parameters to ensure a strong bond between the first outer layer board and the first multilayer board.

[0025] In step S13, after multiple executions of step S12, a second outer layer board is laminated onto the surface of the second multilayer board, and the second multilayer board undergoes outer layer material processing to form the target multilayer board. In step S13, the second outer layer board is laminated onto the surface of the second multilayer board to form the outermost layer of the final target multilayer board. The outer layer material processing involves a series of processes on the second multilayer board to complete the outer layer circuitry and structure. The target multilayer board, after all manufacturing steps, forms the final server motherboard PCB.

[0026] After repeatedly executing step S12, a second outer layer board is laminated onto the surface of the second multilayer board, and the second multilayer board undergoes outer layer material processing to form the target multilayer board. Repeated execution of step S12 means that the process of laminating the inner and outer layers can be repeated according to design requirements to increase the number of PCB layers and complexity. The lamination of the second outer layer board also employs a hot-pressing process. Outer layer material processing can include a series of conventional PCB manufacturing processes, such as circuit fabrication, solder resist printing, text printing, and surface treatment, to achieve the final circuit pattern and surface functionality.

[0027] In a specific example, taking a 34-layer, 4-stage HDI board as an example, its structure is 4+26+4. The inner 26 layers are fabricated through step S11. Then, in step S12, the outermost layer is laminated onto the inner 26 layers sequentially. Finally, the last layer is laminated through step S13. The PCB board is designed as a single PCS, with a single PCS shipping size of 487.5*434mm and a finished board thickness of 4.7±0.47mm. The buried vias are designed at L5-30, with a board thickness of 3.75±0.18mm, a copper plating thickness of 38μm, and a required via copper thickness of 26.65um. The inner layers are all 2oz copper core boards, with an inner layer circuit design trace width of 2.8 / 4mil; the outer layer circuit design is 3 / 4mil, with internal and external impedances of 50Ω, 85Ω, and 100OHM ±8%Ω; the surface treatment is gold plating.

[0028] By homogenizing the copper thickness of the first copper layer after the initial electroplating, this invention effectively solves the problems of uneven copper thickness and microscopic depressions in the BGA area caused by dense vias in existing PCB manufacturing. This provides a flat substrate for subsequent resin plugging, grinding, and dry film lamination processes, avoiding excessive resin buildup and the generation of lamination bubbles, thereby improving the accuracy and yield of circuit fabrication and effectively enhancing the reliability of server motherboard PCBs.

[0029] Example 2 Based on Embodiment 1, the present invention provides a second embodiment of a server motherboard PCB manufacturing method to further describe steps S11-S13 in Embodiment 1.

[0030] In one embodiment of step S11, see Figure 2 Hole plating treatment includes: S21, a dry film treatment is performed on the first electroplated layer to form a first dry film pattern on the first electroplated layer, and a dry film window is made in the first drilling area of ​​the first electroplated layer, wherein the first drilling area is the area extending outward from the first drilling position by a first preset value. S22, The copper thickness of the first drilled area is increased by plating copper in the first drilled area; S23, the first dry film pattern of the first electroplated layer is removed by a film-removing solution.

[0031] In steps S21-S22, a dry film treatment is performed on the first electroplated layer to form a first dry film pattern, and a dry film window is created in the first drilled area of ​​the first electroplated layer, wherein the first drilled area is the region extending outward from the first drilled location by a first preset value. This step aims to precisely define the area requiring additional copper deposition using photolithography. The dry film treatment typically involves laminating a layer of photosensitive dry film onto the surface of the first electroplated layer. Then, a specific pattern, the first dry film pattern, is formed on the dry film through exposure and development processes. The dry film window is created by removing the dry film from the region extending outward from the first drilled location and its surrounding area by a first preset value (i.e., the first drilled area), thereby exposing the underlying copper layer. The setting of this "first preset value" is crucial; it ensures that copper plating not only occurs inside the drilled hole but also forms a reinforcing ring at the drilled edge, thereby improving the bonding strength and reliability between the hole wall and the surface pads. This preset value can be optimized according to the PCB design requirements, hole size, and required mechanical strength and electrical performance; for example, it can be set to 0.05 mm to 0.2 mm.

[0032] Copper plating is applied to the first drilled area to thicken the copper layer there. After the dry film is opened, the exposed first drilled area (including the hole wall and surrounding extension) serves as the cathode for secondary electroplating in the plating solution. This process uses an electrochemical reaction to deposit copper ions on these exposed copper surfaces, selectively increasing the copper thickness in that area. This targeted thickening treatment effectively compensates for any uneven copper thickness that may be caused by the initial plating, especially in high aspect ratio drill holes, ensuring that the hole wall copper thickness meets design requirements and enhancing conductivity and mechanical strength. Electroplating parameters, such as current density, plating time, plating solution composition, and temperature, must be strictly controlled to guarantee coating quality and thickness uniformity.

[0033] The first dry film pattern of the first electroplated layer is removed using a stripping solution. After copper plating thickening is completed, any remaining dry film pattern needs to be completely removed. This is typically done by immersing or spraying the PCB with an alkaline stripping solution to dissolve and peel off the dry film, exposing the entire surface of the first electroplated layer and preparing it for subsequent manufacturing processes. This step must ensure that any dry film residue is completely removed to avoid affecting subsequent circuit fabrication or surface treatment.

[0034] In a specific example, this invention involves a single 38µm copper plating process, divided into a first plating step and a hole plating process. The first plating is a full-board plating with a copper thickness of 15µm. Then, a dry film pattern is applied, exposing the holes for individual hole-layer copper plating, with each hole having a 2.5mil thickness on one side. Next, pulse plating is performed using a pattern electroplating method, setting the copper thickness to 23µm. Once the holes are sufficiently copper-plated, subsequent processes can proceed normally. This process uses 1oz copper foil for lamination to prevent the risk of insufficient copper thickness on the resin-polished board surface, exposing the substrate.

[0035] By employing the aforementioned technical solution and precisely defining the dry film pattern, selective thickening of the copper in the first drilled area is achieved. This localized thickening effectively compensates for potential copper thickness unevenness during the initial electroplating process, especially within the drilled area and at the hole opening. By extending the copper plating area outward from the first drilled location by a predetermined value, not only is the conductivity and mechanical strength of the hole wall enhanced, but the bonding reliability between the hole opening and the surface pads is also significantly improved, effectively avoiding defects such as open circuits and cold solder joints caused by insufficient or uneven copper thickness. For server motherboard PCBs, this ensures the integrity of critical signal transmission and the stability of power supply, thereby significantly improving the overall reliability and lifespan of the PCB.

[0036] In another embodiment of step S11, see Figure 3 The first copper reduction process includes: S31, dry film treatment is performed on the first electroplating layer to form a second dry film pattern on the first electroplating layer, and dry film opening is performed in the BGA area of ​​the first electroplating layer. S32, by reducing the copper in the BGA area, the copper thickness of the BGA area is reduced; S33, the second dry film pattern of the first electroplated layer is removed by a film-removing solution.

[0037] In steps S31-S32, dry film processing of the first electroplated layer refers to attaching a photosensitive dry film to the surface of the first electroplated layer. After exposure and development, this dry film can form a protective layer with a specific pattern, namely the second dry film pattern. The BGA region refers to the area of ​​a ball grid array package, typically the pad array on a PCB used to mount BGA chips. These areas have high requirements for copper thickness and flatness. Dry film windowing in the BGA region of the first electroplated layer refers to removing the dry film of the BGA region from the second dry film pattern using a photolithography process, exposing the copper layer in that region, while other non-BGA regions are covered and protected by the dry film. For example, a pre-cut dry film can first be attached to the surface of the first electroplated layer by hot pressing or vacuum bonding. Subsequently, the dry film is exposed using a photolithography machine, with the windowing pattern for the BGA region pre-set on the exposure mask. Next, the exposed dry film is developed using a developer solution, dissolving and removing any unexposed or insufficiently exposed dry film, thereby forming a window in the BGA region and exposing the underlying copper layer.

[0038] Subsequently, copper reduction is performed on the BGA area to reduce its copper thickness. This step aims to precisely thin any excessively thick copper layer in the BGA area, ensuring the copper thickness meets design requirements and guaranteeing the flatness of the BGA pads and the reliability of subsequent soldering. After opening windows in the dry film of the BGA area, the PCB board can be immersed in a specific copper reduction solution, such as an acidic etching solution (e.g., copper chloride etching solution, ammonium persulfate etching solution) or an alkaline etching solution. The etching solution will chemically react with the exposed copper layer, dissolving the copper. The copper reduction process requires precise control of etching time, etching solution concentration, and temperature to ensure that the copper thickness in the BGA area is uniformly and accurately reduced to the target value. Alternatively, electrolytic copper reduction can be used, removing copper by controlling the current and time.

[0039] Finally, the second dry film pattern of the first electroplated layer is removed using a stripping solution. The purpose of this step is to remove the unwanted dry film protective layer after the copper reduction treatment, restoring the entire first electroplated layer to a state suitable for subsequent processes. Specifically, the PCB board that has undergone copper reduction treatment is immersed in a stripping solution (such as sodium hydroxide solution or a specialized stripping agent). The stripping solution dissolves and peels off the dry film, exposing the underlying protected copper layer. Subsequently, the PCB board is thoroughly cleaned to remove any remaining stripping solution and dry film residue.

[0040] In one specific example, after electroplating, the present invention measures the copper thickness of the BGA area and the difference in copper thickness between it and other areas. Then, a dry film is applied to the BGA area, exposing areas with thicker copper for copper reduction, eliminating the thickness difference and ensuring that the BGA area has the same board thickness as other areas, without any depressions. This facilitates normal grinding operations after resin plugging, allowing the resin in the BGA area to be cleaned. This process uses 0.33 oz copper foil for lamination.

[0041] The above technical solution allows for precise copper reduction in BGA areas where the copper thickness in the first plating layer may be excessive, following the initial electroplating. Dry film windowing technology ensures that the copper reduction operation only affects the target BGA area, avoiding unnecessary thinning of other areas. This localized, precise copper reduction effectively solves the problem of uneven copper thickness in BGA areas, ensuring that the copper thickness of the BGA pads meets design requirements and significantly improving the flatness and consistency of the BGA pads. This not only facilitates subsequent solder mask, surface treatment, and component soldering processes, reducing soldering defect rates, but also enhances the overall reliability and electrical performance of the server motherboard PCB, ensuring stable connections of BGA devices.

[0042] In some optional embodiments, before performing a dry film treatment on the first electroplated layer to form a second dry film pattern on the first electroplated layer, the method further includes: The copper thickness of the first electroplated layer is measured to obtain the BGA area of ​​the first electroplated layer, and the copper thickness difference between the BGA area and other areas of the first electroplated layer is calculated; the copper thickness difference of the BGA area is removed by the first copper reduction process.

[0043] Specifically, before the first copper reduction process, the copper thickness of the first electroplated layer is measured. Copper thickness measurement refers to the precise measurement of the copper thickness on the surface of the first electroplated layer using specialized measuring equipment. This can be achieved through various non-contact or contact methods, such as eddy current method, X-ray fluorescence (XRF) method, or microresistance method. The eddy current method measures copper thickness by inducing changes in the magnetic field generated by an induced current, offering advantages such as non-destructiveness and speed. The XRF method determines copper thickness by analyzing the fluorescence spectrum generated by X-ray excitation of the sample, offering high accuracy. The microresistance method estimates copper thickness by measuring the resistance of a specific area. The choice of measurement method depends on the required accuracy, measurement speed, and the structural characteristics of the PCB. This step aims to obtain the overall copper thickness distribution of the first electroplated layer, providing a data basis for subsequent precise copper reduction.

[0044] After copper thickness measurement, it is necessary to obtain the BGA area of ​​the first electroplated layer. Obtaining the BGA area means accurately identifying and locating the corresponding area of ​​the BGA (Ball Grid Array) package on the first electroplated layer according to the PCB design drawings or preset coordinate information after copper thickness measurement. The BGA area is usually the mounting location of integrated circuit chips on the PCB, and it has high requirements for copper thickness consistency and flatness. This step ensures that subsequent copper thickness difference calculations and copper reduction processing can be accurately applied to the target area, avoiding misoperation or omissions.

[0045] Subsequently, the copper thickness difference between the BGA region and other regions of the first electroplated layer is calculated. After obtaining the copper thickness data for the BGA region and other regions of the first electroplated layer, data processing and analysis are used to calculate the difference between the average copper thickness of the BGA region and the average copper thickness of other regions of the first electroplated layer. This difference is a key indicator for measuring copper thickness uniformity. The calculation method can be to compare the average value of multiple measurement points within the BGA region with the average value of multiple measurement points outside the BGA region, or to use more complex statistical methods to assess the differences between regions. The purpose of this step is to quantify the non-uniformity of copper thickness, providing a precise basis for subsequent copper reduction.

[0046] Finally, the copper thickness difference in the BGA area is removed through the first copper reduction treatment. Based on the previously calculated copper thickness difference, the process parameters of the first copper reduction treatment are precisely controlled, such as the concentration of the copper-reducing solution, temperature, and treatment time, to specifically remove excess copper thickness in the BGA area, making it consistent with or within acceptable tolerances of the copper thickness in other areas of the first electroplating layer. Here, "removing the copper thickness difference" means that the goal of the copper reduction treatment is no longer simply to thin the copper thickness in the BGA area, but to balance its copper thickness with the surrounding areas, thereby achieving uniformity of the copper thickness of the entire first electroplating layer. This can be achieved by adjusting the size of the dry film opening, the spray intensity or time of the copper-reducing solution, etc.

[0047] In some optional embodiments, after step S11 and before step S12, the method further includes: The first drilled hole is sequentially treated with resin plugging, dry film sealing, second copper reduction, resin grinding, capping electroplating, outer layer circuit fabrication, and outer layer AOI inspection.

[0048] Through the above technical solutions, firstly, the synergistic effect of resin plugging and resin polishing effectively solves the problems of voids and uneven surfaces inside the first drilled holes, providing an extremely flat and solid base for subsequent high-precision circuit fabrication, significantly improving the mechanical strength and reliability of the holes. Secondly, the combination of dry film sealing and the second copper reduction process achieves precise control and uniformity of copper thickness in the plugged area, avoiding differences in circuit etching or fluctuations in electrical performance caused by uneven copper thickness, thus ensuring the fineness and consistency of the circuit. Thirdly, the via plating process further enhances the conductivity and mechanical connection reliability of the plugged area, ensuring the integrity of signal transmission between inner and outer layers. Finally, after the outer layer circuit fabrication is completed, AOI inspection of the outer layer can promptly detect and correct potential circuit defects, thereby significantly improving the circuit fabrication yield and overall product quality of the server motherboard PCB. The introduction of these steps effectively solves problems such as hole reliability, board surface flatness, and copper thickness uniformity that may exist in the first multilayer board stage, laying a solid foundation for the high-density and high-reliability requirements of server motherboard PCBs, thus significantly improving the overall electrical performance and long-term operational stability of the product.

[0049] In some optional embodiments, step S12, in which the first outer layer is pressed onto the surface of the first multilayer board, further includes: The second multilayer board is sequentially subjected to edge forming treatment, LDD browning treatment, laser blind via fabrication treatment, plasma adhesive removal treatment, browning removal treatment, blind via AOI treatment, via filling electroplating treatment, outer layer circuit fabrication, and outer layer AOI inspection.

[0050] Specifically, edge forming refers to the machining of the second-layer board to obtain a preset outer contour or internal slots. This process is usually completed by CNC milling machines or laser cutting equipment, which precisely cuts the board according to the design drawings, removes excess edge material, or forms specific shapes inside the board, providing a foundation for subsequent assembly and functional implementation. Its purpose is to ensure that the dimensional accuracy and shape of the PCB board meet the design requirements, facilitating subsequent automated production and installation.

[0051] LDD browning is a chemical surface treatment process designed to enhance the adhesion between the inner copper foil of a second multilayer board and the subsequently laminated dielectric layer, and to prevent copper surface oxidation. LDD (Low Density Deposit) browning technology significantly improves interlayer bonding strength and effectively avoids delamination by forming a dense organic or inorganic thin film on the copper surface, providing a rough microstructure.

[0052] Laser-etched blind vias utilize a high-energy laser beam to precisely ablate blind vias into a multilayer board. A blind via is a hole that penetrates only a portion of the dielectric layer without completely penetrating the entire board thickness. This process, by controlling the laser energy, pulse width, and scanning path, achieves precise removal of the dielectric material, forming blind vias with specific depths and diameters. These are used to connect circuits between different layers, increasing wiring density.

[0053] Plasma desmearing refers to the process of cleaning the interior of blind vias using plasma after laser ablation. This treatment uses active gas plasma to bombard the via walls, removing resin residues, carbides, and other contaminants generated during laser ablation. This cleans the via surface and slightly roughens it, thereby improving the adhesion between the subsequent electroplated copper layer and the via wall, ensuring the quality and reliability of the blind via plating.

[0054] De-browning is a chemical treatment performed on the surface of a second-layer multilayer board after LDD browning and before certain subsequent processes (such as electroplating). Its purpose is to remove or adjust the browning layer to ensure that subsequent processes (such as outer layer circuit fabrication) can proceed smoothly and achieve good adhesion or electroplating results.

[0055] Blind hole AOI (Automated Optical Inspection) is a process that uses automated optical inspection equipment to perform quality checks on fabricated blind holes. This process uses high-resolution cameras and image processing algorithms to detect the location, diameter, depth, and wall integrity of the blind holes, as well as the presence of defects such as residual adhesive or foreign matter. This ensures that the fabrication quality of the blind holes meets design specifications and avoids potential electrical connection problems.

[0056] Through-hole plating is a process that uses electrochemical deposition to fill blind vias with conductive material (usually copper). This process aims to completely fill the blind vias with copper, creating a flat surface to facilitate subsequent outer layer fabrication and provide reliable electrical connections. Through-hole plating typically employs specialized plating solutions and process parameters to ensure a uniform, dense, and void-free copper layer.

[0057] Outer layer fabrication refers to the formation of conductive patterns on the outermost surface of a second-layer multilayer board. This process typically includes steps such as photolithography, development, etching, and electroplating. First, a resist layer for the circuit pattern is formed on copper foil using photolithography. Then, the copper not covered by the resist layer is removed by etching to form the desired circuitry. Alternatively, the circuitry can be thickened by electroplating, followed by the removal of the resist layer and excess copper.

[0058] Outer layer AOI inspection utilizes automated optical inspection equipment to perform quality checks on outer layer circuitry. This process scans the outer layer circuitry pattern to detect defects such as short circuits, open circuits, uneven line widths, residual copper, and foreign objects. Through high-efficiency and high-precision inspection, the electrical performance and reliability of the outer layer circuitry are ensured, preventing defective products from entering subsequent processes.

[0059] Through the above technical solution, a series of refined processing steps are systematically introduced after the formation of the second multilayer board. The forming and milling process ensures the precise shape of the board, laying the foundation for subsequent processing. The combination of LDD browning and debrowning treatments effectively improves interlayer bonding and provides a suitable surface condition for subsequent processes. Laser blind via fabrication combined with plasma adhesive removal enables high-precision, high-quality blind via fabrication and thoroughly removes residue from the via walls, significantly improving the reliability of blind vias and electroplating quality. Blind via AOI processing and outer layer AOI inspection rigorously control blind vias and outer layer circuitry at critical nodes, promptly identifying and correcting potential defects. Through-hole electroplating ensures the conductivity and surface flatness of the blind vias, providing an ideal substrate for outer layer circuitry fabrication. Outer layer circuitry fabrication completes the final circuit layout. This organic combination of processing steps not only solves the problems of poor blind via reliability and numerous circuit defects that may be encountered after the formation of the second multilayer board, but also significantly improves the wiring density, electrical performance, and overall reliability of server motherboard PCBs, meeting the stringent requirements of high-end server applications for PCB boards.

[0060] In some optional embodiments, the second multilayer board undergoes outer layer processing, specifically including: The second multilayer board is subjected to the following processes in sequence: LDD browning treatment, laser treatment, plasma desmearing treatment, browning removal treatment, blind via AOI treatment, via filling electroplating treatment, third copper reduction treatment, drilling treatment, baking treatment, PLASMA treatment, second electroplating treatment, resin via plugging treatment, drilling treatment, baking treatment, dry film sealing treatment, copper reduction treatment, film removal treatment, resin grinding treatment, via capping electroplating treatment, outer layer circuit treatment, external inspection AOI treatment, solder mask treatment, first text processing, second text processing, IR treatment, impedance testing treatment, electroless gold treatment, molding treatment, electrical testing treatment, withstand voltage testing treatment, FQC treatment, OQC treatment and packaging treatment to produce the target multilayer board.

[0061] Through the aforementioned series of refined and systematic outer layer board processing steps, this invention significantly improves the overall quality and reliability of server motherboard PCBs. LDD browning and de-browning processes ensure strong interlayer bonding, effectively preventing delamination. The combination of laser processing, plasma adhesive removal, blind via AOI processing, and via-filling electroplating greatly improves the manufacturing precision, hole wall cleanliness, and filling integrity of blind vias, thereby ensuring the electrical reliability of high-density interconnects. Multiple drilling, baking, copper reduction, and electroplating processes, combined with resin plugging, resin grinding, and via-capping electroplating, achieve a high degree of board flatness and precise control of copper thickness, which is crucial for the manufacturing precision and impedance matching of subsequent outer layer circuitry. Outer layer circuitry processing and external AOI inspection ensure the integrity and defect-free nature of the circuitry. Solder resist treatment, first text processing, second text processing, and electroless gold plating provide excellent protection, marking, and solderability. The final impedance testing, electrical testing, withstand voltage testing, FQC processing, OQC processing, and other comprehensive inspections ensure that every server motherboard PCB has excellent electrical performance and structural stability. This effectively solves problems that may occur in traditional processes, such as poor reliability of blind vias, impedance mismatch, and low yield, thus providing a solid foundation for the stable operation of the server.

[0062] In some alternative embodiments, the target multilayer board has 24 inner layers, 8 first outer layers, and 2 second outer layers.

[0063] The aforementioned technical solution designs the target multilayer board into a specific stacked structure comprising 24 inner layers, 8 first outer layers, and 2 second outer layers. This effectively addresses the signal integrity, power integrity, and manufacturing process optimization challenges faced by traditional multilayer boards in meeting the complex functional requirements of server motherboards. Specifically, the 24 inner layers provide ample routing space, enabling precise layout of high-speed signal lines, power layers, and ground layers. This effectively reduces signal crosstalk and electromagnetic interference, ensuring the stability and integrity of signal transmission. The configuration of 8 first outer layers and 2 second outer layers, combined with multiple lamination processes, not only provides sufficient layer support for complex circuit designs but also allows for targeted process treatments at different lamination stages. For example, drilling, electroplating, and copper reduction can be performed at the first and second multilayer board stages, thereby optimizing the overall production process and improving manufacturing precision and yield. This precise layer configuration allows the server motherboard to achieve high-density integration and high-performance operation while better controlling impedance matching, reducing power supply noise, and improving overall product reliability.

[0064] In some optional embodiments, the first multilayer board is browned before step S12; and the second multilayer board is browned before step S13.

[0065] By performing a browning treatment on the respective multilayer boards before laminating the first outer layer board to the first multilayer board, and before laminating the second outer layer board to the second multilayer board, this invention effectively solves the problem of insufficient interlayer bonding strength during multilayer board lamination. The browning treatment forms a micro-roughened and chemically active oxide layer on the copper foil surface, significantly improving the mechanical anchoring and chemical bonding capabilities between the copper foil and the dielectric material. This not only greatly reduces the risk of defects such as delamination and board bursting during PCB manufacturing, but also enhances the interlayer bonding strength and overall reliability of server motherboard PCBs under long-term operation and complex thermal cycling conditions, thereby ensuring the stability and service life of the final product.

[0066] Example 3 According to another aspect of the present invention, a server motherboard PCB manufacturing apparatus is provided, which is used in the server motherboard PCB manufacturing method of Embodiment 1 or Embodiment 2.

[0067] The aforementioned technical solution enables the systematic, automated, and integrated management of the complex steps in server motherboard PCB manufacturing. By precisely controlling various process parameters, such as drilling location, plating thickness, and via plugging quality, this device significantly reduces the impact of human error and environmental factors on product quality. Particularly for blind via fabrication, the device ensures the accuracy of drilling depth and location, as well as the uniformity of subsequent plugging and plating, effectively avoiding defects such as internal voids and uneven copper thickness within blind vias, thus greatly improving their reliability. Furthermore, the integrated production process enhances production efficiency and consistency, reduces production costs, and ultimately guarantees the high quality and long lifespan of server motherboard PCBs.

[0068] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. Similarly, for the sake of brevity and to aid in understanding one or more aspects of the invention, in the description of exemplary embodiments of the invention above, various features of the embodiments are sometimes grouped together in a single embodiment, figure, or description thereof. The claims, which follow the detailed description, are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the invention.

[0069] Those skilled in the art will understand that the modules in the device of the embodiment can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiment can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components, except that at least some of such features and / or processes or units are mutually exclusive.

[0070] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several systems, several of these systems may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names. The steps in the above embodiments, unless otherwise specified, should not be construed as limiting the order of execution.

Claims

1. A method for manufacturing a server motherboard PCB, characterized in that, The method includes: S11, multiple inner layer boards are pressed together to form a first multilayer board, a first hole is drilled in the first multilayer board and a plasma desmearing treatment is performed on the first multilayer board, a first electroplating is performed on the first multilayer board to form a first copper plating layer on the surface of the first multilayer board and the first hole, and a hole plating treatment or a first copper reduction treatment is performed on the first multilayer board to make the copper thickness of the first copper plating layer uniform. S12, a first outer layer is pressed onto the surface of the first multilayer board to form a second multilayer board; S13, after executing step S12 multiple times, a second outer layer is pressed onto the surface of the second multilayer board, and the second multilayer board is subjected to outer layer material processing to form the target multilayer board.

2. The server motherboard PCB manufacturing method according to claim 1, characterized in that, The hole plating process includes: S21, a dry film treatment is performed on the first electroplating layer to form a first dry film pattern on the first electroplating layer, and a dry film window is made in the first drilling area of ​​the first electroplating layer, wherein the first drilling area is the area extending outward from the first drilling position by a first preset value. S22, the copper thickness of the first drilled area is increased by plating copper on the first drilled area; S23, the first dry film pattern of the first electroplated layer is removed by a film-removing solution.

3. The server motherboard PCB manufacturing method according to claim 1, characterized in that, The first copper reduction process includes: S31, dry film treatment is performed on the first electroplating layer to form a second dry film pattern on the first electroplating layer, and dry film opening is performed in the BGA area of ​​the first electroplating layer. S32 reduces the copper thickness of the BGA region by reducing the copper content of the BGA region. S32, the second dry film pattern of the first electroplated layer is removed by a film-removing solution.

4. The server motherboard PCB manufacturing method according to claim 3, characterized in that, Before step S31, the method further includes: The copper thickness of the first electroplated layer is measured to obtain the BGA area of ​​the first electroplated layer, and the copper thickness difference between the BGA area and other areas of the first electroplated layer is calculated; the copper thickness difference of the BGA area is removed by the first copper reduction process.

5. The server motherboard PCB manufacturing method according to claim 1, characterized in that, After step S11 and before step S12, the method further includes: The first drilled hole is subjected to resin plugging treatment, dry film sealing treatment, second copper reduction treatment, resin grinding treatment, capping electroplating treatment, outer layer circuit fabrication, and outer layer AOI inspection in sequence.

6. The server motherboard PCB manufacturing method according to claim 1, characterized in that, In step S12, the process of pressing the first outer layer onto the surface of the first multilayer board further includes: The second multilayer board is sequentially subjected to edge forming treatment, LDD browning treatment, laser blind via fabrication treatment, plasma adhesive removal treatment, browning removal treatment, blind via AOI treatment, via filling electroplating treatment, outer layer circuit fabrication, and outer layer AOI inspection.

7. The server motherboard PCB manufacturing method according to claim 1, characterized in that, The outer layer processing of the second multilayer board specifically includes: The second multilayer board is subjected to the following processes in sequence: LDD browning treatment, laser treatment, plasma desmearing treatment, browning removal treatment, blind via AOI treatment, via filling electroplating treatment, third copper reduction treatment, drilling treatment, baking treatment, PLASMA treatment, second electroplating treatment, resin via plugging treatment, drilling treatment, baking treatment, dry film sealing treatment, copper reduction treatment, film removal treatment, resin grinding treatment, via capping electroplating treatment, outer layer circuit treatment, external inspection AOI treatment, solder mask treatment, first text processing, second text processing, IR treatment, impedance testing treatment, electroless gold treatment, molding treatment, electrical testing treatment, withstand voltage testing treatment, FQC treatment, OQC treatment and packaging treatment to produce the target multilayer board.

8. The server motherboard PCB manufacturing method according to claim 1, characterized in that, The target multilayer board has 24 inner layers, 8 first outer layers, and 2 second outer layers.

9. The server motherboard PCB manufacturing method according to claim 1, characterized in that, Before step S12, the first multilayer board is subjected to browning treatment; before step S13, the second multilayer board is subjected to browning treatment.

10. A server motherboard PCB manufacturing apparatus, characterized in that, The apparatus is used to perform the server motherboard PCB manufacturing method according to any one of claims 1-9.

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