Silicon-on-insulator substrate and preparation method thereof
By employing a two-stage ion implantation and intelligent stripping process, combined with rapid thermal processing and oxide layer removal, the problems of crystal quality and film thickness uniformity of ultrathin SOI substrates were solved, resulting in the fabrication of high-performance silicon-on-insulator substrates, which improved the operating speed and reliability of devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIAN ESWIN MATERIAL TECHNOLOGY CO LTD
- Filing Date
- 2025-11-21
- Publication Date
- 2026-05-22
AI Technical Summary
Existing technologies struggle to stably and efficiently fabricate ultrathin SOI substrates that simultaneously possess high crystal quality and excellent film thickness uniformity, especially in addressing challenges related to high defect density and film thickness unevenness caused by low-energy ion implantation.
The process employs two independent ion implantation and smart stripping processes. A high-quality intermediate substrate is prepared by high-energy ion implantation in the first stage, followed by a second ion implantation and stripping to precisely reduce the thickness of the top silicon layer. Combined with rapid thermal processing and oxide layer removal, a high-quality silicon-on-insulator substrate is formed.
An ultrathin SOI substrate with low defect density and excellent film thickness uniformity was achieved, which improved device performance and reliability, avoided defects caused by low-energy injection and etching thinning, and ensured high carrier mobility and low power consumption.
Smart Images
Figure CN122073992A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor materials technology, and in particular to silicon-on-insulator substrates and methods for their preparation. Background Technology
[0002] Silicon-on-Insulator (SOI) technology is a key platform technology in modern semiconductor manufacturing. SOI substrates with ultra-thin top single-crystal silicon are essential materials for manufacturing high-performance, low-power integrated circuits.
[0003] As semiconductor process nodes continue to evolve towards smaller dimensions, increasingly stringent requirements are being placed on the crystal quality and film thickness uniformity of ultrathin SOI substrates. However, in related technologies, how to stably and efficiently fabricate ultrathin SOI substrates that simultaneously possess high crystal quality and excellent film thickness uniformity remains a challenge. Summary of the Invention
[0004] This disclosure provides a silicon-on-insulator substrate and a method for fabricating the same. The method employs two independent ion implantation and smart lift-off processes to achieve precise reduction of the top silicon layer thickness through a two-stage lift-off thinning process, thereby enabling the fabrication of a silicon-on-insulator substrate with high crystal quality and excellent film thickness uniformity.
[0005] The technical solution disclosed herein is implemented as follows: In a first aspect, some embodiments of this disclosure provide a method for fabricating a silicon-on-insulator substrate, comprising: Perform a first ion implantation to obtain a first donor substrate with a first lift-off plane; The first donor substrate is bonded to the first support substrate to form a first bonded sheet; The first bonded sheet is separated at the first peeling plane to form an intermediate substrate including a first top silicon layer; The intermediate substrate is subjected to intermediate planarization to form a planarized intermediate substrate; A second ion implantation is performed on the planarized intermediate substrate to form a second lift-off plane inside the first top silicon layer of the planarized intermediate substrate after the second ion implantation. The planarized intermediate substrate, which has undergone a second ion implantation, is bonded to the second support substrate to form a second bonded sheet; The second bonding sheet is separated at the second peeling plane to form a first silicon-on-insulator (SII) structure including a first supporting substrate and a second SII structure including a second supporting substrate, wherein the top silicon thickness of the first SII structure is less than the top silicon thickness of the second SII structure; and The first silicon-on-insulator structure is then planarized to form the target silicon-on-insulator substrate.
[0006] In some examples, the implantation energy of the first ion implantation is greater than that of the second ion implantation.
[0007] In some examples, the implantation energies for the first and second ion implantations are greater than 10 keV.
[0008] In some examples, both the first and second ion implantations use hydrogen ions, helium ions, or a combination thereof.
[0009] In some examples, the step of bonding the planarized intermediate substrate, which has undergone a second ion implantation, to the second support substrate includes forming an oxide layer on at least one of the first top silicon layer and the second support substrate.
[0010] In some examples, the fabrication method further includes planarizing the silicon-on-a-second insulator structure.
[0011] In some examples, both intermediate planarization and final planarization involve rapid thermal processing.
[0012] In some examples, intermediate flattening also includes: Following rapid heat treatment, a sacrificial oxide layer is grown via rapid thermal oxidation; and Remove the sacrificial oxide layer.
[0013] In some examples, the step of bonding the second ion-implanted planarized intermediate substrate to the second support substrate includes plasma activation of at least one of the second ion-implanted planarized intermediate substrate and the second support substrate prior to bonding.
[0014] Secondly, some embodiments of this disclosure also provide a silicon-on-insulator substrate, which is fabricated by the method for fabricating a silicon-on-insulator substrate according to the first aspect, wherein the thickness of the single-crystal silicon layer of the silicon-on-insulator substrate is less than 100 nanometers, and the defect density of the single-crystal silicon layer is less than 1 × 10⁻⁶. 3 cm -2 .
[0015] In some examples, the standard deviation of the uniformity of the film thickness of the single-crystal silicon layer is less than 0.5 nm.
[0016] In some examples, the surface roughness of the single-crystal silicon layer is less than or equal to 0.1 nm.
[0017] This disclosure provides a silicon-on-insulator (SiIn) substrate and its fabrication method. The method employs a continuous layer-by-layer transfer strategy: First, a high-quality, highly flattened intermediate substrate is fabricated through a first layer transfer and intermediate planarization. Then, using this planarized intermediate substrate as a donor, a lift-off plane is formed within its top silicon layer, and a second layer transfer precisely divides it in two to separate an ultrathin top silicon layer, thus forming the target SiIn substrate. This fabrication method, on the one hand, physically avoids the low-energy ion implantation required in traditional processes for fabricating ultrathin layers, fundamentally solving the problem of near-surface crystal defect enrichment caused by low-energy implantation, which is difficult to repair. On the other hand, compared to top-layer thinning techniques such as sacrificial layer etching, this method can obtain ultrathin SiIn substrates with higher crystal quality and better film thickness uniformity. Attached Figure Description
[0018] Figure 1 Schematic diagram of secondary ion mass spectrometry (SIMS) analysis under different low-energy hydrogen ion implantations.
[0019] Figure 2 A schematic cross-sectional view of a silicon-on-insulator substrate provided for some embodiments of this disclosure.
[0020] Figure 3 A flowchart illustrating a method for fabricating a silicon-on-insulator substrate provided for some embodiments of this disclosure.
[0021] Figure 4 for Figure 3 The diagram shows the process flow of a method for fabricating a silicon-on-insulator substrate.
[0022] Figure 5 A schematic cross-sectional view of the fabrication process of a silicon-on-insulator substrate provided for some embodiments of this disclosure. Detailed Implementation
[0023] To make the objectives, technical solutions, and beneficial effects of this disclosure clearer and more explicit, the following detailed description of this disclosure will be provided in conjunction with the accompanying drawings.
[0024] Silicon-on-insulator (SOI) substrates can have a three-layer structure, including: a "support substrate" for mechanical support, a "buried oxide (BOX) layer" for electrical isolation, and a "top single-crystal silicon layer" for manufacturing semiconductor devices. The buried oxide layer is located between the support substrate and the top single-crystal silicon layer. The presence of the buried oxide layer ensures complete electrical isolation between transistors and other devices built on the top single-crystal silicon layer and the underlying support substrate. This significantly reduces parasitic capacitance and leakage current, thereby improving processing speed and reducing power consumption. Therefore, the thickness, thickness uniformity, and crystal quality of the top single-crystal silicon layer are crucial factors determining the final chip performance and reliability.
[0025] In the fabrication process of SOI substrates, smart cut TM This technology has already been adopted. The core principle of this technology is to first implant light ions such as hydrogen or helium into a "donor substrate," for example, into the original silicon wafer providing the top monocrystalline silicon layer. These ions form a gas-rich layer, or "release layer," at a predetermined depth within the silicon wafer. This implantation depth can be adjusted by precisely controlling the ion implantation energy. Subsequently, the implanted donor substrate can be bonded to a support substrate with an oxide layer. Finally, through heat treatment, plate-like defects within the release layer accumulate, thereby precisely "splitting" the donor substrate along the release layer, achieving the transfer of a monocrystalline silicon film of a specific thickness from the donor substrate to the support substrate, forming an SOI structure.
[0026] In their research, the inventors discovered that when using the above-mentioned intelligent lift-off technology to prepare SOI substrates, if an attempt is made to directly obtain a top single-crystal silicon layer with a thickness of less than 100 nanometers through a single lift-off, the resulting ultrathin single-crystal silicon layer is often accompanied by a high lattice defect density and poor film thickness uniformity.
[0027] The inventors conducted in-depth research and experiments to explore the root cause. Analysis revealed that the fundamental reason for this phenomenon lies in the necessity of extremely low-energy gas ion implantation to directly form an ultrathin layer through a single intelligent lift-off. Under low-energy implantation conditions, the lateral straggle and longitudinal projection range (Rp) of ions are shortened, resulting in a shallow depth of the gas-rich lift-off layer formed within the top silicon layer, with the defect layer close to the bonding interface. Furthermore, the channeling effect is more pronounced at low energy implantation, introducing more lattice distortion. The surface region, due to the large ion scattering angle, is prone to asymmetric damage distribution, exacerbating the surface defect density. This uneven defect layer, too close to the bonding interface, leads to a high defect density in the SOI layer obtained after subsequent bonding and lift-off heat treatments. In some cases, the hydrogen-implanted defect area may even overlap with the lift-off thin film layer, potentially causing incomplete lift-off. This fundamentally determines that the crystal quality and SOI layer thickness uniformity are difficult to achieve ideal levels.
[0028] Figure 1 Schematic diagram of secondary ion mass spectrometry (SIMS) analysis under different low-energy hydrogen ion implantations. It can be seen that, at the same implantation dose of 5 × 10⁻⁶, [the following parameters are observed]. 16 cm -2 Under these conditions, the lower the injection energy, such as 3keV, the shorter the longitudinal projection range Rp of the ions, the higher the peak concentration of hydrogen ions, and the narrower their distribution, resulting in the defect layer being closer to the bonding interface, i.e., the SiO2 layer. This shallow concentration leads to a significant increase in surface defect density.
[0029] Based on the understanding of the low-energy injection problem, in order to improve this phenomenon, the inventors attempted a fabrication scheme represented by EP1547143B1. In this fabrication scheme, a relatively thick and high-quality SOI substrate is first prepared through a high-energy smart lift-off process, and then the target thickness is achieved through subsequent thinning processes. For example, the thinning process may include: growing a sacrificial oxide layer on the surface of the top silicon layer by thermal oxidation, and then removing the sacrificial oxide layer by chemical etching, repeating this process until the desired thickness is achieved. However, the inventors found that although this method is feasible to a certain extent, the uniformity of the film thickness of the top silicon layer gradually deteriorates with the increase of oxidation and etching cycles.
[0030] Given that the above-mentioned thinning methods through etching or polishing each have their own inherent defects, the inventors recognize that the key to obtaining SOI substrates with excellent physical properties lies in finding a technical path that can both avoid low-energy injection problems and achieve high-precision thinning.
[0031] Based on this, the inventors, through research and experimental verification, proposed an improved SOI substrate and its preparation method. This preparation method achieves precise reduction of the top silicon thickness through two independent ion implantation and smart lift-off processes, thereby enabling the preparation of SOI substrates with high crystal quality and excellent film thickness uniformity.
[0032] The technical solutions provided by the various embodiments of this disclosure will now be described in detail. For ease of understanding, some key terms and structures involved in the solutions will be explained first.
[0033] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of a silicon-on-insulator (SOI) substrate 10 provided for some embodiments of this disclosure. The SOI substrate 10 may also be referred to hereinafter as an SOI substrate. Figure 2 As shown, the silicon-on-insulator substrate 10 may include, from bottom to top, a support substrate 12, a buried oxide layer 14 disposed on the support substrate 12, and a single crystal silicon layer 16 disposed on the buried oxide layer 14.
[0034] The main function of the support substrate 12 is to provide mechanical support for the entire silicon-on-insulator substrate 10, ensuring sufficient mechanical strength and stability during subsequent complex chip manufacturing processes. The buried oxide layer 14, often simply referred to as the BOX layer, serves as an electrical insulating layer, completely isolating the monocrystalline silicon layer 16 above it from the support substrate 12 below. The monocrystalline silicon layer 16, also known as the device layer, is the core functional layer of the silicon-on-insulator substrate 10, where all active semiconductor devices are manufactured.
[0035] In some embodiments of this disclosure, the thickness of the monocrystalline silicon layer 16 is less than 100 nanometers. SOI substrates with top silicon layers of this thickness are also referred to as ultrathin SOI substrates. For example, the thickness of the monocrystalline silicon layer 16 can be approximately 50 nanometers, or approximately 20 nanometers, or even 10 nanometers or less.
[0036] The silicon-on-insulator substrate 10 prepared in this disclosure exhibits excellent physical properties. On one hand, the defect density of the single-crystal silicon layer 16 is less than 1 × 10⁻⁶. 3 cm -2 Defect density is a key indicator of crystal quality. High defect density leads to decreased carrier mobility, thereby reducing device operating speed, and also creates leakage paths, increasing static power consumption and reducing reliability. This disclosure fundamentally reduces defect introduction by avoiding low-energy injection.
[0037] On the other hand, the standard deviation of the thickness uniformity of the single-crystal silicon layer 16 is less than 0.5 nm. Thickness uniformity is a key indicator characterizing the consistency of the thickness of the single-crystal silicon layer 16 across the entire wafer. In advanced FD-SOI processes, the threshold voltage of transistors is highly sensitive to the thickness of the top silicon layer; thickness inhomogeneity will lead to significant differences in transistor performance at different locations on the entire chip. This disclosure defines the final thickness by using the difference in ion implantation energy between two high-precision measurements, avoiding the degradation of thickness uniformity caused by etching thinning.
[0038] On another front, the surface roughness of the single-crystal silicon layer 16 is less than or equal to 0.1 nm. The root mean square value Rms of 0.1 nm represents an atomically smooth surface. A smooth surface is crucial for the subsequent growth of the thin gate oxide layer and reduces surface scattering of charge carriers within the channel, thereby ensuring high carrier mobility.
[0039] See Figure 3 The document illustrates a flowchart of a method for fabricating a silicon-on-insulator (SOI) substrate according to some embodiments of the present disclosure. This method employs a layer-by-layer stripping approach, using two layer transfer operations to achieve precise thinning of the top silicon layer, thereby avoiding low-energy injection defects and obtaining an ultrathin SOI substrate with excellent physical properties. The fabrication method includes the following steps S110 to S180: In step S110, a first ion implantation is performed to obtain a first donor substrate having a first peeling plane; In step S120, the first donor substrate is bonded to the first support substrate to form a first bonded sheet; In step S130, the first bonding sheet is separated at the first peeling plane to form an intermediate substrate including a first top silicon layer; In step S140, the intermediate substrate is subjected to intermediate planarization to form a planarized intermediate substrate; In step S150, a second ion implantation is performed on the planarized intermediate substrate to form a second peeling plane inside the first top silicon layer of the planarized intermediate substrate. In step S160, the planarized intermediate substrate that has undergone the second ion implantation is bonded to the second support substrate to form a second bonded sheet; In step S170, the second bonding sheet is separated at the second peeling plane to form a first silicon-on-insulator (SII) structure including a first supporting substrate and a second SII structure including a second supporting substrate, wherein the top silicon thickness of the first SII structure is smaller than the top silicon thickness of the second SII structure; and In step S180, the first silicon-on-insulator structure is subjected to a final planarization process to form the target silicon-on-insulator substrate.
[0040] The following will combine Figure 3 and Figure 4 The above steps will be explained in detail.
[0041] Please see Figure 4 Steps S110 to S130 constitute the first layer transfer, the purpose of which is to prepare an intermediate substrate 302 with high quality, high flatness, and a relatively thick top silicon layer. This intermediate substrate 302 will be used as the target for the subsequent second ion implantation and layer transfer operation.
[0042] In step S110, a first donor substrate 100, such as a single-crystal silicon wafer, is provided. In some embodiments, before the first ion implantation, a first oxide layer OX1 can be formed on the front side 101 of the first donor substrate 100 and / or the front side 201 of the first support substrate 200. The thickness of the first oxide layer OX1 can be in the range of 10 nanometers to 3 micrometers. For example, an oxide layer of 10 nanometers to 200 nanometers can be grown by furnace tube thermo-oxidation at 900°C to 1100°C. This first oxide layer will eventually become the buried oxide layer of the intermediate substrate 302 and also become the buried oxide layer 14 of the final target silicon-on-insulator substrate 10, see [reference]. Figure 2 .
[0043] Next, the first donor substrate 100 is subjected to a first ion implantation to form a first peeling plane 102 at a predetermined depth inside the first donor substrate 100.
[0044] In some embodiments, both the first and second ion implantations employ hydrogen ions, helium ions, or a combination thereof. Co-implantation with hydrogen and helium ions can achieve more effective blistering and stripping at a lower total dose.
[0045] In some embodiments, the implantation energies for the first and second ion implantations are both greater than 10 keV. The purpose of this step is to fabricate a thicker intermediate substrate 302 with a top silicon layer. By employing conventional energy implantation greater than 10 keV, for example, in the range of 10 keV to 200 keV, the implanted ion and defect peaks are controlled deep away from the surface, thereby ensuring that the subsequently transferred top silicon layer has a high-quality crystal structure and avoiding low-energy implantation defect problems from the outset. The implantation dose can be 2 × 10⁻⁶. 16 atoms / cm 2 Up to 1×10 17 atoms / cm 2 Within the range.
[0046] In step S110, a first support substrate 200 is also provided.
[0047] In step S120, the first donor substrate 100, after the first ion implantation, is bonded to the first support substrate 200 to form a first bonded sheet 300. Prior to bonding, the front surface 101 of the first donor substrate 100 and / or the front surface 201 of the first support substrate 200 may be surface-treated to enhance bonding strength. For example, a hydrophilic treatment may be performed, such as cleaning with SC-1 (ammonia-hydrogen peroxide-water mixture), to coat the surface with a high density of hydroxyl groups.
[0048] In some cases, the bonding step may include plasma activation of at least one of the first donor substrate 100 and the first support substrate 200 prior to bonding. For example, any of argon (Ar), nitrogen (N2), oxygen (O2), and mixtures thereof can be used as plasmas to bombard the surface to activate it, thereby achieving a strong room-temperature bond without the need for high-temperature annealing. Bonding can be performed in a vacuum bonding chamber; for example, a vacuum environment of 0.001 mbar to 1000 mbar can prevent air molecules from being trapped at the bonding interface, thus avoiding the formation of voids.
[0049] In step S130, the first bonded sheet 300 is separated at the first peeling plane 102 to form the intermediate substrate 302. This separation can be achieved by performing a first peeling heat treatment on the first bonded sheet 300. The temperature of this peeling heat treatment is typically between 400°C and 600°C, for example, 500°C. This heat treatment can be performed for 1 to 3 hours at normal pressure in an inert gas atmosphere such as argon (Ar) or nitrogen (N2). The heat energy causes the gas at the first peeling plane 102 to accumulate, bubble, and expand, generating internal stress, which causes the first bonded sheet 300 to be precisely cleaved along the plane, forming the intermediate substrate 302 and the first peeling substrate 301.
[0050] The intermediate substrate 302 may include: a first support substrate 200, a first oxide layer OX1 disposed thereon, and a first top silicon layer 200A transferred from the first donor substrate 100. The thickness of this first top silicon layer is determined by the first implantation energy E1. It is understood that the substrate 301 can be subjected to chemical mechanical polishing (CMP) to restore its surface to a smooth state, allowing for recycling.
[0051] In step S140, intermediate substrate 302 undergoes intermediate planarization to form planarized intermediate substrate 304. This step is crucial because the peeling in step S130 is a mechanical splitting process, which introduces a certain degree of lattice damage and high surface roughness on the newly formed surface of intermediate substrate 302. If this planarization step is not performed, the depth and dose of the subsequent second ion implantation in step S150 will become extremely uneven due to the surface unevenness, which will directly compromise the film thickness uniformity.
[0052] In some embodiments, both the intermediate planarization process and the final planarization process include Rapid Thermal Processing (RTP). This RTP process can be performed at high temperatures, such as 1100°C to 1300°C. The RTP process can be performed in a reducing or inert atmosphere, such as a hydrogen / argon mixture (H2 / Ar) at a ratio of 1:20 to 1:2, at ambient pressure, for 10 to 60 seconds. The presence of hydrogen helps promote surface migration of silicon atoms at high temperatures, thereby achieving more efficient surface planarization and simultaneously effectively repairing lattice damage remaining from the stripping in step S130.
[0053] In some embodiments, the intermediate planarization process further includes: growing a sacrificial oxide layer by rapid thermal oxidation (RTO) after rapid thermal processing; and removing the sacrificial oxide layer. The purpose of this RTO step is to sacrifice the outermost silicon layer of the intermediate substrate 302, which contains lift-off damage, by oxidation. The thickness of this sacrificial oxide layer is, for example, less than 100 nanometers. Subsequently, a step of removing the sacrificial oxide layer is performed, for example, by wet etching using a hydrofluoric acid HF solution, to completely remove the sacrificial oxide layer. Through the combination of RTP and RTO, the damaged layer introduced in step S130 is completely removed, thereby obtaining a high-quality, atomically smooth planarized intermediate substrate 304.
[0054] In step S150, a second ion implantation is performed on the planarized intermediate substrate 304 to form a second peeling plane 306 inside the first top silicon layer of the planarized intermediate substrate 304.
[0055] In some embodiments, the implantation energy of the first ion implantation is greater than that of the second ion implantation. This energy relationship is a prerequisite for achieving layer-by-layer thinning. See also Figure 5 For example, the implantation energy E1 for the first ion implantation can be 60 keV, which defines the total thickness T of the first top silicon layer on the planarized intermediate substrate 304. E1 The implantation energy E2 of the second ion implantation can be 48 keV, which defines a relatively shallow second lift-off plane 306 inside the first top silicon layer, the depth of which corresponds to the thickness T. E2 The final target layer thickness is determined by the thickness difference T between the two injections. E1 -T E2 Decide.
[0056] As mentioned earlier, the energies of both injections were greater than 10 keV. This successfully utilized the difference between the two conventional energy injections to achieve equivalent ultrathin layer results, while completely avoiding the high defect density problem inherent in low-energy injection.
[0057] In step S160, a second support substrate 400 is provided. A planarized intermediate substrate 304 is bonded to the second support substrate 400 to form a second bonded sheet 500. The second support substrate 400 serves as a gripping tool for transferring away the thicker portion of the first top silicon layer in a subsequent step S170.
[0058] In some embodiments, the step of bonding the planarized intermediate substrate 304 to the second support substrate 400 includes forming a second oxide layer OX2 on at least one of the first top silicon layer of the planarized intermediate substrate 304 and the second support substrate 400. The second oxide layer OX2 can be grown by means of furnace tube thermal oxidation, chemical vapor deposition (CVD), or RTP, and its thickness can be less than 200 nanometers, for example, in the range of 1 nanometer to 100 nanometers.
[0059] In some embodiments, the step of bonding the planarized intermediate substrate 304 to the second support substrate 400 includes plasma activation of at least one of the planarized intermediate substrate 304 and the second support substrate 400 prior to bonding. The process parameters may be similar to those for the first bonding, for example, using argon, nitrogen, or oxygen plasma.
[0060] In step S170, the second bonded sheet 500 is separated at the second peeling plane 306. This step is achieved by performing a second peeling heat treatment on the second bonded sheet 500. The process parameters of this heat treatment can be similar to those of step S130, for example, at a temperature of 400°C to 600°C, such as 500°C, in an inert atmosphere such as argon or nitrogen, for 1 to 3 hours. This heat treatment causes the second bonded sheet 500 to separate along the second peeling plane 306 formed in step S150.
[0061] This separation resulted in two different structures: a first silicon-on-insulator structure 501 and a second silicon-on-insulator structure 502.
[0062] The first silicon-on-insulator structure 501 includes a first support substrate 200 and a portion retained on the first support substrate 200. The top silicon thickness of the first silicon-on-insulator structure 501, i.e., the first top silicon thickness, is equal to the total top silicon thickness T of the planarized intermediate substrate 304. E1 Subtract the second peeling plane depth T of 306 E2 The remaining difference T E1 -T E2 It was decided.
[0063] The second silicon-on-insulator structure 502 includes a second support substrate 400 and portions transferred from the first support substrate 200 to the second support substrate 400. The top silicon thickness of the second silicon-on-insulator structure 502, i.e., the second top silicon thickness, is determined by the depth T of the second ion implantation step S150. E2 It was decided.
[0064] Based on the energy relationship that the injection energy E1 is greater than the injection energy E2, the thickness T of the first top silicon layer can be determined. E1 -T E2 Less than the thickness T of the second top silicon layer E2 .
[0065] By using this layer-by-layer method, this disclosure successfully fabricates an ultrathin SOI structure, for example, less than 100 nanometers, of the first silicon-on-insulator structure 501 by utilizing the difference between two conventional energy injections, both of which are greater than 10 keV, and the ultrathin top silicon layer is retained on the original first support substrate 200.
[0066] In step S180, the first silicon-on-insulator structure 501 is subjected to a final planarization process to form the target silicon-on-insulator substrate 504. This is because the peeling surface in step S170 also has lattice damage and surface roughness introduced by splitting.
[0067] In some embodiments, the final planarization process also includes rapid thermal annealing (RTP). This RTP process can be performed at high temperatures, such as between 1100°C and 1300°C, for example, at 1200°C. The RTP process can be performed in a reducing atmosphere, such as a hydrogen / argon mixture with a volume ratio of, for example, 1:20 to 1:2, at atmospheric pressure, for 10 to 60 seconds. In some exemplary cases, step S180 may also include RTO growth, for example, of a sacrificial oxide layer with a thickness of less than 100 nanometers, following the RTP, and a subsequent removal step.
[0068] Since step S150 of this disclosure, the second implantation step, is performed on the already stripped SOI surface, the damaged layer left after stripping in step S170 is thinner and has a lower hydrogen concentration distribution. This means that less RTO needs to be removed in step S180. Since a greater amount of RTO removal results in a worse TTV, the smaller amount of removal in step S180 of this disclosure further ensures that the target silicon-on-insulator substrate 504 maintains excellent film thickness uniformity as defined by the ion implantation difference.
[0069] In some embodiments, the fabrication method may further include: planarizing the second silicon-on-insulator (SOI) structure 502. This planarization step, such as RTP, may also be applied simultaneously to the second SOI structure 502 to repair its peeled surface, forming a planarized second SOI substrate 503. This allows the second SOI structure 502 to be recycled or used as a conventional thickness SOI substrate product, improving the economics of the process.
[0070] Examples and Comparative Examples To further illustrate the technical effects of this disclosure, specific embodiments and comparative examples are provided below.
[0071] Example 1: This example aims to fabricate an ultrathin SOI substrate with a top single-crystal silicon layer thickness of approximately 50 nm. This example includes the following steps performed sequentially.
[0072] A silicon wafer with a diameter of 300 mm is provided as a first donor substrate 100, and a first support substrate with a diameter of 300 mm is provided as a first support substrate 200. A 50 nm oxide layer is grown on the surface of the first donor substrate and the first support substrate using a furnace tube thermal oxidation process.
[0073] The first hydrogen ion implantation was performed on the first donor substrate at an implantation energy E1 of 52 keV. The implantation dose was 5 × 10⁻⁶. 16 atom / cm 2 .
[0074] Two substrates were hydrophilically bonded at room temperature, followed by a first exfoliation heat treatment at 500°C in a nitrogen atmosphere for 1 hour, forming the intermediate substrate 302. The thickness of its first top silicon layer was measured to be approximately 400 nm at this point.
[0075] The intermediate substrate 302 is subjected to intermediate planarization, for example, by rapid thermal annealing at 1100°C to 1300°C in a mixed atmosphere of H2 / Ar, at atmospheric pressure for 30 seconds, and the 20nm thick damage layer is removed by sacrificial oxidation.
[0076] A second hydrogen ion implantation was performed on the single-crystal silicon layer of the planarized intermediate substrate 304, with an implantation energy E2 of 34 keV. The implantation dose was 5 × 10⁻⁶. 16 atom / cm 2 .
[0077] The planarized intermediate substrate 304, which has undergone a second gas ion implantation, is bonded to a new second support substrate 400 with a 100 nm oxide layer.
[0078] A second stripping heat treatment is performed for 1 hour in a nitrogen atmosphere at 500°C to form a first silicon-on-insulator structure 501 retained on the first support substrate 200 and a second silicon-on-insulator structure 502 transferred to the second support substrate 400.
[0079] The first silicon-on-insulator structure 501 is subjected to final planarization to form the target silicon-on-insulator substrate 504.
[0080] Results Measurement: Using transmission electron microscopy (TEM) and defect etching, the final target silicon-on-insulator substrate 504 was found to have a top single-crystal silicon layer thickness of 52 nm and a defect density of 5 × 10⁻⁶. 2 cm -2 The standard deviation of film thickness uniformity was 0.45 nm, as measured by an ellipsometer.
[0081] Comparative Example 1: Using low-energy injection techniques.
[0082] The comparison includes the following steps performed sequentially.
[0083] A donor substrate and a support substrate are provided, and a 50 nm oxide layer is grown on the surfaces of the donor substrate and the first support substrate by a furnace tube thermo-oxidation process.
[0084] To directly obtain a thin layer of approximately 50 nm, a one-time low-energy hydrogen ion implantation with an energy of 6 keV (less than 10 keV) was performed on the donor substrate.
[0085] After room temperature hydrophilic bonding of the two substrates, a peeling heat treatment and planarization treatment are performed to obtain the SOI substrate.
[0086] Results Measurement: The final SOI substrate had a top single-crystal silicon layer thickness of 55 nm and a film thickness uniformity standard deviation of 0.5 nm, but the defect density was as high as 8 × 10⁻⁶. 4 cm -2 .
[0087] Comparative Example 2: Using corrosion thinning techniques.
[0088] The comparison includes the following steps performed sequentially.
[0089] A donor substrate and a support substrate are provided, and a 50 nm oxide layer is grown on the surfaces of the donor substrate and the support substrate by a furnace tube thermo-oxidation process.
[0090] An SOI substrate with a top single-crystal silicon layer thickness of approximately 400 nm was fabricated through a single ion implantation and peeling process at an energy of 52 keV. This substrate exhibited a low defect density of approximately 6 × 10⁻⁶. 2 cm -2 .
[0091] The 400 nm single-crystal silicon layer was thinned to a target thickness of approximately 50 nm by repeatedly growing a sacrificial oxide layer and removing it by etching with hydrofluoric acid (HF).
[0092] Results Measurement: The defect density of the final SOI substrate is close to that of the initial thick SOI substrate, approximately 6 × 10⁻⁶. 2 cm -2 However, due to the non-uniformity of the corrosion process, the standard deviation of its film thickness uniformity deteriorated to 2.1 nm.
[0093] Performance Comparison Summary To make a more intuitive comparison, the key performance indicators of the above embodiments and comparative examples are summarized in Table 1 below: Table 1 Performance Comparison of Embodiments and Comparative Examples To make a more intuitive comparison, the key performance indicators of the above embodiments and comparative examples are summarized in Table 1 below: Table 1
[0094] As can be seen from the comparison in the table above, the technical solution provided in this disclosure can avoid the high defect density problem caused by low energy injection (as shown in Comparative Example 1) and overcome the defect of poor film thickness uniformity caused by etching thinning method (as shown in Comparative Example 2), thus successfully preparing a high-quality ultrathin SOI substrate with both extremely low defect density and excellent film thickness uniformity.
[0095] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.
[0096] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A method for preparing a silicon-on-insulator substrate, characterized in that, include: Perform a first ion implantation to obtain a first donor substrate with a first lift-off plane; The first donor substrate is bonded to the first support substrate to form a first bonded sheet; The first bonding sheet is separated at the first peeling plane to form an intermediate substrate including a first top silicon layer; The intermediate substrate is subjected to intermediate planarization to form a planarized intermediate substrate; A second ion implantation is performed on the planarized intermediate substrate to form a second lift-off plane inside the first top silicon layer of the planarized intermediate substrate after the second ion implantation. The planarized intermediate substrate, which has undergone the second ion implantation, is bonded to the second support substrate to form a second bonded sheet; The second bonding sheet is separated at the second peeling plane to form a first silicon-on-insulator structure including the first supporting substrate and a second silicon-on-insulator structure including the second supporting substrate, wherein the top silicon thickness of the first silicon-on-insulator structure is smaller than the top silicon thickness of the second silicon-on-insulator structure. as well as The first silicon-on-insulator structure is then planarized to form the target silicon-on-insulator substrate.
2. The method for preparing a silicon-on-insulator substrate according to claim 1, characterized in that, The implantation energy of the first ion implantation is greater than the implantation energy of the second ion implantation.
3. The method for preparing a silicon-on-insulator substrate according to claim 2, characterized in that, The implantation energies of the first ion implantation and the second ion implantation are both greater than 10 keV.
4. The method for preparing a silicon-on-insulator substrate according to claim 2, characterized in that, Both the first and second ion implantations use hydrogen ions, helium ions, or a combination thereof.
5. The method for preparing a silicon-on-insulator substrate according to claim 1, characterized in that, The step of bonding the planarized intermediate substrate, which has undergone the second ion implantation, to the second support substrate includes forming an oxide layer on at least one of the first top silicon layer and the second support substrate.
6. The method for preparing a silicon-on-insulator substrate according to claim 1, characterized in that, The preparation method further includes: planarizing the silicon-on-insulator structure of the second insulator.
7. The method for preparing a silicon-on-insulator substrate according to claim 1, characterized in that, Both the intermediate planarization process and the final planarization process include rapid thermal processing.
8. The method for preparing a silicon-on-insulator substrate according to claim 7, characterized in that, The intermediate flattening process also includes: Following the rapid heat treatment, a sacrificial oxide layer is grown by rapid thermal oxidation; and Remove the sacrificial oxide layer.
9. The method for preparing a silicon-on-insulator substrate according to claim 1, characterized in that, The step of bonding the planarized intermediate substrate, which has undergone the second ion implantation, to the second support substrate includes plasma activation of at least one of the planarized intermediate substrate and the second support substrate before bonding.
10. A silicon-on-insulator substrate, characterized in that, The silicon-on-insulator substrate is prepared by the method for preparing a silicon-on-insulator substrate according to any one of claims 1 to 9, wherein the thickness of the single-crystal silicon layer of the silicon-on-insulator substrate is less than 100 nanometers, and the defect density of the single-crystal silicon layer is less than 1 × 10⁻⁶. 3 cm -2 .
11. The silicon-on-insulator substrate according to claim 10, characterized in that, The standard deviation of the uniformity of the film thickness of the single-crystal silicon layer is less than 0.5 nm.
12. The silicon-on-insulator substrate according to claim 11, characterized in that, The surface roughness of the single-crystal silicon layer is less than or equal to 0.1 nm.