Rectangular coordinate to polar coordinate conversion method and device based on LUT and CORDIC hybrid architecture

Abstract

The invention relates to a rectangular coordinate-to-polar coordinate conversion method and device based on an LUT and CORDIC hybrid architecture. The method comprises the following steps: S1, sector folding preprocessing; s2, performing coarse rotation iteration; s3, generating a dynamic address; s4, a compression lookup table is queried; and S5, data compensation and reconstruction. According to the method, a small amount of CORDIC iteration is introduced to rotate the input vector to a very small angle range, so that the input space required to be covered by a subsequent lookup table is greatly compressed; meanwhile, the bit width and the address depth of a storage value in the LUT are remarkably reduced by combining module value residual storage and a dynamic truncation technology, so that the storage resources of the LUT are greatly reduced on the premise of ensuring the precision, and the hardware implementation cost is lower.

Description

Technical Field

[0001] This invention relates to the technical fields of digital signal processing and dedicated hardware circuit design, and in particular to a method and apparatus for converting Cartesian coordinates to polar coordinates based on a hybrid architecture of LUT and CORDIC. Background Technology

[0002] In applications such as wireless communication transmitters, radar signal processing, and speech signal analysis, obtaining the magnitude and phase information of complex signals is typically required to achieve key processing steps such as signal modulation, beamforming, and spectrum analysis. The transformation from rectangular to polar coordinates is the core operation for achieving this goal. It maps complex signals from a rectangular coordinate system to a polar coordinate system, thus intuitively representing the energy distribution and phase characteristics of the signal. Therefore, this operation has become an indispensable and widely used fundamental operation in the field of digital signal processing.

[0003] In the hardware implementation of Cartesian to polar coordinate conversion, the CORDIC (Coordinate Rotation Numerical Computation Method) algorithm has become a widely adopted technique because it only requires binary shift and addition operations to complete vector rotation and angle calculation, eliminating the need for hardware multipliers. However, the traditional CORDIC algorithm requires multiple iterations to achieve high-precision output, resulting in slow linear convergence, which directly leads to long conversion delays and complex control logic. On the other hand, the LUT (Look-Up Table) based method achieves extremely low computational latency by pre-stored data, effectively compensating for the shortcomings of the CORDIC algorithm. However, this method is limited by the fact that the size of its look-up table grows exponentially with the input data bit width, requiring a large amount of memory resources.

[0004] To reduce the size of lookup tables, existing technologies have proposed schemes such as binary search, multi-segmentation, and non-uniform segmentation. However, these schemes often focus on a single variable, such as independent optimization of phase. In scenarios requiring simultaneous output of high-precision magnitude and phase, they often struggle to achieve efficient resource coordination. Furthermore, existing schemes often fail to fully utilize the inherent mathematical redundancy of the data for bit-width reduction, resulting in low storage resource utilization and making it difficult to balance the requirements of high precision and low resource consumption over a wide dynamic range. Summary of the Invention

[0005] To address the technical problems existing in the prior art, this invention provides a method and apparatus for converting Cartesian coordinates to polar coordinates based on a hybrid architecture of LUT and CORDIC. By introducing a small number of CORDIC iterations to rotate the input vector to a very small angular range, the input space required to be covered by the subsequent lookup table is greatly compressed. At the same time, by combining modulo residual storage and dynamic truncation technology, the bit width and address depth of the stored values ​​in the LUT are significantly reduced, thereby achieving a significant reduction in LUT storage resources while ensuring accuracy, and lowering the hardware implementation cost.

[0006] The method of this invention is implemented using the following technical solution: a method for converting Cartesian coordinates to polar coordinates based on a hybrid architecture of LUT and CORDIC, comprising the following steps:

[0007] S1. Sector folding preprocessing: Determine the input rectangular coordinate vector. The sector to which the rectangular coordinate vector belongs is determined, and the corresponding absolute value and coordinate exchange operations are performed on the rectangular coordinate vector, thereby mapping the rectangular coordinate vector to... Within the sector range, obtain the preprocessed coordinate vector. ;

[0008] S2. Coarse rotation iteration, applying the coordinate vector obtained in step S1... x-coordinate and the vertical axis Simultaneously, a left shift operation of L bits is performed, followed by N CORDIC rotation iterations on the shifted coordinate vector, where N is a positive integer; after the iterations are completed, the cumulative rotation angle is output. The iteratively obtained x-coordinates direct as and the ordinate Take the absolute value as Thus, coordinate vectors are constructed. ;

[0009] S3. Dynamic address generation, detecting the x-coordinate obtained in step S2. The position of the highest non-zero bit, and accordingly adaptively adjust the horizontal coordinate. and ordinate Perform bit sequence truncation or bit sequence truncation and bit-inversion operations, concatenate the processed coordinate components, and finally generate the lookup table index address; where the truncation operation extracts the x-coordinate. The bit sequence is of length M-1, and the truncated ordinate is... The length of the bit sequence is MN;

[0010] S4. Compressed lookup table query: Based on the lookup table index address obtained in step S3, the preset compressed lookup table is read and the corresponding modulus residual and phase are output.

[0011] S5. Data Compensation and Reconstruction: The modulus residuals and phase obtained in step S4 are compensated and reconstructed to generate the target polar coordinate data. ;

[0012] All input, output, and intermediate node data in the processing steps are in binary format.

[0013] The device of this invention is implemented using the following technical solution: a Cartesian to polar coordinate conversion device based on a hybrid architecture of LUT and CORDIC, comprising:

[0014] The sector folding preprocessing unit is configured to receive input Cartesian coordinate vectors. Determine the sector to which the rectangular coordinate vector belongs and output the sector identifier s; perform the corresponding absolute value and coordinate exchange operations on the rectangular coordinate vector, and then map the rectangular coordinate vector to... Within the sector range, obtain the preprocessed coordinate vector. ;

[0015] The coarse rotation iteration unit is configured to receive the preprocessed Cartesian coordinate vector. its x-coordinate and the vertical axis Simultaneously, a left shift operation of L bits is performed, followed by N iterations of CORDIC rotation on the shifted coordinate vector, where N is a positive integer; after the iteration is complete, the ordinate obtained from the iteration is output. With cumulative rotation angle The iteratively obtained x-coordinates direct as and the ordinate Take the absolute value as Thus, coordinate vectors are constructed. ;

[0016] The dynamic address generation unit is configured to detect the x-coordinate of the output of the coarse rotation iteration unit. The position of the highest non-zero bit, and accordingly adaptively adjust the horizontal coordinate. and ordinate Perform bit sequence truncation or bit sequence truncation and bit-inversion operations, concatenate the processed coordinate components, and finally generate the lookup table index address; where the truncation operation extracts the x-coordinate. The bit sequence is of length M-1, and the truncated ordinate is... The length of the bit sequence is MN;

[0017] The compressed lookup table storage unit is configured to store the compressed lookup table and read the lookup table based on the index address generated by the dynamic address generation unit, and output the corresponding modulus residual and phase.

[0018] The data compensation and reconstruction unit is configured to compensate and reconstruct the modulus residuals and phases output by the compressed lookup table storage unit, thereby generating the target polar coordinate data. .

[0019] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0020] 1. This invention introduces a small number of CORDIC iterations to rotate the input vector to a very small angular range, which greatly compresses the input space that the subsequent lookup table needs to cover. At the same time, by combining modulo residual storage and dynamic truncation technology, the bit width and address depth of the stored values ​​in the LUT are significantly reduced, thereby achieving a significant reduction in LUT storage resources while ensuring accuracy, and lowering the hardware implementation cost.

[0021] 2. This invention performs only a few CORDIC iterations, and subsequent calculations directly obtain key reference values ​​through lookup tables, which greatly shortens the critical path delay of the data path, thereby significantly improving the system's computing speed and data throughput.

[0022] 3. In this invention, sector folding and CORDIC rotation are coordinate transformations based on mathematical symmetry and deterministic algorithms, which theoretically do not introduce any approximation errors. The calculation results pre-stored in the lookup table have numerical accuracy that is pre-designed and guaranteed. At the same time, this invention avoids the problem of severe loss of phase information under specific conditions caused by simple truncation through a dynamic truncation strategy, thus ensuring the accuracy benchmark of the entire system.

[0023] 4. This invention replaces some of the high-power iterative operations with lookup table access, which has a higher energy efficiency ratio, so that the system can achieve lower overall dynamic power consumption while maintaining high performance output. Attached Figure Description

[0024] Figure 1 This is a flowchart of the method of the present invention;

[0025] Figure 2 This is a schematic diagram of the phase range compression resulting from sector folding and coarse rotation iteration in this invention;

[0026] Figure 3 (a) is a distribution diagram of the effective coordinate region after the coarse rotation iteration of the present invention;

[0027] Figure 3 (b) is a schematic diagram of region mapping in the generation of the lookup table index address in this invention;

[0028] Figure 4 This is a schematic diagram of the device structure of the present invention. Detailed Implementation

[0029] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings, but the embodiments of the present invention are not limited thereto.

[0030] Example 1

[0031] like Figure 1 As shown in the figure, this embodiment presents a method for converting Cartesian coordinates to polar coordinates based on a hybrid architecture of LUT and CORDIC, which includes the following steps:

[0032] S1. Sector folding preprocessing: Determine the input rectangular coordinate vector. The sector to which the rectangular coordinate vector belongs is determined, and the corresponding absolute value and coordinate exchange operations are performed on the rectangular coordinate vector, thereby mapping the rectangular coordinate vector to... Within the sector range, obtain the preprocessed coordinate vector. ;

[0033] S2. Coarse rotation iteration, applying the coordinate vector obtained in step S1... x-coordinate and the vertical axis Simultaneously, a left shift operation of L bits is performed, followed by N CORDIC rotation iterations on the shifted coordinate vector, where N is a positive integer; after the iterations are completed, the cumulative rotation angle is output. The iteratively obtained x-coordinates direct as and the ordinate Take the absolute value as Thus, coordinate vectors are constructed. ;

[0034] S3. Dynamic address generation, detecting the x-coordinate obtained in step S2. The position of the highest non-zero bit, and accordingly adaptively adjust the horizontal coordinate. and ordinate Perform bit sequence truncation or bit sequence truncation and bit-inversion operations, concatenate the processed coordinate components, and finally generate the lookup table index address; where the truncation operation extracts the x-coordinate. The bit sequence is of length M-1, and the truncated ordinate is... The length of the bit sequence is MN;

[0035] S4. Compressed lookup table query: Based on the lookup table index address obtained in step S3, the preset compressed lookup table is read and the corresponding modulus residual and phase are output.

[0036] S5. Data Compensation and Reconstruction: The modulus residuals and phase obtained in step S4 are compensated and reconstructed to generate the target polar coordinate data. ;

[0037] All input, output, and intermediate node data in the processing steps are in binary format.

[0038] Specifically, in this embodiment, the rectangular coordinate vector input in step S1 It is binary data with a bit width of W0, where W0 is a positive integer.

[0039] Specifically, in this embodiment, in step S1, the "sector" refers to several regions divided into Cartesian coordinate planes based on phase range. More specifically, this embodiment divides the entire coordinate plane into... The phase interval is evenly divided into eight sectors, such as Figure 2 As shown, the phase interval corresponding to each sector is ,in Each sector corresponds to a unique sector identifier s, the value of which is equal to k; the sector identifier s will be passed to the subsequent step S5 for phase correction; the sector determination is based on the input rectangular coordinate vector. middle and The sign bit and absolute value of the vector are related. The rules for determining the sector to which the vector belongs and the corresponding mapping rules are shown in Table 1. In particular, for the special case where the input coordinates are the origin (0,0), this embodiment classifies it into sector 0 by default, that is, let s=0.

[0040] Table 1. Sector Determination and Coordinate Mapping Rules

[0041]

[0042] Specifically, in this embodiment, in step S1, the corresponding absolute value and coordinate exchange operation is performed on the rectangular coordinate vector, specifically: the x-coordinate is changed... and the vertical axis Take the absolute value; if the ordinate at this time The absolute value is greater than the x-axis. When calculating the absolute value, swap the x and y coordinates after taking the absolute value, and map the input vector to... Within the sector range.

[0043] Specifically, in this embodiment, the iterative process in step S2 includes: in each iteration, controlling the rotation direction according to the sign of the ordinate of the current coordinate vector, driving the coordinate vector to approach the horizontal axis, and accumulating the rotation angle generated in each iteration; after N iterations, the coordinate vector is obtained. With cumulative rotation angle The iteratively obtained x-coordinates direct as and the ordinate Take the absolute value as Construct coordinate vectors It should be noted that, due to the characteristics of the CORDIC algorithm, the output coordinate vector at this time... A fixed modulus gain is introduced, which will be compensated in the subsequent step S5.

[0044] Specifically, in this embodiment, when N is large, the remaining angle is small, which can reduce the size of the subsequent lookup table; when N is small, the iteration delay can be reduced.

[0045] Specifically, the CORDIC rotation iteration process follows the following mathematical model:

[0046] To reduce accuracy loss during the iteration process, the coordinates output by S1 are first... Perform an L-bit left shift and expansion process to obtain the initial iteration state. ,in, , ;

[0047] Then, the initial iteration state Use this as the starting coordinate, and accumulate the angle value. Initialize to 0, perform N iterations, with iteration index i ranging from 0 to N-1. In the i-th iteration, the state update formula is as follows:

[0048]

[0049] in, This is the rotation direction factor, whose value is determined by the current ordinate. The sign determines:

[0050]

[0051] After N iterations, the final coordinates are obtained. Middle ordinate Take the absolute value to obtain the output coordinates. ,Right now

[0052]

[0053] At the same time, output the final accumulated angle. Used for phase correction in subsequent step S5.

[0054] Specifically, in step S3, the dynamic address generation adopts an adaptive truncation strategy based on the position of the highest non-zero bit, which specifically includes: detecting the horizontal coordinate. In binary representation, when the position of the most non-zero bit is in the high-order interval (i.e., the position is the Mth bit or higher from the least significant bit), a floating truncation is performed, using this most non-zero bit as the truncation reference bit for the horizontal axis. Extract the M-1 bit sequence immediately below the reference bit, i.e., the extracted sequence does not include the reference bit. For the vertical axis... Starting from the position N bits below the truncation reference bit, a bit sequence of length MN is truncated in the direction of lower bits. When the position of the highest non-zero bit is in the lower bit interval, that is, within the Mth bit from the least significant bit to the most significant bit, the Mth bit from the least significant bit to the most significant bit is used as the truncation reference bit, and fixed truncation and reversal are performed, that is, the horizontal coordinate is directly truncated. The lowest M-1 bit sequence, and the ordinate The lowest MN bit sequence is obtained, and the bitwise inversion operation is performed on each bit sequence obtained.

[0055] Specifically, when the coarse rotation iteration outputs coordinates When the data bit width is W1, and The binary representations are as follows:

[0056]

[0057] The formula for calculating the lookup table index address is as follows:

[0058]

[0059] in, This represents a binary sequence of all "1"s of length M-1. Represents a binary sequence of length MN consisting entirely of "1"s, where i represents the position of the binary number of MN. The highest non-zero bit is the ordinal number of the binary sequence from the highest bit to the lowest bit (starting ordinal number is 1). The situation corresponds to Figure 3 In region B shown in (b), the lookup table index address needs to be generated by bitwise inversion of the bit sequence of the coordinate components.

[0060] The different truncation lengths of the coordinate components are to match the numerical characteristics after coarse rotation; after N CORDIC iterations and absolute value processing, the ordinate... The numerical range has been narrowed down to the horizontal axis. 2-N times (i.e.) This means the ordinate The high N bits are all zero, so they can be discarded.

[0061] against In this case, bitwise inversion of the bit sequence of coordinate components is performed to address the problems of low storage space utilization and discontinuous lookup table indexes. Since the effective coordinates after coarse rotation are distributed in... Within the triangular region, directly concatenating the horizontal and vertical bit sequences would result in approximately half of the original rectangular address space defined by the bit width being unused. Figure 3 As shown in (a), only region A is utilized. This embodiment uses a bitwise inversion operation to transform the original distribution... Figure 3 (b) The coordinate data within region B shown is mapped to Figure 3 (b) shows region C, thereby compressing the storage capacity required for the lookup table to half the size of the original rectangular address space, forming a compact and continuous address distribution space.

[0062] Specifically, in this embodiment, in step S4, the compressed lookup table pre-stores the modulus residual and phase data under the effective bit width determined based on the dynamic truncation strategy; wherein, the effective bit width refers to the horizontal coordinate. The M-bit (composed of the truncated reference bit and the truncated M-1 bit sequence) and the ordinate The MN bits are truncated; the modulus residual and phase data are obtained by traversing all combinations of values ​​of the horizontal and vertical coordinates within the effective bit width, calculating the corresponding modulus residual and phase offline, and then converting them to fixed points; the modulus residual refers to the difference between the vector modulus formed by the horizontal and vertical coordinate values ​​corresponding to the effective bit width and the horizontal coordinate value during the traversal process.

[0063] Specifically, the modulus residuals stored in the compressed lookup table are compressed. and phase The calculation formula is as follows:

[0064]

[0065] in, and Representing the x-coordinates and the vertical axis The fixed-point value corresponding to the bit sequence with effective bit width; specifically, if , Corresponding bit sequence The value, Corresponding bit sequence The value, if ,but Corresponding bit sequence The value, Corresponding bit sequence The numerical value is used to calculate the lookup table by substituting this value into the formula.

[0066] Because the residual value is smaller than the complete modulus, storing this value can significantly reduce the data storage bandwidth. The reason why the residual value is much smaller than the complete modulus is that after N CORDIC rotation iterations, the x-axis... and the vertical axis satisfy condition It can be seen that the order of magnitude of the complete modulus is mainly determined by the horizontal axis. The decision is made by applying a Taylor series expansion to the modulus residual, which yields:

[0067]

[0068]

[0069] Therefore, the upper limit of the magnitude residual is only the value of the complete magnitude. times.

[0070] Specifically, in this embodiment, step S5 includes shifting and restoring the received modulus residual according to a dynamic truncation rule, and comparing it with the abscissa obtained after iteration in step S2. The process involves numerical reconstruction through addition, compensation for the magnitude gain caused by the CORDIC rotation iterations, and right-shift recovery based on the number of left shifts during the coarse rotation phase. Phase operations include using the ordinate at the end of the CORDIC rotation. The sign of the received phase is compared with the cumulative rotation angle generated during the coarse rotation stage. Perform sum or absolute difference operations, and perform inverse transformations to correct phase shifts caused by sector folding.

[0071] The specific process is as follows:

[0072] Regarding the modulus:

[0073] First, according to the dynamic truncation rule, the modulus residual output by the lookup table is shifted to the left to correct the deviation introduced by the dynamic truncation:

[0074]

[0075] Next, by comparing the x-coordinates obtained after iteration in step S2... By adding the values ​​together and reconstructing the numerical values, we obtain... , Corresponding modulus:

[0076]

[0077] Subsequently, the modulus gain introduced during the CORDIC rotation iteration in step S2 is compensated by multiplying it by the rotation factor K, thereby obtaining the compensated modulus output:

[0078]

[0079] The rotation factor K is defined as follows:

[0080]

[0081] Finally, for the left shift and expansion process performed in S2, the compensated modulus value of the output is then right-shifted to restore it, thus obtaining the final true modulus value output:

[0082]

[0083] Regarding phase:

[0084] First, based on the ordinate at the end of N CORDIC rotation iterations... Polarity is determined by performing a sum or absolute difference operation on the rotation angle accumulated during the coarse rotation stage and the phase output from the lookup table to correct the phase shift introduced during the CORDIC iteration process.

[0085]

[0086] Then, based on the sector identifier s determined in step S1, the phase is recovered using its corresponding reverse mapping relationship to correct the phase shift introduced during sector folding, thus obtaining the final compensated phase. The reverse mapping relationship is as follows:

[0087] .

[0088] Example 2

[0089] Based on the same inventive concept, such as Figure 4 As shown, this invention also proposes a Cartesian to Polar coordinate transformation device based on a hybrid LUT and CORDIC architecture, comprising:

[0090] The sector folding preprocessing unit is configured to receive input Cartesian coordinate vectors. Determine the sector to which the rectangular coordinate vector belongs and output the sector identifier s; perform the corresponding absolute value and coordinate exchange operations on the rectangular coordinate vector, and then map the rectangular coordinate vector to... Within the sector range, obtain the preprocessed coordinate vector. ;

[0091] The coarse rotation iteration unit is configured to receive the preprocessed Cartesian coordinate vector. its x-coordinate and the vertical axis Simultaneously, a left shift operation of L bits is performed, followed by N iterations of CORDIC rotation on the shifted coordinate vector, where N is a positive integer; after the iteration is complete, the ordinate obtained from the iteration is output. With cumulative rotation angle The iteratively obtained x-coordinates direct as and the ordinate Take the absolute value as Thus, coordinate vectors are constructed. ;

[0092] The dynamic address generation unit is configured to detect the x-coordinate of the output of the coarse rotation iteration unit. The position of the highest non-zero bit, and accordingly adaptively adjust the horizontal coordinate. and ordinate Perform bit sequence truncation or bit sequence truncation and bit-inversion operations, concatenate the processed coordinate components, and finally generate the lookup table index address; where the truncation operation extracts the x-coordinate. The bit sequence is of length M-1, and the truncated ordinate is... The length of the bit sequence is MN;

[0093] The compressed lookup table storage unit is configured to store the compressed lookup table and read the lookup table based on the index address generated by the dynamic address generation unit, and output the corresponding modulus residual and phase.

[0094] The data compensation and reconstruction unit is configured to compensate and reconstruct the modulus residuals and phases output by the compressed lookup table storage unit, thereby generating the target polar coordinate data. .

[0095] Specifically, in the sector folding preprocessing unit, the input rectangular coordinate vector It is binary data with a bit width of W0, where W0 is a positive integer.

[0096] Specifically, in the sector folding preprocessing unit, the "sector" refers to several regions divided into Cartesian coordinate planes based on phase range. More specifically, this invention divides the entire coordinate plane into... The phase interval is evenly divided into eight sectors, and the phase interval corresponding to each sector is... ,in Each sector corresponds to a unique sector identifier s, the value of which is equal to k; the sector identifier will be passed to the next unit for phase correction; the sector determination is based on the input rectangular coordinate vector. middle and The relationship between the sign bit and the absolute value.

[0097] Specifically, in the sector folding preprocessing unit, the corresponding absolute value and coordinate exchange operations are performed on the rectangular coordinate vector, specifically: the x-coordinate is... and the vertical axis Take the absolute value; if the ordinate at this time The absolute value is greater than the x-axis. When calculating the absolute value, swap the x and y coordinates after taking the absolute value, and map the input vector to... Within the sector range.

[0098] Specifically, the sector folding preprocessing unit of this embodiment is configured to implement the processing logic of step S1 in embodiment one. The unit includes an absolute value operation circuit, a comparator and a multiplexer.

[0099] Specifically, the absolute value operation circuit first receives the x-coordinate and y-coordinate of the input vector and performs an absolute value operation on each; then, the comparator receives the absolute values ​​of the x-coordinate and y-coordinate and compares their magnitudes; based on the comparison result, the multiplexer selectively swaps the absolute values ​​of the x-coordinate and y-coordinate to ensure that the output x-coordinate is always greater than the y-coordinate, thereby uniformly mapping the input vector to... Within the sector range; simultaneously, combining the original sign bit of the input coordinates and the comparison result of the numerical comparator, the sector identifier s corresponding to the input vector is obtained according to the judgment rules in Table 1.

[0100] Specifically, the coarse rotation iteration unit is connected to the sector folding preprocessing unit, configured to receive the preprocessed coordinate vector, and execute the left shift by L bits and N CORDIC rotation iterations in step S2 of Embodiment 1. This unit adopts a pipelined architecture, specifically implemented by an input shift circuit, cascaded shift logic circuits, an adder, a pipelined register, and an absolute value operation circuit. Its specific left shift and iteration formulas are consistent with the mathematical model of step S2 in Embodiment 1.

[0101] Specifically, in the coarse rotation iteration unit, the iteration process includes: in each iteration, controlling the rotation direction according to the sign of the current coordinate vector's ordinate, driving the coordinate vector to approach the horizontal axis, and accumulating the rotation angle generated in each iteration; after N iterations, the coordinate vector is obtained. With cumulative rotation angle The iteratively obtained x-coordinates direct as and the ordinate Take the absolute value as Construct coordinate vectors It should be noted that, due to the characteristics of the CORDIC algorithm, the output coordinate vector at this time... A fixed modulus gain is introduced, which will be compensated in subsequent data compensation and reconstruction units.

[0102] Specifically, the dynamic address generation unit is connected to the coarse rotation iteration unit and configured to execute the address generation logic in step S3 of Embodiment 1; this unit includes a leading zero detection circuit (LZD), a bit truncation logic circuit, and an address mapping logic circuit; the leading zero detection circuit is used to detect the horizontal coordinate. The highest non-zero bit is used as the basis for decision-making and branch processing.

[0103] Specifically, the dynamic address generation unit employs an adaptive truncation strategy based on the position of the highest non-zero bit, which includes: detecting the horizontal coordinate. In binary representation, when the position of the most non-zero bit is in the high-order interval (i.e., the position is the Mth bit or higher from the least significant bit), a floating truncation is performed, using this most non-zero bit as the truncation reference bit for the horizontal axis. Extract the M-1 bit sequence immediately below the reference bit, i.e., the extracted sequence does not include the reference bit. For the vertical axis... Starting from the position N bits below the truncation reference bit, a bit sequence of length MN is truncated in the direction of lower bits. When the position of the highest non-zero bit is in the lower bit interval, that is, within the Mth bit from the least significant bit to the most significant bit, the Mth bit from the least significant bit to the most significant bit is used as the truncation reference bit, and fixed truncation and reversal are performed, that is, the horizontal coordinate is directly truncated. The lowest M-1 bit sequence, and the ordinate The lowest MN bit sequence is obtained, and the bitwise inversion operation is performed on each bit sequence obtained by the truncation. Finally, the coordinate components processed by any of the above branches are concatenated to generate the lookup table index address.

[0104] Specifically, the compressed lookup table storage unit is connected to the dynamic address generation unit and is configured to output the corresponding modulus residual and phase according to the received index address. The unit contains a read-only memory (ROM) for storing the pre-calculated compressed lookup table. The data stored in the lookup table is obtained by pre-calculating and fixed-pointing according to the formula in step S4 of embodiment one. After fixed-pointing, the bit width of the modulus residual is W2 bits and the phase is W3 bits.

[0105] Specifically, the compressed lookup table storage unit pre-stores the modulus residual and phase data under the effective bit width determined based on the dynamic truncation strategy; wherein, the effective bit width refers to the horizontal coordinate. The M-bit (composed of the truncated reference bit and the truncated M-1 bit sequence) and the ordinate The MN bits are truncated; the modulus residual and phase data are obtained by traversing all combinations of values ​​of the horizontal and vertical coordinates within the effective bit width, calculating the corresponding modulus residual and phase offline, and then converting them to fixed points; the modulus residual refers to the difference between the vector modulus formed by the horizontal and vertical coordinate values ​​corresponding to the effective bit width and the horizontal coordinate value during the traversal process.

[0106] Specifically, the data compensation and reconstruction unit is connected to the compressed lookup table storage unit, the coarse rotation iteration unit, and the sector folding preprocessing unit, respectively, and is configured to perform the compensation and reconstruction operation in step S5 of Embodiment 1.

[0107] Specifically, in the data compensation and output reconstruction unit, the operations on the modulus include shifting and restoring the received modulus residual according to the dynamic truncation rule, and using the abscissa obtained after iteration with the coarse rotation iteration unit. The process involves numerical reconstruction through addition, compensation for the magnitude gain caused by the CORDIC rotation iterations, and right-shift recovery based on the number of left shifts during the coarse rotation phase. Phase operations include using the ordinate at the end of the CORDIC rotation. The sign of the received phase is compared with the cumulative rotation angle generated during the coarse rotation stage. Perform sum or absolute difference operations, and perform inverse transformations based on sector identifiers s to correct phase shifts caused by sector folding.

[0108] Specifically, in the modulus processing path, the data compensation and reconstruction unit internally includes cascaded modulus reconstruction circuits and gain compensation circuits. First, the modulus reconstruction circuit uses a dynamic shifter to perform shift recovery on the modulus residual based on the shift amount provided by the dynamic address generation unit. Then, an adder is used to combine the recovered modulus residual with the abscissa obtained after rotation iteration. The two values ​​are added together to complete the initial reconstruction of the modulus. Subsequently, the gain compensation circuit receives the initially reconstructed modulus, performs the multiplication operation of the gain factor K using a shift-add tree (i.e., combinational logic composed of shift logic and adders), and completes the final compensation output of the modulus through a right shift circuit.

[0109] In the phase processing path, this unit includes a conditional arithmetic operation circuit and a multiplexer. It first uses the conditional arithmetic operation circuit to compare the phase output from the lookup table with the cumulative rotation angle generated during the coarse rotation stage. Perform sum or absolute difference operations, and then use a multiplexer to select between different operation paths according to the sector identifier s to perform phase inversion mapping, and finally generate the output phase.

[0110] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A method for converting Cartesian coordinates to polar coordinates based on a hybrid architecture of LUT and CORDIC, characterized in that, Includes the following steps: S1. Sector folding preprocessing: Determine the input rectangular coordinate vector. The sector to which the rectangular coordinate vector belongs is determined, and the corresponding absolute value and coordinate exchange operations are performed on the rectangular coordinate vector, thereby mapping the rectangular coordinate vector to... Within the sector range, obtain the preprocessed coordinate vector. ; S2. Coarse rotation iteration, applying the coordinate vector obtained in step S1... x-coordinate and the vertical axis Simultaneously, a left shift operation of L bits is performed, followed by N CORDIC rotation iterations on the shifted coordinate vector, where N is a positive integer; after the iterations are completed, the cumulative rotation angle is output. The iteratively obtained x-coordinates direct as and the ordinate Take the absolute value as Thus, coordinate vectors are constructed. ; S3. Dynamic address generation, detecting the x-coordinate obtained in step S2. The position of the highest non-zero bit, and accordingly adaptively adjust the horizontal coordinate. and ordinate Perform bit sequence truncation or bit sequence truncation and bit-inversion operations, concatenate the processed coordinate components, and finally generate the lookup table index address; where the truncation operation extracts the x-coordinate. The bit sequence is of length M-1, and the truncated ordinate is... The length of the bit sequence is MN; S4. Compressed lookup table query: Based on the lookup table index address obtained in step S3, the preset compressed lookup table is read and the corresponding modulus residual and phase are output. S5. Data Compensation and Reconstruction: The modulus residuals and phase obtained in step S4 are compensated and reconstructed to generate the target polar coordinate data. ; All input, output, and intermediate node data in the processing steps are in binary format.

2. The method for converting Cartesian coordinates to polar coordinates based on a hybrid LUT and CORDIC architecture as described in claim 1, characterized in that, The rectangular coordinate vector input in step S1 This is binary data with a bit width of W0, where W0 is a positive integer; In step S1, the "sector" refers to several regions divided into Cartesian coordinate planes based on phase range; the entire coordinate plane is divided into... The phase interval is evenly divided into eight sectors, and the phase interval corresponding to each sector is... ,in Each sector corresponds to a unique sector identifier s, the value of which is equal to k; the sector identifier s will be passed to the subsequent step S5 for phase correction; the sector determination is based on the input rectangular coordinate vector. middle and The relationship between the sign bit and the absolute value; In step S1, the corresponding absolute value and coordinate exchange operations are performed on the rectangular coordinate vector, specifically: the x-coordinate is changed... and the vertical axis Take the absolute value; if the ordinate at this time The absolute value is greater than the x-axis. When calculating the absolute value, swap the x and y coordinates after taking the absolute value, and map the input vector to... Within the sector range.

3. The method for converting Cartesian coordinates to polar coordinates based on a hybrid LUT and CORDIC architecture as described in claim 1, characterized in that, The iterative process in step S2 specifically includes: in each iteration, controlling the rotation direction according to the sign of the ordinate of the current coordinate vector, driving the coordinate vector to approach the horizontal axis, and accumulating the rotation angle generated in each iteration; after N iterations, the coordinate vector is obtained. With cumulative rotation angle The iteratively obtained x-coordinates direct as and the ordinate Take the absolute value as Construct coordinate vectors .

4. The method for converting Cartesian coordinates to polar coordinates based on a hybrid LUT and CORDIC architecture as described in claim 1, characterized in that, In step S3, the dynamic address generation adopts an adaptive truncation strategy based on the position of the highest non-zero bit, specifically including: detecting the horizontal coordinate. In binary representation, when the position of the most non-zero bit is in the high-order interval (i.e., the position is the Mth bit or higher from the least significant bit), a floating truncation is performed, using this most non-zero bit as the truncation reference bit for the horizontal axis. Extract the M-1 bit sequence immediately below the reference bit, i.e., the extracted sequence does not include the reference bit. For the vertical axis... Starting from the position N bits below the truncation reference bit, a bit sequence of length MN is truncated in the direction of lower bits. When the position of the highest non-zero bit is in the lower bit interval, that is, within the Mth bit from the least significant bit to the most significant bit, the Mth bit from the least significant bit to the most significant bit is used as the truncation reference bit, and fixed truncation and reversal are performed, that is, the horizontal coordinate is directly truncated. The lowest M-1 bit sequence, and the ordinate The lowest MN bit sequence is obtained, and the bitwise inversion operation is performed on each bit sequence obtained.

5. The method for converting Cartesian coordinates to polar coordinates based on a hybrid LUT and CORDIC architecture as described in claim 1, characterized in that, In step S4, the compressed lookup table pre-stores the modulus residual and phase data under the effective bit width determined based on the dynamic truncation strategy; where the effective bit width refers to the horizontal axis. M position and ordinate The MN bits are truncated; among them, the modulus residual and phase data are obtained by traversing all combinations of values ​​of the horizontal and vertical coordinates within the effective bit width, calculating the corresponding modulus residual and phase offline, and then converting them to fixed points; the modulus residual refers to the difference between the vector modulus formed by the horizontal and vertical coordinate values ​​corresponding to the effective bit width and the horizontal coordinate value during the traversal process.

6. The method for converting Cartesian coordinates to polar coordinates based on a hybrid LUT and CORDIC architecture as described in claim 1, characterized in that, In step S5, the operations on the modulus value include shifting and restoring the received modulus residual according to the dynamic truncation rule, and comparing it with the abscissa obtained after iteration in step S2. The process involves numerical reconstruction through addition, compensation for the magnitude gain caused by the CORDIC rotation iterations, and right-shift recovery based on the number of left shifts during the coarse rotation phase. Phase operations include using the ordinate at the end of the CORDIC rotation. The sign of the received phase is compared with the cumulative rotation angle generated during the coarse rotation stage. Perform sum or absolute difference operations, and perform inverse transformations to correct phase shifts caused by sector folding.

7. A Cartesian to Polar Coordinate Transformation Device Based on a Hybrid LUT and CORDIC Architecture, characterized in that, include: The sector folding preprocessing unit is configured to receive input Cartesian coordinate vectors. Determine the sector to which the rectangular coordinate vector belongs and output the sector identifier s; perform the corresponding absolute value and coordinate exchange operations on the rectangular coordinate vector, and then map the rectangular coordinate vector to... Within the sector range, obtain the preprocessed coordinate vector. ; The coarse rotation iteration unit is configured to receive the preprocessed rectangular coordinate vector. its x-coordinate and the vertical axis Simultaneously, a left shift operation of L bits is performed, followed by N CORDIC rotation iterations on the shifted coordinate vector, where N is a positive integer; after the iteration is complete, the ordinate obtained from the iteration is output. With cumulative rotation angle ; The x-coordinate obtained from the iteration direct as and the ordinate Take the absolute value as Thus, coordinate vectors are constructed. ; The dynamic address generation unit is configured to detect the x-coordinate of the output of the coarse rotation iteration unit. The position of the highest non-zero bit, and accordingly adaptively adjust the horizontal coordinate. and ordinate Perform bit sequence truncation or bit sequence truncation and bit-inversion operations, concatenate the processed coordinate components, and finally generate the lookup table index address; where the truncation operation extracts the x-coordinate. The bit sequence is of length M-1, and the truncated ordinate is... The length of the bit sequence is MN; The compressed lookup table storage unit is configured to store the compressed lookup table and read the lookup table based on the index address generated by the dynamic address generation unit, and output the corresponding modulus residual and phase. The data compensation and reconstruction unit is configured to compensate and reconstruct the modulus residuals and phases output by the compressed lookup table storage unit, thereby generating the target polar coordinate data. .

8. The Cartesian to Polar Coordinate Conversion Device based on a LUT and CORDIC Hybrid Architecture according to claim 7, characterized in that, In the sector folding preprocessing unit, the input rectangular coordinate vector This is binary data with a bit width of W0, where W0 is a positive integer; In the sector folding preprocessing unit, a "sector" refers to several regions divided into Cartesian coordinate planes based on phase range; the entire coordinate plane is folded... The phase interval is evenly divided into eight sectors, and the phase interval corresponding to each sector is... ,in Each sector corresponds to a unique sector identifier s, the value of which is equal to k; the sector identifier will be passed to the next unit for phase correction; the sector determination is based on the input rectangular coordinate vector. middle and The relationship between the sign bit and the absolute value; In the sector folding preprocessing unit, the corresponding absolute value and coordinate exchange operations are performed on the rectangular coordinate vector. Specifically, the x-coordinate is changed... and the vertical axis Take the absolute value; if the ordinate at this time The absolute value is greater than the x-axis. When calculating the absolute value, swap the x and y coordinates after taking the absolute value, and map the input vector to... Within the sector range.

9. A rectangular-to-polar coordinate conversion device based on a hybrid LUT and CORDIC architecture according to claim 7, characterized in that, In the coarse rotation iterative unit, the iterative process specifically includes: in each iteration, controlling the rotation direction according to the sign of the current coordinate vector's ordinate, driving the coordinate vector to approach the horizontal axis, and accumulating the rotation angle generated in each iteration; after N iterations, the coordinate vector is obtained. With cumulative rotation angle The iteratively obtained x-coordinates direct as and the ordinate Take the absolute value as Construct coordinate vectors ; The dynamic address generation unit employs an adaptive truncation strategy based on the position of the highest non-zero bit, specifically including: detecting the horizontal coordinate. In binary representation, when the position of the most non-zero bit is in the high-order interval (i.e., the position is the Mth bit or higher from the least significant bit), a floating truncation is performed, using this most non-zero bit as the truncation reference bit for the horizontal axis. Extract the M-1 bit sequence immediately below the reference bit, i.e., the extracted sequence does not include the reference bit. For the vertical axis... Starting from the position N bits below the truncation reference bit, a bit sequence of length MN is truncated in the direction of lower bits. When the position of the highest non-zero bit is in the lower bit interval, that is, within the Mth bit from the least significant bit to the most significant bit, the Mth bit from the least significant bit to the most significant bit is used as the truncation reference bit, and fixed truncation and reversal are performed, that is, the horizontal coordinate is directly truncated. The lowest M-1 bit sequence, and the ordinate The lowest MN bit sequence is obtained, and the bitwise inversion operation is performed on each bit sequence obtained.

10. A Cartesian to Polar Coordinate Conversion Device Based on a Hybrid LUT and CORDIC Architecture as described in claim 7, characterized in that, The compressed lookup table storage unit pre-stores the modulus residual and phase data under the effective bit width determined by the dynamic truncation strategy; where the effective bit width refers to the horizontal axis. M position and ordinate The MN bits are extracted; the modulus residual and phase data are obtained by traversing all combinations of values ​​of the horizontal and vertical coordinates within the effective bit width, calculating the corresponding modulus residual and phase offline, and then converting them to fixed points; the modulus residual refers to the difference between the vector modulus formed by the horizontal and vertical coordinate values ​​corresponding to the effective bit width and the horizontal coordinate value during the traversal process. In the data compensation and output reconstruction unit, the operations on the modulus include shifting and restoring the received modulus residual according to the dynamic truncation rule, and using the abscissa obtained after iteration with the coarse rotation iteration unit. The process involves numerical reconstruction through addition, compensation for the magnitude gain caused by the CORDIC rotation iterations, and right-shift recovery based on the number of left shifts during the coarse rotation phase. Phase operations include using the ordinate at the end of the CORDIC rotation. The sign of the received phase is compared with the cumulative rotation angle generated during the coarse rotation stage. Perform sum or absolute difference operations, and perform inverse transformations based on sector identifiers s to correct phase shifts caused by sector folding.

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