High-density single-fingered eDRAM memory-computing integrated macro with bit-level sparse perception and kernel-level weight update

Abstract

The invention belongs to the field of artificial intelligence hardware acceleration, and discloses a high-density single-fingered eDRAM storage and calculation integrated macro with bit-level sparse perception and kernel-level weight update, which comprises an input buffer, a weight buffer, a word line decoder, a bit line driver, a single-fingered eDRAM array and an output buffer, the weight buffer is used for writing weights from the off-chip and writing the weights into the single-finger eDRAM array line by line, and each single-finger eDRAM storage unit only stores one bit; the input buffer is used for writing an input activation value and transmitting a multi-bit input activation value into the single-fingered eDRAM array bit by bit from a low bit to a high bit, each row of single-fingered eDRAM is equipped with a bit saliency perception analog-to-digital converter BSA-ADC and is used for executing matrix vector multiplication and transmitting a calculation result to a calculation line CL, the BSA-ADC digitalizes an accumulation result on the calculation line, and the calculation line CL is connected with the input buffer. The result is transmitted to the output buffer; the output buffer is used for outputting the calculation result. The integrated macro has the advantages of high density, low energy consumption and high throughput.

Description

Technical Field

[0001] This invention belongs to the field of artificial intelligence hardware acceleration, specifically relating to a compute-in-memory (CIM) macroarchitecture based on embedded dynamic random access memory (eDRAM) for efficiently performing matrix-vector multiplication operations in deep neural networks (DNN). Background Technology

[0002] With the rapid development of technologies such as AI, IoT, and autonomous driving, the demand for data-intensive computing is growing exponentially. Current DNN models have hundreds of millions of parameters, posing a severe challenge to the density and energy efficiency of in-memory computing macrocells. The traditional von Neumann architecture, which separates storage and computation, results in data transfer power consumption accounting for as much as 63.7% (7nm process node), creating a dual bottleneck of "memory wall" and "power wall." To address this issue, Computing-in-Memory (CIM) technology has emerged. Its core is the integration of storage arrays and computing circuits to achieve "in-situ computation," and the CIM macrocell, as a fundamental functional module of the CIM architecture, has become a hot research topic in the industry.

[0003] Currently, in-memory computing macro technology is developing in parallel with multiple technical approaches, and each approach has related patent solutions disclosed, as detailed below: 1. SRAM-based macro computing technology roadmap This approach uses SRAM as the storage medium, emphasizing high speed and low latency characteristics. Related patented solutions include: CN118245431A discloses a configurable logic operation in-memory computing circuit based on SRAM, which realizes Boolean operations such as AND / OR / XOR of weights and activation factors through a data input control module, an SRAM-CIM array, and a hybrid architecture adder tree (binary tree + Wallace tree), supports configuration of operation logic, reduces data transfer power consumption and improves flexibility; CN117033302A discloses a storage computing unit and macro module, which adopts a design of 1-bit multiplication unit + differential capacitor + SAR logic unit, is compatible with a near-standard 6T SRAM storage unit, simplifies wiring to reduce parasitics, improves energy efficiency and storage density, and reduces the number of metal layers to control costs.

[0004] 2. Novel Non-Volatile Storage-Based Macro Computing Technology Roadmap This approach focuses on non-volatile memory such as memristors and RRAM, emphasizing high density and low power consumption. Related patented solutions include: CN120564791A discloses a 3T1R memristor memory array, which introduces a third transistor T0 on the basis of the traditional 1T1R / 2T1R, simplifies the bit line load to the gate capacitance, eliminates charging and discharging delay by combining LDO constant voltage source drive, and achieves high-precision / low-power dual-mode switching by output transistor width-to-length ratio compensation factor. CN114171085A discloses a magnetic field sensing-memory-computing integrated structure based on the magnetoelectric effect. Through ultra-dense nanotube connections of the sensing layer (magnetostrictive + piezoelectric layer), the storage layer (RRAM), and the computing layer, magnetic field signals can be directly and parallelly written into the storage unit, which is suitable for power grid monitoring and equipment life prediction scenarios.

[0005] 3. Macro technology roadmap integrating sensing, storage, and computing This approach integrates sensing, storage, and computing functions, with an emphasis on real-time processing at the edge. Related patented solutions include: CN119537309A discloses a macrocell circuit integrating sensing, storage, and computing, and a digital-to-analog conversion method. It realizes the writing of weight signals and the reading of digital signals through the iSC bus, and completes bit-level conversion and accumulates to obtain analog signals based on the formula "DREGn * weight signal", thereby realizing parallel conversion between digital and analog domain signals. CN119441134A discloses a corresponding analog-to-digital conversion scheme that does not require a dedicated ADC circuit. It utilizes the existing PE circuit to iteratively compare the analog signal with the reference signal and output a digital signal, thus simplifying the circuit structure. CN119562174A discloses a 3D sensing and computing macro unit, which converts time-of-flight into pulse signals through a 3D optical signal sensing unit, and then converts them into analog electrical signals through a time conversion analog circuit (control + integration + readout module), suitable for 3D vision scenes; CN116881193A discloses a sensing-memory-computing macrocell based on MSC / INS dual bus, in which the analog signal output by the sensing unit is processed directly within the macrocell, eliminating the need for digital-to-analog conversion and external transmission, thus improving real-time performance.

[0006] Existing technologies generally suffer from the following problems: 1) Low memory density: Traditional eDRAM-CIM requires large-capacity capacitors to maintain the weighting voltage, which leads to an increase in cell area, and its density is even lower than that of SRAM-CIM; 2) High energy consumption: Sparse input activation (IA) results in low computational energy efficiency (>80% of energy-saving potential is not utilized), and high-precision analog-to-digital converters (ADCs) contribute 69% of the total energy consumption; 3) Insufficient utilization: When weights are updated / refreshed, the entire macro needs to be idle, resulting in a throughput loss of up to 45% (e.g., ResNet-18). Summary of the Invention

[0007] The purpose of this invention is to overcome at least one deficiency of the prior art and provide a high-density single-finger eDRAM in-memory computing macro with bit-level sparse awareness and kernel-level weight update / refresh.

[0008] The technical solution adopted in this invention is: A first aspect of the present invention provides: a single-finger eDRAM memory cell based on low-leakage retention technology, comprising: three transistors M1-M3 and an interlayer metal-moment (MOM) capacitor C. SF The drain of M1 is connected to bit line BL, the gate of M1 is connected to word line WL, the source of M1 is connected to the gate of M2 and M3, the source of M2 is connected to input activation, and the drain of M2 and M3 is connected to C. SF The capacitor base plate, the source terminal of M3 is connected to V. S C SF The capacitor base plate is connected to the calculation line CL.

[0009] In some instances, M1 is a high-threshold PMOS transistor, M2 is a low-threshold PMOS transistor, and M3 is a low-threshold NMOS transistor.

[0010] In some instances, the parasitic capacitances at the source of M1 and the gates of M2 and M3 are used to store weights, controlled by the substrate voltage V of M1. BP and drain voltage V BL To manage storage node V W The leakage current.

[0011] In some instances, a p-source input structure is used, transmitting input activation from the source of M2 while setting the source of M3 to a fixed low level V. S .

[0012] In some instances, C SF Constructed from the upper metal layer, adjacent C SF They share the same metal roof.

[0013] A second aspect of the present invention provides: a high-density single-finger eDRAM in-memory macro, comprising an input buffer, a weighted buffer, a word line decoder, a bit line driver, a single-finger eDRAM array, and an output buffer, wherein: The weight buffer is used to write weights from off-chip and write the weights row by row into the single-finger eDRAM array. Each single-finger eDRAM storage cell stores only one bit, and different bit weights are stored in different single-finger eDRAM rows. The input buffer is used to write the input activation value and to pass the multi-bit input activation value bit by bit from the least significant bit to the most significant bit into the single-finger eDRAM array. As described in the first aspect of the present invention, the single-finger eDRAM memory cell of the single-finger eDRAM array includes a word line WL in the horizontal direction, a bit line BL in the vertical direction, and a computation line CL in the horizontal direction. Each row of single-finger eDRAM is equipped with a bit saliency-aware analog-to-digital converter (BSA-ADC) for performing matrix-vector multiplication and transmitting the calculation result to the computation line CL. The BSA-ADC digitizes the accumulated result on the computation line and transmits the result to the output buffer. The bitline driver is used to transmit the data to be written during weight writing, and maintains a bias voltage V during calculation or data reading. BL To minimize storage node V W Leakage current; The word line decoder is used to control the parallel word line-compute line architecture; The output buffer is used to output the calculation results.

[0014] In some instances, the BSA-ADC includes a capacitive digital-to-analog converter (CDAC), an analog comparator, a successive approximation logic module (SAR logic), and an early stop control module; One input port of the analog comparator is connected to a capacitive digital-to-analog converter, and the other input port is connected to a computing line. The output of the analog comparator is transmitted to the SAR logic. The SAR logic controls the output voltage of the CDAC based on the comparator's result, which is then sent to the analog comparator for the next round of comparison. The early stop control module is connected to the SAR logic to control the number of comparison rounds; By statistically summing different bits and partially summing or outputting the distribution of activated values, the corresponding ADC precision is assigned according to the distribution of values. Lower ADC precision is assigned to the LSB (Least Significant Bit) of the weight to reduce power consumption, and higher precision ADC is assigned to the MSB (Most Significant Bit) of the weight to ensure accuracy. Different rows of BSA-ADCs are configured with corresponding precision, and the results on the calculation line are collected and digitally converted.

[0015] In some instances, the BSA-ADC dynamically configures the ADC resolution based on weighted bit importance (MSB / LSB).

[0016] In some instances, the ADC precision is determined by the weighted data format. All MSBs are stored in one row of an eDRAM in-memory macro, and the corresponding row of ADCs is assigned high precision, while LSBs are assigned low precision.

[0017] In some instances, the single-finger eDRAM array adopts a parallel word-line-compute-line architecture. During weight update / refresh, word lines WL from the first row to the last row are opened sequentially, and weight update / refresh is performed on the single-finger eDRAM in the opened row. At the same time, the BSA-ADC corresponding to the single-finger eDRAM in the opened row is closed, and the remaining word lines WL continue to perform operations until all word lines WL have been traversed.

[0018] In some instances, the single-finger eDRAM array has 128 rows and 1024 columns.

[0019] These features can be combined arbitrarily as long as they do not conflict with each other.

[0020] The beneficial effects of this invention are: The single-finger eDRAM memory cell in some embodiments of this invention is a single-finger eDRAM memory cell based on low-leakage retention (LLR) technology. By dynamically biasing to suppress transistor leakage current, it can improve the retention time by 3.35 times without the need for external capacitors, achieving a single-finger eDRAM memory cell density of 2.28 Mb / mm². 2 (2.26 times that of SOTA eDRAM).

[0021] In some examples of this invention, the single-point eDRAM memory cell adopts a bit-level input sparse awareness (ISA) strategy: it adopts a p-source input structure, and shuts off the current path when IA=0, saving 83.7% of array power consumption compared to the n-source structure (ResNet-18@CIFAR-100).

[0022] Some examples of this invention feature a high-density single-finger eDRAM in-memory computing macro that employs a bit saliency-aware (BSA) ADC, dynamically configuring the ADC accuracy (3b-6b) according to the weighted bit importance (MSB / LSB), thereby reducing digitization power consumption by approximately 21% without additional circuitry.

[0023] Some examples of this invention feature a high-density single-finger eDRAM in-memory computing macro that employs a core-level weighted update / refresh (KWUR) strategy, parallelizes word lines (WL) and compute lines (CL), and allows other cores to continue computing while a single core is refreshed, thereby increasing throughput by 1.83 times.

[0024] Some examples of this invention feature high-density single-finger eDRAM in-memory computing macros with ultra-high density, achieving 2.28 Mb / mm². 2 Memory density and 18.7 TOPS / mm 2Throughput density, peak energy efficiency reaches 234.6 TOPS / W (0.54V@25MHz); kernel-level weight update / refresh (KWUR) reduces convolutional layer idle time by 45.7%, and ResNet-50 inference frame rate is increased by 1.11 times; under BSA-ADC, the accuracy loss of ResNet-18@CIFAR-100 is only 0.13%. Attached Figure Description

[0025] Figure 1 : Single-point (SF) eDRAM CIM macroarchitecture diagram.

[0026] Figure 2 The diagram shows the circuit schematic (left) and layout diagram (right) of eDRAM.

[0027] Figure 3 The layout (left) and operation table (right) of the 3D stacked MOM capacitors in eDRAM are shown separately.

[0028] Figure 4 : LLR working principle diagram.

[0029] Figure 5 ISA working principle diagram.

[0030] Figure 6 : Working principle diagram of BSA-ADC.

[0031] Figure 7 Parallel word-line-compute-line architecture.

[0032] Figure 8 : Continuous calculation and weight update / refresh operation process based on KWUR. Detailed Implementation

[0033] A first aspect of the present invention provides: a single-finger eDRAM memory cell based on low-leakage retention technology, comprising: three transistors M1-M3 and an interlayer metal-moment (MOM) capacitor C. SF The drain of M1 is connected to bit line BL, the gate of M1 is connected to word line WL, the source of M1 is connected to the gate of M2 and M3, the source of M2 is connected to input activation, and the drain of M2 and M3 is connected to C. SF The capacitor base plate, the source terminal of M3 is connected to V. S C SF The capacitor base plate is connected to the calculation line CL.

[0034] In some instances, M1 is a high-threshold PMOS transistor, M2 is a low-threshold PMOS transistor, and M3 is a low-threshold NMOS transistor.

[0035] In some instances, the parasitic capacitances at the source of M1 and the gates of M2 and M3 are used to store weights, controlled by the substrate voltage V of M1. BP and drain voltage V BL To manage storage node V W The leakage current.

[0036] In some instances, a p-source input structure is used, transmitting input activation from the source of M2 while setting the source of M3 to a fixed low level V. S By adopting a p-source input structure, bit-level input sparse sensing (ISA) can be achieved. When IA=0, the current path is turned off, saving 83.7% of array power consumption compared to the n-source structure (ResNet-18@CIFAR-100).

[0037] In some instances, C SF Constructed from the upper metal layer, adjacent C SF They share the same metal top plate. By sharing the metal top plate, the capacitance density can be increased by 1.72 times.

[0038] A second aspect of the present invention provides: a high-density single-finger eDRAM in-memory macro, comprising an input buffer, a weighted buffer, a word line decoder, a bit line driver, a single-finger eDRAM array, and an output buffer, wherein: The weight buffer is used to write weights from off-chip and write the weights row by row into the single-finger eDRAM array. Each single-finger eDRAM storage cell stores only one bit, and different bit weights are stored in different single-finger eDRAM rows. The input buffer is used to write the input activation value and to pass the multi-bit input activation value bit by bit from the least significant bit to the most significant bit into the single-finger eDRAM array. As described in the first aspect of the present invention, the single-finger eDRAM memory cell of the single-finger eDRAM array includes a word line WL in the horizontal direction, a bit line BL in the vertical direction, and a computation line CL in the horizontal direction. Each row of single-finger eDRAM is equipped with a bit saliency-aware analog-to-digital converter (BSA-ADC) for performing matrix-vector multiplication and transmitting the calculation result to the computation line CL. The BSA-ADC digitizes the accumulated result on the computation line and transmits the result to the output buffer. The bitline driver is used to transmit the data to be written during weight writing, and maintains a bias voltage V during calculation or data reading. BL To minimize storage node V W Leakage current; The word line decoder is used to control the parallel word line-compute line architecture; The output buffer is used to output the calculation results.

[0039] In some instances, the BSA-ADC includes a capacitive digital-to-analog converter (CDAC), an analog comparator, a successive approximation logic module (SAR logic), and an early stop control module; One input port of the analog comparator is connected to a capacitive digital-to-analog converter, and the other input port is connected to a computing line. The output of the analog comparator is transmitted to the SAR logic. The SAR logic controls the output voltage of the CDAC based on the comparator's result, which is then sent to the analog comparator for the next round of comparison. The early stop control module is connected to the SAR logic to control the number of comparison rounds; By statistically summing different bits and partially summing or outputting the distribution of activated values, the corresponding ADC precision is assigned according to the distribution of values. Lower ADC precision is assigned to the LSB (Least Significant Bit) of the weight to reduce power consumption, and higher precision ADC is assigned to the MSB (Most Significant Bit) of the weight to ensure accuracy. Different rows of BSA-ADCs are configured with corresponding precision, and the results on the calculation line are collected and digitally converted.

[0040] In some instances, the BSA-ADC dynamically configures the ADC resolution based on weighted bit importance (MSB / LSB). By dynamically configuring the ADC accuracy (e.g., 3b-6b), approximately 21% of digitization power consumption can be reduced without additional circuitry.

[0041] In some instances, the ADC precision is determined by the weighted data format. All MSBs are stored in one row of an eDRAM in-memory macro, and the corresponding row of ADCs is assigned high precision, while LSBs are assigned low precision.

[0042] In some instances, the single-finger eDRAM array adopts a parallel word-line-compute-line architecture. During weight update / refresh, word lines WL from the first row to the last row are opened sequentially, and weight update / refresh is performed on the single-finger eDRAM in the opened row. At the same time, the BSA-ADC corresponding to the single-finger eDRAM in the opened row is closed, and the remaining word lines WL continue to perform operations until all word lines WL have been traversed.

[0043] In some instances, the single-point eDRAM array has 128 rows and 1024 columns. The specific size can be set according to the computational needs.

[0044] These features can be combined arbitrarily as long as they do not conflict with each other.

[0045] The technical solution of the present invention will be further illustrated below with examples.

[0046] A high-density single-finger eDRAM in-memory computing macro, its macro architecture is as follows: Figure 1 As shown, it includes: Input buffer; weight buffer; word line decoder with integrated KWUR (core-level weight update / refresh) controller; bit line driver; A 128-row, 1024-column single-finger eDRAM array (including horizontal word lines WL, vertical bit lines BL, and horizontal compute lines CL; each row of single-finger eDRAM is equipped with a BSA-ADC; the single-finger eDRAM memory cell is a high-density 3T1C single-finger eDRAM memory cell based on low leakage retention (LLR) technology). Output buffer; At runtime: Weights are written from off-chip to the weight buffer; The weight buffer writes the weights row by row into the single-finger eDRAM array. Each single-finger eDRAM storage cell stores only one bit, and different bit weights are stored in different single-finger eDRAM rows. Write the input activation value to the input buffer; The input buffer feeds the multi-bit input activation value bit by bit into the single-finger eDRAM array from the least significant bit to the most significant bit. A single eDRAM array performs matrix-vector multiplication and transmits the calculation results to the computation line; The BSA-ADC digitizes the accumulated result on the calculation line and transmits the result to the output buffer; The output buffer outputs the calculation results.

[0047] The high-density 3T1C single-finger eDRAM memory cell based on low-leakage retention (LLR) technology is specifically as follows: Main components like Figure 2 and Figure 3 As shown, each single-finger eDRAM memory cell contains three minimum-size transistors (M1-M3) and interlayer MOM capacitors C. SF The unit area is only 0.178μm. 2 The drain of M1 is connected to bit line BL, the gate of M1 is connected to word line WL, the source of M1 is connected to the gate of M2 and M3, the source of M2 is connected to input activation, and the drain of M2 and M3 is connected to C. SF The capacitor base plate, the source terminal of M3 is connected to V. S C SF The capacitor base plate is connected to the calculation line CL; M1 is a high-threshold PMOS transistor, M2 is a low-threshold PMOS transistor, and M3 is a low-threshold NMOS transistor; The parasitic capacitances at the source of M1 and the gates of M2 and M3 store weights, which are controlled by the substrate voltage V of M1. BP and drain voltage V BL To manage storage node V W Leakage current; C SF Constructed from an upper metal layer, it incurs no additional area overhead, and adjacent C... SF They share the same metal top plate, which increases the capacitance density by 1.72 times.

[0048] Operating procedures A single eDRAM memory cell has four operating modes: write mode, read mode, refresh mode, and compute mode.

[0049] Write mode: Step 1: Transfer the weights to be written to the bit line BL; Step 2: Set word line WL low to enable word line WL and transfer the voltage on bit line BL to memory node V. W middle; Step 3: Set word line WL high to turn off word line WL, and set bit line BL to the bias voltage V under low leakage voltage condition. BL .

[0050] Read mode: Step 1: Set word line WL to low level to enable word line WL; Step 2: The voltage of the storage node is transmitted to the bit line BL and read out.

[0051] Refresh Mode: Step 1: Set the single-finger eDRAM to read mode and read out the storage weight; Step 2: Set the single-finger eDRAM to write mode and write the weight read in Step 1 back to the single-finger eDRAM memory cell.

[0052] Calculation mode: Step 1: Input activation is transmitted to the source terminal of M2. When input activation is 0, the corresponding voltage is V. S When the input activation is 1, the corresponding voltage is V. DD ; Step 2: Storage Node V W The stored weights determine whether to transmit input activation to C. SF The base plate performs a logical AND operation between input activation and weights; the result of the logical AND is C. SF The base plate voltage; Step 3: C for each single-point eDRAM SFCharge sharing is performed between them, that is, an analog domain accumulation operation is performed, and the accumulation result is reflected as the voltage on the calculation line CL.

[0053] Low Leakage Retention (LLR) Operating Procedures Figure 4 ): Step 1: Analyze storage node V W The distribution of leakage current; Step 2: Adjust V BP and V BL Ensure storage node V W The leakage current is minimal. Bit-level input sparse sensing (ISA) strategy

[0054] like Figure 5 As shown, a p-source input structure is used: input activation is transmitted from the source end of M2, while the source end of M3 is set to a fixed low level V. S .

[0055] When the single-finger eDRAM is operating in computing mode, the voltage drop between the sources of M2 and M3 is almost zero when IA=0, exhibiting bit-level input sparsity awareness. The measured array power consumption is reduced by 70% at 80% sparsity ratio. Bis-salience sensing (BSA) ADC

[0056] refer to Figure 6 The main hardware components of the BSA-ADC include: a capacitive digital-to-analog converter (CDAC), an analog comparator (one input port is connected to the capacitive digital-to-analog converter, and the other input port is connected to the computing line), a successive approximation logic module (SAR logic), and an early stop control module to enable programmable accuracy of the analog-to-digital converter (ADC).

[0057] Workflow: Step 1: Calculate the cumulative sum of different bits in the algorithm, or output the distribution of activated values; Step 2: Assign corresponding ADC precision based on the numerical distribution. Assign lower ADC precision to low significant bits to reduce power consumption, and assign higher precision ADC to high significant bits to ensure accuracy. Step 3: Configure the BSA-ADCs of different rows to the corresponding precision, collect the results on the calculation line and perform the digitization conversion process. Core-level weight update / refresh (KWUR)

[0058] refer to Figure 7 , Figure 8 Main components: Parallel layout (horizontal in this example) word line WL and compute line CL architecture.

[0059] Workflow: Step 1: Weight Update / Refresh Begins Step 2: Open the first line word line WL, perform weight update / refresh on the first line single finger eDRAM, and at the same time turn off the BSA-ADC corresponding to the first line single finger eDRAM. Continue to perform the operation on the remaining lines (line 2 to line 127). Step 3: Open the word line WL of the next row (e.g., the second row) in sequence, perform weight update / refresh on the single-point eDRAM of that row, and at the same time turn off the BSA-ADC corresponding to the single-point eDRAM of that row. Continue to perform the operation on the remaining rows (the first row, the second row to the 127th row) until all rows have been traversed.

[0060] The single-finger eDRAM memory cell in some embodiments of this invention is a single-finger eDRAM memory cell based on low-leakage retention (LLR) technology. By dynamically biasing to suppress transistor leakage current, it can improve the retention time by 3.35 times without the need for external capacitors, achieving a single-finger eDRAM memory cell density of 2.28 Mb / mm². 2 (2.26 times that of SOTA eDRAM).

[0061] In some examples of this invention, the single-point eDRAM memory cell adopts a bit-level input sparse awareness (ISA) strategy: it adopts a p-source input structure, and shuts off the current path when IA=0, saving 83.7% of array power consumption compared to the n-source structure (ResNet-18@CIFAR-100).

[0062] Some examples of this invention feature a high-density single-finger eDRAM in-memory computing macro that employs a bit saliency-aware (BSA) ADC, dynamically configuring the ADC resolution (3b-6b) according to the weighted bit importance (MSB / LSB), thereby reducing digitization power consumption by 21% without additional circuitry.

[0063] Some examples of this invention feature a high-density single-finger eDRAM in-memory computing macro that employs a core-level weighted update / refresh (KWUR) strategy, parallelizes word lines (WL) and compute lines (CL), and allows other cores to continue computing while a single core is refreshed, thereby increasing throughput by 1.83 times.

[0064] Some examples of this invention feature high-density single-finger eDRAM in-memory computing macros with ultra-high density, achieving 2.28 Mb / mm². 2 Memory density and 18.7 TOPS / mm 2Throughput density, peak energy efficiency reaches 234.6 TOPS / W (0.54V@25MHz); kernel-level weight update / refresh (KWUR) reduces convolutional layer idle time by 45.7%, and ResNet-50 inference frame rate is increased by 1.11 times; under BSA-ADC, the accuracy loss of ResNet-18@CIFAR-100 is only 0.13%.

[0065] The above is a further detailed description of the present invention and should not be considered as a limitation on the specific implementation of the present invention. For those skilled in the art, simple deductions or substitutions without departing from the concept of the present invention are all within the protection scope of the present invention.

Claims

1. A single-finger eDRAM memory cell based on low-leakage retention technology, characterized in that, include: Three transistors M1-M3 and interlayer MOM capacitor C SF The drain of M1 is connected to bit line BL, the gate of M1 is connected to word line WL, the source of M1 is connected to the gate of M2 and M3, the source of M2 is connected to input activation, and the drain of M2 and M3 is connected to C. SF The capacitor base plate, the source terminal of M3 is connected to V. S C SF The capacitor base plate is connected to the calculation line CL.

2. The single-finger eDRAM memory cell according to claim 1, characterized in that, M1 is a high-threshold PMOS transistor, M2 is a low-threshold PMOS transistor, and M3 is a low-threshold NMOS transistor.

3. The single-finger eDRAM memory cell according to claim 1, characterized in that, The parasitic capacitances at the source terminal of M1 and the gate terminals of M2 and M3 are used to store weights, which are controlled by the substrate voltage V of M1. BP and drain voltage V BL To manage storage node V W The leakage current.

4. The single-finger eDRAM memory cell according to claim 1, characterized in that, A p-source input structure is used, with input activation transmitted from the source of M2, while the source of M3 is set to a fixed low level V. S .

5. The single-finger eDRAM memory cell according to claim 1, characterized in that, C SF Constructed from the upper metal layer, with two adjacent C SF They share the same metal roof.

6. A high-density single-finger eDRAM in-memory computing macro, characterized in that, include: Input buffer, weighted buffer, word line decoder, bit line driver, single-finger eDRAM array, output buffer, where: The weight buffer is used to write weights from off-chip and write the weights row by row into the single-finger eDRAM array. Each single-finger eDRAM storage cell stores only one bit, and different bit weights are stored in different single-finger eDRAM rows. The input buffer is used to write the input activation value and to pass the multi-bit input activation value bit by bit from the least significant bit to the most significant bit into the single-finger eDRAM array. The single-finger eDRAM memory cell of the single-finger eDRAM array as described in any one of claims 1 to 5 includes a word line WL in the horizontal direction, a bit line BL in the vertical direction, and a computation line CL in the horizontal direction. Each row of single-finger eDRAM is equipped with a bit saliency-aware analog-to-digital converter (BSA-ADC) for performing matrix-vector multiplication and transmitting the calculation result to the computation line CL. The BSA-ADC digitizes the accumulated result on the computation line and transmits the result to the output buffer. The bitline driver is used to transmit the data to be written during weight writing, and maintains a bias voltage V during calculation or data reading. BL To minimize storage node V W Leakage current; The output buffer is used to output the calculation results.

7. The high-density single-finger eDRAM in-memory computing macro according to claim 6, characterized in that, The BSA-ADC includes a capacitive digital-to-analog converter (CDAC), an analog comparator, a successive approximation logic module (SAR logic), and an early stop control module. One input port of the analog comparator is connected to a capacitive digital-to-analog converter, and the other input port is connected to a computing line. The output of the analog comparator is transmitted to the SAR logic. The SAR logic controls the output voltage of the CDAC based on the comparator's result, which is then sent to the analog comparator for the next round of comparison. The early stop control module is connected to the SAR logic to control the number of comparison rounds; By statistically analyzing the cumulative sum of different bits and the partial sum or the numerical distribution of the output activation, the corresponding ADC precision is assigned according to the numerical distribution. A lower ADC precision is assigned to the LSB of the weight to reduce power consumption, and a higher precision ADC is assigned to the MSB of the weight to ensure accuracy. Different rows of BSA-ADCs are configured with corresponding precision, and the results on the calculation line are collected and digitally converted.

8. The high-density single-finger eDRAM in-memory computing macro according to claim 6, characterized in that, The BSA-ADC dynamically configures the ADC resolution according to the weighted bit importance (MSB / LSB).

9. The high-density single-finger eDRAM in-memory macro according to claim 6 or 7, characterized in that, The single-finger eDRAM array adopts a parallel word line-computation line architecture. During weight update / refresh, word lines WL from the first row to the last row are opened in sequence, and weight update / refresh is performed on the single-finger eDRAM in the opened row. At the same time, the BSA-ADC corresponding to the single-finger eDRAM in the opened row is closed. The remaining word lines WL continue to perform operations until all word lines WL have been traversed.

10. The high-density single-finger eDRAM in-memory computing macro according to claim 7, characterized in that, The ADC accuracy is determined by the weighted data format. All MSBs are stored in one row of the eDRAM in-memory macro, and the corresponding row of the ADC is assigned high precision, while the LSBs are assigned low precision.

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