Battery management system

Abstract

The invention discloses a battery management system. The battery management system comprises a first chip which is connected with the battery unit and comprises a discharge control pin; the second chip comprises a discharge input pin and a control electrode output pin; the first end of the power switch is connected to the negative end of the battery unit, and the second end of the power switch serves as a first external interface of the battery unit to be connected with a load or a charger; and the control end of the power switch is connected with the control electrode output pin and is used for being switched on or switched off under the control of a signal of the control electrode output pin.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more particularly to a battery management system. Background Technology

[0002] The Battery Management System (BMS) is the core control unit in battery applications. The BMS collects key parameters such as voltage, current, and temperature of the battery cells, combines them with algorithms to estimate the battery's state, and ensures the safe operation of the battery cells through functions such as equalization management and thermal management. However, existing battery management systems still need improvement. Summary of the Invention

[0003] The purpose of this application is to disclose a battery management system.

[0004] This application discloses a battery management system for a battery cell, comprising: The first chip is connected to the battery cell and includes a discharge control pin and a charge control pin. The second chip includes a discharge input pin, a charge input pin, and a control output pin, wherein the charge control pin is connected to the charge input pin. A power switch has a first terminal connected to the negative terminal of the battery cell and a second terminal serving as the first external interface of the battery cell for connecting to a load or charger; the control terminal of the power switch is connected to the output pin of the control electrode and is used to turn on or off under the control of the signal from the output pin of the control electrode. A protection circuit is connected to the discharge control pin, the first node, the first voltage terminal, and the negative terminal of the battery cell, and is used to control the first node to be connected to one of the first voltage terminal and the negative terminal when the discharge control pin outputs a discharge cut-off signal, so as to apply a conduction control signal to the first node. A pull-down transistor is configured such that its control terminal is connected to the first node, its first terminal is connected to the negative terminal of the battery cell, and its second terminal is connected to the discharge input pin. The transistor is used to conduct under the control of the conduction control signal, so that the negative terminal of the battery cell is connected to the discharge input pin.

[0005] In some alternative embodiments, the protection circuit is further configured to control the first node to be connected to the other of the first voltage terminal and the negative terminal when the discharge control pin outputs a discharge-allowing signal, so as to apply a shutdown control signal to the first node; the pull-down transistor is further configured to be turned off under the control of the shutdown control signal so as to disconnect the negative terminal of the battery cell from the discharge input pin.

[0006] In some optional embodiments, the protection circuit includes: a first switching circuit connected to the discharge control pin, the second node, and the negative terminal of the battery cell, and configured to control the negative terminal to connect to the second node when the discharge control pin outputs the discharge allow signal, and to control the negative terminal to disconnect from the second node when the discharge control pin outputs the discharge cut-off signal; a second switching circuit connected to the second node, the first voltage terminal, and the third node, and configured to control the first voltage terminal to connect to the third node when the negative terminal is connected to the second node, and to control the first voltage terminal to disconnect from the third node when the negative terminal is disconnected from the second node; the third node is connected to the discharge input pin; a push-pull circuit connected to the third node, the first node, the first voltage terminal, and the negative terminal, configured to control the first node to connect to one of the first voltage terminal and the negative terminal when the first voltage terminal is connected to the third node, so as to apply the cut-off control signal to the first node; the push-pull circuit is further configured to control the first node to connect to the other of the first voltage terminal and the negative terminal when the first voltage terminal is disconnected from the third node, so as to apply the conduction control signal to the first node.

[0007] In some alternative embodiments, the first switching circuit includes: a first transistor, a first electrode connected to the negative terminal of the battery cell, a second electrode connected to the second node, and a control electrode connected to the discharge control pin.

[0008] In some alternative embodiments, the second switching circuit includes: a second transistor, with a first terminal connected to the first voltage terminal, a second terminal connected to the third node, and a control terminal connected to the second node.

[0009] In some alternative embodiments, the battery management system further includes: a first resistor connected between the third node and the second terminal of the second transistor; and / or a second resistor connected between the third node and the second terminal of the pull-down transistor; and / or a third resistor connected between the second terminal of the pull-down transistor and the discharge input pin.

[0010] In some alternative embodiments, the push-pull circuit includes: a third transistor, with its first terminal connected to the first voltage terminal, its second terminal connected to the first node, and its control terminal connected to the third node; and a fourth transistor, with its first terminal connected to the negative terminal of the battery cell, its second terminal connected to the first node, and its control terminal connected to the third node.

[0011] In some alternative implementations, the battery management system further includes a Zener diode connected between the control terminal of the pull-down transistor and the negative terminal of the battery cell.

[0012] In some alternative implementations, the battery management system further includes a sampling resistor connected between the negative terminal and the power switch.

[0013] In some alternative implementations, the power switch is a bidirectional power device.

[0014] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0016] Figure 1 This is a schematic diagram of a battery management system according to an embodiment of this application.

[0017] Figure reference numerals: AFE, first chip; BU, battery cell; DSG, discharge control pin; CHG, charge control pin; DIC, second chip; DSGI, discharge input pin; CHGI, charge input pin; GATE, gate output pin; SW, power switch; P-, first external interface; P+, second external interface; N1, first node; N2, second node; N3, third node; VF, first voltage terminal; VCC, power supply pin; GND, ground terminal; SUB, substrate pin; Q1, first transistor; Q2, second transistor; Q3, third transistor; Q4, fourth transistor; Q5, pull-down transistor; VD, Zener diode; 1. Protection circuit; 101. First switching circuit; 102. Second switching circuit; 103. Push-pull circuit; Rsense, sampling resistor; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; R8, eighth resistor; R9, ninth resistor; R10, tenth resistor; R11, eleventh resistor; R12, twelfth resistor; R13, thirteenth resistor; R14, fourteenth resistor; R15, fifteenth resistor; C1, first capacitor; BATN, first monitoring pin; PAKN, second monitoring pin; D1, first diode; D2, second diode. Detailed Implementation

[0018] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0019] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0020] like Figure 1 As shown, this application provides a battery management system for a battery cell (BU). The battery management system includes: a first chip AFE, connected to the battery cell BU, and including a discharge control pin DSG and a charging control pin CHG; a second chip DIC, including a discharge input pin DSGI, a charging input pin CHGI, and a control electrode output pin GATE, with the charging control pin CHG connected to the charging input pin CHGI; a power switch SW, with its first terminal TE1 connected to the negative terminal of the battery cell BU (the negative terminal is grounded), and its second terminal TE2 serving as the first external interface P- of the battery cell BU for connecting a load or charger; the control terminal of the power switch SW is connected to the control electrode output pin GATE, used for controlling the output of the battery cell BU via the control electrode output pin GATE. The circuit is turned on or off under the control of the signal from TE; the protection circuit 1 is connected to the discharge control pin DSG, the first node N1, the first voltage terminal VF, and the negative terminal of the battery cell BU, and is used to control the first node N1 to be connected to one of the first voltage terminal VF and the negative terminal when the discharge control pin DSG outputs a discharge off signal, so as to apply a conduction control signal to the first node N1; the pull-down transistor Q5 has its control terminal connected to the first node N1, its first terminal connected to the negative terminal of the battery cell BU, and its second terminal connected to the discharge input pin DSGI, and is used to be turned on under the control of the conduction control signal so that the negative terminal of the battery cell BU is connected to the discharge input pin DSGI.

[0021] In the embodiments of this application, under short-circuit conditions, a very large short-circuit current will flow between the negative terminal of the battery cell BU and the second terminal TE2 of the power switch SW, flowing from the second terminal TE2 of the power switch SW to the negative terminal of the battery cell BU. The parasitic inductance between node A and the first terminal TE1 of the power switch SW will induce a voltage where node A is negative and the first terminal TE1 of the power switch SW is positive. When short-circuit protection is triggered and the power switch SW is turned off (requiring the discharge control pin DSG to output a discharge off signal), the parasitic inductance will induce a reverse voltage (the first terminal TE1 of the power switch SW will be negative). (Node A is positive); since the discharge control pin DSG outputs a discharge-off signal, the pull-down transistor Q5 of this application can be turned on under the control of the conduction control signal, so that the negative terminal of the battery cell BU is connected to the discharge input pin DSGI, thereby ensuring that the potential of the discharge input pin DSGI is pulled low (when the power switch SW is turned off, the potential of the discharge input pin DSGI must be low). At the same time, the turned-on pull-down transistor Q5 reduces the impedance, preventing the potential of the discharge input pin DSGI from being raised under the effect of the above-mentioned parasitic inductance, improving the reliability of short-circuit protection and enhancing the safety of the circuit.

[0022] The embodiments of this application will now be described in detail.

[0023] This application includes a first chip AFE. The discharge control pin DSG of the first chip AFE is used to output a discharge-off signal (e.g., a low-level signal) or a discharge-enable signal (e.g., a high-level signal). The charging control pin CHG of the first chip AFE is used to output a charging control signal to the charging input pin CHGI of the second chip DIC. The first chip AFE is used to acquire the voltage, loop current, and temperature parameters of the battery cell BU in real time, and output corresponding signals according to the acquired parameters. The battery cell BU can be composed of a single cell or multiple cells connected in series or parallel. The positive terminal of the battery cell BU serves as the second external interface P+. The battery cell BU is used to store electrical energy, provide power to an external load, or receive power from an external charger to complete charging.

[0024] This application includes a second chip DIC. The charging input pin CHGI of the second chip DIC is connected to the charging control pin CHG of the first chip AFE. The control output pin GATE of the second chip DIC is connected to the control terminal of the power switch SW. The first monitoring pin BATN of the second chip DIC is connected to the first terminal TE1 of the power switch SW. The second monitoring pin PAKN of the second chip DIC is connected to the second terminal TE2 of the power switch SW. The substrate pin SUB of the second chip DIC is connected to both a first diode D1 and a second diode D2. The second chip DIC outputs a signal to the power switch SW based on the signal states of the charging input pin CHGI and the discharging input pin DSGI, using the lower potential of the first monitoring pin BATN and the second monitoring pin PAKN as a reference ground.

[0025] This application includes a power switch SW. The power switch SW is a bidirectional power device. Compared to a unidirectional power device, a bidirectional power device is a semiconductor switching device that allows current to flow in both directions. It can conduct current in both directions and withstand voltage in both directions. Further, the power switch SW is a bidirectional GaN power device. The second terminal TE2 of the power switch SW serves as the first external interface P- of the battery cell BU, used to connect to a load or charger. The control terminal of the power switch SW is connected to the control output pin GATE of the second chip DIC. The power switch SW is used to turn on or off under the control of the drive signal of the second chip DIC, realizing the on / off control of the circuit.

[0026] This application includes a protection circuit 1. The protection circuit 1 is connected to the discharge control pin DSG, the first node N1, the first voltage terminal VF, and the negative terminal of the battery cell BU. It is used to control the first node N1 to connect with one of the first voltage terminal VF and the negative terminal when the discharge control pin DSG outputs a discharge-off signal, thereby applying a conduction control signal to the first node N1. The protection circuit 1 is also used to control the first node N1 to connect with the other of the first voltage terminal VF and the negative terminal when the discharge control pin DSG outputs a discharge-allow signal, thereby applying a shutdown control signal to the first node N1. The voltage of the first voltage terminal VF can be positive, for example, 10V, 12V, 14V, etc.

[0027] For example, the protection circuit 1 of this application includes a first switching circuit 101, a second switching circuit 102, and a push-pull circuit 103. The first switching circuit 101 is connected to the discharge control pin DSG, the second node N2, and the negative terminal of the battery cell BU. It is used to control the negative terminal to connect to the second node N2 when the discharge control pin DSG outputs a discharge-allowing signal, and to control the negative terminal to disconnect from the second node N2 when the discharge control pin DSG outputs a discharge-off signal. The first switching circuit 101 may include a first transistor Q1. The first transistor Q1 is an NPN transistor. The first terminal (emitter) of the first transistor Q1 is connected to the negative terminal of the battery cell BU. The second terminal (collector) of the first transistor Q1 is connected to the second node N2. The control terminal (base) of the first transistor Q1 is connected to the discharge control pin DSG. The first transistor Q1 is used to conduct when the discharge control pin DSG outputs a discharge-allowing signal.

[0028] The aforementioned second switching circuit 102 is connected to the second node N2, the first voltage terminal VF, and the third node N3. It controls the first voltage terminal VF to connect to the third node N3 when the negative terminal is connected to the second node N2, and also controls the first voltage terminal VF to disconnect from the third node N3 when the negative terminal is disconnected from the second node N2. The third node N3 is connected to the discharge input pin DSGI. The second switching circuit 102 may include a second transistor Q2. The second transistor Q2 is a PNP transistor. The first terminal (emitter) of the second transistor Q2 is connected to the first voltage terminal VF. The second terminal (collector) of the second transistor Q2 is connected to the third node N3. The control terminal (base) of the second transistor Q2 is connected to the second node N2.

[0029] The push-pull circuit 103 is connected to the third node N3, the first node N1, the first voltage terminal VF, and the negative terminal. When the first voltage terminal VF is connected to the third node N3, it controls the first node N1 to be connected to either the first voltage terminal VF or the negative terminal, thus applying a turn-off control signal to the first node N1. The push-pull circuit 103 is also used to control the first node N1 to be connected to the other of the first voltage terminal VF and the negative terminal when the first voltage terminal VF is disconnected from the third node N3, thus applying a turn-on control signal to the first node N1. The push-pull circuit 103 includes a third transistor Q3 and a fourth transistor Q4. The third transistor Q3 is a PNP transistor. The first terminal (emitter) of the third transistor Q3 is connected to the first voltage terminal VF. The second terminal (collector) of the third transistor Q3 is connected to the first node N1. The control terminal (base) of the third transistor Q3 is connected to the third node N3. The third transistor Q3 is used to turn on when the third node N3 is at a low level, pulling the first node N1 to the potential of the first voltage terminal VF. The fourth transistor Q4 is an NPN transistor. The first terminal (emitter) of the fourth transistor Q4 is connected to the negative terminal of the battery cell BU. The second terminal (collector) of the fourth transistor Q4 is connected to the first node N1. The control terminal (base) of the fourth transistor Q4 is connected to the third node N3. The fourth transistor Q4 is used to turn on when the third node N3 is high, pulling the first node N1 to the negative terminal potential of the battery.

[0030] This application includes a pull-down transistor Q5. The pull-down transistor Q5 is an NMOS transistor. The control electrode (gate) of the pull-down transistor Q5 is connected to the first node N1. The first electrode (source) of the pull-down transistor Q5 is connected to the negative terminal of the battery cell BU. The second electrode (drain) of the pull-down transistor Q5 is connected to the discharge input pin DSGI. The pull-down transistor Q5 is used to turn on under the control of a turn-on control signal, so that the negative terminal of the battery cell BU is connected to the discharge input pin DSGI. The pull-down transistor Q5 is also used to turn off under the control of a turn-off control signal, so that the negative terminal of the battery cell BU is disconnected from the discharge input pin DSGI.

[0031] This application includes a first resistor R1, a second resistor R2, and a third resistor R3. The first terminal of the first resistor R1 is connected to the second terminal of the second transistor Q2. The second terminal of the first resistor R1 is connected to the third node N3. The first terminal of the second resistor R2 is connected to the third node N3. The second terminal of the second resistor R2 is connected to the second terminal of the pull-down transistor Q5. The first terminal of the third resistor R3 is connected to the second terminal of the pull-down transistor Q5. The second terminal of the third resistor R3 is connected to the discharge input pin DSGI of the second chip DIC.

[0032] This application includes a Zener diode VD. The cathode of the Zener diode VD is connected to the control terminal of the pull-down transistor Q5. The anode of the Zener diode VD is connected to the cathode of the battery cell BU. The Zener diode VD is used to prevent damage to the control terminal (i.e., gate) of the pull-down transistor Q5 due to overvoltage.

[0033] This application includes a sampling resistor Rsense. The sampling resistor Rsense is a current sampling device. The first terminal of the sampling resistor Rsense is connected to the negative terminal of the battery cell BU. The second terminal of the sampling resistor Rsense is connected to the first terminal TE1 of the power switch SW. The two terminals of the sampling resistor Rsense are respectively connected to the current sampling pins of the first chip AFE. The sampling resistor Rsense is used to convert the loop current into a voltage signal, which is then acquired by the first chip AFE to implement overcurrent and short-circuit protection.

[0034] This application includes a fourth resistor R4 and a first capacitor C1. The first terminal of the fourth resistor R4 is connected to the positive terminal of the battery cell BU. The second terminal of the fourth resistor R4 is connected to the power supply pin VCC of the second chip DIC and the first terminal of the first capacitor C1. The fourth resistor R4 is used to limit the input current of the second chip DIC and also serves as a filter for interference suppression. The first capacitor C1 is the filter capacitor for the second chip DIC. The first terminal of the first capacitor C1 is connected to the power supply pin VCC of the second chip DIC. The second terminal of the first capacitor C1 is connected to the ground terminal GND.

[0035] This application includes a fifth resistor R5 and a sixth resistor R6. The first terminal of the fifth resistor R5 is connected to the discharge control pin DSG of the first chip AFE. The second terminal of the fifth resistor R5 is connected to the control electrode of the first transistor Q1 and the first terminal of the sixth resistor R6. The fifth resistor R5 is used to limit the current flowing into the control electrode of the first transistor Q1. The first terminal of the sixth resistor R6 is connected to the control electrode of the first transistor Q1. The second terminal of the sixth resistor R6 is connected to the first electrode of the first transistor Q1.

[0036] This application includes a seventh resistor R7 and an eighth resistor R8. The first terminal of the seventh resistor R7 is connected to the control electrode of the second transistor Q2 and the second terminal of the eighth resistor R8. The second terminal of the seventh resistor R7 is connected to the second electrode of the first transistor Q1. The seventh resistor R7 is used to limit the current flowing into the control electrode of the second transistor Q2, preventing damage to the second transistor Q2 due to overcurrent. The first terminal of the eighth resistor R8 is connected to the first electrode of the second transistor Q2 and the first voltage terminal VF. The second terminal of the eighth resistor R8 is connected to the control electrode of the second transistor Q2 and the first terminal of the seventh resistor R7.

[0037] This application includes a ninth resistor R9 and a tenth resistor R10. The first terminal of the ninth resistor R9 is connected to the third node N3. The second terminal of the ninth resistor R9 is connected to the control electrode of the third transistor Q3. The ninth resistor R9 is used to limit the current flowing into the control electrode of the third transistor Q3, preventing overcurrent damage to the third transistor Q3. The first terminal of the tenth resistor R10 is connected to the first electrode of the third transistor Q3 and the first voltage terminal VF. The second terminal of the tenth resistor R10 is connected to the control electrode of the third transistor Q3.

[0038] This application includes an eleventh resistor R11 and a twelfth resistor R12. The first terminal of the eleventh resistor R11 is connected to the third node N3. The second terminal of the eleventh resistor R11 is connected to the control electrode of the fourth transistor Q4. The eleventh resistor R11 is used to limit the current flowing into the control electrode of the fourth transistor Q4, preventing overcurrent damage to the fourth transistor Q4. The first terminal of the twelfth resistor R12 is connected to the first electrode of the fourth transistor Q4 and the negative terminal of the battery cell BU. The second terminal of the twelfth resistor R12 is connected to the control electrode of the fourth transistor Q4.

[0039] This application includes a thirteenth resistor R13 and a fourteenth resistor R14. The first terminal of the thirteenth resistor R13 is connected to the first node N1. The second terminal of the thirteenth resistor R13 is connected to the control electrode of the pull-down transistor Q5. The thirteenth resistor R13 is mainly used to regulate the voltage at the control electrode of the pull-down transistor Q5 and the current flowing into the Zener diode VD. The first terminal of the fourteenth resistor R14 is connected to the control electrode of the pull-down transistor Q5 and the second terminal of the thirteenth resistor R13. The second terminal of the fourteenth resistor R14 is connected to the first electrode of the pull-down transistor Q5 and the negative terminal of the battery cell BU.

[0040] This application includes a fifteenth resistor R15. The first terminal of the fifteenth resistor R15 is connected to the third node N3. The second terminal of the fifteenth resistor R15 is connected to the negative terminal of the battery cell BU. The fifteenth resistor R15 is used to regulate the voltage of the third node N3 to control the switching states of the third transistor Q3 and the fourth transistor Q4.

[0041] This application includes a first diode D1 and a second diode D2. The first diode D1 can be a Schottky diode, but this disclosure is not limited thereto. The cathode of the first diode D1 is connected to the second terminal TE2 of the power switch SW. The anode of the first diode D1 is connected to the substrate pin SUB of the second chip DIC. The second diode D2 can be a Schottky diode, but is not limited thereto. The cathode of the second diode D2 is connected to the first terminal TE1 of the power switch SW and the first monitoring pin BATN of the second chip DIC. The anode of the second diode D2 is connected to the substrate pin SUB of the second chip DIC.

[0042] The specific workflow of the battery management system in this embodiment is as follows: In normal operating mode, the first external interface P- and the second external interface P+ are connected to the external load. The discharge control pin DSG of the first chip AFE outputs a high-level discharge enable signal, and the charging control pin CHG outputs a low-level signal. The first transistor Q1 is in the on state, the second node N2 is pulled to the low potential of the negative terminal, the second transistor Q2 is turned on, and the high level of the first voltage terminal VF is transmitted to the third node N3. The push-pull circuit 103 (the third transistor Q3 is off, the fourth transistor Q4 is on) outputs a turn-off control signal (low level) to the first node N1, pulls down transistor Q5 (taking an NMOS transistor as an example) to turn off, the discharge input pin DSGI of the second chip DIC is in a high-impedance state, the second chip DIC controls the power switch SW to turn on, realizing the normal operation of the battery cell BU.

[0043] In short-circuit protection scenarios, when a load short circuit occurs during operation, the first chip AFE detects that the loop current exceeds the current threshold through the sampling resistor Rsense. The discharge control pin DSG of the first chip AFE outputs a low-level shutdown discharge signal, turning off the first transistor Q1, the second transistor Q2, and the fourth transistor Q4, while turning on the third transistor Q3, thus controlling the power switch SW to turn off. At this time, the parasitic inductor induces a reverse voltage. Since the pull-down transistor Q5 is in the conducting state, the input impedance of the discharge input pin DSGI of the second chip DIC is pulled low, preventing the DSGI signal from rising above the interference threshold again. This completely avoids the risk of the power switch SW turning on again during the shutdown process, significantly improving the reliability of short-circuit protection.

[0044] This embodiment also provides a battery pack, including a battery unit (BU) and the aforementioned battery management system. The battery pack may further include a housing, a heat dissipation structure, etc. The battery management system included in the battery pack of this embodiment is the same as the battery management system in the above embodiments; therefore, it has the same beneficial effects, and will not be described again here.

[0045] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A battery management system for a battery unit (BU), characterized in that, include: The first chip (AFE) is connected to the battery cell (BU) and includes a discharge control pin (DSG). The second chip (DIC) includes a discharge input pin (DSGI) and a control output pin (GATE). The power switch (SW) has its first terminal connected to the negative terminal of the battery cell (BU), and its second terminal serving as the first external interface (P-) of the battery cell (BU) for connecting to a load or charger. The control terminal of the power switch (SW) is connected to the control electrode output pin (GATE) and is used to turn on or off under the control of the signal from the control electrode output pin (GATE). The protection circuit (1) is connected to the discharge control pin (DSG), the first node (N1), the first voltage terminal (VF), and the negative terminal of the battery cell (BU). It is used to control the first node (N1) to be connected to one of the first voltage terminal (VF) and the negative terminal when the discharge control pin (DSG) outputs a discharge cut-off signal, so as to apply a conduction control signal to the first node (N1). The pull-down transistor (Q5) has its control electrode connected to the first node (N1), its first electrode connected to the negative terminal of the battery cell (BU), and its second electrode connected to the discharge input pin (DSGI). It is used to conduct under the control of the conduction control signal so that the negative terminal of the battery cell (BU) is connected to the discharge input pin (DSGI).

2. The battery management system according to claim 1, characterized in that, The protection circuit (1) is also used to control the first node (N1) to connect with the first voltage terminal (VF) and the other of the negative terminal when the discharge control pin (DSG) outputs a discharge enable signal, so as to apply a shutdown control signal to the first node (N1); the pull-down transistor (Q5) is also used to turn off under the control of the shutdown control signal so as to disconnect the negative terminal of the battery cell (BU) from the discharge input pin (DSGI).

3. The battery management system according to claim 2, characterized in that, The protection circuit (1) includes: The first switching circuit (101) is connected to the discharge control pin (DSG), the second node (N2) and the negative terminal of the battery cell (BU), and is used to control the negative terminal to connect with the second node (N2) when the discharge control pin (DSG) outputs the discharge enable signal, and is also used to control the negative terminal to disconnect from the second node (N2) when the discharge control pin (DSG) outputs the discharge cut-off signal. The second switching circuit (102) is connected to the second node (N2), the first voltage terminal (VF), and the third node (N3), and is used to control the first voltage terminal (VF) to connect to the third node (N3) when the negative terminal is connected to the second node (N2), and to control the first voltage terminal (VF) to disconnect from the third node (N3) when the negative terminal is disconnected from the second node (N2); the third node (N3) is connected to the discharge input pin (DSGI); A push-pull circuit (103) is connected to the third node (N3), the first node (N1), the first voltage terminal (VF), and the negative terminal. When the first voltage terminal (VF) is connected to the third node (N3), the push-pull circuit (103) controls the first node (N1) to be connected to one of the first voltage terminal (VF) and the negative terminal to apply the shutdown control signal to the first node (N1). The push-pull circuit (103) is also used to control the first node (N1) to be connected to the other of the first voltage terminal (VF) and the negative terminal when the first voltage terminal (VF) is disconnected from the third node (N3) to apply the conduction control signal to the first node (N1).

4. The battery management system according to claim 3, characterized in that, The first switching circuit (101) includes: The first transistor (Q1) has its first electrode connected to the negative terminal of the battery cell (BU), its second electrode connected to the second node (N2), and its control electrode connected to the discharge control pin (DSG).

5. The battery management system according to claim 3, characterized in that, The second switching circuit (102) includes: The second transistor (Q2) has its first terminal connected to the first voltage terminal (VF), its second terminal connected to the third node (N3), and its control terminal connected to the second node (N2).

6. The battery management system according to claim 5, characterized in that, The battery management system also includes: A first resistor (R1) is connected between the third node (N3) and the second terminal of the second transistor (Q2); and / or The second resistor (R2) is connected between the third node (N3) and the second terminal of the pull-down transistor (Q5); and / or The third resistor (R3) is connected between the second terminal of the pull-down transistor (Q5) and the discharge input pin (DSGI).

7. The battery management system according to claim 3, characterized in that, The push-pull circuit (103) includes: The third transistor (Q3) has its first terminal connected to the first voltage terminal (VF), its second terminal connected to the first node (N1), and its control terminal connected to the third node (N3). The fourth transistor (Q4) has its first electrode connected to the negative terminal of the battery cell (BU), its second electrode connected to the first node (N1), and its control electrode connected to the third node (N3).

8. The battery management system according to claim 1, characterized in that, The battery management system also includes: A Zener diode (VD) is connected between the control terminal of the pull-down transistor (Q5) and the negative terminal of the battery cell (BU).

9. The battery management system according to claim 1, characterized in that, The battery management system also includes: A sampling resistor (Rsense) is connected between the negative terminal and the power switch (SW).

10. The battery management system according to claim 1, characterized in that, The power switch (SW) is a bidirectional power device.

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