Digital-to-analog converters, offset calibration methods, and electronic devices

Abstract

This application discloses a digital-to-analog converter (DAC), an offset calibration method, and an electronic device. The DAC includes an operational amplifier, a control unit, an offset calibration unit, and a resistor network. The operational amplifier includes a non-inverting input terminal, an inverting input terminal, a control terminal, and an output terminal. The control unit outputs a first control signal to control the operational amplifier to enter comparator mode and performs offset calibration on the operational amplifier based on the signal output from the output terminal. The offset calibration unit generates a reference voltage when the operational amplifier is in comparator mode. The resistor network outputs an inverting input voltage when the operational amplifier is in comparator mode. The technical solution of this application generates a reference voltage by adding an offset calibration unit and processes the offset voltage of the operational amplifier based on the reference voltage, thereby achieving rapid calibration of the circuit in a specific operating mode.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a digital-to-analog converter, an offset calibration method, and an electronic device. Background Technology

[0002] With the development of computer technology, multimedia technology, signal processing technology, and microelectronics technology, the application of electronic technology has gradually permeated every corner of military and civilian fields, constantly introducing advanced electronic systems. Analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are used at both the front and back ends of modern advanced electronic systems to improve the performance of digital processing technology. DACs have always been a focus of research. Driven by related technologies in analog and digital integrated circuits, the speed and accuracy of DACs have significantly improved in recent years. There are various types of DACs, among which R2R DACs have the advantages of low noise and high accuracy, and are widely used in high-speed and medium-to-high resolution scenarios, holding significant research value in the industry.

[0003] like Figure 1 As shown, a traditional R2R DAC mainly consists of a resistor network and an operational amplifier. Factors such as the offset voltage of the operational amplifier can affect the accuracy of the DAC. Among them, the offset voltage of the operational amplifier is a significant factor affecting the static characteristics of the R2R DAC, especially in high-precision cases. When the input voltages at both ends of the operational amplifier are the same but the output is not zero, it indicates that the operational amplifier has offset, which in turn affects the accuracy of the DAC.

[0004] The offset voltage of an operational amplifier can affect the accuracy and stability of signal processing. Current DAC architectures do not address the offset voltage of operational amplifiers, which necessitates a wide offset voltage range to achieve accurate analog output voltages. However, due to factors such as manufacturing processes and temperature, the offset voltage of operational amplifiers still exhibits a considerable range. Summary of the Invention

[0005] This application discloses a digital-to-analog converter, an offset calibration method, and an electronic device that can achieve rapid circuit calibration.

[0006] To address the aforementioned technical problems, this application provides a digital-to-analog converter, comprising: An operational amplifier includes a non-inverting input terminal, an inverting input terminal, a control terminal, and an output terminal; wherein the non-inverting input terminal is connected to an offset calibration unit, the inverting input terminal is connected to a resistor network, and the control terminal is connected to a control unit; The control unit is configured to output a first control signal to control the operational amplifier to enter comparator mode, and to perform offset calibration on the operational amplifier according to the signal output from the output terminal. The offset calibration unit is used to generate a reference voltage when the operational amplifier is in comparator mode; The resistor network is used to output an inverted input voltage when the operational amplifier is in the comparator mode.

[0007] In some embodiments, the offset calibration unit includes a resistor divider network, the resistor divider network comprising an identical branch, each branch including a resistor of the same resistance value and a control switch; Wherein, N is the number of bits in the control signal output by the control unit, and the closing or opening of the control switch is controlled by the control signal output by the control unit.

[0008] In some embodiments, for any branch of the resistor divider network, when the input signal corresponding to any branch is determined to be high level according to the control signal output by the control unit, the control switch of any branch is in a closed state. When the input signal corresponding to any branch is determined to be low based on the control signal, the control switch of any branch is in the off state.

[0009] In some embodiments, the resistor network includes an A-bit R2R type resistor network and a 1-bit thermometer code bit; Wherein, A and B are determined according to the number of bits of the digital-to-analog converter.

[0010] In some embodiments, in the operational amplifier, the gate of the first MOS transistor and the gate of the second MOS transistor serve as the non-inverting input terminal and the inverting input terminal of the operational amplifier, respectively, and the first MOS transistor, the second MOS transistor, and the drain of the sixth MOS transistor in the adjustable current mirror load are connected. The gate and drain of the third MOS transistor and the gate of the fourth MOS transistor are respectively connected to the drain of the first MOS transistor. The drain of the fourth MOS transistor and the gate of the fifth MOS transistor are respectively connected to the drain of the second MOS transistor; The drain of the fifth MOS transistor is connected to the gate of the seventh MOS transistor and the upper plate of the voltage regulator capacitor, respectively. The upper plate of the compensation capacitor is connected to the drain of the second MOS transistor, and the lower plate of the compensation capacitor is connected to the drain of the fifth MOS transistor. One end of the bias current source is connected to the gate of the eighth MOS transistor, the drain of the eighth MOS transistor, and the gate of the seventh MOS transistor, respectively. The other end of the bias current is connected to the source of the third MOSFET, the source of the fourth MOSFET, the source of the fifth MOSFET, and the lower plate of the voltage regulator capacitor, and grounded. Wherein, the first MOS transistor, the second MOS transistor, the sixth MOS transistor, the seventh MOS transistor, and the eighth MOS transistor are PMOS transistors; the third MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are NMOS transistors; the adjustable current mirror load is composed of the third MOS transistor, the fourth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, and the eighth MOS transistor; The mode switching switch is in the off state when the operational amplifier is in comparator mode.

[0011] In some embodiments, the digital-to-analog converter further includes a first switch, a feedback resistor, a second switch, a load resistor, a load capacitor, and a third switch; One end of the first switch is connected to the feedback resistor, and the other end of the feedback resistor is connected to one end of the second switch and one end of the third switch, respectively. The first end of the first switch is connected to the inverting input terminal of the operational amplifier. The other end of the second switch is connected to one end of the load resistor and one end of the load capacitor, and the other end of the load resistor and the load capacitor is grounded. The other end of the third switch is connected to the output of the digital-to-analog converter. When the operational amplifier is in comparator mode, the first switch is in the open state, the second switch is in the closed state, and the third switch is in the closed state. When the operational amplifier is in operational amplification mode, the first switch is closed, the second switch is open, and the third switch is open.

[0012] In some embodiments, the control unit is further configured to control the operational amplifier to enter operational amplification mode based on a second control signal output from the control terminal; The resistor network is also used to generate a corresponding analog voltage signal based on a given digital signal when the operational amplifier is in the operational amplification mode.

[0013] This application also provides an offset calibration method, the method comprising the following steps: When the operational amplifier is in comparator mode, the reference voltage value output by the offset calibration unit and the inverted voltage value output by the resistor network are detected; wherein, the output terminal of the offset calibration unit is connected to the non-inverting input terminal of the operational amplifier, and the output terminal of the resistor network is connected to the inverting input terminal of the operational amplifier. If the reference voltage value is less than or equal to the inverting voltage value, then the reference voltage value is increased according to the resistance value in the offset calibration unit; If the reference voltage value is greater than the inverting voltage value, the target output signal is controlled to indicate that the offset calibration is complete.

[0014] In some embodiments, after increasing the reference voltage value based on the resistance value in the offset calibration unit, the method further includes: The increased reference voltage is compared with the inverted voltage value; If the reference voltage value is still less than or equal to the inverting voltage value, the step of increasing the reference voltage value according to the resistance value in the offset calibration unit is repeated until the reference voltage is greater than the inverting voltage value. If the reference voltage value is greater than the inverting voltage value, the target output signal is controlled to indicate that the offset calibration is complete.

[0015] This application also provides an electronic device, including: a processor and a memory storing a computer program, wherein when the processor runs the computer program, the steps of the above-described misalignment calibration method are implemented.

[0016] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described offset calibration method.

[0017] Compared with related technologies, the embodiments of this application have the following beneficial effects: The digital-to-analog converter of this application includes an operational amplifier, a control unit, an offset calibration unit, and a resistor network. The operational amplifier includes a non-inverting input, an inverting input, a control terminal, and an output terminal; wherein the non-inverting input is connected to the offset calibration unit, the inverting input is connected to the resistor network, and the control terminal is connected to the control unit; the control unit is used to output a first control signal to control the operational amplifier to enter comparator mode, and to perform offset calibration on the operational amplifier based on the signal output from the output terminal; the offset calibration unit is used to generate a reference voltage when the operational amplifier is in comparator mode; the resistor network is used to output an inverted input voltage when the operational amplifier is in comparator mode. The technical solution of this application, by adding an offset calibration unit to generate a reference voltage, and processing the offset voltage of the operational amplifier based on the reference voltage, thereby achieving rapid calibration of the circuit in a specific operating mode. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of an R2R type DAC in the prior art; Figure 2This is a schematic diagram of the structure of a digital-to-analog converter according to one embodiment; Figure 3 This is a schematic diagram of the structure of a digital-to-analog converter according to another embodiment; Figure 4 This is a schematic diagram of the structure of a resistor network according to one embodiment; Figure 5 This is a schematic diagram of the structure of an operational amplifier according to one embodiment; Figure 6 This is a schematic diagram of the structure of an offset calibration unit according to one embodiment; Figure 7 This is a flowchart illustrating an offset calibration method according to one embodiment; Figure 8 This is a timing diagram illustrating the correspondence between various signals according to an embodiment; Figure 9 This is a schematic diagram illustrating the calibration process of a digital-to-analog converter according to one embodiment. Detailed Implementation

[0019] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. In this invention, "each" includes one or more items.

[0021] Figure 1 This is a schematic diagram of the structure of an existing R2R type digital-to-analog converter (DAC). For example... Figure 1 As shown, the existing R2R type DAC mainly consists of two parts: a resistor network and an operational amplifier. The non-inverting input of the operational amplifier is connected to a fixed reference voltage, and the inverting input is connected to the resistor network. The output of the operational amplifier outputs an analog voltage and is also connected to a feedback resistor, which is then fed back to the inverting input.

[0022] A digital-to-analog converter (DAC) is a device that converts digital signals into analog signals; that is, it converts discrete signals in binary digital form into analog quantities based on a standard quantity (or reference quantity). An R2R DAC refers to a DAC that uses a ladder network to reduce the number of resistors.

[0023] In this application, offset calibration refers to the process of compensating for offset voltage caused by transistors due to manufacturing limitations or external factors such as humidity, temperature, and pressure. This is achieved by adding components such as resistors and capacitors externally to the operational amplifier, adding circuitry internally to the operational amplifier, or using digital signal processing techniques. The offset voltage of the operational amplifier and the parasitic capacitance of the resistor network affect the accuracy of the DAC. Among these factors, the offset voltage of the operational amplifier is a crucial factor affecting the static characteristics of R2R DACs, especially in high-precision applications. When the input voltages at both ends of the operational amplifier are the same but the output is not zero, it indicates that the operational amplifier has offset, which in turn affects the accuracy of the DAC. The offset voltage of the operational amplifier affects the accuracy and stability of signal processing. Current DAC structures do not address the offset voltage of the operational amplifier, which necessitates a high offset voltage range to obtain a relatively accurate analog output voltage. However, due to factors such as manufacturing processes and temperature, the offset voltage of the operational amplifier still has a considerable range.

[0024] like Figure 2 As shown, in one embodiment, a digital-to-analog converter (DAC) 200 is provided. This DAC may include an operational amplifier 210, an offset calibration unit 220, a resistor network 230, and a control unit 240. The operational amplifier 210 includes a non-inverting input, an inverting input, a control terminal, and an output terminal. The non-inverting input of the operational amplifier 210 is connected to the offset calibration unit 220, the inverting input is connected to the resistor network 230, and the control terminal is connected to the control unit 240.

[0025] The control unit 240 is used to output a first control signal to control the operational amplifier 210 to enter comparator mode, and to perform offset calibration on the operational amplifier 210 according to the signal output from the output terminal.

[0026] Offset calibration unit 220 is used to generate a reference voltage when operational amplifier 210 is in comparator mode.

[0027] Resistor network 230 is used to output an inverted input voltage when operational amplifier 210 is in comparator mode.

[0028] In the embodiments of this application, the operational amplifier 210 may be a general-purpose operational amplifier 210, a high-impedance operational amplifier 210, or a low-temperature drift operational amplifier 210, etc., and no specific limitation is made here.

[0029] In this embodiment, operational amplifier 210 refers to an amplifier circuit unit with high voltage amplification. In this application, operational amplifier 210 has two operating modes: operational amplification mode and comparator mode. In operational amplification mode, operational amplifier 210 functions as an amplifier to amplify the input signal. In comparator mode, operational amplifier 210 functions as a comparator to compare the voltages at the non-inverting and inverting input terminals and outputs a corresponding level signal based on the comparison result.

[0030] In this embodiment, resistor network 230 refers to the circuit that outputs corresponding voltage signals when operational amplifier 210 is in different operating modes. Control unit 240 refers to the controller that controls the operating mode of operational amplifier 210. The digital-to-analog converter controls operational amplifier 210 to switch between two modes through control unit 240. When offset calibration is required, control unit 240 outputs a first control signal to put operational amplifier 210 into comparator mode. In comparator mode, offset calibration unit 220 provides an adjustable reference voltage to the non-inverting input terminal of operational amplifier 210, and resistor network 230 provides an inverting input voltage to the inverting input terminal of operational amplifier 210. Operational amplifier 210 compares the voltages at the two input terminals and outputs a signal based on the comparison result. Control unit 240 adjusts the reference voltage output by offset calibration unit 220 according to the signal output by operational amplifier 210, thereby calibrating the offset voltage of operational amplifier 210.

[0031] Through the above technical solution, the digital-to-analog converter of the present invention can automatically calibrate the offset voltage of the operational amplifier 210 during operation, effectively eliminating the influence of offset voltage on conversion accuracy and improving the performance of the digital-to-analog converter.

[0032] In some embodiments, the digital-to-analog converter further includes a first switch, a feedback resistor, a second switch, a load resistor, a load capacitor, and a third switch; one end of the first switch is connected to the feedback resistor, the other end of the feedback resistor is connected to one end of the second switch and one end of the third switch respectively, the first end of the first switch is connected to the inverting input terminal of the operational amplifier 210; the other end of the second switch is connected to one end of the load resistor and the load capacitor respectively, the other ends of the load resistor and the load capacitor are grounded; the other end of the third switch is connected to the target output signal.

[0033] In this embodiment, the digital-to-analog converter further includes a first switch, a feedback resistor, a second switch, a load resistor, a load capacitor, and a third switch; one end of the first switch is connected to the feedback resistor, the other end of the feedback resistor is connected to one end of the second switch and one end of the third switch respectively, the first end of the first switch is connected to the inverting input terminal of the operational amplifier 210; the other end of the second switch is connected to one end of the load resistor and the load capacitor respectively, the other ends of the load resistor and the load capacitor are grounded; the other end of the third switch is connected to the output terminal of the digital-to-analog converter.

[0034] The first switch refers to the control switch that controls the on / off state of the feedback path of the operational amplifier 210; the feedback resistor refers to the resistor used to adjust the gain and stability of the operational amplifier 210; the second switch refers to the control switch that controls the on / off state of the output path of the operational amplifier 210; the load resistor refers to the resistor that performs filtering, compensation, limiting, protection, load buffering and gain adjustment on the output of the operational amplifier 210; the load capacitor refers to the capacitor that performs filtering, compensation, limiting, protection, load buffering and gain adjustment on the output of the operational amplifier 210; and the third switch refers to the control switch that controls the on / off state of the target output signal path of the operational amplifier 210.

[0035] In this embodiment, when the operational amplifier 210 is in comparator mode, the first switch is open, the second switch is closed, and the third switch is closed. At this time, the negative feedback path of the operational amplifier 210 is disconnected, and the operational amplifier 210 operates in an open-loop state. The output terminal of the operational amplifier 210 is connected to the load resistor and load capacitor via the third and second switches, and is also connected to the input terminal of the control unit 240 for offset calibration.

[0036] When operational amplifier 210 is in operational amplification mode, the first switch is closed, the second switch is open, and the third switch is open. At this time, the negative feedback path of operational amplifier 210 is connected, and operational amplifier 210 operates in a closed-loop state. The output of operational amplifier 210 is fed back to the inverting input through the first switch and the feedback resistor, forming a negative feedback amplification circuit. The second switch is open, ensuring that the load resistor and load capacitor do not affect the operation of operational amplifier 210. The third switch is open, preventing the output of operational amplifier 210 from being directly connected to the output of the digital-to-analog converter.

[0037] In a specific example, the first, second, and third switches are all constructed from MOS transistors. The control terminals of the switches are connected to the control unit 240 and receive control signals output by the control unit 240. When the control signal is high, the switch is closed; when the control signal is low, the switch is open. By outputting different control signals by the control unit 240, the state of each switch can be controlled, thereby enabling the operational amplifier 210 to switch between different modes.

[0038] The value of the feedback resistor is determined based on the gain requirements of the digital-to-analog converter. In operational amplifier mode, the gain of operational amplifier 210 is equal to the ratio of the feedback resistor to the equivalent resistance of resistor network 230. By appropriately selecting the value of the feedback resistor, the required conversion gain can be achieved.

[0039] The values ​​of the load resistor and load capacitor are determined based on the driving capability and bandwidth requirements of the digital-to-analog converter (DAC). The load resistor reflects the size of the load that the DAC needs to drive, while the load capacitor reflects the parasitic capacitance at the output and the input capacitance of the subsequent circuitry. By properly designing the load resistor and load capacitor, sufficient driving capability and bandwidth of the DAC can be ensured.

[0040] The circuit structure of a digital-to-analog converter is as follows: Figure 3 As shown. The first switch is... Figure 3 The switch S1 in the middle has a feedback resistor of Figure 3 The resistor RF in the middle, the second switch is Figure 3 The switch S2 in the middle has a load resistance of Figure 3 The resistor Rload in the figure is [resistance Rload], and the load capacitance is [capacity]. Figure 3 The capacitor Cload in the middle, the third switch is Figure 3 The target output signal of switch S3 in the middle is Figure 3 TRIM_ok in. Additionally, control unit 240 in Figure 3 Not shown in the image. Figure 3The signal `comp_en` is the control signal output by the control unit 240 to the control terminal of the operational amplifier 210. A switch S2 is connected between the output terminal of the operational amplifier 210 and the output voltage VDAC of the DAC. Switch S2 is connected to a mode switching signal; when the mode switching signal is high, switch S2 becomes high, closing the switch. A switch S1 and a feedback resistor RF are connected between the negative input terminal of the operational amplifier 210 and the output terminal of the offset operational amplifier. Switch S1 is connected to a mode switching signal; when the mode switching signal is high, switch S1 becomes low, opening the switch. A switch S3 is connected between the output terminal of the operational amplifier 210 and the output signal `TRIM_ok`. Switch S3 is connected to a mode switching signal; when the mode switching signal is high, switch S3 becomes high, closing the switch. The mode switching signals connected to switches S1, S2, and S3 can be from the same source or different sources. The output signal `TRIM_ok` is used to indicate completion of offset calibration.

[0041] By using the above embodiments, the accuracy of the digital-to-analog converter can be further improved by adding other components outside the operational amplifier 210, offset calibration unit 220, and resistor network 230.

[0042] In this embodiment, the digital-to-analog converter is preferably an R2R type DAC with an offset calibration unit 220. Therefore, as Figure 4 As shown, the resistor network 230 in the digital-to-analog converter includes an A-bit R2R type resistor network 230 and a B-bit thermometer code bit. A and B are determined according to the number of bits in the digital-to-analog converter.

[0043] In this embodiment, the sum of A and B represents the number of bits in the digital-to-analog converter (DAC). Thermometer code is a digital representation method. The main difference between thermometer code and binary code is that thermometer code uses -1 digital input to represent 1 different digital value. For the same 1 digital value, binary code only requires B digital inputs. Therefore, thermometer code requires more bits than binary representation. However, using thermometer code in a DAC can reduce differential nonlinear noise, ensure monotonicity, and reduce glitches compared to using binary code.

[0044] In this embodiment, each thermometer code bit corresponds to one branch, and the number of bits in the R2R resistor network 230 also corresponds to the same number of branches. That is, the resistor network 230 contains at least A+B branches. For example, if the digital-to-analog converter is a 12-bit DAC, it can be composed of an 8-bit R2R resistor network 230 and 16-bit thermometer code bits, i.e., B=4. If the digital-to-analog converter is a 21-bit DAC, it can be composed of a 16-bit R2R resistor network 230 and 32-bit thermometer code bits, i.e., B=5.

[0045] In this embodiment, the digital-to-analog converter is preferably a 12-bit DAC, specifically composed of an 8-bit R2R resistor network 230 and a 16-bit thermometer code. For example... Figure 4 As shown, the input signals from bits 0 to 7 control the D0 to D7 selection signals of the resistor network 230, respectively. When the input signal is high, the corresponding DX signal is high, causing the switch of the Xth branch to select the power supply voltage; when the input signal is low, the corresponding DX signal is low, causing the switch of the Xth branch to select ground. For example, when the input signal at bit 0 is high, the corresponding D0 signal is high, causing the switch of the 0th branch in the R2R type resistor network 230 to select the power supply voltage. Here, the 0th branch in the R2R type resistor network 230 refers to... Figure 4 The branch controlled by the D0 signal, the first branch in the R2R type resistor network 230 refers to... Figure 4 The branch controlled by the D1 signal.

[0046] The 8th to 11th input signals control the A0 to A15 strobe signals of the thermometer code bits via logic control. When the input is high, the corresponding AX signal is high, causing the switch of the Xth branch to select the power supply voltage; when the input signal is low, the corresponding AX signal is low, causing the switch of the Xth branch to select ground. For example, when the input signal is 0000, the corresponding strobe signal A0 is high, causing the switch of the 0th branch in the thermometer code bits to select the power supply voltage. When the input signal is 1111, the corresponding strobe signal A15 is high, causing the switch of the 15th branch in the thermometer code bits to select the power supply voltage. In other words, the decimal value corresponding to the 4-bit binary number controls the corresponding branch in the thermometer code bits. For example, when the input signal is 0000, only the A0 strobe signal is controlled to be low, causing the switch of the 0th branch in the thermometer code position to be grounded, while the other strobe signals are controlled to be high, causing the switches of the other branches in the thermometer code position to be powered by the power supply voltage. When the input signal is 1000, the A0-A7 strobe signals are controlled to be low, causing the switches of the 0th to 7th branches in the thermometer code position to be grounded, and the A8-A15 strobe signals are controlled to be high, causing the switches of the 8th to 15th branches in the thermometer code position to be powered by the power supply voltage. Here, the 0th branch in the thermometer code position refers to... Figure 4 The branch controlled by the A0 signal, the first branch in the thermometer code refers to... Figure 4 The branch controlled by the A15 signal.

[0047] In this embodiment, the input signals from bit 0 to bit 11 can be a set of discrete 12-bit digital signals; or a set of discrete 8-bit digital signals can be used as the input signals from bit 0 to bit 7, plus a set of discrete 4-bit digital signals as the input signals from bit 8 to bit 11. That is, a single signal input source can simultaneously control the D0 to D7 gating signals of the R2R type resistor network 230 and the A0 to A15 gating signals of the thermometer code bits; alternatively, a single digital signal source can control the D0 to D7 gating signals of the resistor network 230, and another digital signal source can control the A0 to A15 gating signals of the thermometer code bits.

[0048] In this embodiment, for the resistor network 230, when the control signal connected to each branch is high, the branch switch selects the power supply voltage; when the control signal connected to each branch is low, the branch switch selects ground. When the digital-to-analog converter (DAC) is in open-loop calibration mode, the operational amplifier 210 in the DAC is in comparator mode. At this time, the output of the resistor network 230 is associated with the voltage values ​​connected to each branch. Specifically, when the DAC is in open-loop calibration mode, the control signals D0 to D7 of the resistor network 230 are forced to low, A0 to A7 are forced to low, and A8 to A15 are forced to high. At this time, the output Vout of the resistor network 230 is VDD / 2, where VDD is the power supply voltage.

[0049] In some embodiments, in the operational amplifier 210, the gate of the first MOS transistor and the gate of the second MOS transistor serve as the non-inverting input terminal and the inverting input terminal of the operational amplifier 210, respectively, and the first MOS transistor, the second MOS transistor and the drain of the sixth MOS transistor in the adjustable current mirror load are connected. The gate and drain of the third MOSFET and the gate of the fourth MOSFET are respectively connected to the drain of the first MOSFET. The drain of the fourth MOSFET and the gate of the fifth MOSFET are connected to the drain of the second MOSFET, respectively. The drain of the fifth MOSFET is connected to the gate of the seventh MOSFET and the upper plate of the Zener capacitor, respectively. The upper plate of the compensation capacitor is connected to the drain of the second MOSFET, and the lower plate of the compensation capacitor is connected to the drain of the fifth MOSFET. One end of the bias current source is connected to the gate of the eighth MOSFET, the drain of the eighth MOSFET, and the gate of the seventh MOSFET, respectively. The other end of the bias current is connected to the source of the third MOSFET, the source of the fourth MOSFET, the source of the fifth MOSFET, and the lower plate of the voltage regulator capacitor, and grounded. Among them, the first, second, sixth, seventh, and eighth MOS transistors are PMOS transistors; the third, fourth, and fifth MOS transistors are NMOS transistors; and the adjustable current mirror load is composed of the third, fourth, sixth, seventh, and eighth MOS transistors. The mode switch is off when the operational amplifier 210 is in comparator mode.

[0050] In this embodiment, the circuit structure of the operational amplifier 210 in the digital-to-analog converter is as follows: Figure 5 As shown. The first MOS transistor is... Figure 5 The MOSFET M1 and the second MOSFET are Figure 5The MOSFETs M2 and M3 are... Figure 5 The MOSFETs M3 and M4 are... Figure 5 MOSFET M4 and the fifth MOSFET are Figure 5 MOSFET M5 and the sixth MOSFET are Figure 5 The MOSFETs M6 and the seventh MOSFET are Figure 5 The MOSFETs M7 and the eighth MOSFET are Figure 5 The MOSFET M8 in the middle. Furthermore, from... Figure 5 As can be seen from the diagram, the capacitors in operational amplifier 210 include compensation capacitors and voltage regulating capacitors, wherein the compensation capacitor is... Figure 5 The capacitor Cc in the figure is the voltage regulator capacitor. Figure 5 The capacitor C1 in the middle has a bias current of Figure 5 The current in the middle, the mode switching switch is Figure 5 Switch S1 in the middle.

[0051] In this embodiment, the operational amplifier 210 includes multiple transistors and capacitors. In the operational amplifier 210, the gates of the first MOSFET and the second MOSFET serve as the non-inverting and inverting input terminals, respectively. The sources of the first and second MOSFETs are connected and connected to the drain of the sixth MOSFET in the adjustable current mirror load, forming a differential input pair.

[0052] The gate and drain of the third MOSFET are connected, forming a diode connection structure, and are connected to the drain of the first MOSFET. The gate of the fourth MOSFET is connected to the gate of the third MOSFET. The third and fourth MOSFETs form a current mirror structure, providing a load for the differential input pair.

[0053] The drain of the fourth MOSFET is connected to the drain of the second MOSFET and to the gate of the fifth MOSFET. The fifth MOSFET forms the output stage, amplifying the output signal of the differential input pair. The drain of the fifth MOSFET is connected to the gate of the seventh MOSFET and to the upper plate of the Zener capacitor.

[0054] The upper plate of the compensation capacitor is connected to the drain of the second MOSFET, and the lower plate is connected to the drain of the fifth MOSFET. The compensation capacitor is used to improve the circuit performance of operational amplifier 210. It performs frequency compensation to ensure the stability of operational amplifier 210. Specifically, it can compensate for phase delays or losses caused by passive components such as inductors or resistors by providing the required reactive power at a specific frequency, thereby optimizing the circuit's response characteristics. Adding an appropriate compensation capacitor to the circuit of operational amplifier 210 can change the amplifier's frequency response characteristics, such as widening or limiting the bandwidth, ensuring the desired gain flatness across different frequency ranges.

[0055] One end of the bias current source is connected to the gate and drain of the eighth MOSFET and the gate of the seventh MOSFET. The bias current source provides bias current to the operational amplifier 210, ensuring that each transistor operates at the appropriate operating point. The eighth MOSFET, together with the sixth and seventh MOSFETs, forms a current mirror structure, replicating the bias current to the differential input pair and the output stage.

[0056] The other end of the bias current source is connected to the sources of the third, fourth, and fifth MOSFETs, as well as the lower plate of the voltage regulator capacitor, and grounded. Through this connection, the bias current flows from the bias current source, through each transistor, and finally to the ground terminal, forming a complete current path. The voltage regulator capacitor is a capacitor used to stabilize the voltage and provide filtering; its main function is to eliminate AC ripple and noise in the DC power supply while maintaining the stability of the output voltage.

[0057] In this embodiment, the first, second, sixth, seventh, and eighth MOS transistors are PMOS transistors. The third, fourth, and fifth MOS transistors are NMOS transistors. The adjustable current mirror load is composed of the third, fourth, sixth, seventh, and eighth MOS transistors.

[0058] A PMOS transistor is a P-channel metal-oxide-semiconductor field-effect transistor. A PMOS transistor conducts when the gate voltage is lower than the source voltage by a certain value. An NMOS transistor is an N-channel metal-oxide-semiconductor field-effect transistor. An NMOS transistor conducts when the gate voltage is higher than the source voltage by a certain value. By appropriately selecting PMOS and NMOS transistors, complementary circuit structures can be constructed to achieve a full-swing output range.

[0059] An adjustable current mirror load refers to a current mirror circuit that can adjust the current magnitude. In this embodiment, the adjustable current mirror load controls the output current of the current mirror through the gate voltage of the eighth MOSFET. By adjusting the current magnitude of the bias current source, the current flowing through the differential input pair and the output stage can be changed, thereby adjusting the performance parameters of the operational amplifier 210, such as gain and bandwidth.

[0060] Operational amplifier 210 also includes a mode switching switch. The mode switching switch controls the operational amplifier 210 to switch between operational amplification mode and comparator mode. When operational amplifier 210 is in comparator mode, the mode switching switch is in the open state. At this time, the negative feedback path of operational amplifier 210 is disconnected, and operational amplifier 210 operates in an open-loop state, functioning as a comparator. When operational amplifier 210 is in operational amplification mode, the mode switching switch is in the closed state. At this time, the negative feedback path of operational amplifier 210 is connected, and operational amplifier 210 operates in a closed-loop state, functioning as an amplifier. In this embodiment, the mode switching switch of operational amplifier 210 is controlled by a control signal as follows: Figure 3 The control signal Comp_en controls the opening and closing of the mode switching switch S1 by switching between high and low levels. Specifically, when the control signal is high, the mode switching switch S1 is open, the operational amplifier 210 is in comparator mode, and the digital-to-analog converter is in open-loop calibration mode. When the control signal is low, the mode switching switch S1 is closed, the operational amplifier 210 is in operational amplification mode, and the digital-to-analog converter is in normal operation mode.

[0061] In a specific example, a mode switch is positioned between the drain of the fourth MOSFET and the gate of the fifth MOSFET. When the mode switch is open, the gate voltage of the fifth MOSFET is controlled by an external circuit, and operational amplifier 210 operates in comparator mode. When the mode switch is closed, the gate voltage of the fifth MOSFET is determined by the drain voltage of the fourth MOSFET, and operational amplifier 210 operates in operational amplification mode.

[0062] In another embodiment, operational amplifier 210 may further include a common-mode feedback circuit. The common-mode feedback circuit is used to stabilize the common-mode operating point of operational amplifier 210 and improve its common-mode rejection ratio. The common-mode feedback circuit detects the common-mode voltage at the output of operational amplifier 210 and stabilizes the common-mode voltage at a set value by adjusting the bias current or load current.

[0063] In another embodiment, the operational amplifier 210 may further include an overload protection circuit. The overload protection circuit protects the transistors inside the operational amplifier 210 from damage when excessive voltage or current occurs at the input or output terminals of the operational amplifier 210. The overload protection circuit can be implemented using structures such as current-limiting circuits or clamping circuits.

[0064] By employing the above embodiments, and by setting up capacitors, mode switching switches, bias current sources, and multiple transistors, the operational amplifier 210 in the digital-to-analog converter can operate normally while also allowing the operational amplifier 210 and even the digital-to-analog converter to switch between different operating modes, thereby achieving rapid calibration of the digital-to-analog converter. Furthermore, by employing the above embodiments, and by setting up compensation capacitors, voltage regulator circuits, and using the circuit connection methods described in the embodiments of this application, the offset voltage can be reduced to a maximum extent.

[0065] In some embodiments, the offset calibration unit 220 includes a resistor voltage divider network. The circuit structure of the resistor voltage divider network is as follows: Figure 6 As shown, the resistor divider network contains several identical branches, each including a resistor of the same value and a control switch. Here, N represents the number of bits in the control signal; the closing or opening of the control switch is controlled by the control signal.

[0066] In this embodiment, a resistor voltage divider network refers to a voltage divider circuit formed by connecting multiple resistors in series or parallel. The resistor voltage divider network includes multiple parallel branches, each branch comprising a resistor and a control switch. By controlling the switching states of different branches, the equivalent resistance of the resistor voltage divider network can be changed, thereby adjusting the output reference voltage.

[0067] In this embodiment, for any branch in the resistor divider network, when the control signal output by the control unit 240 determines that the input signal corresponding to that branch is high, the control switch of that branch is closed. At this time, the resistor of that branch is connected to the resistor divider network and participates in voltage division. When the control signal determines that the input signal corresponding to that branch is low, the control switch of that branch is open. At this time, the resistor of that branch is not connected to the resistor divider network and does not participate in voltage division.

[0068] By controlling the closure of different numbers of branches, the total resistance of the resistor divider network can be adjusted, thereby regulating the output reference voltage. Since the resistor divider network contains 32 branches, it can achieve 32 different reference voltage levels. For example, when N is 5, the resistor divider network contains 32 branches, allowing for 32 different reference voltage levels.

[0069] For example, assuming the power supply voltage VDD is 5V and the ground voltage GND is 0V, the resistor divider network contains 32 branches. Each branch includes a resistor with a resistance of R and a control switch. When all branch control switches are open, the reference voltage is at its minimum. As the control switches of the 1st, 2nd, and 3rd branches are closed sequentially, the reference voltage gradually increases. By calculating the proportional relationship of the resistors in the resistor divider network, the reference voltage value corresponding to each setting can be determined. Furthermore, if the resistance of each branch is R, then the resistance of the resistor directly connected to the ground terminal and the power supply terminal is preferably 1860R. That is, the resistance of the resistor directly connected to the ground terminal and the power supply terminal is preferably 1860 times the resistance of the resistor connected to each branch. For example, when the offset voltage to be calibrated is 10mV, the number of branches that need to be closed can be calculated based on the voltage division ratio of the resistor divider network, thereby determining the corresponding setting. Assuming the calculation result is level 24, meaning the control switches for the first 24 branches need to be closed, the reference voltage is approximately equal to the output voltage of resistor network 230 plus a 10mV offset voltage. This method allows for precise calibration at different offset voltage values.

[0070] In another embodiment, the offset calibration unit 220 may further include a decoder. The decoder's input is connected to the control unit 240, receiving the N-bit control signal output by the control unit 240. The decoder's output is connected to the control switches of each branch in the resistor divider network. The decoder converts the N-bit control signal into bit-by-bit gating signals, with each gating signal controlling the control switch of one branch. The decoding function of the decoder simplifies the control logic and facilitates the control of the resistor divider network.

[0071] In this embodiment, when the digital-to-analog converter (DAC) is in open-loop calibration mode, the operational amplifier 210 in the DAC is in comparator mode. At this time, the voltage value Vout output by the operational amplifier 210 is VDD / 2, which is half of the power supply voltage connected to each branch of the resistor network 230. The voltage value required for offset calibration of the operational amplifier 210 is 10mV. The resistance value of each branch connected to the resistor divider network of the calibration unit is R, and the resistance value of the resistor directly connected to the ground terminal and the power supply terminal is 1860R. Therefore, according to... Figure 6 By analyzing the proportional relationship of the resistor array in the offset calibration unit 220, we can obtain the correspondence between each branch in the resistor divider network shown in Table 1 and the generated reference voltage value.

[0072] Table 1

[0073] In this embodiment, to calibrate the offset voltage of operational amplifier 210, the reference voltage output by offset calibration unit 220 needs to be greater than or equal to the sum of the voltage output by resistor network 230 and the offset voltage. The sum of the voltage output by resistor network 230 and the offset voltage is Vout + Vos = 2.5V + 0.1V = 2.51V. Therefore, the offset calibration voltage needs to be greater than or equal to 2.51V. According to the correspondence in Table 1, the gear position when offset calibration is complete is A24. This means that offset calibration unit 220 needs to control the control signal of the branch corresponding to A24 to a high level to close the control switch of the branch corresponding to A24, thereby calibrating the offset voltage of operational amplifier 210.

[0074] The design of the resistor divider network in the offset calibration unit 220 needs to consider the offset voltage range. In one embodiment, the offset voltage range of the operational amplifier 210 is -20mV to 20mV. To cover this offset voltage range, the reference voltage output by the resistor divider network needs to be adjustable within a certain range. By properly designing the resistance values ​​and the number of branches in the resistor divider network, complete coverage of the offset voltage range can be achieved while ensuring sufficient adjustment accuracy.

[0075] In one specific implementation, the reference voltage adjustment range of the resistive voltage divider network is designed to cover more than twice the offset voltage range to ensure effective calibration of the offset voltage under various process deviations and temperature variations. For example, when the offset voltage range is -20mV to 20mV, the reference voltage adjustment range can be designed to be -50mV to 50mV, thereby providing sufficient calibration margin.

[0076] By using the above embodiments, the reference voltage value generated by the offset calibration unit 220 can be precisely controlled, thereby accurately and effectively calibrating the offset voltage of the operational amplifier 210 and improving the offset calibration effect.

[0077] In one embodiment, the control unit 240 is further configured to control the operational amplifier 210 to enter operational amplification mode based on a second control signal output from the control terminal. The resistor network 230 is further configured to generate a corresponding analog voltage signal based on a given digital signal when the operational amplifier 210 is in operational amplification mode.

[0078] The digital-to-analog converter has two operating states: offset calibration state and normal operating state. The offset calibration state corresponds to the comparator mode of the operational amplifier 210, and the normal operating state corresponds to the operational amplification mode of the operational amplifier 210.

[0079] In the offset calibration state, the control unit 240 outputs a first control signal to open the first switch and close the second and third switches, causing the operational amplifier 210 to enter comparator mode. At this time, the control signal of the resistor network 230 is forced to a specific value, causing the resistor network 230 to output a fixed inverted input voltage Vout, which is VDD / 2.

[0080] Offset calibration unit 220 generates a reference voltage VREF based on the control signal output by control unit 240. The reference voltage VREF is input to the non-inverting input of operational amplifier 210, and the inverting input voltage Vout is input to the inverting input of operational amplifier 210. Operational amplifier 210 compares the magnitudes of VREF and Vout and outputs the comparison result at its output terminal.

[0081] When VREF is less than or equal to Vout plus the offset voltage Vos of operational amplifier 210, the output of operational amplifier 210 is low. Upon detecting the low output, control unit 240 increases the control signal of offset calibration unit 220, causing the reference voltage VREF to increase. When VREF is greater than Vout plus Vos, the output of operational amplifier 210 flips to high. Upon detecting the output flip, control unit 240 determines that offset calibration is complete.

[0082] During offset calibration, the control signal of the offset calibration unit 220 gradually increases from low to high, and the corresponding reference voltage VREF gradually increases from low to high. Each time the control signal increases by one step, the reference voltage increases by the corresponding voltage value. This voltage step size is determined based on the design of the resistor voltage divider network in the offset calibration unit 220.

[0083] In a specific example, assume that the offset voltage Vos of operational amplifier 210 is 10mV, the supply voltage VDD is 5V, the ground voltage GND is 0V, and the inverting input voltage Vout of resistor network 230 is 2.5V. Offset calibration unit 220 contains 32 branches, each with a voltage step size of 1.25mV.

[0084] At the start of offset calibration, the control signal of offset calibration unit 220 is 0, and the reference voltage VREF is at its minimum value. At this time, VREF is less than Vout plus Vos, and operational amplifier 210 outputs a low level. Control unit 240 increases the control signal by 1, and the reference voltage VREF increases by 1.25mV. This process is repeated until the control signal increases to a certain value, at which point VREF is greater than Vout plus Vos, and the output of operational amplifier 210 flips to a high level.

[0085] The magnitude of the offset voltage Vos can be determined based on the control signal value when the operational amplifier 210 outputs a flip. The reference voltage VREF corresponding to this control signal value is approximately equal to Vout plus Vos. In subsequent normal operation, the offset calibration unit 220 maintains this control signal value unchanged and continuously outputs the corresponding reference voltage to compensate for the offset voltage of the operational amplifier 210.

[0086] After offset calibration is completed, the control unit 240 outputs a second control signal to close the first switch and open the second and third switches, causing the operational amplifier 210 to enter operational amplification mode. At this time, the resistor network 230 generates a corresponding analog voltage signal based on the input digital signal and outputs it to the inverting input of the operational amplifier 210. The offset calibration unit 220 continuously outputs a reference voltage at the time of calibration completion, which is input to the non-inverting input of the operational amplifier 210 to compensate for the offset voltage of the operational amplifier 210.

[0087] Under normal operating conditions, operational amplifier 210 forms a negative feedback amplifier circuit. The output voltage of operational amplifier 210 adjusts the voltage at the inverting input terminal, making the voltage at the inverting input terminal equal to the voltage at the non-inverting input terminal. Since the reference voltage output by offset calibration unit 220 has already compensated for the offset voltage of operational amplifier 210, operational amplifier 210 can accurately amplify the analog voltage output by resistor network 230 to the output terminal, achieving high-precision digital-to-analog conversion.

[0088] In one embodiment, see Figure 7 , Figure 7 This is a schematic flowchart of an offset calibration method disclosed in one embodiment. This method can be applied to, for example... Figure 2 or Figure 3 The digital-to-analog converter shown. (As shown in the image.) Figure 7 As shown, the method may include the following steps: 710. When the operational amplifier is in comparator mode, detect the reference voltage value output by the offset calibration unit and the inverted voltage value output by the resistor network; wherein, the output terminal of the offset calibration unit is connected to the non-inverting input terminal of the operational amplifier, and the output terminal of the resistor network is connected to the inverting input terminal of the operational amplifier.

[0089] 720. If the reference voltage value is less than or equal to the inverting voltage value, the reference voltage value is increased according to the resistance value in the offset calibration unit.

[0090] 730. If the reference voltage value is greater than the inverting voltage value, the target output signal is controlled to indicate that the offset calibration is complete.

[0091] In this embodiment, the control unit first outputs a first control signal to put the operational amplifier into comparator mode. The control unit sets a control signal for the resistor network, causing the resistor network to output a fixed inverted voltage value. The control unit sets a control signal for the offset calibration unit, causing the offset calibration unit to output an initial reference voltage value. The initial reference voltage value can be set to the minimum value of the reference voltage range. By gradually increasing the reference voltage from the minimum value, the critical point that causes the operational amplifier output to flip can be found. Alternatively, the initial reference voltage value can be set to the middle value of the reference voltage range, using a binary search method for calibration.

[0092] After obtaining the reference voltage value and the reverse voltage value, you can determine the relationship between the reference voltage value and the reverse voltage value yourself, or you can send the reference voltage value and the reverse voltage value to the computer device so that the computer device can determine the relationship between the reference voltage value and the reverse voltage value.

[0093] If the reference voltage is determined to be less than or equal to the inverting voltage, the operational amplifier compares the voltages at its non-inverting and inverting inputs. Because of the operational amplifier's offset voltage, the output will not be zero even if the voltages at both inputs are equal. When the reference voltage is less than the inverting voltage plus the offset voltage, the operational amplifier output is low.

[0094] The control unit detects the output of the operational amplifier to determine the output level. When a low output level is detected, the control unit adds a control signal to the offset calibration unit. Based on the added control signal, the offset calibration unit adjusts the number of closed branches in the resistor divider network, thereby increasing the output reference voltage value.

[0095] The increment of the reference voltage value is determined by the voltage step size of the offset calibration unit. The voltage step size equals the supply voltage divided by the total number of branches in the resistor divider network. For example, when the supply voltage is 5V and the resistor divider network contains 32 branches, the voltage step size is approximately 0.15625V divided by 32, which is approximately 4.88mV. By appropriately designing the number of branches in the resistor divider network, the required calibration accuracy can be achieved.

[0096] If the reference voltage is greater than the inverting voltage, the operational amplifier output flips to a high level when the reference voltage is greater than the inverting voltage plus the offset voltage. The control unit detects this output flip and determines that offset calibration is complete. The control unit outputs a target output signal, which can be a flag indicating that offset calibration is complete. The target output signal can be output to the external interface of the digital-to-analog converter (DAC) for use by subsequent circuits or systems. Upon receiving the target output signal, the subsequent circuits or systems can begin inputting digital signals to the DAC for normal digital-to-analog conversion. The target output signal is... Figure 3The TRIM_ok signal shown can be controlled by the detection or computer equipment to toggle, indicating that the DAC offset calibration is complete. The relationships between the target output signal, power supply voltage, control signal, analog voltage signal, and reference voltage signal are as follows: Figure 8 As shown.

[0097] By using the above embodiments, the reference voltage value and the inverting voltage value output by the offset calibration unit and the resistor network in the digital-to-analog converter are detected, and the offset calibration is determined based on their magnitude relationship. If the offset calibration is not completed, the offset calibration continues. This enables offset calibration of the operational amplifier and improves the output accuracy of the digital-to-analog converter.

[0098] In some embodiments, after performing the process of increasing the reference voltage value based on the resistance value in the offset calibration unit, the following steps may also be performed: The increased reference voltage is compared with the inverting voltage value; If the reference voltage value is still less than or equal to the reverse voltage value, repeat the step of increasing the reference voltage value according to the resistance value in the offset calibration unit until the reference voltage is greater than the reverse voltage value. If the reference voltage value is greater than the inverting voltage value, the target output signal is controlled to indicate that the offset calibration is complete.

[0099] In this embodiment, the offset calibration unit outputs an increased reference voltage, and the operational amplifier compares the increased reference voltage with the inverting voltage value. Based on the comparison result, the operational amplifier outputs a corresponding level signal at its output terminal. The control unit detects the output terminal of the operational amplifier to determine the state of the output level.

[0100] If the reference voltage value is still less than or equal to the inverting voltage value, the step of increasing the reference voltage value based on the resistance value in the offset calibration unit is repeated until the reference voltage is greater than the inverting voltage value.

[0101] In this step, the control unit repeatedly increases the control signal of the offset calibration unit, gradually increasing the reference voltage value. After each increase, the operational amplifier compares the values, and the control unit detects the comparison result. This process continues until the reference voltage value is greater than the inverting voltage value plus the offset voltage, at which point the operational amplifier output flips to a high level.

[0102] By repeating the above steps, the offset voltage can be gradually approximated, eventually finding a reference voltage value that can compensate for the offset voltage. This method has the advantages of being simple to implement and highly reliable.

[0103] If the reference voltage value is greater than the inverting voltage value, the target output signal is controlled to indicate that the offset calibration is complete.

[0104] This step is the same as the previous step. When the operational amplifier output is detected to be flipped, the control unit outputs the target output signal to indicate that the misalignment calibration is complete.

[0105] In a specific example, assume the operational amplifier's offset voltage is 8mV, the inverting voltage output of the resistor network is 2.5V, and the voltage step size of the offset calibration unit is 1.25mV. The offset calibration process is as follows: First comparison: The reference voltage is 0V, which is less than 2.508V (2.5V plus 8mV), and the operational amplifier outputs a low level. The control unit adds a control signal, increasing the reference voltage to 1.25mV.

[0106] Second comparison: The reference voltage is 1.25mV, which is less than 2.508V, so the operational amplifier outputs a low level. The control unit continues to increase the control signal, raising the reference voltage to 2.5mV.

[0107] In the embodiments of this application, such as Figure 9 The diagram shows a flowchart illustrating the calibration process for a digital-to-analog converter. Figure 9 As shown, when a digital-to-analog converter begins its self-calibration process, in the initial cycle, the output of the offset calibration unit, i.e., the reference voltage value VREF, is necessarily less than the output Vout of the resistor network plus the offset voltage Vos of the operational amplifier. When the input signal to the offset calibration unit increases in the next cycle, the formula for calculating the reference voltage value output by the offset calibration unit is: VREF=((Rr+X*1) / RR)*VDD Where Rr is the multiple of the resistance value of the resistor directly connected to the ground terminal and the power supply terminal in the voltage divider network of the offset calibration unit to the resistance value of the resistor connected to each branch; RR is the sum of the resistance values ​​of all resistors in the voltage divider network of the offset calibration unit; and X is the number of cycles that the digital-to-analog converter takes to start its own calibration process.

[0108] Using the above embodiment, each time the input signal to the offset calibration unit increases, the offset calibration unit outputs a new adjustment signal, thereby achieving precise offset calibration of the output voltage. This offset calibration method allows the reference voltage value output by the offset calibration unit to gradually approach the inverted voltage value output by the resistor network plus the offset voltage of the operational amplifier, thus achieving effective offset calibration of the DAC offset voltage.

[0109] This application also provides an electronic device, including a storage medium and a controller, wherein a computer program is stored on the storage medium, and when the computer program is executed by the controller, it implements the steps of the offset calibration method as described in the above embodiment.

[0110] This application also provides a storage medium storing a computer program, which, when executed by a processor, implements the steps of the offset calibration method as described in the above embodiments.

[0111] This application discloses a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to perform any of the offset calibration methods disclosed in this application.

[0112] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A digital-to-analog converter, characterized in that, include: An operational amplifier includes a non-inverting input terminal, an inverting input terminal, a control terminal, and an output terminal; wherein the non-inverting input terminal is connected to an offset calibration unit, the inverting input terminal is connected to a resistor network, and the control terminal is connected to a control unit; The control unit is configured to output a first control signal to control the operational amplifier to enter comparator mode, and to perform offset calibration on the operational amplifier according to the signal output from the output terminal. The offset calibration unit is used to generate a reference voltage when the operational amplifier is in comparator mode; The resistor network is used to output an inverted input voltage when the operational amplifier is in the comparator mode.

2. The digital-to-analog converter according to claim 1, characterized in that, The offset calibration unit includes a resistor divider network, which contains identical branches, each branch including a resistor of the same resistance value and a control switch; Wherein, N is the number of bits in the control signal output by the control unit, and the closing or opening of the control switch is controlled by the control signal output by the control unit.

3. The digital-to-analog converter according to claim 2, characterized in that, For any branch in the resistor divider network, when the input signal corresponding to any branch is determined to be high level according to the control signal output by the control unit, the control switch of any branch is in the closed state. When the input signal corresponding to any branch is determined to be low based on the control signal, the control switch of any branch is in the off state.

4. The digital-to-analog converter according to claim 1, characterized in that, The resistor network includes an A-bit R2R type resistor network and a 1-bit thermometer code bit; Wherein, A and B are determined according to the number of bits of the digital-to-analog converter.

5. The digital-to-analog converter according to claim 1, characterized in that, In the operational amplifier, the gate of the first MOS transistor and the gate of the second MOS transistor serve as the non-inverting input and the inverting input of the operational amplifier, respectively. The first MOS transistor, the second MOS transistor, and the drain of the sixth MOS transistor in the adjustable current mirror load are connected. The gate and drain of the third MOS transistor and the gate of the fourth MOS transistor are respectively connected to the drain of the first MOS transistor. The drain of the fourth MOS transistor and the gate of the fifth MOS transistor are respectively connected to the drain of the second MOS transistor; The drain of the fifth MOS transistor is connected to the gate of the seventh MOS transistor and the upper plate of the voltage regulator capacitor, respectively. The upper plate of the compensation capacitor is connected to the drain of the second MOS transistor, and the lower plate of the compensation capacitor is connected to the drain of the fifth MOS transistor. One end of the bias current source is connected to the gate of the eighth MOS transistor, the drain of the eighth MOS transistor, and the gate of the seventh MOS transistor, respectively. The other end of the bias current is connected to the source of the third MOSFET, the source of the fourth MOSFET, the source of the fifth MOSFET, and the lower plate of the voltage regulator capacitor, and grounded. Wherein, the first MOS transistor, the second MOS transistor, the sixth MOS transistor, the seventh MOS transistor, and the eighth MOS transistor are PMOS transistors; the third MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are NMOS transistors; the adjustable current mirror load is composed of the third MOS transistor, the fourth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, and the eighth MOS transistor; The mode switching switch is in the off state when the operational amplifier is in comparator mode.

6. The digital-to-analog converter according to claim 1, characterized in that, The digital-to-analog converter also includes a first switch, a feedback resistor, a second switch, a load resistor, a load capacitor, and a third switch; One end of the first switch is connected to the feedback resistor, and the other end of the feedback resistor is connected to one end of the second switch and one end of the third switch, respectively. The first end of the first switch is connected to the inverting input terminal of the operational amplifier. The other end of the second switch is connected to one end of the load resistor and one end of the load capacitor, and the other end of the load resistor and the load capacitor is grounded. The other end of the third switch is connected to the output of the digital-to-analog converter. When the operational amplifier is in comparator mode, the first switch is in the open state, the second switch is in the closed state, and the third switch is in the closed state. When the operational amplifier is in operational amplification mode, the first switch is closed, the second switch is open, and the third switch is open.

7. The digital-to-analog converter according to any one of claims 1-6, characterized in that, The control unit is also used to control the operational amplifier to enter operational amplification mode based on the second control signal output by the control terminal; The resistor network is also used to generate a corresponding analog voltage signal based on a given digital signal when the operational amplifier is in the operational amplification mode.

8. An offset calibration method, characterized in that, The method includes: When the operational amplifier is in comparator mode, the reference voltage value output by the offset calibration unit and the inverted voltage value output by the resistor network are detected; wherein, the output terminal of the offset calibration unit is connected to the non-inverting input terminal of the operational amplifier, and the output terminal of the resistor network is connected to the inverting input terminal of the operational amplifier. If the reference voltage value is less than or equal to the inverting voltage value, then the reference voltage value is increased according to the resistance value in the offset calibration unit; If the reference voltage value is greater than the inverting voltage value, the target output signal is controlled to indicate that the offset calibration is complete.

9. The offset calibration method according to claim 8, characterized in that, After increasing the reference voltage value based on the resistance value in the offset calibration unit, the method further includes: The increased reference voltage is compared with the inverted voltage value; If the reference voltage value is still less than or equal to the inverting voltage value, the step of increasing the reference voltage value according to the resistance value in the offset calibration unit is repeated until the reference voltage is greater than the inverting voltage value. If the reference voltage value is greater than the inverting voltage value, the target output signal is controlled to indicate that the offset calibration is complete.

10. An electronic device, characterized in that, include: A processor and a memory storing a computer program, wherein, when the processor runs the computer program, the steps of the offset calibration method as described in claim 8 or 9 are implemented.

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