Semiconductor structure, preparation method thereof and electronic equipment

Abstract

The invention relates to a semiconductor structure, a preparation method thereof and electronic equipment. The semiconductor structure includes: an oxide semiconductor layer; the source / drain electrode is arranged around the oxide semiconductor layer; and the induction layer is positioned between the source / drain electrode and the oxide semiconductor layer and is used for inducing the oxide semiconductor layer to be converted into a crystalline structure from an amorphous structure. The thermal stability and reliability of the oxide transistor can be effectively improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure, its fabrication method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of semiconductor devices are shrinking, and the types and number of semiconductor devices contained in a single chip are increasing, making it possible for even the slightest differences in the manufacturing process to affect the performance of semiconductor devices.

[0003] To minimize product costs, the goal is to fabricate as many semiconductor devices as possible on a substrate with limited area. Since the advent of Moore's Law, the industry has proposed various structural designs and process optimizations for semiconductor devices to meet current product demands. Summary of the Invention

[0004] Based on this, the present disclosure provides a semiconductor structure and its fabrication method, as well as an electronic device, which can effectively improve the thermal stability and reliability of oxide transistors.

[0005] According to some embodiments, this disclosure provides a semiconductor structure, including: an oxide semiconductor layer;

[0006] Source / drain electrodes are disposed around the oxide semiconductor layer;

[0007] An induction layer, located between the source / drain electrode and the oxide semiconductor layer, is used to induce the oxide semiconductor layer to transform from an amorphous structure to a crystalline structure.

[0008] According to some embodiments, the source / drain includes a first source / drain and a second source / drain spaced apart in a vertical direction; the semiconductor structure further includes: a first insulating layer, a second insulating layer, and a third insulating layer stacked in a vertical direction; wherein, the first source / drain is located between the first insulating layer and the second insulating layer, and the second source / drain is located between the second insulating layer and the third insulating layer; a receiving hole is provided in the third insulating layer, the second source / drain, the second insulating layer, and the first source / drain, and a receiving groove is also provided in the second source / drain and the first source / drain, surrounding and communicating with the receiving hole; an induction layer is filled in the receiving groove; an oxide semiconductor layer at least covers the inner wall of the receiving hole and the induction layer is exposed on the sidewall of the receiving hole.

[0009] According to some embodiments, the semiconductor structure further includes: a gate dielectric layer covering the oxide semiconductor layer, and a gate covering the gate dielectric layer and filling the accommodating via.

[0010] According to some embodiments, the crystal axis of the oxide semiconductor layer with a crystalline structure is an upright c-axis (or an upright Z-axis).

[0011] According to some embodiments, the inducing layer comprises a tantalum metal layer.

[0012] According to some embodiments, this disclosure also provides a method for fabricating a semiconductor structure, comprising the following steps:

[0013] An amorphous oxide semiconductor layer is formed, a source / drain electrode surrounds the oxide semiconductor layer, and an induction layer is located between the source / drain electrode and the oxide semiconductor layer;

[0014] An annealing process is performed on the obtained structure to induce the oxide semiconductor layer to transform from an amorphous structure to a crystalline structure.

[0015] According to some embodiments, the source / drain includes a first source / drain and a second source / drain spaced apart in a vertical direction; an oxide semiconductor layer forming an amorphous structure, a source / drain surrounding the oxide semiconductor layer, and an induction layer located between the source / drain and the oxide semiconductor layer, comprising:

[0016] The first insulating layer, the first source / drain electrode, the second insulating layer, the second source / drain electrode, and the third insulating layer are sequentially stacked along the vertical direction;

[0017] An accommodating via is formed in the third insulating layer, the second source / drain, the second insulating layer, and the first source / drain;

[0018] Based on the transverse etching of the second source / drain and the first source / drain based on the accommodating hole, accommodating grooves that surround and connect to the accommodating hole are formed in the second source / drain and the first source / drain, respectively.

[0019] Fill the receiving groove with an induction layer;

[0020] An oxide semiconductor layer is formed within the accommodating hole, at least covering the inner wall of the accommodating hole and the induction layer is exposed on the sidewall within the accommodating hole.

[0021] According to some embodiments, the method for fabricating a semiconductor structure further includes:

[0022] Forming a gate dielectric layer covering the oxide semiconductor layer;

[0023] A gate is formed by covering the gate dielectric layer and filling the accommodating via.

[0024] According to some embodiments, the annealing process includes in-situ annealing or non-in-situ annealing.

[0025] The annealing temperature range for the annealing process includes: 300℃~700℃;

[0026] The annealing time range for the annealing process includes 1 min to 120 min;

[0027] The annealing atmosphere in the annealing process includes a gaseous atmosphere formed by oxygen or an oxygen-containing mixture.

[0028] According to some embodiments, this disclosure provides another aspect of an electronic device, including a semiconductor structure as described in the foregoing embodiments, or a semiconductor structure fabricated according to the method for fabricating the semiconductor structure described in the foregoing embodiments.

[0029] The embodiments disclosed herein may have, or at least have, the following advantages:

[0030] In this embodiment, the inducing layer is located between the source / drain and the oxide semiconductor layer, and is used to induce the oxide semiconductor layer to transform from an amorphous structure to a crystalline structure. That is, through the inducing effect of the inducing layer, the oxide semiconductor layer becomes a crystalline oxide semiconductor. Thus, because the crystalline oxide semiconductor has good thermal stability, fewer defect states, and reduced contact resistance with the source / drain, the semiconductor structure of this embodiment can effectively improve the thermal stability and reliability of the subsequently formed oxide transistor. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a cross-sectional view of a semiconductor structure provided in one embodiment of the present disclosure;

[0033] Figure 2 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0034] Figure 3 This is a schematic flowchart of step S100 in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0035] Figure 4 This is a schematic flowchart of a method for fabricating another semiconductor structure provided in one embodiment of the present disclosure;

[0036] Figure 5 This is a schematic cross-sectional view of the structure obtained in step S101 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0037] Figure 6 This is a schematic cross-sectional view of the structure obtained in step S102 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0038] Figure 7 This is a schematic cross-sectional view of the structure obtained in step S103 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0039] Figure 8 This is a schematic cross-sectional view of the structure obtained after forming an inducing material layer in a method for preparing a semiconductor structure according to an embodiment of the present disclosure.

[0040] Figure 9 This is a schematic cross-sectional view of the structure obtained in step S104 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0041] Figure 10 This is a schematic cross-sectional view of the structure obtained in step S105 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0042] Figure 11 This is a schematic cross-sectional view of the structure obtained in step S200 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0043] Figure 12 This is a schematic cross-sectional view of the structure obtained in step S300 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0044] Figure 13 This is a schematic cross-sectional view of the structure obtained in step S400 of a semiconductor structure fabrication method provided in an embodiment of the present disclosure.

[0045] Figure 14 This is a schematic cross-sectional view of the structure obtained after forming stacked transistors in a method for fabricating a semiconductor structure according to an embodiment of this disclosure.

[0046] Explanation of reference numerals in the attached figures:

[0047] 1. Oxide semiconductor layer; 2. Source / drain, 21. First source / drain, 22. Second source / drain; 3. Inducing layer, 30. Inducing material layer; 41. First insulating layer, 42. Second insulating layer, 43. Third insulating layer; 51. Gate dielectric layer, 52. Gate; K1. Receiving via; C1. Receiving trench. Detailed Implementation

[0048] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0050] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., can be used here to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0051] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. When using “comprising,” “having,” and “including” as described herein, another component may be added unless explicitly qualified terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0052] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0053] In the description of this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; or they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure based on the specific circumstances.

[0054] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0055] When used here, "deposition" processes include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0056] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the present disclosure.

[0057] Amorphous oxide transistors are becoming increasingly important in emerging fields due to their low leakage current and simple low-temperature fabrication process. For example, they have great application prospects in display panel driving, flexible displays, IoT word lines, wearable electronics, and memory.

[0058] Vertical-channel amorphous oxide transistors (VCDs) are considered to have a smaller footprint and are easier to integrate in three dimensions, thus holding great potential for application in high-density chips. Currently, the biggest challenges for VCDs lie in their poor thermal stability and reliability.

[0059] Based on this, the present disclosure provides a semiconductor structure and its fabrication method, which can effectively improve the thermal stability and reliability of oxide transistors.

[0060] Please see Figure 1 This disclosure provides a semiconductor structure in some embodiments, including: an oxide semiconductor layer 1, a source / drain electrode 2, and an inducing layer 3. The source / drain electrode 2 is disposed around the oxide semiconductor layer 1. The inducing layer 3 is located between the source / drain electrode 2 and the oxide semiconductor layer 1, and is used to induce the oxide semiconductor layer 1 to transform from an amorphous structure to a crystalline structure.

[0061] In this embodiment, the inducing layer 3 is located between the source / drain electrode 2 and the oxide semiconductor layer 1, and is used to induce the oxide semiconductor layer 1 to transform from an amorphous structure to a crystalline structure. That is, through the inducing effect of the inducing layer 3, the oxide semiconductor layer 1 becomes a crystalline oxide semiconductor. Thus, because the crystalline oxide semiconductor has good thermal stability, fewer defect states, and reduced contact resistance with the source / drain electrode 2, the semiconductor structure of this embodiment can effectively improve the thermal stability and reliability of the subsequently formed oxide transistor.

[0062] In some examples, the material of oxide semiconductor layer 1 includes, but is not limited to, one or a combination of common oxide semiconductor materials such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), or indium tungsten oxide (In2O3:WO3, IWO).

[0063] In some examples, the source / drain 2 materials include, but are not limited to, one or a combination of conductive materials such as indium zinc oxide (IZO), indium tin oxide (ITO), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), titanium aluminum nitride (TiAl), or tantalum nitride (TaN).

[0064] In some examples, the inducing layer 3 includes a tantalum (Ta) metal layer.

[0065] In some embodiments, please continue reading Figure 1 The source / drain 2 includes a first source / drain 21 and a second source / drain 22 spaced apart in a vertical direction (e.g., the Y direction). The semiconductor structure also includes a first insulating layer 41, a second insulating layer 42, and a third insulating layer 43 stacked in a vertical direction (e.g., the Y direction). The first source / drain 21 is located between the first insulating layer 41 and the second insulating layer 42, and the second source / drain 22 is located between the second insulating layer 42 and the third insulating layer 43. Receiving holes are provided in the third insulating layer 43, the second source / drain 22, the second insulating layer 42, and the first source / drain 21. Receiving grooves surrounding and communicating with the receiving holes are also provided in the second source / drain 22 and the first source / drain 21. An inducing layer 3 fills the receiving groove. The oxide semiconductor layer 1 at least covers the inner wall of the receiving hole and the inducing layer 3 is exposed on the sidewall of the receiving hole.

[0066] In some examples, the thickness of the inducing layer 3 (i.e., the scale in the direction away from the inner wall of the accommodating aperture) does not exceed 5 nm. For example, the thickness of the inducing layer 3 can be 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm, etc.

[0067] In some examples, the materials of the first source / drain 21 and the second source / drain 22 can be the same or different. In order to reduce the influence of source-drain parasitic resistance, the materials of the first source / drain 21 and the second source / drain 22 can both be metal materials with low resistivity, such as tungsten (W), molybdenum (Mo) or ruthenium (Ru).

[0068] In some examples, the materials of the first insulating layer 41, the second insulating layer 42, and the third insulating layer 43 can be the same or different. In order to reduce the influence of parasitic capacitance, the materials of the first insulating layer 41, the second insulating layer 42, and the third insulating layer 43 can all be insulating materials with low dielectric constants, such as silicon dioxide (SiO2) or silicon nitride (SiN).

[0069] Furthermore, for example, the dimensions of the second insulating layer 42 in the vertical direction (e.g., the Y direction) determine the length of the subsequently formed crystallized oxide semiconductor channel.

[0070] In some embodiments, please continue reading Figure 1 The oxide semiconductor layer 1 also covers the surface of the third insulating layer 43 that is away from the second source / drain electrode 22.

[0071] In some embodiments, please continue reading Figure 1 The semiconductor structure also includes: a gate dielectric layer 51 covering the oxide semiconductor layer 1, and a gate 52 covering the gate dielectric layer 51 and filling the accommodating hole.

[0072] In some examples, the material of the gate dielectric layer 51 includes, but is not limited to, one or a combination of high dielectric constant materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), alumina-hafnium oxide (HfAlO), and lanthanum hafnium oxide (HfLaO). That is, in some examples, the gate dielectric layer 51 can be a single-layer structure containing one gate dielectric material, such as aluminum oxide (Al2O3), or it can be a multilayer structure containing multiple gate dielectric materials, such as hafnium oxide (HfO2) and aluminum oxide (Al2O3). This application does not impose any limitations on this.

[0073] In some examples, the material of gate 52 includes, but is not limited to, one or a combination of conductive materials such as indium zinc oxide (IZO), indium tin oxide (ITO), tungsten (W), titanium nitride (TiN), titanium aluminum nitride (TiAl), or tantalum nitride (TaN).

[0074] In some embodiments, the crystal axis of the oxide semiconductor layer 1 with a crystalline structure is an upright c-axis (or an upright Z-axis).

[0075] Please see Figure 2 In another aspect, some embodiments of this disclosure provide a method for preparing a semiconductor structure, including steps S100 to S200.

[0076] S100, forming an amorphous oxide semiconductor layer, a source / drain surrounding the oxide semiconductor layer, and an induction layer located between the source / drain and the oxide semiconductor layer.

[0077] S200, an annealing process is performed on the obtained structure to induce the oxide semiconductor layer to change from an amorphous structure to a crystalline structure.

[0078] In this embodiment, the inducing layer 3 is located between the source / drain electrode 2 and the oxide semiconductor layer 1. By performing an annealing process on the oxide semiconductor layer 1, the inducing layer induces the oxide semiconductor layer to transform from an amorphous structure to a crystalline structure. That is, through the inducing effect of the inducing layer 3, the oxide semiconductor layer 1 becomes a crystalline oxide semiconductor. Thus, because the crystalline oxide semiconductor has good thermal stability, fewer defect states, and reduced contact resistance with the source / drain electrode, the semiconductor structure of this embodiment can effectively improve the thermal stability and reliability of the subsequently formed oxide transistor.

[0079] In some embodiments, the annealing process includes in-situ annealing or off-situ annealing.

[0080] The annealing temperature range for the annealing process includes 300℃ to 700℃. For example, the annealing temperature can be 300℃, 400℃, 500℃, 600℃, or 700℃, etc.

[0081] The annealing time range for the annealing process includes 1 min to 120 min. For example, the annealing time for the annealing process can be 1 min, 10 min, 20 min, 30 min, 40 min, 50 min, 60 min, 70 min, 80 min, 90 min, 100 min, 110 min, or 120 min.

[0082] The annealing atmosphere in the annealing process includes a gaseous atmosphere formed by oxygen or an oxygen-containing mixture.

[0083] In some embodiments, the source / drain includes a first source / drain and a second source / drain spaced apart in a vertical direction. See also... Figure 3Step S100 forms an amorphous oxide semiconductor layer 1, a source / drain electrode 2 surrounding the oxide semiconductor layer, and an induction layer 3 located between the source / drain electrode and the oxide semiconductor layer, including steps S101 to S105.

[0084] S101, a first insulating layer, a first source / drain electrode, a second insulating layer, a second source / drain electrode, and a third insulating layer are sequentially stacked in the vertical direction.

[0085] S102, forming a receiving hole in the third insulating layer, the second source / drain, the second insulating layer and the first source / drain.

[0086] S103, based on the accommodating hole, the second source / drain and the first source / drain are etched laterally to form accommodating grooves that surround and connect to the accommodating hole in the second source / drain and the first source / drain, respectively.

[0087] S104, fill the receiving groove with an induction layer.

[0088] S105, an oxide semiconductor layer is formed in the accommodating hole that at least covers the inner wall of the accommodating hole and the induction layer is exposed on the side wall of the accommodating hole.

[0089] It should be noted that in the above embodiments, the execution order of the steps in the method is not strictly limited. These steps may not necessarily be executed in the described order, and may be executed in other ways. Moreover, at least a portion of any step may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps. The method is limited to enabling the fabrication of the corresponding memory.

[0090] Based on this, and in view of the semiconductor structure fabrication methods provided in the above embodiments, the present disclosure illustrates some methods in the following embodiments as some possible implementations of the above fabrication methods.

[0091] In some embodiments, please refer to Figure 4 The method for preparing the semiconductor structure also includes steps S300 to S400.

[0092] S300, forming a gate dielectric layer covering the oxide semiconductor layer.

[0093] S400, forming a gate covering the gate dielectric layer and filling the accommodating via.

[0094] To more clearly illustrate the semiconductor structure fabrication method provided in the above embodiments, the following is combined with... Figures 5-13The preparation method is described in detail.

[0095] In step S101, please refer to Figure 5 The first insulating layer 41, the first source / drain 21, the second insulating layer 42, the second source / drain 22 and the third insulating layer 43 are sequentially stacked along the vertical direction (e.g., the Y direction).

[0096] In some examples, a first insulating layer 41, a first source / drain 21, a second insulating layer 42, a second source / drain 22 and a third insulating layer 43 may be sequentially stacked on a substrate along a vertical direction (e.g., the Y direction).

[0097] For example, the substrate can be made of semiconductor material, insulating material, conductive material, or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be such as a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate can be a layered substrate comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0098] In some examples, the materials of the first source / drain 21 and the second source / drain 22 include, but are not limited to, one or a combination of conductive materials such as indium zinc oxide (IZO), indium tin oxide (ITO), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), titanium aluminum nitride (TiAl), or tantalum nitride (TaN).

[0099] In some examples, the materials of the first source / drain 21 and the second source / drain 22 can be the same or different. In order to reduce the influence of source-drain parasitic resistance, the materials of the first source / drain 21 and the second source / drain 22 can both be metal materials with low resistivity, such as tungsten (W), molybdenum (Mo) or ruthenium (Ru).

[0100] In some examples, the materials of the first insulating layer 41, the second insulating layer 42, and the third insulating layer 43 can be the same or different. In order to reduce the influence of parasitic capacitance, the materials of the first insulating layer 41, the second insulating layer 42, and the third insulating layer 43 can all be insulating materials with low dielectric constants, such as silicon dioxide (SiO2) or silicon nitride (SiN).

[0101] Furthermore, for example, the dimensions of the second insulating layer 42 in the vertical direction (e.g., the Y direction) determine the length of the subsequently formed crystallized oxide semiconductor channel.

[0102] In some examples, processes such as Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD) can be used to sequentially stack the first insulating layer 41, the first source / drain 21, the second insulating layer 42, the second source / drain 22, and the third insulating layer 43 along the vertical direction (e.g., the Y direction).

[0103] In step S102, please refer to Figure 6 An accommodating hole K1 is formed in the third insulating layer 43, the second source / drain 22, the second insulating layer 42, and the first source / drain 21.

[0104] In some examples, photolithography and etching processes can be used to form accommodating holes K1 in the third insulating layer 43, the second source / drain 22, the second insulating layer 42, and the first source / drain 21.

[0105] In some examples, the accommodating aperture K1 passes through the third insulating layer 43, the second source / drain 22, the second insulating layer 42, and part of the first source / drain 21, exposing the surface of the first source / drain 21 facing away from the first insulating layer 41.

[0106] In step S103, please refer to Figure 7 Based on the accommodating hole K1, the second source / drain 22 and the first source / drain 21 are etched laterally, and accommodating grooves C1 are formed in the second source / drain 22 and the first source / drain 21 respectively, surrounding the accommodating hole K1 and communicating with the accommodating hole K1.

[0107] In some examples, a high selectivity etching process can be used to laterally etch the second source / drain 22 and the first source / drain 21, ensuring precise and uniform lateral etching of both, with the etching depth controlled within 5nm. For example, the etching depth can be 1nm, 2nm, 3nm, 4nm, or 5nm, etc.

[0108] For example, the second source / drain 22 and the first source / drain 21 can be laterally etched using a high-selectivity wet etching process, a dry etching process, or an atomic layer etching (ALE) process.

[0109] In step S104, please refer to Figure 8 and Figure 9 Induction layer 3 is filled into the receiving groove C1.

[0110] In some examples, filling the receiving groove C1 with the induction layer 3 includes:

[0111] Please see Figure 8 This forms a layer of guiding material 30 that fills the receiving groove C1 and covers the inner wall and bottom surface of the receiving hole K1.

[0112] In some examples, an atomic layer deposition (ALD) process can be used to deposit the induced material layer 30.

[0113] In some examples, the thickness of the inducing material layer 30 ranges from 1 nm to 5 nm. For example, the thickness of the inducing material layer 30 can be 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm, etc.

[0114] Please see Figure 9 Remove the guiding material layer 30 from the inner wall and bottom surface of the receiving hole K1 so that the guiding material layer 30 retained in the receiving groove C1 forms the guiding layer 3.

[0115] In some examples, the material of the inducing layer 3 includes tantalum (Ta). Tantalum (Ta) can induce the amorphous oxide semiconductor layer to become a crystalline oxide semiconductor layer with a crystallization axis of the upright c-axis (or upright Z-axis) during subsequent annealing.

[0116] In some examples, anisotropic etching processes can be used to remove the induction material layer 30 on the inner wall and bottom surface of the accommodating hole K1, so that the induction material layer 30 retained in the accommodating groove C1 forms the induction layer 3.

[0117] In step S105, please refer to Figure 10 An oxide semiconductor layer 1 is formed within the accommodating hole K1, at least covering the inner wall of the accommodating hole K1 and the sidewall of the inducing layer 3 exposed within the accommodating hole K1. Here, the oxide semiconductor layer 1 is an amorphous oxide semiconductor layer.

[0118] In some examples, an oxide semiconductor layer 1 can be formed within the accommodating hole K1 using an atomic layer deposition (ALD) process, which at least covers the inner wall of the accommodating hole K1 and exposes the sidewall of the inducing layer 3 within the accommodating hole K1.

[0119] In some examples, the material of oxide semiconductor layer 1 includes, but is not limited to, one or a combination of common oxide semiconductor materials such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), or indium tungsten oxide (In2O3:WO3, IWO).

[0120] In step S200, please refer to Figure 11An annealing process is performed on the obtained structure to induce the oxide semiconductor layer 1 to change from an amorphous structure to a crystalline structure by the inducing layer 3.

[0121] In some embodiments, the annealing process includes in-situ annealing or off-situ annealing.

[0122] The annealing temperature range for the annealing process includes 300℃ to 700℃. For example, the annealing temperature can be 300℃, 400℃, 500℃, 600℃, or 700℃, etc.

[0123] The annealing time range for the annealing process includes 1 min to 120 min. For example, the annealing time for the annealing process can be 1 min, 10 min, 20 min, 30 min, 40 min, 50 min, 60 min, 70 min, 80 min, 90 min, 100 min, 110 min, or 120 min.

[0124] The annealing atmosphere in the annealing process includes a gaseous atmosphere formed by oxygen or an oxygen-containing mixture.

[0125] In step S300, please refer to Figure 12 A gate dielectric layer 51 is formed covering the oxide semiconductor layer 1.

[0126] In some examples, the material of the gate dielectric layer 51 includes, but is not limited to, one or a combination of high dielectric constant materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), alumina-hafnium oxide (HfAlO), and lanthanum hafnium oxide (HfLaO). That is, in some examples, the gate dielectric layer 51 can be a single-layer structure containing one gate dielectric material, such as aluminum oxide (Al2O3), or it can be a multilayer structure containing multiple gate dielectric materials, such as hafnium oxide (HfO2) and aluminum oxide (Al2O3). This application does not impose any limitations on this.

[0127] In some examples, an atomic layer deposition (ALD) process can be used to form the gate dielectric layer 51 covering the oxide semiconductor layer 1.

[0128] In step S400, please refer to Figure 13 A gate 52 is formed by covering the gate dielectric layer 51 and filling the accommodating hole K1.

[0129] In some examples, the material of gate 52 includes, but is not limited to, one or a combination of conductive materials such as indium zinc oxide (IZO), indium tin oxide (ITO), tungsten (W), titanium nitride (TiN), titanium aluminum nitride (TiAl), or tantalum nitride (TaN).

[0130] In some examples, an atomic layer deposition (ALD) process can be used to form the gate 52 that covers the gate dielectric layer 51 and fills the accommodating via K1.

[0131] In some embodiments, please continue reading Figure 1 Photolithography and etching processes are performed on the gate 52, the gate dielectric layer 51, and the oxide semiconductor layer 1.

[0132] In some embodiments, please refer to Figure 14 The semiconductor structure fabrication method described in the foregoing embodiments is repeated to stack transistor T2 on top of transistor T1. However, this application is not limited to this; capacitors or other effective devices can also be formed in a layer away from the substrate of transistor T1 to form a memory cell or other effective semiconductor device, forming a multilayer device stack structure. This application does not limit this.

[0133] Some embodiments of this disclosure also provide an electronic device, including the semiconductor structure described in any of the foregoing embodiments, or a semiconductor structure formed according to the fabrication method of the semiconductor structure described in any of the foregoing embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0134] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0135] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0136] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0137] The above embodiments are merely illustrative of several implementation methods of this disclosure, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the disclosed patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Oxide semiconductor layer; Source / drain electrodes are disposed around the oxide semiconductor layer; An induction layer, located between the source / drain electrode and the oxide semiconductor layer, is used to induce the oxide semiconductor layer to transform from an amorphous structure to a crystalline structure.

2. The semiconductor structure according to claim 1, characterized in that, The source / drain includes a first source / drain and a second source / drain that are spaced apart in the vertical direction; The semiconductor structure further includes: a first insulating layer, a second insulating layer, and a third insulating layer stacked in the vertical direction; wherein... The first source / drain is located between the first insulating layer and the second insulating layer, and the second source / drain is located between the second insulating layer and the third insulating layer; The third insulating layer, the second source / drain, the second insulating layer and the first source / drain are provided with receiving holes, and the second source / drain and the first source / drain are also provided with receiving grooves surrounding and communicating with the receiving holes; The induction layer fills the receiving groove; The oxide semiconductor layer at least covers the inner wall of the accommodating hole, and the induction layer is exposed on the sidewall inside the accommodating hole.

3. The semiconductor structure according to claim 2, characterized in that, Also includes: A gate dielectric layer covering the oxide semiconductor layer, and a gate covering the gate dielectric layer and filling the accommodating via.

4. The semiconductor structure according to claim 1, characterized in that, The crystal axis of the oxide semiconductor layer in the crystalline structure is an upright c-axis (or an upright Z-axis).

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that, The induction layer includes a tantalum metal layer.

6. A method for fabricating a semiconductor structure, characterized in that, include: An amorphous oxide semiconductor layer is formed, a source / drain electrode surrounds the oxide semiconductor layer, and an induction layer is located between the source / drain electrode and the oxide semiconductor layer; An annealing process is performed on the obtained structure to induce the oxide semiconductor layer to transform from the amorphous structure to the crystalline structure.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The source / drain includes a first source / drain and a second source / drain spaced apart in a vertical direction; the oxide semiconductor layer forming an amorphous structure, the source / drain surrounding the oxide semiconductor layer, and the inducing layer located between the source / drain and the oxide semiconductor layer include: The first insulating layer, the first source / drain electrode, the second insulating layer, the second source / drain electrode, and the third insulating layer are sequentially stacked along the vertical direction; An accommodating via is formed in the third insulating layer, the second source / drain, the second insulating layer, and the first source / drain; Based on the accommodating hole, the second source / drain and the first source / drain are etched laterally to form accommodating grooves that surround and communicate with the accommodating hole in the second source / drain and the first source / drain, respectively; The induction layer is filled into the receiving groove; An oxide semiconductor layer is formed within the accommodating hole, at least covering the inner wall of the accommodating hole and the sidewall of the induction layer exposed within the accommodating hole.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, Also includes: A gate dielectric layer is formed covering the oxide semiconductor layer; A gate is formed that covers the gate dielectric layer and fills the accommodating via.

9. The method for preparing a semiconductor structure according to any one of claims 6 to 8, characterized in that, The annealing process includes in-situ annealing or non-in-situ annealing. The annealing temperature range of the annealing process includes: 300℃~700℃; The annealing time range of the annealing process includes: 1 min to 120 min; The annealing atmosphere of the annealing process includes a gaseous atmosphere formed by oxygen or an oxygen-containing mixture.

10. An electronic device, characterized in that, include: The semiconductor structure as described in any one of claims 1 to 5, or the semiconductor structure prepared by the method of preparing the semiconductor structure according to any one of claims 6 to 9.

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