A wafer-level chip packaging method, a wafer-level chip packaging intermediate, a wafer-level chip packaging unit, and a wafer-level chip packaging structure having the above are disclosed.
By applying and curing molding compound around the wafer perimeter and within the dicing channels, the problems of high molding compound consumption and long grinding time in traditional wafer-level packaging are solved, resulting in cost reduction and efficiency improvement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING HUAFENG INTEGRATED ELECTRONICS CO LTD
- Filing Date
- 2025-12-30
- Publication Date
- 2026-05-26
AI Technical Summary
Traditional wafer-level packaging processes consume large amounts of molding compound and require long grinding times, resulting in high production costs and low efficiency.
The molding compound is applied only to the periphery and dicing channels of the wafer. It is applied precisely through a dispensing process and cured within the dicing channels to form a molding layer. The molding compound on the back surface of the chip is then removed by grinding.
It reduced the amount of molding compound used, lowered production costs, shortened grinding time, and improved production efficiency.
Smart Images
Figure CN122094546A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor packaging technology, specifically to a wafer-level chip packaging method, a wafer-level chip packaging intermediate, a wafer-level chip packaging unit, and a wafer-level chip packaging structure having the same. Background Technology
[0002] In the semiconductor packaging field, wafer-level packaging (WLP) offers advantages such as miniaturization, high performance, and low cost. Traditional wafer-level molding compounding typically involves applying molding compound to the entire active surface of the wafer using a monolithic molding process, completely covering all areas where the chip is located and those not. The molded compound on the back surface of the chip is then removed through a polishing process (for efficient heat dissipation or subsequent integration) until the back surface is fully exposed before dicing to obtain individual chip package units. However, this approach suffers from high molding compound consumption and time-consuming subsequent polishing, increasing production costs (purchase costs of molding compound and polishing consumables) and reducing overall production efficiency. Summary of the Invention
[0003] This application aims to address one of the technical problems in related technologies to a certain extent. To this end, this application provides a wafer-level chip packaging method, a wafer-level chip packaging intermediate, a wafer-level chip packaging unit, and a wafer-level chip packaging structure having the same.
[0004] To achieve the above objectives, this application adopts the following technical solution: a wafer-level chip packaging method, comprising:
[0005] A wafer is provided, wherein a plurality of chips are integrated on the active surface of the wafer at intervals, and cleaving channels are formed on the active surface of the wafer around the chips;
[0006] The molding compound is applied to the peripheral edge of the wafer and the dicing groove;
[0007] The molding compound is cured to obtain an intermediate product;
[0008] The intermediate product is ground to fully expose the surface of the chip on the wafer;
[0009] The intermediate product after grinding is cut to obtain individual chip packaging units.
[0010] The application of this application has the following advantages: By limiting the application area of the molding compound to the periphery of the wafer and within the dicing grooves, the amount of molding compound used can be saved, thereby reducing costs. Simultaneously, since the molding compound is applied to the dicing grooves and does not cover the entire surface of the chip after curing, only a portion of the chip is covered by the cured molding compound, which significantly reduces polishing time, thereby reducing the use of polishing consumables and improving production efficiency.
[0011] Optionally, applying the molding compound to the periphery of the wafer and the dicing track includes: applying the molding compound to the periphery of the wafer and the dicing track using a dispensing method with a glue applicator. Applying the molding compound to the dicing track using a dispensing process with a glue applicator is a mature process with high control precision, accurately applying the molding compound to narrow dicing tracks, reducing unnecessary diffusion of the molding compound, and ensuring the reliability and repeatability of this step.
[0012] Optionally, applying the molding compound to the peripheral edge and dicing grooves of the wafer includes: the molding compound applied to the dicing grooves is configured such that the surface height of the cured molding compound is higher than the surface height of the back surface of the chip. This provides a safe process margin for subsequent polishing operations, avoiding damage to the chip during polishing of the cured molding compound.
[0013] Optionally, the curing process of the molding compound to obtain an intermediate product includes: after the molding compound applied to the dicing channel is cured, a molding layer is formed in a portion of the back surface of the chip.
[0014] Optionally, the area on the back surface of the chip where the molding compound is formed accounts for no more than 50% of the area of the back surface of the chip. During the application and curing of the molding compound, a small amount of molding compound will flow to the surface of the chip and cover the surface of the chip after curing. Allowing the molding compound to cover the chip surface helps to reduce the process requirements for molding compound application, which is conducive to the promotion of this solution. At the same time, it can also achieve the effects of saving molding compound and reducing polishing time.
[0015] In addition, this application also provides a wafer-level chip packaging intermediate, comprising:
[0016] A wafer having an active side and a back side;
[0017] A chip, mounted on the active surface of a wafer, wherein dicing channels are formed around the chip on the active surface of the wafer; and,
[0018] A molding compound is cured and formed on the active surface of the wafer, and the molding compound fills and covers the peripheral edge of the wafer, the dicing, and part of the back surface of the chip.
[0019] The reasoning process for the beneficial effects of the wafer-level chip packaging intermediate provided in this application is similar to that of the aforementioned wafer-level chip packaging method, and will not be repeated here.
[0020] Optionally, the molding layer partially covers the surrounding area of the back surface of the chip.
[0021] Optionally, the area covered by the molding compound on the back surface of the chip accounts for no more than 50% of the area of the back surface of the chip.
[0022] This application also provides a wafer-level chip packaging unit, which is manufactured using the wafer-level chip packaging method as described in any of the foregoing technical solutions.
[0023] The reasoning process for the beneficial effects of the wafer-level chip packaging unit provided in this application is similar to that of the aforementioned wafer-level chip packaging method, and will not be repeated here.
[0024] This application also provides a wafer-level chip packaging structure, including a packaging substrate and a wafer-level chip packaging unit as described in the above technical solution, wherein the wafer-level chip packaging unit is mounted on the packaging substrate.
[0025] The wafer-level chip packaging structure provided in this application has a similar deductive process to the aforementioned wafer-level chip packaging method, and will not be repeated here.
[0026] These features and advantages of this application will be disclosed in detail in the following specific embodiments and accompanying drawings. The best embodiments or means of this application will be shown in detail in conjunction with the accompanying drawings, but are not intended to limit the technical solutions of this application. In addition, each of these features, elements and components appearing in the following text and drawings is multiple and is labeled with different symbols or numbers for convenience, but all represent parts with the same or similar structure or function. Attached Figure Description
[0027] The following description, in conjunction with the accompanying drawings, further illustrates this application:
[0028] Figure 1 A flowchart illustrating a wafer-level chip packaging method provided for the first aspect of this application;
[0029] Figure 2 This is a schematic diagram of a wafer without molding compound applied.
[0030] Figure 3 A partial side view of a wafer without molding compound applied;
[0031] Figure 4 A schematic diagram of a wafer-level chip packaging intermediate provided for the second aspect of this application;
[0032] Figure 5for Figure 4 A partial side view of a wafer-level chip packaging intermediate.
[0033] Figure 6 To Figure 4 A partial side view of the wafer-level chip packaging intermediate after grinding.
[0034] Among them, 1 is a wafer; 10 is a first active surface; 11 is a dicing channel; 2 is a chip; 20 is a second back surface; and 3 is a molding layer. Detailed Implementation
[0035] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described are intended to explain this application and should not be construed as limiting it.
[0036] The terms "an embodiment," "example," or "trademark" used in this specification refer to a particular feature, structure, or characteristic described in connection with the embodiment itself that may be included in at least one embodiment disclosed in this application. The phrase "in an embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment.
[0037] In the description of this application, it should be understood that the terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In the description of this application, "a plurality of" means two or more, unless otherwise precisely specified.
[0038] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected," "linked," and "connected" should be interpreted broadly. For example, they can refer to a fixed connection, a connection through an intermediary, or a connection within two elements or an interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0039] The first aspect of this application provides a wafer-level chip packaging method, such as... Figures 1 to 6 As shown, the wafer-level chip packaging method includes the following steps:
[0040] Step S100: Provide wafer 1, such as Figure 2 and Figure 3As shown, multiple chips 2 are integrated on the active surface of wafer 1 at intervals, and dicing channels 11 are formed around the chips 2 on the active surface of wafer 1. Specifically, wafer 1 is a silicon wafer 1, and its diameter can be 200mm (8 inches) or 300mm (12 inches), etc. Wafer 1 has opposing active surfaces and back surfaces, and the chips 2 on wafer 1 also have opposing active surfaces and back surfaces. For the sake of distinction, the active surface and back surface on wafer 1 are referred to as the first active surface 10 and the first back surface in this application, and the active surface and back surface on chip 2 are referred to as the second active surface and the second back surface 20. In this application, chip 2 is integrated on wafer 1 in a flip-chip manner, that is, the second active surface on chip 2 is bonded to the pad structure on the first active surface 10 of wafer 1 through microbumps, and the chips 2 are arranged regularly in a matrix, with the dicing channels 11 formed around the chips 2.
[0041] Step S200: Apply molding compound to the peripheral edge of wafer 1 and the dicing groove 11; the molding compound used is a thermosetting material suitable for semiconductor packaging, such as epoxy molding compound (EMC, an existing molding compound), which has good flowability (to ensure filling), appropriate thixotropy (to prevent overflow), and suitable curing shrinkage. The molding compound applied to the peripheral edge of wafer 1 can enhance the strength of the peripheral edge of wafer 1 after curing. The peripheral edge mentioned herein generally has a radial dimension along the radial direction of wafer 1 with a ratio of the radius of wafer 1 to a selected value between 0.05 and 0.1.
[0042] Specifically, a dispensing machine can be used to apply molding compound to the dicing groove 11 via dispensing. Applying molding compound to the dicing groove 11 using a dispensing process is a mature and highly precise technique, accurately applying molding compound to the narrow dicing groove 11, reducing unnecessary diffusion of the molding compound, and ensuring the reliability and repeatability of this step. High-precision automated dispensing machines equipped with vision positioning systems can be purchased commercially. These machines can accurately identify the position of the dicing groove 11 on wafer 1 and automatically apply molding compound to the dicing groove 11.
[0043] Another important process control point is the amount of molding compound applied. Too much molding compound should be applied to avoid completely covering the back surface of chip 2 after flow, while too little should be applied to avoid failing to completely fill the dicing groove 11. In this application, applying molding compound to the peripheral edge of wafer 1 and the dicing groove 11 includes configuring the molded compound applied to the dicing groove 11 such that its cured surface height is higher than the surface height of the back surface of chip 2. This provides a safe process margin for subsequent polishing operations, preventing damage to chip 2 during polishing of the cured molding compound. For example, if the back surface of chip 2 is 400 μm above the surface of wafer 1, the top surface height of the molding layer 3 formed in the dicing groove 11 region after curing can be controlled to be approximately 500 μm.
[0044] Step S300: Curing the molding compound to obtain an intermediate product; specifically, after the molding compound is applied, wafer 1 can be transferred to a curing device, and a suitable curing temperature profile is set according to the selected molding compound, and the molding compound is cured by the curing device.
[0045] Combination Figure 4 and Figure 5 As shown, after the curing process is completed, the molding compound forms a molding layer 3 within the dicing channel 11 and on the periphery of the back surface of the chip 2. At this point, the wafer 1, the chip 2, and the molding layer 3 together constitute an intermediate product.
[0046] Step S400: Grinding the intermediate product to fully expose the surface of chip 2 on wafer 1; specifically, a grinding machine can be used to grind the intermediate product to remove the molding compound 3 covering the back surface of chip 2, such as... Figure 6 As shown, this fully exposes the back surface of chip 2, preparing it for subsequent heat dissipation, detection, or possible stacking integration.
[0047] The grinding operation can first use a relatively coarse-grained diamond grinding pad for rapid thinning to quickly remove most of the molding compound protrusions, and then switch to a fine-grained grinding pad for fine grinding and polishing, so that the back surface of the chip 2 and the top surface of the molding layer 3 in the dicing channel 11 are smooth and coplanar.
[0048] Step S500: The intermediate product after grinding is cut to obtain individual chip 2 packaging units. Specifically, a wafer dicing machine is used to cut along the center of the dicing track 11, which has been filled with molding compound.
[0049] By applying the above-described wafer-level chip packaging method, the amount of molding compound used can be reduced by limiting the application area of the molding compound to the dicing groove 11, thereby reducing costs. Simultaneously, since the molding compound is applied to the dicing groove 11 and does not cover the entire surface of the chip 2 after curing, only a portion of the chip 2 is covered by the cured molding compound. This significantly reduces polishing time, thereby reducing the use of polishing consumables and improving production efficiency.
[0050] The intermediate product obtained by curing the molding compound in the above-described wafer-level chip packaging method includes: after curing, the molding compound applied to the dicing groove 11 forms a molding layer 3 in a portion of the back surface of the chip 2. It is readily understood that during the application and curing process, a small amount of molding compound will flow to the surface of the chip 2 and cover the surface of the chip 2 after curing. For example... Figure 5 As shown, a portion of the molding compound 3 extends to the back surface of the chip 2. The area of the molding compound 3 covering the back surface of the chip 2 depends on the precision of applying the molding compound to the dicing groove 11. The more precise the molding compound application, the less molding compound is applied, and the less molding compound flows to the back surface of the chip 2. The smaller the area of the molding compound 3 covering the back surface of the chip 2, the less time is required for subsequent polishing operations, and the more molding compound is saved.
[0051] During the application and curing process of molding compound, a small amount of molding compound will flow to the surface of chip 2 and cover the surface of chip 2 after curing. Allowing the molding compound to cover the surface of chip 2 helps to reduce the process requirements for molding compound application, which is conducive to the promotion of this solution. At the same time, it can also achieve the effects of saving molding compound and reducing grinding time.
[0052] Furthermore, the area on the back surface of chip 2 where the molding compound 3 is formed accounts for no more than 50% of the area of the back surface of chip 2, and the area on the back surface of chip 2 covered by the molding compound 3 accounts for no more than 50% of the area of the back surface of chip 2. This reduces the process requirements for molding compound and helps to promote the application of this solution.
[0053] The second aspect of this application provides a wafer-level chip packaging intermediate, such as Figure 4 and Figure 5 As shown, the wafer-level chip packaging intermediate includes a wafer 1, a chip 2, and a molding compound 3. Multiple chips 2 are integrated at intervals on the active surface of the wafer 1, and dicing channels 11 are formed around the chips 2 on the active surface of the wafer 1. The molding compound 3 is solidified on the active surface of the wafer 1, and fills and covers the dicing channels 11 and part of the back surface of the chips 2.
[0054] On the one hand, since only part of the back surface of chip 2 is covered by the molding compound 3 in this wafer-level chip packaging intermediate, the use of molding compound is saved, and subsequent grinding operations consume less material and save time. On the other hand, this wafer-level chip packaging intermediate can serve as a storable and transportable semi-finished product, facilitating phased production in different locations.
[0055] Similarly, as mentioned above, Figure 5 As shown, in this embodiment, the molding compound 3 partially covers the surrounding area of the back surface of the chip 2, and the area of the back surface of the chip 2 covered by the molding compound 3 accounts for 20% of the area of the back surface of the chip 2. In other optional embodiments, the area of the back surface of the chip 2 covered by the molding compound 3 can be controlled to be no more than 50%.
[0056] A third aspect of this application provides a wafer-level chip packaging unit, which is manufactured using the aforementioned wafer-level chip packaging method.
[0057] The fourth aspect of this application provides a wafer-level chip packaging structure, which includes a packaging substrate and the aforementioned wafer-level chip packaging unit, wherein the wafer-level chip packaging unit is mounted on the packaging substrate.
[0058] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Those skilled in the art should understand that this application includes, but is not limited to, the contents described in the accompanying drawings and the specific embodiments above. Any modifications that do not depart from the functional and structural principles of this application will be included within the scope of the claims.
Claims
1. A wafer level chip packaging method, characterized by, The application provides a wafer-level chip packaging method, which comprises the following steps: providing a wafer, wherein a plurality of chips are arranged on the active surface of the wafer in a spaced manner, and a cutting groove is formed around the chips on the active surface of the wafer; applying plastic sealing material to the peripheral edge of the wafer and the cutting groove; curing the plastic sealing material to obtain an intermediate product; grinding the intermediate product to expose the surface of the chips on the wafer completely; cutting the intermediate product to obtain single chip packaging units.
2. The wafer level chip encapsulation method of claim 1, wherein, The step of applying plastic sealing material to the peripheral edge of the wafer and the cutting groove comprises the following steps: applying the plastic sealing material to the peripheral edge of the wafer and the cutting groove by using a glue spreading machine.
3. The wafer level chip encapsulation method of claim 1 or 2, wherein, The step of applying plastic sealing material to the peripheral edge of the wafer and the cutting groove comprises the following steps: the plastic sealing material applied to the peripheral edge of the wafer and the cutting groove is configured to have a surface height higher than that of the back surface of the chips after being cured.
4. The wafer level chip encapsulation method of claim 3, wherein, The step of curing the plastic sealing material to obtain an intermediate product comprises the following steps: the plastic sealing material applied to the cutting groove forms a plastic sealing layer on a part of the back surface of the chips after being cured.
5. The wafer level chip encapsulation method of claim 4, wherein, The area of the back surface of the chips on which the plastic sealing layer is formed accounts for no more than 50% of the area of the back surface of the chips.
6. A wafer level chip scale package intermediate, characterized by, The application provides a wafer-level chip packaging structure, which comprises the following components: a wafer having opposite active surfaces and back surfaces; chips attached to the active surface of the wafer, wherein a cutting groove is formed around the chips on the active surface of the wafer; a plastic sealing layer formed on the active surface of the wafer and covering the peripheral edge of the wafer, the cutting groove and part of the back surface of the chips. The plastic sealing layer covers the peripheral area on the back surface of the chips.
7. The wafer-level chip-scale package intermediate of claim 6, wherein the underfill material is a polymer material. The area of the back surface of the chips covered by the plastic sealing layer accounts for no more than 50% of the area of the back surface of the chips.
8. The wafer-level chip-scale package intermediate of claim 7, wherein the dielectric layer is a polymer layer. The wafer-level chip packaging structure is manufactured by using the wafer-level chip packaging method according to any one of claims 1 to 5.
9. A wafer level chip scale package unit, characterized by, The application provides a wafer-level chip packaging structure, which comprises a packaging substrate and a wafer-level chip packaging unit according to claim 9, wherein the wafer-level chip packaging unit is attached to the packaging substrate.
10. A wafer level chip scale package structure, comprising: