Deposition mask, method of manufacturing a deposition mask, and electronic device

Abstract

A deposition mask, a method of manufacturing a deposition mask, and an electronic device are disclosed. The deposition mask includes a mask frame through which cell openings are defined, and a membrane disposed on the mask frame, wherein the membrane includes mask cell regions respectively exposed through the cell openings and dummy regions respectively surrounding the mask cell regions. Pixel openings are defined through the mask cell regions of the membrane, and dummy openings are defined through the dummy regions of the membrane.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2024-0174438, filed on November 29, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to deposition masks, methods for manufacturing deposition masks, and electronic devices manufactured using deposition masks. Background Technology

[0004] Wearable devices that focus at a distance close to the user's eyes have been developed in the form of glasses or helmets. For example, wearable devices can be head-mounted displays (HMDs) or AR glasses. Wearable devices can provide users with augmented reality (AR) or virtual reality (VR) visuals.

[0005] In the case of wearable devices such as HMDs or AR glasses, a display specification of approximately 3000 pixels per inch (PPI) or higher is desired to allow users to use them for extended periods without experiencing dizziness. For this purpose, organic light-emitting diode-on-silicon (OLEDoS) technology is emerging for high-resolution, small-scale organic light-emitting display devices. OLEDoS is a technology in which organic light-emitting diodes (OLEDs) are disposed on a semiconductor substrate upon which complementary metal-oxide-semiconductor (CMOS) elements are placed. Summary of the Invention

[0006] To manufacture display panels with a high resolution of approximately 3000 PPI or higher, high-resolution deposition masks can be used. For example, a deposition mask can be manufactured by forming a diaphragm with multiple pixel openings on a mask substrate such as a silicon wafer and partially removing the mask substrate to form cell openings that expose the pixel openings. However, during the fabrication of the deposition mask, warping may occur in the deposition mask due to differences in the coefficients of thermal expansion between the mask substrate and the diaphragm, or residual stress in the diaphragm.

[0007] Embodiments of this disclosure provide a deposition mask in which warpage is reduced, a method of manufacturing a deposition mask, and an electronic device manufactured using a deposition mask.

[0008] However, the embodiments of this disclosure are not limited to those set forth herein. The above and other embodiments of this disclosure will become more apparent to those skilled in the art from the following detailed description of this disclosure.

[0009] According to embodiments of this disclosure, a deposition mask includes: a mask frame, with cell openings defined through the mask frame; and a diaphragm disposed on the mask frame, wherein the diaphragm includes mask cell regions exposed through the cell openings and dummy regions surrounding the mask cell regions. In such embodiments, pixel openings are defined through the mask cell regions of the diaphragm, and dummy openings are defined through the dummy regions of the diaphragm.

[0010] According to some embodiments of this disclosure, the deposition mask may further include an intermediate inorganic film disposed between the mask frame and the diaphragm. In such embodiments, an intermediate opening may be defined by the intermediate inorganic film passing through the cell opening and the mask cell region.

[0011] According to some embodiments of this disclosure, the mask frame may include a first rib region defining a unit opening, the intermediate inorganic film may include a second rib region disposed on the first rib region and defining the intermediate opening, and the groove may be defined by the first rib region, the second rib region and the dummy region.

[0012] According to some embodiments of this disclosure, the deposition mask may further include: a first post-inorganic film disposed on the rear surface of the mask frame and communicating with a cell opening through a first rear opening defined by the first post-inorganic film; and a second post-inorganic film disposed on the first post-inorganic film and communicating with the first rear opening through a second rear opening defined by the second post-inorganic film. In such embodiments, an intermediate inorganic film and a diaphragm may be disposed on the front surface of the mask frame.

[0013] According to some embodiments of this disclosure, the diaphragm and the second post-inorganic membrane may comprise the same material as each other, and the area of ​​the remaining area of ​​the diaphragm after removing the mask unit region and the dummy region may be equal to the area of ​​the second post-inorganic membrane.

[0014] According to some embodiments of this disclosure, the intermediate inorganic membrane and the first post-inorganic membrane may comprise the same material as each other, and the area of ​​the intermediate inorganic membrane may be equal to the area of ​​the first post-inorganic membrane.

[0015] According to some embodiments of this disclosure, the cell opening may have a width that gradually decreases from the rear surface of the mask frame toward the front surface of the mask frame.

[0016] According to some embodiments of this disclosure, the second dummy opening may be defined through an edge portion of the diaphragm or a portion of the diaphragm between dummy regions.

[0017] According to some embodiments of this disclosure, the deposition mask may further include an intermediate inorganic membrane disposed between the mask frame and the diaphragm. In such embodiments, an intermediate opening may be defined through the intermediate inorganic membrane between a cell opening and a mask cell region, and a second intermediate opening may be defined through the intermediate inorganic membrane to communicate with a second dummy opening and partially expose the mask frame.

[0018] According to some embodiments of this disclosure, the deposition mask may further include: a first post-inorganic film disposed on the rear surface of the mask frame and communicating with a cell opening through a first rear opening defined by the first post-inorganic film; and a second post-inorganic film disposed on the first post-inorganic film and communicating with the first rear opening through a second rear opening defined by the second post-inorganic film. In such embodiments, an intermediate inorganic film and a diaphragm may be disposed on the front surface of the mask frame.

[0019] According to some embodiments of this disclosure, the diaphragm and the second post-inorganic membrane may comprise the same material as each other, and the area of ​​the remaining area of ​​the diaphragm after removing the mask unit region, the dummy region, and the second dummy opening may be equal to the area of ​​the second post-inorganic membrane.

[0020] According to some embodiments of this disclosure, the intermediate inorganic membrane and the first post-inorganic membrane may comprise the same material as each other, and the area of ​​the intermediate inorganic membrane may be equal to the area of ​​the first post-inorganic membrane.

[0021] According to another embodiment of the present disclosure, a method for manufacturing a deposition mask includes: forming a diaphragm on a mask substrate including a mask unit region and dummy regions respectively surrounding the mask unit region; patterning the diaphragm to form pixel openings through the mask unit region and dummy openings through the dummy regions; and patterning the mask substrate to form unit openings respectively exposing the mask unit region.

[0022] According to some embodiments of this disclosure, the method may further include: forming an intermediate inorganic film on a mask substrate; and patterning the intermediate inorganic film to form intermediate openings such that mask cell regions are exposed through cell openings. In such embodiments, a diaphragm may be formed on the intermediate inorganic film, and the intermediate openings may be formed after the cell openings are formed.

[0023] According to some embodiments of this disclosure, the central opening can be formed by a wet etching process, and the annular groove can be formed between the dummy area of ​​the diaphragm and the mask substrate by a wet etching process.

[0024] According to some embodiments of this disclosure, the method may further include: forming a first rear inorganic film on the rear surface of a mask substrate; forming a second rear inorganic film on the first rear inorganic film; and patterning the first and second rear inorganic films to form a first rear opening and a second rear opening, each exposing a rear portion of the mask substrate. In such embodiments, an intermediate inorganic film and a diaphragm may be formed on the front surface of the mask substrate, and the cell openings may be formed by a wet etching process using the first and second rear inorganic films as etching masks.

[0025] According to some embodiments of this disclosure, the cell opening may have a width that gradually decreases from the rear surface of the mask substrate toward the front surface of the mask substrate.

[0026] According to some embodiments of this disclosure, the diaphragm and the second post-inorganic membrane can be formed of the same material as each other, and the area of ​​the remaining area of ​​the diaphragm after removing the mask unit region and the dummy region can be equal to the area of ​​the second post-inorganic membrane forming the second post-opening.

[0027] According to some embodiments of this disclosure, the intermediate inorganic membrane and the first post-inorganic membrane can be formed of the same material as each other, and the area of ​​the intermediate inorganic membrane forming the intermediate opening can be equal to the area of ​​the first post-inorganic membrane forming the first post-opening.

[0028] According to some embodiments of this disclosure, the method may further include: patterning the diaphragm to form a second dummy opening through an edge portion of the diaphragm or a portion of the diaphragm between dummy regions.

[0029] According to some embodiments of this disclosure, the method may further include: forming an intermediate inorganic film on a mask substrate; and patterning the intermediate inorganic film to form intermediate openings such that mask cell regions are exposed through cell openings. In such embodiments, a diaphragm may be formed on the intermediate inorganic film, and the intermediate openings may be formed after the cell openings are formed.

[0030] According to some embodiments of this disclosure, the method may further include patterning an intermediate inorganic film to form a second intermediate opening that communicates with the second dummy opening and partially exposes the mask substrate. In such embodiments, the intermediate opening and the second intermediate opening may be formed simultaneously with each other.

[0031] According to another embodiment of this disclosure, an electronic device includes a display panel. In such an embodiment, the display panel includes: a substrate; and a plurality of light-emitting layers formed on the substrate using a deposition mask. In such an embodiment, the deposition mask includes: a mask frame having cell openings; and a diaphragm disposed on the mask frame and including mask cell regions exposed through the cell openings and dummy regions surrounding the mask cell regions. In such an embodiment, pixel openings are defined through the mask cell regions of the diaphragm, and dummy openings are defined through the dummy regions of the diaphragm.

[0032] According to some embodiments of this disclosure, the electronic device may also include at least one selected from a processor, a memory, and a power module.

[0033] As described above according to embodiments of the present disclosure, the diaphragm may include dummy regions surrounding the mask unit regions, and dummy openings may be defined through the dummy regions. As a result, the forces exerted on the mask frame due to residual stress of the diaphragm can be reduced, and thus the warpage of the deposition mask can be reduced.

[0034] Other features and embodiments will become apparent in the following detailed description and accompanying drawings. Attached Figure Description

[0035] The above and other features of the embodiments of this disclosure will become more apparent from the detailed description of the embodiments with reference to the accompanying drawings, in which:

[0036] Figure 1 This is a block diagram of an electronic device according to embodiments of the present disclosure;

[0037] Figure 2 These are schematic diagrams of electronic devices according to various embodiments of the present disclosure;

[0038] Figure 3 This is an exploded perspective view illustrating a display device according to an embodiment of the present disclosure;

[0039] Figure 4 It is shown Figure 3 Block diagram of the display device shown;

[0040] Figure 5 It is shown Figure 4 The equivalent circuit diagram of the example of the first sub-pixel shown;

[0041] Figure 6 It is shown Figure 3 A schematic floor plan of an example of a display panel shown;

[0042] Figure 7 It is shown Figure 6 A schematic enlarged plan view of an example of the display area shown;

[0043] Figure 8 It is shown Figure 6 A schematic enlarged plan view of another example of the display area shown;

[0044] Figure 9 It shows along Figure 7 A schematic cross-sectional view of an example display panel, shown by line I1-I1'.

[0045] Figure 10 It shows along Figure 7 A schematic cross-sectional view of another example of a display panel, shown by line I1-I1';

[0046] Figure 11 This is a schematic perspective view showing an example of a head-mounted display;

[0047] Figure 12 It is shown Figure 11 A schematic exploded perspective view of the head-mounted display shown;

[0048] Figure 13 This is a schematic perspective view showing another example of a head-mounted display;

[0049] Figure 14 This is a schematic diagram illustrating a deposition mask and a deposition apparatus including the deposition mask according to an embodiment of the present disclosure;

[0050] Figure 15 It is shown Figure 14 A schematic bottom view of the backplate base shown;

[0051] Figure 16 It is shown Figure 14 A schematic plan view of the deposition mask shown;

[0052] Figure 17 It is shown Figure 16 A schematic plan view of the mask unit area shown;

[0053] Figure 18 It is along Figure 17 The schematic cross-sectional view of the line I2-I2' shown in the figure;

[0054] Figure 19 It is shown Figure 17 A schematic enlarged plan view of the virtual area shown;

[0055] Figure 20 It is shown Figure 18 A schematic enlarged cross-sectional view of the dummy area shown;

[0056] Figure 21 This is a schematic plan view illustrating a deposition mask according to another embodiment of the present disclosure;

[0057] Figure 22 It is shown Figure 21 A schematic cross-sectional view of the second illusory opening shown;

[0058] Figure 23 It is shown Figure 21 A schematic enlarged plan view of another example of the second illusory opening shown;

[0059] Figure 24 It is shown Figure 21 A schematic enlarged plan view of yet another example of the second illusory opening shown;

[0060] Figure 25 This is a schematic cross-sectional view showing a deposition mask according to yet another embodiment of the present disclosure; and

[0061] Figures 26 to 31 This is a schematic cross-sectional view illustrating a method for manufacturing a deposition mask according to an embodiment of the present disclosure. Detailed Implementation

[0062] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments of the invention are illustrated. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0063] It will also be understood that when an element or layer is referred to as being "on" another element or layer, the element or layer may be directly on the other element or layer, or an intervening layer may be present. Throughout the specification, the same reference numerals denote the same components.

[0064] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element discussed below may be referred to as a second element without departing from the teachings of the invention. Similarly, a second element may also be referred to as a first element.

[0065] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, as used herein, “a,” “an,” “the,” and “at least one” do not imply a limitation on quantity and are intended to include both the singular and plural forms. Thus, a reference to the element “a” following a reference to the element in the claims includes one element and multiple elements. For example, unless the context clearly indicates otherwise, “an element” has the same meaning as “at least one element.” “At least one” is not to be construed as limited to “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that, when used in this specification, the terms “comprises and / or comprising” or “includes and / or including” indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0066] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to cover different orientations of the device. For example, if the device is flipped in a drawing, an element described as being “below” the other element will subsequently be positioned “above” the other element. Thus, depending on the specific orientation of the drawing, the term “below” can cover both “below” and “above” orientations. Similarly, if the device is flipped in a drawing, an element described as being “below” or “under” the other element will subsequently be positioned “above” the other element. Thus, the terms “below” or “under” can cover both “above” and “below” orientations.

[0067] Features of each of the various embodiments of this disclosure may be combined with each other in part or in whole, and may be technically interoperable with each other in various ways, and the corresponding embodiments may be implemented independently of each other or may be implemented together in relation to each other.

[0068] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, “about” or “approximately” includes the stated value and means within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0069] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their context in the relevant field and their meaning in this disclosure, and shall not be interpreted in an idealized or overly formalized sense.

[0070] The embodiments are described herein with reference to cross-sectional views of schematic illustrations as idealized examples. Thus, variations in the shape of the illustrations due to, for example, manufacturing techniques and / or tolerances will be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the areas shown herein, but should include deviations in shape due to, for example, manufacturing processes. For example, areas shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the precise shapes of the areas, nor are they intended to limit the scope of the claims.

[0071] In the following description, embodiments will be described in detail with reference to the accompanying drawings.

[0072] The display device according to embodiments of the present disclosure can be applied to various electronic devices. Electronic devices according to embodiments of the present disclosure include the aforementioned display device, and may further include modules or devices with additional functions in addition to the display device.

[0073] Figure 1 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0074] Reference Figure 1 The electronic device 10 according to embodiments of the present disclosure may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0075] The processor 12 may include at least one selected from a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0076] The memory 13 can store data information for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals are sent to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0077] The power module 14 may include a power module such as a power adapter or battery, and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 10.

[0078] At least one of the components of the electronic device 10 according to embodiments of the present disclosure may be included in the display device 20 according to embodiments of the present disclosure (see...). Figure 3 Furthermore, some modules that are functionally included in a single module may be included in the display device 20, while other modules may be provided separately from the display device 20. In embodiments, for example, the display device 20 may include a display module 11, and the processor 12, memory 13, and power module 14 may be provided as other devices within the electronic device 10 instead of the display device 20.

[0079] Figure 2 This is a schematic diagram of an electronic device according to various embodiments of the present disclosure.

[0080] Reference Figure 2 The display device 20 according to an embodiment of the present disclosure (see also...) Figure 3The various electronic devices used can include not only image display electronic devices such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d and desktop monitors 10_1e, but also wearable electronic devices such as smart glasses 10_2a, head-mounted displays 10_2b and smartwatches 10_2c that include display modules, as well as vehicle electronic devices 10_3 such as central information displays (CIDs) and rearview mirror displays arranged on the dashboard, central instrument panel and dashboard of a car.

[0081] Figure 3 This is an exploded perspective view showing a display device according to an embodiment of the present disclosure. Figure 4 It is shown Figure 3 Block diagram of the display device shown.

[0082] Reference Figure 3 and Figure 4 The display device 20 according to the embodiment can be a device for displaying moving images or still images. The display device 20 according to the embodiment can be used as an electronic device 10 (see...). Figure 1 The display device 20 according to the embodiment can be used as a display module 11 of an electronic device 10, such as a mobile phone, smartphone, tablet PC, mobile communication terminal, electronic notebook, e-book, portable multimedia player (PMP), navigation system, and ultra-mobile PC (UMPC). The display device 20 according to the embodiment can also be used as a display module 11 of an electronic device 10, such as a television, laptop computer, monitor, billboard, or Internet of Things (IoT) terminal. The display device 20 according to the embodiment can also be used in electronic devices 10 such as smartwatches, smartwatch phones, and head-mounted displays (HMDs) for realizing virtual and augmented reality.

[0083] The display device 20 according to the embodiment may include a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0084] The display panel 100 may have a planar shape similar to a quadrilateral. In an embodiment, for example, the display panel 100 may have a planar shape similar to a quadrilateral, having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. Here, the planar shape can be the shape viewed in a plan view or viewed in a third direction DR3. Here, the third direction DR3 can be the thickness direction of the display panel 100. In the display panel 100, the angle where the short side in the first direction DR1 intersects the long side in the second direction DR2 can be a right angle or rounded with a predetermined curvature. The planar shape of the display panel 100 is not limited to a quadrilateral shape, and can be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 20 may conform to the planar shape of the display panel 100, but this disclosure is not limited thereto.

[0085] In this embodiment, the display panel 100 may include multiple pixels PX, multiple scan lines SL, multiple emission control lines EL, multiple data lines DL, a scan driver 610, an emission driver 620, and a data driver 700. For example... Figure 4 As shown, the display panel 100 can be divided into a display area DAA for displaying images and a non-display area NDA in which no images are displayed.

[0086] Multiple pixels (PX) can be set in the display area (DAA). Multiple pixels (PX) can be arranged in a matrix along the first direction (DR1) and the second direction (DR2). Multiple scan lines (SL) and multiple emission control lines (EL) can extend along the first direction (DR1) and be arranged along the second direction (DR2). Multiple data lines (DL) can extend along the second direction (DR2) and be arranged along the first direction (DR1).

[0087] Multiple scan lines SL can include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. Multiple emit control lines EL include multiple first emit control lines ECL1 and multiple second emit control lines ECL2.

[0088] Multiple pixels PX can include multiple sub-pixels SP1, SP2, and SP3. The multiple sub-pixels SP1, SP2, and SP3 can include, for example... Figure 5 The multiple pixel transistors shown can be formed by semiconductor processes and disposed on a semiconductor substrate SSUB (see [reference]). Figure 9 In this embodiment, for example, the plurality of pixel transistors may include or be formed of complementary metal-oxide-semiconductor (CMOS), but this disclosure is not limited thereto.

[0089] Each of the multiple sub-pixels SP1, SP2, and SP3 can be connected to a write scan line GWL, a control scan line GCL, a bias scan line GBL, a first emission control line ECL1, a second emission control line ECL2, and a data line DL. Each of the multiple sub-pixels SP1, SP2, and SP3 can receive the data voltage of the data line DL in response to the write scan signal of the write scan line GWL, and emit light from the light-emitting element according to the data voltage.

[0090] The scan driver 610, transmit driver 620, and data driver 700 can be located in the non-display area NDA.

[0091] The scan driver 610 includes multiple scan transistors, and the emitter driver 620 includes multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed on a semiconductor substrate SSUB using semiconductor processes (see [reference]). Figure 9 In an embodiment, for example, the plurality of scanning transistors and the plurality of light-emitting transistors may include or be formed of CMOS, but this disclosure is not limited thereto.

[0092] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS from the timing control circuit 400 and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal in response to the scan timing control signal SCS and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS and sequentially output the bias scan signal to the bias scan line GBL.

[0093] The transmit driver 620 includes a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 can receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 can generate a first transmit control signal based on the transmit timing control signal ECS and sequentially output the first transmit control signal to a first transmit control line ECL1. The second transmit control driver 622 can generate a second transmit control signal based on the transmit timing control signal ECS and sequentially output the second transmit control signal to a second transmit control line ECL2.

[0094] The data driver 700 may include multiple data transistors, and the multiple data transistors may be formed on a semiconductor substrate SSUB using semiconductor processes (see [reference]). Figure 9 In this embodiment, for example, multiple data transistors may be formed by CMOS, but this disclosure is not limited thereto.

[0095] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. Based on the data timing control signal DCS, the data driver 700 converts the digital video data DATA into an analog data voltage and outputs the analog data voltage to the data line DL. In this case, sub-pixels SP1, SP2, and SP3 can be selected by the write scan signal of the scan driver 610, and the analog data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0096] The heat dissipation layer 200 may overlap with the display panel 100 on a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on one surface of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a metal with high thermal conductivity (such as silver (Ag), copper (Cu), or aluminum (Al)) or graphite.

[0097] Circuit board 300 can be electrically connected to the first pad portion of display panel 100 PDA1 (see [link to PDA1]) using conductive adhesive components such as anisotropic conductive film. Figure 6 Multiple first pads PD1 (see) Figure 6 Circuit board 300 can be a flexible printed circuit board or a flexible film made of flexible material. Although circuit board 300 is in Figure 3 The circuit board 300 is shown unfolded, but it can be bent. When the circuit board 300 is bent, one end of the circuit board 300 can be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The other end of the circuit board 300 can be attached to the first pad portion of the display panel 100, PDA1, using conductive adhesive components (see [link to PDA1]). Figure 6 Multiple first pads PD1 (see) Figure 6 One end of circuit board 300 can be the opposite end of the other end of circuit board 300.

[0098] The timing control circuit 400 can receive digital video data DATA and timing signals input from an external source. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0099] The power supply circuit 500 can generate multiple panel driving voltages based on external power voltage. In an embodiment, for example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. This will be discussed later. Figure 5 The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT are described.

[0100] In this embodiment, each of the timing control circuit 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) or defined by an integrated circuit (IC) and attached to a surface of the circuit board 300. In such an embodiment, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 via the circuit board 300. Furthermore, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 via the circuit board 300.

[0101] Alternatively, each of the timing control circuit 400 and the power supply circuit 500 may be disposed in the non-display area NDA of the display panel 100, similar to the scan driver 610, transmit driver 620, and data driver 700. In such an embodiment, the timing control circuit 400 may include a plurality of timing transistors, and each power supply circuit 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed on a semiconductor substrate SSUB (see [link to semiconductor process]) using semiconductor technology. Figure 9 In an embodiment, for example, the multiple timing transistors and multiple power transistors may include or be formed of CMOS, but this disclosure is not limited thereto. Each of the timing control circuitry 400 and the power supply circuitry 500 may be disposed in the data driver 700 and the first pad portion of PDA1 (see...). Figure 6 )between.

[0102] Figure 5It is shown Figure 4 The equivalent circuit diagram of the example of the first sub-pixel shown.

[0103] Reference Figure 5 In this embodiment, the first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emit control line ECL1, the second emit control line ECL2, and the data line DL. Furthermore, the first sub-pixel SP1 can be connected to a first driving voltage VSS corresponding to a low potential voltage (see...). Figure 4 The first driving voltage line VSL applied, and the second driving voltage VDD corresponding to the high potential voltage (see...) Figure 4 The second driving voltage line VDL and the third driving voltage VINT corresponding to the initialization voltage (see...) are applied. Figure 4 The third driving voltage line VIL applied.

[0104] The first sub-pixel SP1 may include multiple transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0105] The light-emitting element LE emits light in response to a drive current flowing through the channel of the first transistor T1. The amount of light emitted by the light-emitting element LE can be proportional to the drive current. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but this disclosure is not limited thereto. In embodiments, for example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode; in this case, the light-emitting element LE can be a miniature light-emitting diode.

[0106] The first transistor T1 can be a driving transistor that controls the source-drain current (referred to herein as the "driving current") flowing between the source and drain electrodes of the first transistor T1 based on the voltage applied to the gate electrode of the first transistor T1.

[0107] The second transistor T2 can be connected between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by the write scan signal of the write scan line GWL to connect one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1.

[0108] The third transistor T3 can be connected between the first node N1 and the second node N2. The third transistor T3 is turned on by the control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. Therefore, when the gate electrode and drain electrode of the first transistor T1 are connected, the first transistor T1 can operate like a diode.

[0109] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emitter control signal of the first emitter control line ECL1 to connect the second node N2 to the third node N3. Therefore, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. A fifth transistor T5 can be disposed between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line GBL to connect the third node N3 to the third drive voltage line VIL. Therefore, the third drive voltage Vint of the third drive voltage line VIL can be applied to the first electrode of the light-emitting element LE.

[0110] The sixth transistor T6 can be connected between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second emitter control signal of the second emitter control line ECL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1.

[0111] The first capacitor CP1 is connected or formed between the first node N1 and the drain electrode of the second transistor T2. The second capacitor CP2 is connected or formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL.

[0112] Each of the first transistors T1 to the sixth transistor T6 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). In an embodiment, for example, each of the first transistors T1 to the sixth transistor T6 may be a P-type MOSFET, but this disclosure is not limited thereto. Each of the first transistors T1 to the sixth transistor T6 may be an N-type MOSFET. Alternatively, some of the first transistors T1 to the sixth transistor T6 may be P-type MOSFETs, and each of the remaining transistors may be an N-type MOSFET.

[0113] although Figure 5 An embodiment of the first sub-pixel SP1 including six transistors T1 to T6 and two capacitors CP1 and CP2 is shown. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to this embodiment. Figure 5The equivalent circuit diagram is shown. In embodiments, for example, the number of transistors and capacitors of the first sub-pixel SP1 is not limited to... Figure 5 Those shown.

[0114] In the embodiment, the second sub-pixel SP2 (see...) Figure 4 The equivalent circuit diagram of ) and the third sub-pixel SP3 (see Figure 4 The equivalent circuit diagram of ) can be combined with Figure 5 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, any repeated detailed descriptions of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 will be omitted.

[0115] Figure 6 It is shown Figure 3 A schematic floor plan of an example of a display panel shown.

[0116] Reference Figure 6 In an embodiment, the display area DAA of the display panel 100 according to the embodiment includes a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to the embodiment includes a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0117] The scan driver 610 can be disposed on a first side of the display area DAA, and the transmit driver 620 can be disposed on a second side of the display area DAA. In an embodiment, for example, the scan driver 610 can be disposed on one side of the display area DAA in the first direction DR1, and the transmit driver 620 can be disposed on the other side of the display area DAA in the first direction DR1. However, this disclosure is not limited thereto, and both the scan driver 610 and the transmit driver 620 can be disposed on either the first side or the second side of the display area DAA.

[0118] The first pad portion of PDA1 may include a connection to circuit board 300 via a conductive adhesive component (see...). Figure 3 The data driver 700 has multiple first pads PD1 for pads or bumps. The first pad portion PDA1 can be located on the third side of the display area DAA. In an embodiment, for example, the first pad portion PDA1 can be located on one side of the display area DAA in the second direction DR2. The first pad portion PDA1 can also be located on the outside of the data driver 700 in the second direction DR2.

[0119] The second pad portion PDA2 may include multiple second pads PD2 corresponding to the inspection pads used to test whether the display panel 100 is operating correctly. The multiple second pads PD2 may be connected to a fixture or probe during the inspection process, or they may be connected to a circuit board used for inspection. The circuit board used for inspection may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0120] The second pad portion PDA2 can be disposed on the fourth side of the display area DAA. In an embodiment, for example, the second pad portion PDA2 can be disposed on the other side of the display area DAA in the second direction DR2. The second pad portion PDA2 can be disposed on the second direction DR2 outside the second distribution circuit 720.

[0121] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to multiple data lines DL (see...). Figure 4 In an embodiment, for example, the first distribution circuit 710 can distribute the data voltage applied through a first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or greater) data lines DL, and as a result, the number of multiple first pads PD1 can be reduced. The first distribution circuit 710 can be disposed on the third side of the display area DAA of the display panel 100. In an embodiment, for example, the first distribution circuit 710 can be disposed on one side of the display area DAA in the second direction DR2.

[0122] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be located on the fourth side of the display area DAA of the display panel 100. In an embodiment, for example, the second distribution circuit 720 can be located on the other side of the display area DAA in the second direction DR2.

[0123] The cathode connection (CCA) can be the display element layer (EML) (see...). Figure 9 The second electrode CAT (see) Figure 9 ) and the first drive voltage line VSL of the non-display area NDA (see Figure 5 The cathode connection portion (CCA) can be disposed on at least one outer side of the display area (DAA). In an embodiment, for example, the cathode connection portion (CCA) can be disposed on at least one outer side among the left, right, upper, and lower sides of the display area (DAA). Alternatively, as... Figure 6As shown, the cathode connection CCA can be configured to surround the display area DAA, so that the first drive voltage VSS (see Figure 1) is caused by a voltage drop (IR drop) or voltage rise (IR rise) of the second electrode CAT in the display area DAA. Figure 4 Minimize the deviation in ).

[0124] Figure 7 It is shown Figure 6 A schematic enlarged plan view of an example of the display area shown. Figure 8 It is shown Figure 6 A schematic enlarged plan view of another example of the display area shown.

[0125] Reference Figure 7 and Figure 8 In the embodiment, pixel PX (see Figure 6 Each of the sub-pixels includes a first emission region EA1 as the emission region of the first sub-pixel SP1, a second emission region EA2 as the emission region of the second sub-pixel SP2, and a third emission region EA3 as the emission region of the third sub-pixel SP3.

[0126] The first launch area EA1, the second launch area EA2, and the third launch area EA3 can have the following configuration in the plan view: Figure 7 and Figure 8 The quadrilateral or hexagonal shape shown is not the only one described herein. The first emission region EA1, the second emission region EA2, and the third emission region EA3 may have other polygonal shapes, circular shapes, elliptical shapes, or irregular shapes in the plan view besides quadrilateral or hexagonal shapes.

[0127] In an embodiment, such as Figure 7 As shown, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1. Furthermore, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. Additionally, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the second direction DR2. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different.

[0128] Alternatively, such as Figure 8As shown, the emission regions EA1, EA2, EA3, and EA4 can have a hexagonal shape in the plan view. In such an embodiment, the first emission region EA1 and the third emission region EA3 can be adjacent in the first direction DR1, and the second emission region EA2 and the fourth emission region EA4 can be adjacent in the second direction DR2. Furthermore, the first emission region EA1 and the second emission region EA2 can be adjacent in the first diagonal direction DD1, and the second emission region EA2 and the third emission region EA3 can be adjacent in the second diagonal direction DD2. Additionally, the first emission region EA1 and the fourth emission region EA4 can be adjacent in the second diagonal direction DD2, and the third emission region EA3 and the fourth emission region EA4 can be adjacent in the first diagonal direction DD1. The first diagonal direction DD1 can be the direction between the first direction DR1 and the second direction DR2, and can refer to a direction inclined at 45 degrees relative to the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 can be a direction perpendicular to the first diagonal direction DD1.

[0129] The first sub-pixel SP1 can emit a first light, the second sub-pixel SP2 can emit a second light, the third sub-pixel SP3 can emit a third light, and the fourth sub-pixel SP4 can emit a second light. Here, the first light can be blue light, the second light can be green light, and the third light can be red light. In an embodiment, for example, the blue band can be a band with the main peak wavelength of light in the range of about 370 nanometers (nm) to about 460 nm, the green band can be a band with the main peak wavelength of light in the range of about 480 nm to about 560 nm, and the red band can be a band with the main peak wavelength of light in the range of about 600 nm to about 750 nm.

[0130] In an embodiment, each of the plurality of pixels PX can be as follows: Figure 7 The diagram shows three launch zones: EA1, EA2, and EA3, or it can be as follows: Figure 8 The diagram shows four emission regions: EA1, EA2, EA3, and EA4. In such an embodiment, the fourth emission region EA4 may emit the same second light as the second emission region EA2, but this disclosure is not limited thereto.

[0131] The emission regions of multiple pixels PX can be arranged in a strip structure along the first direction DR1, wherein the emission regions EA1, EA2, EA3, and EA4 are as follows: Figure 8 The arrangement shown is in a diamond shape. The structure or the hexagonal structure in which the emission area is arranged is a hexagonal structure.

[0132] Figure 9 It shows along Figure 7The diagram shows a schematic cross-sectional view of an example display panel taken by line I1-I1'.

[0133] Reference Figure 9 The embodiment of the display panel 100 includes a semiconductor backplane SBP, a light-emitting element backplane EBP, a display element layer EML, a packaging layer TFE, an optical layer OPL, a capping layer CVL, and a polarizing plate POL.

[0134] The semiconductor backplane (SBP) includes a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films (SINS1 to SINS3) covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) can be referenced... Figure 5 The first transistor T1 to the sixth transistor T6 are described.

[0135] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions WA can be disposed on or defined on the top surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the first type of impurity. In an embodiment, for example, if the first type of impurity is a P-type impurity, the second type of impurity can be an N-type impurity. In another embodiment, for example, if the first type of impurity is an N-type impurity, the second type of impurity can be a P-type impurity.

[0136] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0137] The lower insulating film (BINS) can be disposed between the gate electrode GE and the well region WA. The side insulating film (SINS) can be disposed on the side surface of the gate electrode GE. The side insulating film (SINS) can be disposed on the lower insulating film (BINS).

[0138] Each of the source region SA and the drain region DA can be a region doped with a type 1 impurity. The gate electrode GE of the pixel transistor PTR can overlap with the well region WA on a third direction DR3, which is the thickness direction of the display panel 100 or the semiconductor substrate SSUB. The channel region CH can overlap with the gate electrode GE on the third direction DR3. The source region SA can be disposed on one side of the gate electrode GE, and the drain region DA can be disposed on the other side of the gate electrode GE.

[0139] Each of the multiple well regions WA also includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. Due to the lower insulating film BINS, the first low-concentration impurity region LDD1 can be a region with a lower impurity concentration than the source region SA. Due to the lower insulating film BINS, the second low-concentration impurity region LDD2 can be a region with a lower impurity concentration than the drain region DA. The distance between the source region SA and the drain region DA can be increased due to the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, thereby increasing the length of the channel region CH of each of the pixel transistors PTR.

[0140] The first semiconductor insulating film SINS1 can be disposed on the semiconductor substrate SSUB. The second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1.

[0141] Multiple contact terminals (CTEs) can be disposed on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to a corresponding one of the gate electrode (GE), source region (SA), and drain region (DA) of each of the pixel transistors (PTRs) through holes penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2) (holes defined or formed via the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2)). The multiple contact terminals (CTEs) can include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or alloys thereof, or can be formed from at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or alloys thereof.

[0142] The third semiconductor insulating film (SINS3) can be disposed on the side surface of each of the plurality of contact terminals (CTEs). The top surface of each of the plurality of contact terminals (CTEs) can be exposed and not covered by the third semiconductor insulating film (SINS3).

[0143] Each of the first semiconductor insulating film SINS1, the second semiconductor insulating film SINS2, and the third semiconductor insulating film SINS3 may include silicon carbonitride (SiCN) or silicon oxide (SiO2). x Inorganic films based on silicon carbonitride (SiCN) or silicon oxide (SiO2) x Inorganic membrane formation based on ) base, but this disclosure is not limited thereto.

[0144] In this embodiment, the semiconductor substrate SSUB can be replaced with a glass substrate or a polymer resin substrate including polyimide. In such an embodiment, the thin-film transistor can be disposed on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that cannot be bent, and the polymer resin substrate can be a flexible substrate that can be bent or flexed.

[0145] The backplane EBP of the light-emitting element includes multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple interlayer insulating films INS1 to INS9.

[0146] Interlayer insulating films INS1 to INS9 are used to insulate first conductive layers ML1 to eighth conductive layers ML8. First conductive layers ML1 to eighth conductive layers ML8 are used to connect multiple contact terminals CTE exposed from the semiconductor backplane SBP, thereby achieving... Figure 5 The circuit of the first sub-pixel SP1 shown.

[0147] In an embodiment, for example, combined with Figure 5 The first transistor T1 to the sixth transistor T6 are formed only in the semiconductor backplane SBP, and the connection between the first transistor T1 to the sixth transistor T6 and the first capacitor CP1 and the second capacitor CP2 is achieved through the first conductive layer ML1 to the eighth conductive layer ML8. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light-emitting element LE is also achieved through the first conductive layer ML1 to the eighth conductive layer ML8.

[0148] The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 may comprise or be formed of substantially the same material. The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 may comprise at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or alloys thereof, or formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or alloys thereof. The first interlayer insulating films INS1 to INS8 may comprise or be made of substantially the same material. The first interlayer insulating films INS1 to INS8 may comprise silicon oxide (SiO2). x Inorganic films based on silicon dioxide (SiO2) or made of silicon oxide (SiO2) x Inorganic membrane formation based on ) base, but this disclosure is not limited thereto.

[0149] The ninth interlayer insulating film INS9 can be disposed on the eighth interlayer insulating film INS8 and the eighth conductive layer ML8. The ninth interlayer insulating film INS9 can be made of silicon oxide (SiO2). x Inorganic membrane formation based on ) base, but this disclosure is not limited thereto.

[0150] Each of the ninth vias VA9 can penetrate the ninth interlayer insulating film INS9 and connect to the exposed eighth conductive layer ML8. The ninth via VA9 may comprise at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or an alloy thereof, or may be formed from at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or an alloy thereof.

[0151] The display element layer (EML) can be disposed on the backplane (EBP) of the light-emitting element. The display element layer (EML) may include a tenth interlayer insulating film (INS10) and an eleventh interlayer insulating film (INS11), a reflective electrode (RL), a first electrode (AND), a light-emitting stack (IL), a second electrode (CAT), a pixel defining film (PDL), and multiple trenches (TRC).

[0152] The reflective electrodes RL can be disposed on the ninth interlayer insulating film INS9. Each of the reflective electrodes RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. In an embodiment, for example, as shown... Figure 9 As shown, each of the reflective electrodes RL may include a first reflective electrode RL1, a second reflective electrode RL2, a third reflective electrode RL3, and a fourth reflective electrode RL4.

[0153] The first reflective electrode RL1 can be disposed on the ninth interlayer insulating film INS9 and can be connected to the ninth via VA9. Each of the second reflective electrodes RL2 can be disposed on the first reflective electrode RL1 corresponding to the second reflective electrode RL2. Each of the third reflective electrodes RL3 can be disposed on the second reflective electrode RL2 corresponding to the third reflective electrode RL3. Each of the fourth reflective electrodes RL4 can be disposed on the third reflective electrode RL3 corresponding to the fourth reflective electrode RL4.

[0154] Since the second reflective electrode RL2 is an electrode that essentially reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4.

[0155] The first reflective electrode RL1, the second reflective electrode RL2, the third reflective electrode RL3, and the fourth reflective electrode RL4 may comprise at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or alloys or nitrides thereof, or may be formed from at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or alloys or nitrides thereof. In embodiments, for example, the first reflective electrode RL1 may comprise titanium nitride (TiN), the second reflective electrode RL2 may comprise aluminum (Al), the third reflective electrode RL3 may comprise titanium nitride (TiN), and the fourth reflective electrode RL4 may comprise titanium (Ti).

[0156] The tenth interlayer insulating film INS10 can be disposed on the ninth interlayer insulating film INS9. The tenth interlayer insulating film INS10 can be disposed between adjacent reflective electrodes RL. The tenth interlayer insulating film INS10 can be a film used to flatten the stepped portion caused by the reflective electrode RL. The eleventh interlayer insulating film INS11 can be disposed on the tenth interlayer insulating film INS10 and the reflective electrode RL.

[0157] The tenth interlayer insulating film INS10 and the eleventh interlayer insulating film INS11 may include silicon oxide (SiO2). x Inorganic films based on silicon dioxide (SiO2) or made of silicon oxide (SiO2) x Inorganic membrane formation based on ) base, but this disclosure is not limited thereto.

[0158] The eleventh interlayer insulating film INS11 can be an optical auxiliary layer for adjusting the resonant distance of light emitted from the light-emitting stack IL in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The thickness of the eleventh interlayer insulating film INS11 can be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. That is, in order to adjust the distance from the reflective electrode RL to the second electrode CAT according to the dominant wavelength of the light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the thickness of the eleventh interlayer insulating film INS11 can be set for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0159] In an embodiment, for example, such as Figure 9As shown, the thickness of the eleventh interlayer insulating film INS11 in the first sub-pixel SP1 can be greater than the thickness of the eleventh interlayer insulating film INS11 in the second sub-pixel SP2, and the thickness of the eleventh interlayer insulating film INS11 in the second sub-pixel SP2 can be greater than the thickness of the eleventh interlayer insulating film INS11 in the third sub-pixel SP3. In such an embodiment, the distance between the first electrode AND and the reflective electrode RL in the first sub-pixel SP1 is greater than the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2. Furthermore, the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2 is greater than the distance between the first electrode AND and the reflective electrode RL in the third sub-pixel SP3.

[0160] Each of the tenth vias VA10 can penetrate the eleventh interlayer insulating film INS11 and connect to the exposed fourth reflective electrode RL4. The tenth via VA10 can comprise at least one or an alloy of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or be formed from at least one or an alloy of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). The thickness of the tenth via VA10 in the first sub-pixel SP1 can be greater than the thickness of the tenth via VA10 in the second sub-pixel SP2, and the thickness of the tenth via VA10 in the second sub-pixel SP2 can be greater than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0161] The first electrode AND of each of the light-emitting elements LE can be disposed on the eleventh interlayer insulating film INS11 and connected to the tenth via VA10. The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the tenth via VA10, the reflective electrode RL, the first vias VA1 to the ninth via VA9, the first conductive layers ML1 to the eighth conductive layers ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE can include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or nitride thereof, or formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or nitride thereof. In an embodiment, for example, the first electrode AND of each of the light-emitting elements LE can be titanium nitride (TiN).

[0162] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL can separate a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3. Each of the first emitting region EA1, the second emitting region EA2, and the third emitting region EA3 can be a region in which a light-emitting element LE comprising the first electrode AND, a light-emitting stack IL, and a second electrode CAT is disposed.

[0163] The first emitting region EA1 can be defined as the region in which a first electrode AND, a light-emitting stack IL, and a second electrode CAT are sequentially stacked in a first sub-pixel SP1 to emit light. The second emitting region EA2 can be defined as the region in which a first electrode AND, a light-emitting stack IL, and a second electrode CAT are sequentially stacked in a second sub-pixel SP2 to emit light. The third emitting region EA3 can be defined as the region in which a first electrode AND, a light-emitting stack IL, and a second electrode CAT are sequentially stacked in a third sub-pixel SP3 to emit light.

[0164] The pixel-defining film (PDL) may include a first pixel-defining film (PDL1), a second pixel-defining film (PDL2), and a third pixel-defining film (PDL3). The first pixel-defining film (PDL1) may be disposed on the edge of the first electrode AND of each of the light-emitting elements (LEs). The second pixel-defining film (PDL2) may be disposed on the first pixel-defining film (PDL1), and the third pixel-defining film (PDL3) may be disposed on the second pixel-defining film (PDL2). The first pixel-defining film (PDL1), the second pixel-defining film (PDL2), and the third pixel-defining film (PDL3) may comprise silicon oxide (SiO2). x Inorganic films based on silicon dioxide (SiO2) or made of silicon oxide (SiO2) x An inorganic film based on silicon nitride (SiN) is formed. Alternatively, the first pixel defining film PDL1 and the third pixel defining film PDL3 can be formed from silicon nitride (SiN). x An inorganic film based on silicon dioxide (SiO2) is formed, while the second pixel defining film PDL2 can be formed from silicon dioxide (SiO2). x An inorganic film based on ) is formed. The first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 can each have approximately The thickness.

[0165] In this embodiment, to reduce or prevent the possibility of the first encapsulated inorganic film TFE1 being cut due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may have a cross-sectional structure with stepped portions. Step coverage refers to the ratio of the degree of film coating on the inclined portion to the degree of film coating on the flat portion. The lower the step coverage, the more likely the film will be cut at the inclined portion.

[0166] Each of the multiple trench TRCs can penetrate the first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3. The eleventh interlayer insulating film INS11 can be partially recessed at each of the multiple trench TRCs.

[0167] At least one trench TRC can be defined between adjacent sub-pixels SP1, SP2, and SP3. Although Figure 9 An embodiment is shown in which two trench TRCs are defined between adjacent sub-pixels SP1, SP2 and SP3, but this disclosure is not limited thereto.

[0168] The light-emitting stack IL can include multiple stacked layers IL1, IL2 and IL3. Figure 9 An embodiment of a light-emitting stack IL having a three-tiered structure including a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3 is shown, but this disclosure is not limited thereto. In another embodiment, for example, the light-emitting stack IL may have as follows: Figure 10 The diagram shows a dual-tandem structure comprising two stacked layers, IL1 and IL2.

[0169] In a three-tiered structure, the light-emitting stack IL can have a series structure comprising multiple stacked layers IL1, IL2, and IL3 that emit different lights. In an embodiment, for example, the light-emitting stack IL may include a first stacked layer IL1 that emits a first light, a second stacked layer IL2 that emits a second light, and a third stacked layer IL3 that emits a third light. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 may be stacked sequentially.

[0170] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first light-emitting layer emitting first light, and a first electron transport layer are stacked sequentially. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second light-emitting layer emitting second light, and a second electron transport layer are stacked sequentially. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third light-emitting layer emitting third light, and a third electron transport layer are stacked sequentially.

[0171] A first charge generation layer for supplying holes to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first stacked layer IL1 and a P-type charge generation layer for supplying holes to the second stacked layer IL2. The N-type charge generation layer may include a dopant of a metallic material.

[0172] A second charge generation layer for supplying holes to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be disposed between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second stacked layer IL2 and a P-type charge generation layer for supplying holes to the third stacked layer IL3.

[0173] A first stacked layer IL1 can be disposed on the first electrode AND and the pixel defining film PDL, and the residual film RIL disposed on the bottom surface of each trench TRC can be made of the same material as the first stacked layer IL1. Due to the trench TRC, the first stacked layer IL1 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A second stacked layer IL2 can be disposed on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A cavity ESS or empty space can be disposed in the trench TRC between the residual film RIL and the second stacked layer IL2. A third stacked layer IL3 can be disposed on the second stacked layer IL2. The third stacked layer IL3 is not cut by the trench TRC and can be configured to cover the second stacked layer IL2 in each of the trench TRCs.

[0174] In a three-series structure, each of the plurality of trench TRCs can be a structure for cutting off the first hole transport layer to the third hole transport layer, the first charge generation layer, and the second charge generation layer of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3. Furthermore, in a two-series structure, each of the plurality of trench TRCs can be a structure for cutting off the charge generation layer and the lower stacked layer disposed between the lower stacked layer and the upper stacked layer.

[0175] In an embodiment, to stably cut off the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of trench TRCs can be greater than the height of the pixel defining film PDL. The height of each of the plurality of trench TRCs refers to the length of each of the plurality of trench TRCs in the third direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL in the third direction DR3. In an embodiment, to cut off the charge generation layer and hole transport layer of the light-emitting stack IL of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, different structures can exist instead of trench TRCs. In an embodiment, for example, instead of trench TRCs, reverse tapered partition walls can be provided in the pixel defining film PDL.

[0176] also, Figure 9 An embodiment is shown in which a light-emitting stack IL is disposed in a first emission region EA1, a second emission region EA2, and a third emission region EA3, but this disclosure is not limited thereto. In another embodiment, for example, instead of the light-emitting stack IL, a first light-emitting layer may be disposed in the first emission region EA1 and may be omitted from the second emission region EA2 and the third emission region EA3. Furthermore, a second light-emitting layer may be disposed in the second emission region EA2 and may be omitted from the first emission region EA1 and the third emission region EA3. Furthermore, a third light-emitting layer may be disposed in the third emission region EA3 and may be omitted from the first emission region EA1 and the second emission region EA2. In such an embodiment, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0177] The second electrode CAT can be disposed on the light-emitting stack IL. That is, the second electrode CAT can be disposed on the third stack layer IL3. The second electrode CAT can include a transparent conductive material (TCO) capable of transmitting light (such as ITO or IZO) or a semi-transmissive conductive material (such as (Mg), silver (Ag), or an alloy of Mg and Ag), or can be formed of a transparent conductive material (TCO) capable of transmitting light (such as ITO or IZO) or a semi-transmissive conductive material (such as (Mg), silver (Ag), or an alloy of Mg and Ag). In embodiments where the second electrode CAT is formed of a semi-transmissive conductive material, light emission efficiency can be improved in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 due to the microcavity effect.

[0178] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic film TFE1 and TFE3 to prevent oxygen or moisture from penetrating into the display element layer EML. The first encapsulation inorganic film TFE1 can be disposed on the second electrode CAT, and the second encapsulation inorganic film TFE3 can be disposed above the first encapsulation inorganic film TFE1. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 can be made of silicon nitride (SiN). x ) layer, silicon oxynitride (SiON) layer, silicon oxide (SiO) layer x ) layer, titanium oxide (TiO) x ) layer and aluminum oxide (AlO) x Multiple layers are formed or defined by alternating stacking of one or more inorganic layers in a layer.

[0179] Furthermore, the encapsulation layer TFE may include at least one organic film TFE2 to protect the display element layer EML from foreign substances such as dust. The encapsulation organic film TFE2 may be disposed between the first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3. The encapsulation organic film TFE2 may be a monomer. Alternatively, the encapsulation organic film TFE2 may be an organic film comprising materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0180] The adhesive layer ADL can be a layer used to bond the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL can be a double-sided adhesive component. Furthermore, the adhesive layer ADL can be a transparent adhesive component comprising, for example, a transparent adhesive or a transparent adhesive resin.

[0181] The optical layer OPL includes multiple color filters CF1, CF2, and CF3, multiple lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the adhesive layer ADL.

[0182] The first color filter CF1 can overlap with the first emission region EA1 of the first sub-pixel SP1. The first color filter CF1 can transmit light of a first color, namely, light in the blue band. The blue band can be from about 370 nm to about 460 nm. Therefore, the first color filter CF1 can transmit light of the first color emitted from the first emission region EA1.

[0183] The second color filter CF2 can overlap with the second emission region EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of a second color, namely, light in the green band. The green band can be from approximately 480 nm to approximately 560 nm. Therefore, the second color filter CF2 can transmit light of the second color emitted from the second emission region EA2.

[0184] The third color filter CF3 can overlap with the third emission region EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of the third color, that is, light in the red band. The red band can be from approximately 600nm to approximately 750nm. Therefore, the third color filter CF3 can transmit light of the third color emitted from the third emission region EA3.

[0185] Multiple lenses LNS can be respectively disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the multiple lenses LNS can be a structure for increasing the proportion of light directed toward the front of the display device 10. Each of the multiple lenses LNS can have a cross-sectional shape that convexes in the upward direction.

[0186] A filler layer (FIL) can be disposed on multiple lens lenses (LNS). The filler layer FIL can have a predetermined refractive index, such that light travels in the third direction (DR3) at the interface between the filler layer FIL and the multiple lens lenses (LNS). Furthermore, the filler layer FIL can be a planarization layer. The filler layer FIL can be an organic film comprising materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0187] A capping layer CVL can be disposed on a filler layer FIL. The capping CVL can be a glass substrate or a polymer resin substrate. In embodiments where the capping CVL is a glass substrate, the capping CVL can be attached to the filler layer FIL. In this case, the filler layer FIL can be used to bond the capping CVL. In embodiments where the capping CVL is a glass substrate, the capping CVL can be used as an encapsulation substrate. In embodiments where the capping CVL is a polymer resin substrate, the capping CVL can be directly applied to the filler layer FIL.

[0188] A polarizing plate (POL) can be disposed on one surface of the capping layer CVL. The polarizing plate POL can be a structure used to reduce or prevent visibility degradation caused by reflection of external light. The polarizing plate POL can include a linear polarizing plate and a phase retardation film. In embodiments, for example, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but this disclosure is not limited thereto. However, the polarizing plate POL can be omitted when the first color filter CF1, the second color filter CF2, and the third color filter CF3 sufficiently overcome the visibility degradation caused by reflection of external light.

[0189] Figure 10 It shows along Figure 7 The diagram shows a schematic cross-sectional view of another example of a display panel, taken by line I1-I1'.

[0190] In addition to the first electrode AND of each of the light-emitting elements LEs being in contact with and electrically connected to the side surface of the connection electrode ANC connected to the eighth conductive layer ML8, and the omission of the trench TRC, and instead, the third pixel defining film PDL3 and the fourth pixel defining film PDL4 having an eaves-shaped or mushroom-shaped cross-sectional structure, Figure 10 Implementation examples and Figure 9 The implementation examples are basically the same. Figure 10 In the description of the embodiments, the terms will be omitted or simplified. Figure 9 The detailed description of any repetition of elements that are the same or identical to those in the embodiments.

[0191] Reference Figure 10 Multiple connecting electrodes ANC can be respectively disposed on the first portion AA1 of the ninth interlayer insulating film INS9. Each of the multiple connecting electrodes ANC can be disposed on the first portion AA1 of the ninth interlayer insulating film INS9 corresponding to each of the multiple connecting electrodes ANC. The multiple connecting electrodes ANC may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), their alloys, or transparent conductive oxides, or formed from at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), their alloys, or transparent conductive oxides. In embodiments, for example, the multiple connecting electrodes ANC may include titanium (Ti), titanium nitride (TiN), indium tin oxide (ITO), or indium zinc oxide (IZO), but this disclosure is not limited thereto.

[0192] Multiple reflective electrodes RL can be respectively disposed on multiple connecting electrodes ANC. Each of the multiple reflective electrodes RL can be disposed on a connecting electrode ANC corresponding to each of the multiple reflective electrodes RL. The multiple reflective electrodes RL may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or alloys thereof, or formed from at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or alloys thereof. In an embodiment, for example, each of the multiple reflective electrodes RL may include aluminum (Al) having high reflectivity.

[0193] Multiple optical auxiliary films (OALs) can be separately disposed on multiple reflective electrodes (RLs). Each of the multiple optical auxiliary films (OALs) can be disposed on a reflective electrode (RL) corresponding to each of the multiple optical auxiliary films (OALs). The multiple optical auxiliary films (OALs) can be made of silicon oxide (SiO2). x Inorganic membrane formation based on ) base, but this disclosure is not limited thereto.

[0194] In each of the first emission region EA1 and the third emission region EA3, a stepped layer STPL can be formed on the reflective electrode RL, and an optical auxiliary film OAL can be formed on the stepped layer STPL. In the second emission region EA2, only the optical auxiliary film OAL can be formed on the reflective electrode RL. The thickness of the optical auxiliary film OAL can be substantially the same in the first emission region EA1, the second emission region EA2, and the third emission region EA3.

[0195] Due to the stepped layer STPL, the distance between the reflective electrode RL and the first electrode AND in the first emission region EA1 and the third emission region EA3 can be larger than the distance between the reflective electrode RL and the first electrode AND in the second emission region EA2. The thickness of the stepped layer STPL and the thickness of the optical auxiliary film OAL can be determined by considering the wavelength and resonant distance of the light emitted from the first stacked layer IL1 of the light-emitting stack IL and the wavelength and resonant distance of the light emitted from the second stacked layer IL2 of the light-emitting stack IL.

[0196] Each of the light-emitting elements LE may include a first electrode AND, a light-emitting stack IL, and a second electrode CAT.

[0197] The first electrode AND of each of the light-emitting elements LE can be disposed on the optical auxiliary film OAL corresponding to each of the light-emitting elements LE. In such an embodiment, the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL are stacked sequentially, such that the first electrode AND of each of the light-emitting elements LE can be disposed on the top and side surfaces of the optical auxiliary film OAL, the side surface of the reflective electrode RL, and the side surface of the connecting electrode ANC. Therefore, the first electrode AND of each of the light-emitting elements LE can contact and be electrically connected to the side surfaces of the reflective electrode RL and the connecting electrode ANC. Therefore, compared to the case where the first electrode AND of each of the light-emitting elements LE is connected to the reflective electrode RL exposed through a through-hole penetrating the optical auxiliary film OAL, the number of mask processing steps can be reduced, thereby reducing manufacturing costs and improving manufacturing efficiency.

[0198] The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the connecting electrode ANC, the first via VA1 to the ninth via VA9, the first conductive layer ML1 to the eighth conductive layer ML8, and the contact terminal CTE.

[0199] The ninth interlayer insulating layer INS9 may include a first portion AA1 that overlaps with the connecting electrode ANC on the third-direction DR3 and a second portion AA2 that does not overlap with the connecting electrode ANC on the third-direction DR3. The thickness of the first portion AA1 and the thickness of the second portion AA2 of the ninth interlayer insulating film INS9 may be substantially the same as each other.

[0200] Alternatively, the thickness of the first portion AA1 of the ninth interlayer insulating film INS9 can be greater than the thickness of the second portion AA2 of the ninth interlayer insulating film INS9. In this case, the side surface of the first portion AA1 of the ninth interlayer insulating film INS9 can be exposed, and the first electrode AND of each of the light-emitting elements LE can be disposed on the exposed side surface of the first portion AA1 of the ninth interlayer insulating film INS9.

[0201] The first electrode AND of each of the light-emitting elements LE may comprise at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), an alloy thereof, or a transparent conductive oxide thereof, or may be formed from at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), an alloy thereof, or a transparent conductive oxide thereof. In embodiments, for example, the first electrode AND of each of the light-emitting elements LE may comprise titanium (Ti), titanium nitride (TiN), indium tin oxide (ITO), or indium zinc oxide (IZO), but this disclosure is not limited thereto.

[0202] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL can separate a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3.

[0203] The pixel-limiting film (PDL) may include a first pixel-limiting film (PDL1), a second pixel-limiting film (PDL2), a third pixel-limiting film (PDL3), and a fourth pixel-limiting film (PDL4).

[0204] The first pixel defining film PDL1 can be disposed on the first electrode AND of each of the light-emitting elements LE. Specifically, the first pixel defining film PDL1 can cover a portion of the top surface of the first electrode AND disposed on the optical auxiliary film OAL. Furthermore, the first pixel defining film PDL1 can cover the first electrode AND disposed on the side surface of the connecting electrode ANC, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary film OAL. The first pixel defining film PDL1 can be disposed on the top surface of the second portion AA2 of the ninth interlayer insulating film INS9.

[0205] The planarization film PNS is a film used to planarize the step regions caused by the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL.

[0206] The planarization film PNS can be disposed on the first pixel-defining film PDL1 covering the first electrode AND, wherein the first electrode AND is disposed on the side surface of the connecting electrode ANC, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary film OAL. The planarization film PNS can be disposed on the first pixel-defining film PDL1 disposed on the second part AA2 of the ninth interlayer insulating film INS9.

[0207] The planarization film PNS can be disposed between adjacent connecting electrodes ANC in the first direction DR1 or the second direction DR2. The planarization film PNS can be disposed between adjacent reflecting electrodes RL in the first direction DR1 or the second direction DR2. The planarization film PNS can be disposed between adjacent optical auxiliary films OAL in the first direction DR1 or the second direction DR2.

[0208] The step layer STPL is absent in the second reflective region EA2, while it exists in both the first emitting region EA1 and the third emitting region EA3. Therefore, the heights of the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL in the second emitting region EA2 can be smaller than those in the first emitting region EA1 and the third emitting region EA3. Consequently, the planarization film PNS can cover the top surface of the first pixel defining film PDL1 disposed on the top surface of the first electrode AND disposed in the second emitting region EA2.

[0209] In another embodiment, the top surface of the planarization film PNS can be planarly connected to the top surface of the first pixel defining film PDL1 disposed on the top surface of the first electrode AND disposed in the first emission region EA1 and the third emission region EA3. That is, the planarization film PNS may not cover the top surface of the first pixel defining film PDL1 disposed on the top surface of the first electrode AND disposed in each of the first emission region EA1 and the third emission region EA3.

[0210] The second pixel limiting film PDL2 can be disposed on the first pixel limiting film PDL1 and the planarization film PNS, the third pixel limiting film PDL3 can be disposed on the second pixel limiting film PDL2, and the fourth pixel limiting film PDL4 can be disposed on the third pixel limiting film PDL3. The first pixel limiting film PDL1 and the third pixel limiting film PDL3 may include silicon nitride (SiN). x Inorganic films based on silicon nitride (SiN) or made of silicon nitride (SiN) x The inorganic film is formed based on silicon dioxide (SiO2), while the second pixel defining film PDL2, the fourth pixel defining film PDL4, and the planarization film PNS may include silicon dioxide (SiO2). x Inorganic films based on silicon dioxide (SiO2) or made of silicon oxide (SiO2) x An inorganic film based on ) is formed. The first pixel defining film PDL1 is formed of a material different from that of the planarization film PNS, and therefore can be used as a stop layer in the chemical mechanical polishing process used for the planarization film PNS.

[0211] Both the planarization film PNS and the second pixel-defining film PDL2 are formed of silicon oxide (SiO2). x In the embodiment of the inorganic film based on ), the planarization film PNS and the second pixel defining film PDL2 can be formed as a single film.

[0212] Because the length of the third pixel-defining film PDL3 in one direction is smaller than that of the fourth pixel-defining film PDL4 in one direction, the bottom surface of the fourth pixel-defining film PDL4 can be exposed without being covered by the third pixel-defining film PDL3. In other words, the third pixel-defining film PDL3 and the fourth pixel-defining film PDL4 can have an eaves-shaped or mushroom-shaped cross-sectional structure.

[0213] A light-emitting stack IL can be disposed on a first electrode AND and a pixel-defining film PDL. The light-emitting stack IL can include a first stacked layer IL1 and a second stacked layer IL2 that emit different wavelengths of light. In an embodiment where the light-emitting stack IL has a dual-tandem structure, one of the first stacked layer IL1 and the second stacked layer IL2 can emit light within a wavelength range including one of a first light, a second light, and a third light, and the other can emit light within a wavelength range including two of the first, second, and third light. In an embodiment, for example, the first stacked layer IL1 can emit light including both the wavelength range of the first light and the wavelength range of the third light, and the second stacked layer IL2 can emit light including the wavelength range of the second light. Here, the first light can be blue light, the second light can be green light, and the third light can be red light.

[0214] A charge generation layer for supplying holes to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The charge generation layer may include an N-type charge generation layer for supplying electrons to the first stacked layer IL1 and a P-type charge generation layer for supplying holes to the second stacked layer IL2. The N-type charge generation layer may include a dopant of a metallic material.

[0215] In an embodiment, the first stacked layer IL1 is not formed on the bottom surface of the fourth pixel defining film PDL4 that is not covered by the third pixel defining film PDL3 and is therefore exposed, and can therefore be cut by the eaves-shaped or mushroom-shaped cross-sectional structure of the third pixel defining film PDL3 and the fourth pixel defining film PDL4. In such an embodiment, the first hole transport layer of the first stacked layer IL1 and the charge generation layer disposed between the first stacked layer IL1 and the second stacked layer IL2 can also be cut. Furthermore, although Figure 10 An embodiment is shown where the second stacked layer IL2 is connected but not disconnected; however, the second hole transport layer of the second stacked layer IL2 can be disconnected, and the second electron transport layer of the second stacked layer IL2 can be connected but not disconnected. Therefore, leakage current can be effectively prevented from flowing through the first hole transport layer of the first stacked layer IL1, the second hole transport layer of the second stacked layer IL2, and the charge generation layer between adjacent emission regions EA1, EA2, and EA3. Therefore, it is possible to effectively prevent the light-emitting stacks IL in adjacent emission regions EA1, EA2, and EA3 from emitting light other than the initially intended light due to the influence of the aforementioned current.

[0216] although Figure 10 An embodiment of a light-emitting stack IL having a dual-tandem structure in which the light-emitting stack IL comprises two stacked layers IL1 and IL2 is shown, but this disclosure is not limited thereto. In the embodiment, for example, the light-emitting stack IL may have, as Figure 9 The diagram shows a triple-cascaded structure comprising three stacked layers IL1, IL2, and IL3. In such an embodiment, the charge-generating layer between the first stacked layer IL1 and the second stacked layer IL2, as well as between the second stacked layer IL2 and the third stacked layer IL3, can be designed to be interrupted by adjusting the height of the third pixel-defining film PDL3. Alternatively, as Figure 9 As shown, a trench TRC that penetrates the first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 can be added. In this case, the trench TRC can penetrate at least a portion of the ninth interlayer insulating film INS9, but this disclosure is not limited thereto.

[0217] Figure 11 This is a schematic perspective view showing an example of a head-mounted display. Figure 12 It is shown Figure 11 The schematic exploded perspective view of the head-mounted display shown.

[0218] Reference Figure 11 and Figure 12 According to an embodiment, the head-mounted display 1000 includes a first display device 20_1, a second display device 20_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0219] The first display device 20_1 provides an image to the user's left eye, and the second display device 20_2 provides an image to the user's right eye. Because each of the first display device 20_1 and the second display device 20_2 is combined... Figures 3 to 10 The display devices 20 described are substantially the same, so any repeated detailed descriptions of the first display device 20_1 and the second display device 20_2 will be omitted.

[0220] The first optical component 1510 may be disposed between the first display device 20_1 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 20_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0221] The intermediate frame 1400 can be disposed between the first display device 20_1 and the control circuit board 1600, and between the second display device 20_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 20_1, the second display device 20_2, and the control circuit board 1600.

[0222] The control circuit board 1600 can be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 20_1 and the second display device 20_2 via connectors. The control circuit board 1600 can convert externally input image sources into digital video data and transmit the digital video data to the first display device 20_1 and the second display device 20_2 via connectors.

[0223] The control circuit board 1600 can transmit digital video data corresponding to a left-eye image optimized for the user's left eye to the first display device 20_1, and can transmit digital video data corresponding to a right-eye image optimized for the user's right eye to the second display device 20_2. Alternatively, the control circuit board 1600 can transmit the same digital video data to both the first display device 20_1 and the second display device 20_2.

[0224] The display device housing 1100 is used to house the first display device 20_1, the second display device 20_2, the intermediate frame 1400, the first optical component 1510, the second optical component 1520, and the control circuit board 1600. The housing cover 1200 is configured to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Figure 11 and Figure 12 The first eyepiece 1210 and the second eyepiece 1220 are shown separately, but this disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined into one.

[0225] The first eyepiece 1210 can be aligned with the first display device 20_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 20_2 and the second optical component 1520. Therefore, the user can view the image of the first display device 20_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 20_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0226] A headband 1300 is used to secure the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are positioned over the user's left and right eyes, respectively. In embodiments where the display device housing 1100 is intended to be lightweight and compact, the head-mounted display 1000 can be as follows: Figure 13 The image shown provides eyeglass frames instead of a headband 1300.

[0227] Figure 13This is a schematic perspective view showing another example of a head-mounted display.

[0228] Reference Figure 13 The head-mounted display 1000_1 according to an embodiment may be an eyeglass-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display 1000_1 according to an embodiment may include a display device 20_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, an optical path changing component 1070, and a display device housing 1200_1.

[0229] The display device housing 1200_1 can accommodate the display device 20_3, the optical component 1060, and the light path changing component 1070. The image displayed on the display device 20_3 can be magnified by the optical component 1060 and, after its light path is changed by the light path changing component 1070, provided to the user's right eye through the right eye lens 1020. As a result, the user can view an augmented reality image through their right eye, which combines the virtual image displayed on the display device 20_3 with the real image seen through the right eye lens 1020.

[0230] Figure 13 An embodiment is shown where the display device housing 1200_1 is located at the right end of the support frame 1030, but this disclosure is not limited thereto. In another embodiment, for example, the display device housing 1200_1 may be located at the left end of the support frame 1030, and in such an embodiment, the image displayed on the display device 20_3 can be provided to the user's left eye. Alternatively, the display device housing 1200_1 may be located at both the left and right ends of the support frame 1030, and in such an embodiment, the user can view the image displayed on the display device 20_3 through both the left and right eyes.

[0231] Figure 14 This is a schematic diagram illustrating a deposition mask and a deposition apparatus including the deposition mask according to an embodiment of the present disclosure.

[0232] Reference Figure 14 An embodiment of the deposition apparatus 2000 can be used on the display panel 100 (see [reference]). Figure 3 In the manufacturing process of [the material], a light-emitting material layer is formed on the backplate substrate 3000. In an embodiment, for example, such as... Figure 9As shown, a semiconductor backplane (SBP) and a light-emitting element backplane (EBP) can be disposed on a backplane substrate 3000, and a reflective electrode RL and interlayer insulating films INS10 and INS11 can be disposed on the light-emitting element backplane EBP. An electrode pattern (e.g., a first electrode AND serving as an anode electrode) and a pixel-defining film PDL exposing the first electrode AND can be disposed on an eleventh interlayer insulating film INS11, and the first electrode AND can be electrically connected to the reflective electrode RL through a tenth via VA10. In an embodiment, for example, a deposition apparatus 2000 can form a first light-emitting layer on the first electrode AND of a first emission region EA1. In an embodiment, for example, a deposition apparatus 2000 can form a second light-emitting layer on the first electrode AND of a second emission region EA2. In an embodiment, for example, a deposition apparatus 2000 can form a third light-emitting layer on the first electrode AND of a third emission region EA3.

[0233] The deposition apparatus 2000 may include a deposition source 2200 for providing vapor deposition material to a backing substrate 3000, a substrate chuck 2300 for supporting the backing substrate 3000 facing the deposition source 2200, and a mask chuck 2400 disposed between the deposition source 2200 and the substrate chuck 2300 for supporting a deposition mask 4000 facing the backing substrate 3000. The deposition source 2200, substrate chuck 2300, and mask chuck 2400 may be disposed in a processing chamber (or evaporation chamber) 2100.

[0234] Processing chamber 2100 may have an internal space, and the deposition process for forming a deposition material layer on the backplane substrate 3000 can be performed within the internal space of processing chamber 2100. Processing chamber 2100 may be connected to a vacuum pump (not shown), and a vacuum (or substantially low-pressure) atmosphere may be generated within the internal space of processing chamber 2100 by the vacuum pump. An opening (not shown) for loading / unloading the backplane substrate 3000 and the deposition mask 4000 may be provided on one wall of processing chamber 2100, and said opening may be opened and closed by a gate valve (not shown).

[0235] A deposition source 2200 can be disposed in a processing chamber 2100, and deposition material can be stored in the deposition source 2200. The deposition source 2200 can evaporate deposition material, such as organic, inorganic, or conductive material, toward a backplane substrate 3000, and the evaporated deposition material can be deposited on the backplane substrate 3000 through a deposition mask 4000. In an embodiment, for example, the deposition source 2200 can evaporate organic material for forming a light-emitting material layer on the backplane substrate 3000, and a heater (not shown) for evaporating the organic material can be provided. The evaporated organic material can be deposited on an electrode pattern on the backplane substrate 3000 through a deposition mask 4000. In an embodiment, such as... Figure 14 As shown, the deposition source 2200 can be disposed on the central portion of the bottom surface of the processing chamber 2100, but the deposition source 2200 can be configured to move horizontally by a separate actuator (not shown).

[0236] The substrate chuck 2300 can be disposed above the deposition source 2200 and can support the backplate substrate 3000 such that the backplate substrate 3000 faces the deposition source 2200. In an embodiment, for example, the substrate chuck 2300 can be an electrostatic chuck that uses electrostatic force to hold the rear surface of the backplate substrate 3000. Specifically, the electrode pattern (i.e., the first electrode AND) can be disposed on the front surface of the backplate substrate 3000, and the substrate chuck 2300 can hold the rear surface of the backplate substrate 3000 such that the front surface of the backplate substrate 3000 faces downward, i.e., facing the deposition source 2200.

[0237] Multiple lifting fingers 2350 for loading the backplate substrate 3000 onto the substrate chuck 2300 may be disposed in the processing chamber 2100. The lifting fingers 2350 may be disposed around the substrate chuck 2300 and the mask chuck 2400, and may be vertically moved by finger actuators 2360 respectively. In embodiments, for example, three or four lifting fingers 2350 may be disposed around the substrate chuck 2300 and the mask chuck 2400.

[0238] In one embodiment, the backplate substrate 3000 can be loaded into the processing chamber 2100 by a transfer robot (not shown) and can be transferred from the transfer robot to the lifting finger 2350 below the base chuck 2300. In such an embodiment, the rear surface of the backplate substrate 3000 can face the bottom surface of the base chuck 2300, and the lifting finger 2350 can support the front edge portion of the backplate substrate 3000. The finger actuator 2360 can raise the lifting finger 2350 so that the backplate substrate 3000 becomes adjacent to the bottom surface of the base chuck 2300, and the rear surface of the backplate substrate 3000 can be held on the bottom surface of the base chuck 2300 by electrostatic force.

[0239] Finger actuators 2360 may be disposed on the upper cover of the processing chamber 2100 and may be connected to lifting fingers 2350 via drive shafts 2362 extending vertically through the upper cover of the processing chamber 2100. Finger actuators 2360 may vertically move the lifting fingers 2350 to load or unload the backplate substrate 3000. Furthermore, finger actuators 2360 may rotate the lifting fingers 2350 relative to each of the drive shafts 2362. In an embodiment, for example, finger actuators 2360 may rotate the lifting fingers 2350 such that the ends of the lifting fingers 2350 do not overlap with the base chuck 2300 and the mask chuck 2400, thereby enabling the lifting fingers 2350 to move vertically. Additionally, finger actuators 2360 may rotate the lifting fingers 2350 such that the ends of the lifting fingers 2350 overlap with the edge portions of the backplate substrate 3000 to support the edge portions of the backplate substrate 3000.

[0240] The deposition mask 4000 can be loaded into the processing chamber 2100 by a transfer robot and can be transferred onto a lifting finger 2350 above the mask chuck 2400. An edge portion of the deposition mask 4000 can be positioned on the end of the lifting finger 2350, and a finger actuator 2360 can lower the lifting finger 2350 to load the deposition mask 4000 onto the mask chuck 2400. In an embodiment, a recess (not shown) for inserting the end of the lifting finger 2350 can be provided at an edge portion of the top surface of the mask chuck 2400, and the finger actuator 2360 can rotate the lifting finger 2350 such that the lifting finger 2350 does not overlap with the mask chuck 2400 after the deposition mask 4000 has been loaded onto the mask chuck 2400.

[0241] The mask chuck 2400 can support the edge portion of the deposition mask 4000. In an embodiment, for example, the mask chuck 2400 can be an electrostatic chuck configured to use electrostatic forces to hold the edge portion of the deposition mask 4000. In an embodiment, the mask chuck 2400 can be provided with a circular opening defined therethrough to expose the deposition mask 4000 toward the deposition source 2200. In an embodiment, for example, the mask chuck 2400 can have a disk shape or a quadrilateral plate shape with a circular opening.

[0242] The deposition apparatus 2000 may include a substrate chuck driver 2500 for moving a substrate chuck 2300 and a mask chuck driver 2600 for moving a mask chuck 2400. In an embodiment, for example, the substrate chuck driver 2500 may move the substrate chuck 2300 in a first direction DR1, a second direction DR2, and a third direction DR3 to adjust the position of the backplane substrate 3000. In such an embodiment, the first direction DR1 may be a first horizontal direction, the second direction DR2 may be a second horizontal direction perpendicular to the first direction DR1, and the third direction DR3 may be a vertical direction. That is, the first direction DR1, the second direction DR2, and the third direction DR3 may be the X-axis direction, the Y-axis direction, and the Z-axis direction, respectively.

[0243] The base chuck actuator 2500 can rotate the base chuck 2300 about the Z-axis to adjust the azimuth angle of the backplate base 3000. Furthermore, the base chuck actuator 2500 can rotate the base chuck 2300 about the X-axis and about the Y-axis to adjust the tilt of the backplate base 3000. In an embodiment, for example, the base chuck actuator 2500 may include a hexapod actuator 2510 that provides movement in six degrees of freedom (X, Y, Z, θx, θy, and θz).

[0244] The base chuck driver 2500 may include a base stage 2520 and a second actuator 2530 connected to the base stage 2520, with a hexapod actuator 2510 mounted to the base stage 2520. The base stage 2520 may be horizontally disposed within the processing chamber 2100, and the second actuator 2530 may be disposed above the processing chamber 2100. The second actuator 2530 may be connected to the base stage 2520 via a plurality of drive shafts 2532 extending through the top cover of the processing chamber 2100 in a third direction DR3 (i.e., the vertical direction (Z-axis direction)), and may move the base stage 2520 in the direction of the central axis of the hexapod actuator 2510 (i.e., the vertical direction). In embodiments, for example, the second actuator 2530 may be configured to use a brushless DC (DC) motor, a linear motor, or a direct drive (DD) motor, and the height of the base chuck 2300 may be adjustable for loading or unloading the backplane base 3000.

[0245] The hexa-legged actuator 2510 may include a first platform connected to the base chuck 2300, a second platform mounted to the base stage 2520, and six sub-actuators disposed between the first and second platforms. In embodiments, for example, the six sub-actuators may each be configured to use a brushless DC motor, a voice coil linear motor, a stepper motor, a DD motor, or a servo motor, and may move and rotate the first platform to adjust the horizontal position, vertical position, azimuth angle, and tilt of the backplate base 3000.

[0246] The mask chuck driver 2600 can move and rotate the mask chuck 2400 to adjust the horizontal position and azimuth angle of the deposition mask 4000. The mask chuck driver 2600 can move the mask chuck 2400 in a direction parallel to the deposition mask 4000 and rotate the mask chuck 2400 relative to its central axis. In an embodiment, for example, the mask chuck driver 2600 can move the mask chuck 2400 in a first direction DR1 (X-axis direction) and a second direction DR2 (Y-axis direction), and can rotate the mask chuck 2400 relative to a third direction DR3 (Z-axis direction).

[0247] The mask chuck driver 2600 may include, for example, a piezoelectric actuator 2610 that provides motion in three degrees of freedom (X, Y, and θz). The piezoelectric actuator 2610 may have an opening communicating with a circular opening in the mask chuck 2400; that is, the opening may be defined within the piezoelectric actuator 2610 to communicate with the circular opening in the mask chuck 2400. The mask chuck 2400 may be configured to be upwardly spaced from the piezoelectric actuator 2610 by a predetermined distance. In embodiments, for example, a plurality of support members 2612 may be disposed on the piezoelectric actuator 2610, and the mask chuck 2400 may be disposed on the plurality of support members 2612.

[0248] The mask chuck driver 2600 may also include a mask stage 2620 horizontally disposed in the processing chamber 2100 and supporting the piezoelectric actuator 2610. In an embodiment, for example, the mask stage 2620 may be provided with an opening communicating with the opening of the piezoelectric actuator 2610 and may be supported by a plurality of posts 2622 connected to a top cover of the processing chamber 2100.

[0249] After the backplate substrate 3000 and the deposition mask 4000 are loaded onto the substrate chuck 2300 and mask chuck 2400, respectively, the second actuator 2530 can lower the substrate chuck 2300 so that the backplate substrate 3000 is adjacent to the deposition mask 4000. The hexapod actuator 2510 can adjust the gap between the backplate substrate 3000 and the deposition mask 4000, and can adjust the tilt of the substrate chuck 2300 to adjust the parallelism between the substrate chuck 2300 and the mask chuck 2400. In an embodiment, for example, although not shown, multiple gap sensors (not shown) for measuring the gap between the substrate chuck 2300 and the mask chuck 2400 can be mounted at the substrate chuck 2300, and the hexapod actuator 2510 can adjust the parallelism between the substrate chuck 2300 and the mask chuck 2400 based on the measurements from the gap sensors.

[0250] The deposition apparatus 2000 may include a camera 2700 for acquiring positional information of the backplane substrate 3000 and the deposition mask 4000 for alignment between the backplane substrate 3000 and the deposition mask 4000. In embodiments, for example, although not shown in the figures, a substrate alignment key (not shown) may be disposed in an edge portion of the backplane substrate 3000, and a mask alignment key (not shown) may be disposed in an edge portion of the deposition mask 4000. The deposition apparatus 2000 may include a camera 2700 for detecting the substrate alignment key and the mask alignment key, and a substrate chuck driver 2500 or a mask chuck driver 2600 may align the backplane substrate 3000 and the deposition mask 4000 with each other based on the positional information of the substrate alignment key and the mask alignment key obtained by the camera 2700.

[0251] Figure 15 It is shown Figure 14 A schematic bottom view of the backplate base shown.

[0252] Reference Figure 15 An embodiment of the back panel base 3000 may include a plurality of display unit areas 3010 and scribe lines 3020 disposed between the display unit areas 3010. For example... Figure 15 As shown, the display unit area 3010 can be arranged in a matrix along the first direction DR1 and the second direction DR2, and can be individualized into the display panel 100 by a cutting process after the display manufacturing process is completed (see...). Figure 3 In an embodiment, for example, the first direction DR1 may be a first horizontal direction, and the second direction DR2 may be a second horizontal direction perpendicular to the first direction DR1. Furthermore, each of the display unit areas 3010 may have a quadrilateral shape, for example, as shown in the accompanying drawings.

[0253] In an embodiment, for example, such as Figure 9 As shown, each of the display unit regions 3010 may include a semiconductor backplane SBP, a light-emitting element backplane EBP disposed on the semiconductor backplane SBP, a reflective electrode RL disposed on the light-emitting element backplane EBP, and interlayer insulating films INS10 and INS11 disposed on the reflective electrode RL. Furthermore, each of the display unit regions 3010 may include multiple electrode patterns (e.g., multiple first electrodes AND disposed on the eleventh interlayer insulating film INS11), and the first electrodes AND can be connected to the reflective electrode RL through multiple tenth vias VA10. In this case, the electrode patterns of the display unit regions 3010 can be disposed on the front surface of the backplane substrate 3000, and the substrate chuck 2300 can hold the rear surface of the backplane substrate 3000 such that the electrode patterns of the display unit regions 3010 face downwards, i.e., facing the deposition source 2200.

[0254] Figure 16 It is shown Figure 14 A schematic plan view of the deposition mask shown. Figure 17 It is shown Figure 16 The diagram shows a schematic plan view of the mask unit area. Figure 18 It is along Figure 17 The diagram shows a schematic cross-section taken by line I2-I2'. Figure 19 It is shown Figure 17 The diagram shows an enlarged plan view of the dummy area. Figure 20 It is shown Figure 18 The diagram shows an enlarged cross-sectional view of the dummy region.

[0255] Reference Figures 16 to 20 An embodiment of the deposition mask 4000 may include a backplane substrate 3000 (see [link to documentation]). Figure 15 The display unit area 3010 (see) Figure 15 The mask unit region 4310. Each of the mask unit regions 4310 may be provided with a plurality of pixel openings 4312 defined therethrough to expose the first electrode AND of the backplane substrate 3000 in the deposition process. Figure 9 In an embodiment, for example, the deposition mask 4000 may include a mask frame 4100, an intermediate inorganic film 4200 disposed on the mask frame 4100, and a diaphragm 4300 disposed on the intermediate inorganic film 4200. In such an embodiment, the diaphragm 4300 may include a plurality of mask unit regions 4310, and each of the mask unit regions 4310 may be provided with a plurality of pixel openings 4312 defined therethrough.

[0256] The mask frame 4100 may have cell openings 4110 corresponding to the mask cell regions 4310, and may include a first rib region 4120 defining the cell openings 4110. The intermediate inorganic film 4200 may have intermediate openings 4210 defined on the cell openings 4110, and includes a second rib region 4220 defining the intermediate openings 4210. In an embodiment, the intermediate openings 4210 may be defined through the intermediate inorganic film 4200 between the cell openings 4110 and the mask cell regions 4310. In an embodiment, the mask cell regions 4310 of the diaphragm 4300 may be respectively disposed above the intermediate openings 4210, and the pixel openings 4312 of the diaphragm 4300 may communicate with the cell openings 4110 through the intermediate openings 4210. That is, the mask cell regions 4310 of the diaphragm 4300 may face the deposition source 2200 (see [reference]) through the cell openings 4110 of the mask frame 4100 and the intermediate openings 4210 of the intermediate inorganic film 4200. Figure 14 The pixel opening 4312 is exposed and can be formed as a penetrating mask unit area 4310.

[0257] In an embodiment, such as Figure 16 As shown, the mask unit regions 4310 can be arranged in a matrix along a first direction DR1 and a second direction DR2. In an embodiment, for example, the first direction DR1 can be a first horizontal direction, and the second direction DR2 can be a second horizontal direction perpendicular to the first horizontal direction. In an embodiment, the mask unit regions 4310 can be arranged to correspond respectively to the display unit regions 3010 of the backplane substrate 3000, and each of the mask unit regions 4310 can have, for example, the following characteristics. Figure 16 The quadrilateral shape shown.

[0258] In an embodiment, such as Figure 18 As shown, the intermediate inorganic film 4200 and the diaphragm 4300 can be disposed on the front surface of the mask frame 4100, and the first rear inorganic film 4400 and the second rear inorganic film 4500 can be disposed on the rear surface of the mask frame 4100. In an embodiment, for example, the first rear inorganic film 4400 can be disposed on the rear surface of the mask frame 4100, and the second rear inorganic film 4500 can be disposed on the first rear inorganic film 4400. The first rear inorganic film 4400 and the second rear inorganic film 4500 can each be provided with a first rear opening 4410 and a second rear opening 4510 communicating with the unit opening 4110, and can be used as an etching mask in the etching process for forming the unit opening 4110. In such an embodiment, the mask unit region 4310 can be exposed toward the deposition source 2200 through the intermediate opening 4210, the unit opening 4110, the first rear opening 4410, and the second rear opening 4510.

[0259] In embodiments, for example, the intermediate inorganic film 4200 may comprise the same material as the first post-inorganic film 4400, or be made of the same material as the first post-inorganic film 4400, and the diaphragm 4300 may comprise the same material as the second post-inorganic film 4500, or be made of the same material as the second post-inorganic film 4500. In embodiments, the diaphragm 4300 may comprise a material having etch selectivity relative to the intermediate inorganic film 4200 and the mask frame 4100, or be made of a material having etch selectivity relative to the intermediate inorganic film 4200 and the mask frame 4100. In embodiments, for example, the mask frame 4100 may be made of silicon (Si), and the intermediate inorganic film 4200 may comprise silicon oxide (SiO2). x ) or made of silicon dioxide (SiO) x It is made of silicon nitride (SiN), and the separator 4300 may include silicon nitride (SiN). x ) or made of silicon nitride (SiN) x Made from ).

[0260] The pixel opening 4312 of the diaphragm 4300 can be formed by an anisotropic etching process (e.g., reactive ion etching (RIE) process). In an embodiment, for example, after forming a photoresist pattern on the diaphragm 4300 that exposes the portion where the pixel opening 4312 will form, a RIE process using the photoresist pattern as an etching mask can be performed to form the pixel opening 4312 that exposes the intermediate inorganic film 4200. In such an embodiment, the intermediate inorganic film 4200 can be used as an etch stop film in the RIE process.

[0261] The first rear opening 4410 and the second rear opening 4510 can be formed by an anisotropic etching process (e.g., RIE process). In an embodiment, for example, after forming a photoresist pattern on the second rear inorganic film 4500 that exposes the portion where the second rear opening 4510 will be formed, a RIE process using the photoresist pattern as an etching mask can be performed to form the first rear opening 4410 and the second rear opening 4510 that expose the rear surface of the mask frame 4100.

[0262] Cell openings 4110 of the mask frame 4100 can be formed to expose the intermediate inorganic film 4200 using an anisotropic etching process that employs a first post-inorganic film 4400 and a second post-inorganic film 4500 as etching masks. In an embodiment, for example, a monocrystalline silicon substrate can be used as the mask frame 4100, and the cell openings 4110 can be formed by a wet etching process using an etchant containing tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH). In this case, the monocrystalline silicon substrate used as the mask frame 4100... <100> The crystal orientation can be a third orientation DR3 perpendicular to the first direction DR1 and the second direction DR2, and therefore, the cell opening 4110 can have a width that gradually decreases from the rear surface of the mask frame 4100 toward the front surface of the mask frame 4100 by the aforementioned wet etching process. In an embodiment, for example, the inner surface of the cell opening 4110 can have an inclination of approximately 54.74° relative to the rear surface of the mask frame 4100. That is, as Figure 18 As shown, the upper width of the unit opening 4110 adjacent to the intermediate inorganic membrane 4200 can be smaller than the lower width adjacent to the first rear inorganic membrane 4400 of the unit opening 4110.

[0263] The intermediate opening 4210 of the intermediate inorganic film 4200 can be formed by a wet etching process after the unit opening 4110 of the mask frame 4100 is formed. In an embodiment, for example, when the intermediate inorganic film 4200 is made of silicon oxide (SiO2), the intermediate opening 4210 is formed by a wet etching process. xDuring fabrication, the intermediate opening 4210 can be formed by a wet etching process using buffer oxide etchant (BOE) or diluted hydrofluoric acid (diluted HF). As a result, the pixel opening 4312 of the diaphragm 4300 can communicate with the unit opening 4110 of the mask frame 4100 through the intermediate opening 4210 of the intermediate inorganic film 4200.

[0264] According to embodiments of this disclosure, the diaphragm 4300 may include dummy regions 4330 surrounding the mask unit regions 4310 and grid regions 4320 defining the dummy regions 4330. In embodiments, for example, the dummy regions 4330 may have a quadrilateral ring shape, each surrounding one of the mask unit regions 4310, and the grid regions 4320 may be disposed between the dummy regions 4330. That is, the dummy regions 4330 may be disposed between the mask unit regions 4310 and the grid regions 4320. In embodiments, the mask unit regions 4310 of the diaphragm 4300 may be disposed above the unit openings 4110 of the mask frame 4100, and the grid regions 4320 and the dummy regions 4330 may be disposed above the first rib region 4120 of the mask frame 4100. In such an embodiment, the grid region 4320 of the diaphragm 4300 may be disposed on the second rib region 4220 of the intermediate inorganic membrane 4200, and the dummy region 4330 may be spaced apart from the first rib region 4120 of the mask frame 4100 by the thickness of the intermediate inorganic membrane 4200.

[0265] The diaphragm 4300 may have a dummy opening 4332 penetrating the dummy region 4330. The dummy opening 4332 may be formed simultaneously with the pixel opening 4312. In an embodiment, for example, after forming a photoresist pattern on the diaphragm 4300 that exposes the portions that will form the pixel opening 4312 and the dummy opening 4332, a RIE process using the photoresist pattern as an etch mask can be performed to form the pixel opening 4312 and the dummy opening 4332 that expose the intermediate inorganic film 4200. In such an embodiment, the intermediate inorganic film 4200 can be used as an etch stop film in the RIE process.

[0266] In the embodiment where the diaphragm 4300 is provided with a dummy opening 4332 as described above, the pixel opening 4312 and the dummy opening 4332 can serve as pathways for providing etchant to the intermediate inorganic film 4200 during a wet etching process for forming the intermediate opening 4210. Therefore, the portion of the intermediate inorganic film 4200 positioned between the dummy region 4330 of the diaphragm 4300 and the first rib region 4120 of the mask frame 4100 can be removed. Thus, as... Figure 18 and Figure 20 As shown, an annular groove 4212 can be formed between the dummy area 4330 of the diaphragm 4300 and the first rib area 4120 of the mask frame 4100.

[0267] The dummy region 4330 of the diaphragm 4300 and the first rib region 4120 of the mask frame 4100 can be spaced apart from each other by a groove 4212. That is, the intermediate opening 4210 can overlap with the dummy region 4330 of the diaphragm 4300 and the first rib region 4120 of the mask frame 4100 on a third-direction DR3 to define a groove 4212 formed between the dummy region 4330 of the diaphragm 4300 and the first rib region 4120 of the mask frame 4100, and therefore, the intermediate opening 4210 can have a larger width than the unit opening 4110. In an embodiment, the intermediate opening 4210 can have a width larger than the upper width of the unit opening 4110. Furthermore, the groove 4212 of the intermediate opening 4210 can be defined by the dummy area 4330 of the diaphragm 4300, the first rib area 4120 of the mask frame 4100 and the second rib area 4220 of the intermediate inorganic membrane 4200, and the dummy area 4330 of the diaphragm 4300 can be disposed above the groove 4212 of the intermediate opening 4210.

[0268] For example, such as Figure 19 As shown, the dummy opening 4332 may have the same shape and size as the pixel opening 4312, and may be arranged in the same pattern as the pixel opening 4312. However, the shape, size, and arrangement of the dummy opening 4332 may be varied, and the scope of this disclosure is not limited thereto. In embodiments, for example, a circular or quadrilateral through-hole or through-slot extending in the first direction DR1 or the second direction DR2 may be used as the dummy opening 4332, and the size and arrangement of the dummy opening 4332 may be configured to differ from the size and arrangement of the pixel opening 4312.

[0269] According to embodiments of this disclosure, the dummy region 4330 and the dummy opening 4332 can be used to reduce the warpage of the deposition mask 4000. In embodiments, for example, the diaphragm 4300 and the second post-inorganic film 4500 can be made of silicon nitride (SiN). x It is made of [material name missing] and can be formed simultaneously by a thermochemical vapor deposition (TCVD) process. In such an embodiment, the diaphragm 4300 and the second post-inorganic film 4500 can have the same area and thickness, and therefore, the diaphragm 4300 and the second post-inorganic film 4500 can have the same residual tensile stress. However, after forming the pixel opening 4312, the second post-opening 4510 and the cell opening 4110, the area of ​​the diaphragm 4300 may become larger than the area of ​​the second post-inorganic film 4500, which may cause warping in the deposition mask 4000.

[0270] According to embodiments of this disclosure, the area of ​​the diaphragm 4300 can be reduced by using dummy regions 4330 and dummy openings 4332, thereby reducing warpage of the deposition mask 4000. In an embodiment, during the formation of the intermediate opening 4210, a groove 4212 can be formed between the dummy region 4330 of the diaphragm 4300 and the first rib region 4120 of the mask frame 4100, thereby reducing the area of ​​the second rib region 4220 of the intermediate inorganic membrane 4200. Furthermore, the area of ​​the mesh region 4320 disposed on the second rib region 4220 of the intermediate inorganic membrane 4200 can be reduced. As a result, the force exerted from the diaphragm 4300 on the mask frame 4100 due to residual tensile stress in the diaphragm 4300 can be reduced, thereby reducing warpage of the deposition mask 4000.

[0271] The area of ​​the dummy region 4330 can be adjusted in such a way that the area of ​​the mask removal unit region 4310 of the diaphragm 4300 and the remaining area of ​​the dummy region 4330 becomes substantially equal to the area of ​​the second post-inorganic membrane 4500 having the second post-opening 4510. In an embodiment, for example, the width of the dummy region 4330 can be adjusted to tens to hundreds of micrometers (μm). In such an embodiment, the force applied from the diaphragm 4300 to the mask frame 4100 and the force applied from the second post-inorganic membrane 4500 to the mask frame 4100 can be balanced against each other, and therefore, the warpage of the deposition mask 4000 can be reduced.

[0272] The diaphragm 4300 and the second post-inorganic membrane 4500, as described above, include silicon nitride (SiN). x ) or made of silicon nitride (SiN) x In embodiments made of [material name], the intermediate inorganic film 4200 and the first post-inorganic film 4400 may comprise silicon oxide (SiO2). x Or made of silicon dioxide (SiO) x It is manufactured using [the process described]. In embodiments, for example, the intermediate inorganic film 4200 and the first post-inorganic film 4400 can be formed simultaneously by a thermal oxidation process, and in this case, the intermediate inorganic film 4200 and the first post-inorganic film 4400 may have residual compressive stress. According to embodiments of the present disclosure, after forming the intermediate opening 4210, the area of ​​the intermediate inorganic film 4200 can become substantially equal to the area of ​​the first post-inorganic film 4400 having the first post-opening 4410. That is, the area of ​​the intermediate inorganic film 4200 with the intermediate opening 4210 and the area of ​​the first post-inorganic film 4400 with the first post-opening 4410 can become substantially equal to each other, thereby reducing the warpage of the deposition mask 4000.

[0273] In an embodiment, when a deposition material layer is formed on a backing substrate 3000 using a deposition mask 4000, a deposition material layer (not shown) may also be formed on the deposition mask 4000. The deposition material layer formed on the deposition mask 4000 as described above can be removed by an ultrasonic cleaning process. In an embodiment, for example, the deposition material layer on the deposition mask 4000 can be removed by an ultrasonic cleaning process using an N-methyl-2-pyrrolidone (NMP) cleaning solution, and ultrasonic vibration can be applied to the deposition mask 4000 while performing the ultrasonic cleaning process. In this case, secondary vibration may occur in the mask unit region 4310 of the diaphragm 4300 due to ultrasonic vibration, and there is a concern that the mask unit region 4310 may be damaged by the secondary vibration. However, according to an embodiment of this disclosure, the mask unit region 4310 of the diaphragm 4300 may be spaced apart from the mask frame 4100 by a groove 4212 of the intermediate opening 4210. Therefore, even if secondary vibrations occur in the mask unit region 4310 of the diaphragm 4300 due to ultrasonic vibrations during the ultrasonic cleaning process, the damping force applied to the mask unit region 4310 from the mask frame 4100 can be reduced by the groove 4212 of the intermediate opening 4210. As a result, damage to the mask unit region 4310 caused by ultrasonic vibrations can be reduced. In this case, the dummy region 4330 of the diaphragm 4300 can be used as a buffer to prevent damage to the mask unit region 4310 caused by ultrasonic vibrations.

[0274] In another embodiment, for example, one of the first post-inorganic film 4400 and the second post-inorganic film 4500 may be omitted. That is, it includes silicon oxide (SiO2). x ) or silicon nitride (SiN) x Or made of silicon dioxide (SiN) x ) or silicon nitride (SiN) x A post-inorganic membrane (not shown) can be disposed on the rear surface of the mask frame 4100. In such an embodiment, the post-inorganic membrane can be formed separately from the diaphragm 4300 and the intermediate inorganic membrane 4200, and the residual stress of the post-inorganic membrane can be adjusted such that the forces applied to the mask frame 4100 by the diaphragm 4300 and the intermediate inorganic membrane 4200 and the forces applied to the mask frame 4100 by the post-inorganic membrane are balanced against each other.

[0275] In another embodiment, for example, both the first and second post-inorganic films 4400 and 4500 can be omitted, and a post-inorganic film (not shown) made of a different material than the first and second post-inorganic films 4400 can be provided on the rear surface of the mask frame 4100. In this embodiment, for example, a post-inorganic film made of an inorganic material such as silicon oxynitride (SiON), metal oxide, or metal nitride can be provided on the rear surface of the mask frame 4100. In this case, the residual stress of the post-inorganic film can be adjusted such that the force applied to the mask frame 4100 by the diaphragm 4300 and the intermediate inorganic film 4200 is balanced with the force applied to the mask frame 4100 by the post-inorganic film.

[0276] Figure 21 This is a schematic plan view illustrating a deposition mask according to another embodiment of the present disclosure. Figure 22 It is shown Figure 21 A schematic cross-sectional view of the second dummy opening shown.

[0277] Reference Figure 21 and Figure 22 According to another embodiment of the present disclosure, a deposition mask 4000 may include a mask frame 4100, an intermediate inorganic film 4200 disposed on the front surface of the mask frame 4100, a diaphragm 4300 disposed on the intermediate inorganic film 4200, a first rear inorganic film 4400 disposed on the rear surface of the mask frame 4100, and a second rear inorganic film 4500 disposed on the first rear inorganic film 4400. The mask frame 4100 may be provided with a cell opening 4110 and may include a first rib region 4120 defining the cell opening 4110 (see [link to documentation]). Figure 18 The diaphragm 4300 may include a pixel opening 4312 (see [reference]). Figure 18 The mask unit area 4310 is provided with a dummy opening 4332 (see [reference]). Figure 18 The dummy region 4330 and the grid region 4320 disposed between the dummy regions 4330. The intermediate inorganic membrane 4200 may have an intermediate opening 4210 and may include a second rib region 4220 defining the intermediate opening 4210 (see Figure 18 The first post-inorganic membrane 4400 and the second post-inorganic membrane 4500 may each be provided with a first post-opening 4410 (see...). Figure 18 ) and the second rear opening 4510 (see Figure 18 ).

[0278] According to an embodiment, the diaphragm 4300 may be provided with a second dummy opening 4340 defined through its edge region, and the intermediate inorganic membrane 4200 may be provided with a second intermediate opening 4230 communicating with the second dummy opening 4340 and exposing the mask frame 4100. In such an embodiment, the remaining components, except for the second dummy opening 4340 of the diaphragm 4300 and the second intermediate opening 4230 of the intermediate inorganic membrane 4200, are the same as those described above. Figures 16 to 20 The components described are essentially the same, and therefore, any repeated detailed descriptions of them will be omitted.

[0279] A second dummy opening 4340 in the diaphragm 4300 and a second intermediate opening 4230 in the intermediate inorganic membrane 4200 can be provided to reduce warpage of the deposition mask 4000. Specifically, if the width of the dummy region 4330 of the diaphragm 4300 is excessively increased, the rigidity of the mask unit region 4310 may decrease, which could cause the mask unit region 4310 to sag during the deposition process due to its own weight. The second dummy opening 4340 in the diaphragm 4300 can reduce the width of the dummy region 4330, thereby reducing the sag of the mask unit region 4310. In an embodiment, for example, when the diaphragm 4300 has a second dummy opening 4340, the dummy region 4330 may have a width in the range of about 50 μm to about 200 μm, and the area of ​​the remaining area of ​​the mask removal unit region 4310, the dummy region 4330 and the second dummy opening 4340 of the diaphragm 4300 may be the same as the area of ​​the second post inorganic membrane 4500 having a second post opening 4510.

[0280] The second dummy opening 4340 of the diaphragm 4300 can be formed simultaneously with the pixel opening 4312 and the dummy opening 4332. In an embodiment, for example, a photoresist pattern exposing the portions that will form the pixel opening 4312, the dummy opening 4332, and the second dummy opening 4340 can be formed on the diaphragm 4300, and an anisotropic etching process (e.g., RIE process) using the photoresist pattern as an etching mask can be performed to form the pixel opening 4312, the dummy opening 4332, and the second dummy opening 4340 exposing the intermediate inorganic film 4200. In this case, the intermediate inorganic film 4200 can be used as an etch stop film in the RIE process.

[0281] The second intermediate opening 4230 of the intermediate inorganic film 4200 can be formed simultaneously with the intermediate opening 4210 via a wet etching process after the formation of the unit opening 4110. In an embodiment, for example, when the intermediate inorganic film 4200 is made of silicon oxide (SiO2), xDuring fabrication, the intermediate opening 4210 and the second intermediate opening 4230 can be formed by a wet etching process using BOE or diluted HF. In this case, the area of ​​the intermediate inorganic film 4200 with the intermediate opening 4210 and the second intermediate opening 4230 can be the same as the area of ​​the first post inorganic film 4400 with the first post opening 4410, and therefore, the warpage of the deposition mask 4000 can be reduced.

[0282] According to the embodiment, global warpage (referring to the overall deformation of the deposition mask 4000) can be reduced by the dummy region 4330, the second dummy opening 4340, and the second intermediate opening 4230. Furthermore, unit warpage (referring to the deformation of the mask unit region 4310) and damage to the mask unit region 4310 can be mitigated by the grooves 4212 of the dummy region 4330 and the intermediate opening 4210 (see...). Figure 18 (to reduce)

[0283] Figure 23 It is shown Figure 21 A schematic enlarged plan view of another example of the second dummy opening shown. Figure 24 It is shown Figure 21 A schematic enlarged plan view of yet another example of the second illusory opening shown.

[0284] Reference Figure 23 and combined Figure 18 In this embodiment, the diaphragm 4300 may be provided with annular second dummy openings 4342 surrounding the dummy region 4330, and the intermediate inorganic membrane 4200 may be provided with annular second intermediate openings (not shown) communicating with the second dummy openings 4342 and exposing the mask frame 4100. In this case, the second dummy openings 4342 may be spaced apart from the dummy region 4330 by a predetermined distance and may be formed as a mesh region 4320 penetrating the diaphragm 4300. Furthermore, the second dummy openings 4342 and the second intermediate opening may expose a portion of the first rib region 4120 of the mask frame 4100. That is, the second intermediate opening may be formed to overlap with the second rib region 4220 of the intermediate inorganic membrane 4200. The method of forming the second dummy openings 4342 and the second intermediate opening is the same as described above. Figure 21 and Figure 22 The methods of description are essentially the same, and therefore, any repeated detailed descriptions will be omitted.

[0285] Reference Figure 24 , combined Figure 18The diaphragm 4300 may have a second dummy opening 4344 extending parallel to each other in a first direction DR1 and a third dummy opening 4346 extending parallel to each other in a second direction DR2. In an embodiment, for example, the second dummy opening 4344 and the third dummy opening 4346 may be formed through the mesh region 4320 of the diaphragm 4300 and may intersect each other to form a mesh shape. The intermediate inorganic membrane 4200 may have a second intermediate opening (not shown) communicating with the second dummy opening 4344 and exposing the mask frame 4100, and a third intermediate opening (not shown) communicating with the third dummy opening 4346 and exposing the mask frame 4100. That is, the second intermediate opening and the third intermediate opening may be formed through the second rib region 4220 of the intermediate inorganic membrane 4200, and the second dummy opening 4344 and the third dummy opening 4346, as well as the second intermediate opening and the third intermediate opening, may expose the first rib region 4120 of the mask frame 4100. The methods for forming the second dummy opening 4344 and the third dummy opening 4346, as well as the second intermediate opening and the third intermediate opening, are the same as those described above. Figure 21 and Figure 22 The methods of description are essentially the same, and therefore, any repeated detailed descriptions will be omitted.

[0286] Figure 25 This is a schematic cross-sectional view showing a deposition mask according to yet another embodiment of the present disclosure.

[0287] Reference Figure 25 According to another embodiment of the present disclosure, a deposition mask 4000 may include a mask frame 4100, a diaphragm 4300 disposed on a front surface of the mask frame 4100, and a second rear inorganic film 4500 disposed on a rear surface of the mask frame 4100. The mask frame 4100 may be provided with cell openings 4110 and may include rib regions defining the cell openings 4110. The diaphragm 4300 may include mask cell regions 4310 provided with pixel openings 4312, dummy regions 4330 provided with dummy openings 4332, and grid regions 4320 disposed between the dummy regions 4330. The second rear inorganic film 4500 may be provided with a second rear opening 4510 communicating with the cell openings 4110.

[0288] According to the embodiment, the deposition mask 4000 may have an intermediate inorganic film 4200 omitted (see...). Figure 18 ) and the first post-inorganic membrane 4400 (see Figure 18 The structure of the mask frame 4100, the unit opening 4110, and the rib region can be integrated with the structure of the mask frame 4100, the unit opening 4110, and the rib region. Figure 18 The mask frame 4100, unit opening 4110, and first rib region 4120 shown are substantially the same, and the second rear inorganic membrane 4500 and the second rear opening 4510 can be... Figure 18 The second post-inorganic membrane 4500 and the second post-opening 4510 shown are substantially the same.

[0289] According to an embodiment, the mask unit region 4310 of the diaphragm 4300 can be exposed through the unit opening 4110 of the mask frame 4100, and therefore, the pixel opening 4312 can communicate directly with the unit opening 4110. The dummy region 4330 of the diaphragm 4300 can be defined to surround the mask unit region 4310, and the dummy opening 4332 can be provided to expose the front surface of the mask frame 4100. Specifically, according to an embodiment, the diaphragm 4300 can be provided with a second dummy opening 4340 that exposes the front portion of the mask frame 4100 through the edge portion of the diaphragm 4300. In such an embodiment, the area of ​​the remaining area of ​​the diaphragm 4300 excluding the mask unit region 4310, the dummy opening 4332, and the second dummy opening 4340 can be the same as the area of ​​the second rear inorganic film 4500 having the second rear opening 4510, and therefore, the warpage of the deposition mask 4000 can be reduced.

[0290] In another embodiment, for example, although not shown in the drawings, the diaphragm 4300 may be provided with Figure 23 The second dummy opening 4342 is shown in the figure. In this case, the rib area of ​​the mask frame 4100 can be exposed through the second dummy opening 4342. In another embodiment, for example, although not shown in the figures, the diaphragm 4300 may be provided with Figure 24 The second dummy opening 4344 and the third dummy opening 4346 are shown. In such an embodiment, the rib area of ​​the mask frame 4100 can be exposed through the second dummy opening 4344 and the third dummy opening 4346.

[0291] Figures 26 to 31 This is a schematic cross-sectional view illustrating a method for manufacturing a deposition mask according to an embodiment of the present disclosure.

[0292] Reference Figure 26 In an embodiment of the method for manufacturing a deposition mask, an intermediate inorganic film 4200 may be formed on a mask substrate 4010. The mask substrate 4010 may be made of monocrystalline silicon. In an embodiment, for example, a monocrystalline silicon substrate having a thickness in the range of about 700 μm to about 800 μm (e.g., about 775 μm) may be used as the mask substrate 4010, and the mask substrate 4010 may be used as the mask frame 4100 of the deposition mask 4000 (see [link to documentation]). Figure 18 ).

[0293] For example, the intermediate inorganic film 4200 can be made of silicon oxide (SiO2). xThe inorganic film 4400 is formed on the front surface of the mask substrate 4010 by a thermal oxidation process to a thickness ranging from about 0.3 μm to about 2 μm. Furthermore, a first post-inorganic film 4400 can be formed on the rear surface of the mask substrate 4010. In an embodiment, for example, the first post-inorganic film 4400 can be formed simultaneously with the intermediate inorganic film 4200 by a thermal oxidation process. Therefore, the first post-inorganic film 4400 can be made of the same material as the intermediate inorganic film 4200 and can have the same thickness as the intermediate inorganic film 4200.

[0294] Reference Figure 27 In embodiments of the method for fabricating a deposition mask, a separator 4300 may be formed on the intermediate inorganic film 4200. In embodiments, for example, the separator 4300 may include or contain silicon nitride (SiN). x It can be formed by a TCVD process. In the embodiments, a silicon source gas such as silane (SiH4), disilane (Si2H6) or dichlorosilane (DCS) (SiH2Cl2) and a nitrogen source gas such as N2 or NH3 can be supplied to the intermediate inorganic membrane 4200, and the membrane 4300 can be formed with a thickness ranging from about 0.3 μm to about 3 μm by the reaction between the silicon source gas and the nitrogen source gas.

[0295] A second inorganic film 4500 can be formed on the first inorganic film 4400. The second inorganic film 4500 can be made of silicon nitride (SiN). x It is made of the same material and can be formed by a TCVD process. In an embodiment, for example, the diaphragm 4300 and the second post-inorganic membrane 4500 can be formed simultaneously by a TCVD process. Therefore, the second post-inorganic membrane 4500 can be made of the same material as the diaphragm 4300 and can have the same thickness as the diaphragm 4300.

[0296] Reference Figure 28 In embodiments of the method for fabricating a deposition mask, the diaphragm 4300 may be patterned to form pixel openings 4312 and dummy openings 4332. In embodiments, the diaphragm 4300 may include components corresponding to the backplane substrate 3000 (see [link to documentation]). Figure 14 The display unit area 3010 (see) Figure 15 The mask unit region 4310 and the dummy region 4330 surrounding the mask unit region 4310 are respectively formed through the mask unit region 4310 and the dummy region 4330. That is, the pixel opening 4312 and the dummy opening 4332 can be formed in a way that partially exposes the intermediate inorganic film 4200.

[0297] In an embodiment, for example, a photoresist pattern can be formed on the diaphragm 4300 to expose portions that will form pixel openings 4312 and dummy openings 4332, and then an anisotropic etching process (e.g., RIE process) using the photoresist pattern as an etching mask can be performed to form pixel openings 4312 and dummy openings 4332 through mask unit regions 4310 and dummy regions 4330. The diaphragm 4300 is made of silicon nitride (SiN). x In embodiments where this is done, the RIE process can be performed using a first reactive gas containing fluorine (such as CF4, C2F4, C2F6, C3F6, C3F8, C4F6, C4F8, CH3F, CH2F2, C2HF5, CHF3, NF3, or SF6), a second reactive gas containing oxygen (such as O2, NO, or NO2), and a sputtering gas (such as He, Ne, Ar, or Xe) until the intermediate inorganic film 4200 is exposed. In such embodiments, the intermediate inorganic film 4200 can be used as an etch stop film in the RIE process.

[0298] According to yet another embodiment of this disclosure, such as Figure 21 and Figure 22 As shown, a second dummy opening 4340 can be formed through the edge portion of the diaphragm 4300. In an embodiment, for example, the second dummy opening 4340 can be formed simultaneously with the pixel opening 4312 and the dummy opening 4332. In this case, a photoresist pattern exposing the portions that will form the pixel opening 4312, the dummy opening 4332, and the second dummy opening 4340 can be formed on the diaphragm 4300, and an anisotropic etching process using the photoresist pattern as an etching mask can be performed until the intermediate inorganic film 4200 is exposed.

[0299] In another embodiment, for example, such as Figure 23 As shown, a second dummy opening 4342 can be formed to surround the dummy region 4330. In another embodiment, for example, as... Figure 24 As shown, a second dummy opening 4344 and a third dummy opening 4346 can be formed to extend between dummy regions 4330 in the first direction DR1 and the second direction DR2.

[0300] Reference Figure 29 and Figure 30 In embodiments of the method for manufacturing a deposition mask, the mask substrate 4010 may be patterned to form a mask frame 4100 having unit openings 4110. In embodiments, for example, such as... Figure 29As shown, a first rear opening 4410 and a second rear opening 4510 can be formed to expose the rear portion of the mask substrate 4010 that will form the unit opening 4110. In an embodiment, for example, after forming a photoresist pattern (not shown) on the second rear inorganic film 4500 that exposes the portion where the second rear opening 4510 will be formed, the photoresist pattern can be used as an etching mask to perform an anisotropic etching process such as a RIE process. The anisotropic etching process can be performed until the rear portion of the mask substrate 4010 (i.e., the portion where the unit opening 4110 will be formed) is exposed, and as a result, the first rear opening 4410 and the second rear opening 4510 penetrating the first rear inorganic film 4400 and the second rear inorganic film 4500 can be formed.

[0301] The unit opening 4110 can be formed using a wet etching process. In an embodiment, for example, as... Figure 30 As shown, the mask substrate 4010 can be partially removed to expose the intermediate inorganic film 4200 by a first wet etching process using a first post-inorganic film 4400 and a second post-inorganic film 4500 as etching masks, and a mask frame 4100 having a plurality of unit openings 4110 can be formed by the process. Furthermore, the first rib region 4120 defining the unit openings 4110 can be formed by the first wet etching process by partially removing the mask substrate 4010. In an embodiment, for example, an etchant containing tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH) can be used to perform the first wet etching process.

[0302] In the embodiment, a single-crystal silicon substrate is used as the mask substrate 4010. <100> The crystal orientation can be a third orientation DR3, and therefore, the cell opening 4110 can be formed with a width that gradually decreases from the rear surface of the mask substrate 4010 toward the front surface of the mask substrate 4010 by a first wet etching process. In an embodiment, for example, the inner surface of the cell opening 4110 can be formed with an inclination of about 54.74° relative to the rear surface of the mask substrate 4010.

[0303] Reference Figure 31In an embodiment of the method for manufacturing a deposition mask, the intermediate inorganic film 4200 may be patterned to form an intermediate opening 4210 for connecting pixel openings 4312 to cell openings 4110. The intermediate opening 4210 may be formed such that the mask cell regions 4310 of the diaphragm 4300 are exposed through the cell openings 4110. The intermediate opening 4210 may be formed by a wet etching process. In an embodiment, for example, the intermediate opening 4210 may be formed by a second wet etching process using BOE or diluted hydrofluoric acid, etc. In this case, the pixel openings 4312 and dummy openings 4332 may serve as pathways for providing etchant to the intermediate inorganic film 4200, and thus, an annular groove 4212 may be formed between the dummy region 4330 of the diaphragm 4300 and the first rib region 4120 of the mask frame 4100. Furthermore, the second rib region 4220 defining the groove 4212 can be formed on the first rib region 4120 of the mask frame 4100 by a second wet etching process, and thus the groove 4212 can be defined by the dummy region 4330 of the diaphragm 4300, the first rib region 4120 of the mask frame 4100 and the second rib region 4220 of the intermediate inorganic film 4200.

[0304] According to embodiments of this disclosure, when the diaphragm 4300 is provided with a second dummy opening 4340, etchant can be provided to the intermediate inorganic film 4200 through the second dummy opening 4340 during the second wet etching process. As a result, as Figure 22 As shown, a second intermediate opening 4230 can be formed to expose the front surface of the mask frame 4100.

[0305] According to another embodiment of this disclosure, the intermediate inorganic membrane 4200 and the first post-inorganic membrane 4400 can be omitted. That is, as... Figure 25 As shown, a diaphragm 4300 with a pixel opening 4312, a dummy opening 4332, and a second dummy opening 4340 can be formed on the front surface of the mask frame 4100, and a rear inorganic film 4500 with a rear opening 4510 (i.e., a second rear inorganic film 4500 with a second rear opening 4510) can be formed on the rear surface of the mask frame 4100.

[0306] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

[0307] Although the invention has been specifically shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A deposition mask, wherein, The deposition mask includes: Mask frame, with unit openings defined through the mask frame; and A diaphragm is disposed on the mask frame, wherein the diaphragm includes mask unit areas exposed through the unit openings and dummy areas surrounding the mask unit areas. The pixel opening is defined by the mask unit region of the diaphragm, and the dummy opening is defined by the dummy region of the diaphragm.

2. The deposition mask according to claim 1, wherein, The deposition mask also includes: An intermediate inorganic membrane is disposed between the mask frame and the diaphragm. The intermediate opening is defined by passing through the intermediate inorganic membrane between the unit opening and the mask unit region.

3. The deposition mask according to claim 2, wherein, The mask frame includes a first rib region defining the opening of the unit. The intermediate inorganic membrane includes a second rib region disposed on the first rib region and defining the intermediate opening. The groove is defined by the first rib region, the second rib region, and the dummy region.

4. The deposition mask according to claim 2, wherein, The deposition mask also includes: A first rear inorganic membrane is disposed on the rear surface of the mask frame and communicates with the cell opening through a first rear opening defined by the first rear inorganic membrane; and A second post-inorganic membrane is disposed on the first post-inorganic membrane and communicates with the first post-opening through a second post-opening defined by the second post-inorganic membrane. The intermediate inorganic membrane and the diaphragm are disposed on the front surface of the mask frame.

5. The deposition mask according to claim 4, wherein, The diaphragm and the second post-inorganic membrane comprise the same material as each other, and The area of ​​the remaining area of ​​the diaphragm after removing the mask unit area and the dummy area is equal to the area of ​​the second inorganic membrane.

6. The deposition mask according to claim 4, wherein, The intermediate inorganic membrane and the first post-inorganic membrane comprise the same material as each other, and The area of ​​the intermediate inorganic membrane is equal to the area of ​​the first post inorganic membrane.

7. The deposition mask according to claim 4, wherein, The unit opening has a width that gradually decreases from the rear surface of the mask frame toward the front surface of the mask frame.

8. The deposition mask according to claim 1, wherein, The second dummy opening extends through the edge portion of the diaphragm or is defined by the portion of the diaphragm between the dummy areas.

9. The deposition mask according to claim 8, wherein, The deposition mask also includes: An intermediate inorganic membrane is disposed between the mask frame and the diaphragm. The intermediate opening is defined by the intermediate inorganic membrane between the unit opening and the mask unit region, and the second intermediate opening is defined by the intermediate inorganic membrane to communicate with the second dummy opening and partially expose the mask frame.

10. A method for manufacturing a deposition mask, wherein, The method includes: A membrane comprising a mask unit region and dummy regions surrounding the mask unit regions is formed on the mask substrate. The diaphragm is patterned to form pixel openings through the mask unit region and to form dummy openings through the dummy region; and The mask substrate is patterned to form cell openings that expose the mask cell regions respectively.

11. The method according to claim 10, wherein, The method further includes: An intermediate inorganic film is formed on the mask substrate; and The intermediate inorganic film is patterned to form an intermediate opening by exposing the mask unit area through the unit opening. The diaphragm is formed on the intermediate inorganic membrane, and The intermediate opening is formed after the unit opening is formed.

12. The method according to claim 11, wherein, The central opening is formed by a wet etching process, and The annular groove is formed between the dummy area of ​​the diaphragm and the mask substrate by the wet etching process.

13. The method according to claim 11, wherein, The method further includes: A first post-inorganic film is formed on the rear surface of the mask substrate; A second post-inorganic membrane is formed on the first post-inorganic membrane; and The first and second post-inorganic films are patterned to form a first and a second post-opening, respectively, that expose the rear portion of the mask substrate. The intermediate inorganic membrane and the diaphragm are formed on the front surface of the mask substrate, and The unit opening is formed by a wet etching process using the first and second post-inorganic films as etching masks.

14. The method according to claim 13, wherein, The diaphragm and the second post-inorganic membrane are formed of the same material as each other, and The area of ​​the remaining area of ​​the diaphragm after removing the mask unit area and the dummy area is equal to the area of ​​the second rear inorganic membrane forming the second rear opening.

15. The method according to claim 13, wherein, The intermediate inorganic membrane and the first post-inorganic membrane are formed of the same material as each other, and The area of ​​the intermediate inorganic membrane forming the intermediate opening is equal to the area of ​​the first post inorganic membrane forming the first post opening.

16. The method of claim 10, wherein, The method further includes: patterning the diaphragm to form a second dummy opening through an edge portion of the diaphragm or a portion of the diaphragm between the dummy regions.

17. The method according to claim 16, wherein, The method further includes: An intermediate inorganic film is formed on the mask substrate; and The intermediate inorganic film is patterned to form an intermediate opening by exposing the mask unit area through the unit opening. The diaphragm is formed on the intermediate inorganic membrane, and The intermediate opening is formed after the unit opening is formed.

18. The method according to claim 17, wherein, The method further includes: patterning the intermediate inorganic film to form a second intermediate opening that communicates with the second dummy opening and partially exposes the mask substrate. The intermediate opening and the second intermediate opening are formed simultaneously.

19. An electronic device, wherein, The electronic device includes: a display panel, The display panel includes: a substrate; and multiple light-emitting layers formed on the substrate using a deposition mask. The deposition mask includes: Mask frame, with unit openings defined through the mask frame; and A diaphragm is disposed on the mask frame, wherein the diaphragm includes mask unit areas exposed through the unit openings and dummy areas surrounding the mask unit areas. The pixel opening is defined by the mask unit region of the diaphragm, and the dummy opening is defined by the dummy region of the diaphragm.

20. The electronic device according to claim 19, wherein, The electronic device also includes at least one selected from a processor, a memory, and a power module.

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