Integrated circuit board timing synchronization intelligent control system

Abstract

The application discloses an integrated circuit board time sequence synchronization intelligent control system and relates to the technical field of integrated circuit board time sequence control; through a time sequence health degree intelligent analysis module, an improved entropy weight-mutual information fusion weight algorithm and an attention enhanced long short-term memory network are adopted to quantitatively evaluate and trend predict the collected multi-dimensional time sequence parameters; the algorithm fuses the entropy value of the parameters and the mutual information value of the time sequence exception events, can more accurately calculate the weight of each parameter, and simultaneously introduces the attention mechanism to enable the model to automatically focus on the parameters with higher correlation degrees with the time sequence exception, so that the precision of time sequence exception evaluation and fault prediction is significantly improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit board timing control technology, specifically to an intelligent control system for integrated circuit board timing synchronization. Background Technology

[0002] With the rapid development of integrated circuit technology, the complexity and integration level of integrated circuit boards are constantly increasing, placing higher demands on the accuracy and stability of timing synchronization. Timing synchronization, as a key factor in ensuring the normal operation of a system, directly affects the accuracy of data transmission and the reliability of system performance. In fields such as high-speed digital circuits, communication systems, and high-performance computing, the timing synchronization problem of integrated circuit boards is particularly prominent. Traditional timing synchronization control methods often rely on fixed timing parameter settings and simple fault detection mechanisms, making it difficult to cope with complex and ever-changing operating environments and potential timing violation risks.

[0003] Traditional timing synchronization control technology for integrated circuit boards has several shortcomings: First, traditional methods often employ static timing analysis, which cannot reflect timing changes during system operation in real time, leading to delayed warnings and responses to timing violations. Second, traditional fault detection mechanisms are often based on single parameters or simple rules, making it difficult to comprehensively and accurately assess the system's timing health, and are prone to false alarms or missed alarms. Third, traditional systems lack self-correction capabilities; once a timing problem is detected, manual intervention is usually required, increasing maintenance costs and downtime. Finally, traditional technologies have limited visualization and remote control capabilities, making it difficult for maintenance personnel to obtain system status information in a timely manner and respond quickly to faults, thus affecting overall maintenance efficiency.

[0004] In view of the shortcomings of traditional integrated circuit board timing synchronization control technology, the present invention proposes an intelligent control system for integrated circuit board timing synchronization, which is of great importance. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies and provide an intelligent control system for timing synchronization of integrated circuit boards. This system integrates a multi-dimensional timing parameter acquisition module, a timing health intelligent analysis module, a timing risk early warning and self-correction module, a hardware acceleration and execution module, and a visualized operation and maintenance management module. This enables high-precision control and intelligent management of timing synchronization on integrated circuit boards. The system employs an improved entropy weight-mutual information fusion weight algorithm and an attention-enhanced long short-term memory network, significantly improving the accuracy of timing violation assessment and fault prediction. Simultaneously, through a multi-level early warning threshold triggering mechanism and a weighted frequent itemset mining algorithm, it achieves early warning and self-correction of faults. Furthermore, the hardware acceleration and execution module based on an FPGA+ARM dual-core architecture ensures high-speed data processing and instruction execution. Finally, the visualized operation and maintenance management module significantly improves operation and maintenance efficiency and reduces operation and maintenance costs through intuitive visualization and convenient remote control functions.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: an intelligent control system for timing synchronization of integrated circuit boards, the system comprising the following components: a multi-dimensional timing parameter acquisition module, a timing health intelligent analysis module, a timing risk warning and self-correction module, a hardware acceleration and execution module, and a visual operation and maintenance management module;

[0007] The multi-dimensional timing parameter acquisition module: collects core operating parameters of each node of the integrated circuit board in real time, such as clock skew, edge response consistency, jitter amplitude, and transmission delay. It deploys a multi-channel parallel acquisition unit and adopts DMA direct memory access technology and adaptive wavelet threshold denoising preprocessing technology to ensure data timeliness and accuracy.

[0008] The time-series health intelligent analysis module: performs quantitative evaluation and trend prediction on the collected parameters, and adopts an improved entropy weight-mutual information fusion weight algorithm and attention-enhanced long short-term memory network to realize parameter weight calculation and health trend prediction, thereby improving the accuracy of time-series violation evaluation and fault prediction.

[0009] The timing risk warning and self-correction module is used to trigger early warning of timing violations and generate personalized correction schemes. Based on a multi-level warning threshold triggering mechanism, combined with a weighted frequent itemset mining algorithm, it realizes fault self-diagnosis and dynamically adjusts clock parameters or switches redundant modules to complete correction.

[0010] The hardware acceleration and execution module is based on an FPGA+ARM dual-core architecture to achieve high-speed data processing and instruction execution. The FPGA side adopts a ping-pong caching mechanism to achieve continuous data acquisition and nanosecond-level timing compensation. The ARM side supports edge-cloud collaboration and online model updates. Redundant design is configured to ensure operational stability.

[0011] The visualized operation and maintenance management module displays operation and maintenance data and supports remote management. It visualizes data through time-series health heatmaps and early warning timelines, and supports remote command issuance, fault log tracing, and multi-format report generation.

[0012] Furthermore, the specific implementation steps of the multi-dimensional timing parameter acquisition module are as follows: First, 512 parallel acquisition channels are deployed at key locations such as the clock tree node, high-speed serial interface, and power management unit of the integrated circuit board. Each channel is configured with an independent high-speed comparator and timestamp generation unit. Second, the acquired raw parameter data is cached in the FPGA on-chip memory at a sampling frequency of not less than 1kHz using DMA direct memory access technology to avoid latency loss caused by CPU intervention. Next, the cached data is preprocessed, including denoising, normalization, and timestamp alignment. The denoising adopts an adaptive wavelet threshold algorithm, and the threshold parameter is dynamically adjusted by detecting the noise variance in real time. Finally, the preprocessed parameter data is transmitted to the health analysis module on the ARM side through the PCIe high-speed interface to provide high-timeliness and fine-grained raw data support for subsequent timing health assessment. The sampling frequency of this acquisition module can be dynamically adjusted according to the system load. Under high load scenarios, the sampling frequency of non-core parameters is automatically reduced to ensure the acquisition accuracy of core parameters. At the same time, it supports hot-swappable expansion of acquisition channels to meet the adaptation needs of integrated circuit boards of different sizes.

[0013] Furthermore, in the aforementioned time-series health intelligent analysis module, an improved entropy weight-mutual information fusion algorithm is used to calculate the weights of each parameter, as shown in the formula: ,in For the first The weight of the item parameter, For the first The entropy value of the parameter is obtained by calculating the entropy of the parameter probability distribution. For the first The mutual information value between the parameter and the timing violation event is obtained by calculating the joint probability distribution of the parameter and the violation event. The weights of all parameters are normalized. , The first The algorithm incorporates the information entropy and mutual information values ​​of the parameters. By introducing a mutual information correction term, it overcomes the shortcomings of traditional entropy weighting methods that rely solely on parameter dispersion while neglecting the correlation between parameters and faults. The weight determination process involves first calculating the entropy value of each parameter. Then, the mutual information between each parameter and historical time-series violation events is calculated. Then, the initial weights are obtained by fusing the above formulas. Finally, the weights are adjusted through iterative optimization until the preset convergence conditions are met, ensuring that the weights can simultaneously reflect the discreteness of the parameters and their correlation with the faults, thereby improving the accuracy of the quantitative assessment of timing violations.

[0014] Furthermore, the time-series health intelligent analysis module employs an improved attention-enhanced long short-term memory network for health prediction, and its output layer prediction formula is as follows: ,in Output the current state. For output gate, In cellular state, The attention weights are calculated by transcribing the cosine similarity between the input parameters and historical violation events, followed by softmax normalization. This algorithm incorporates attention weights. This allows the model to automatically focus on parameters that are more correlated with time-series violations, improving the accuracy of fault prediction. The process of determining the attention weights is as follows: first, the cosine similarity between each input parameter and historical violation events is calculated; then, the attention weights are obtained by normalization using the softmax function; finally, the attention weights are multiplied by the output state of the LSTM to obtain the final health prediction value. This model, trained on 100,000 sets of historical operating data, has achieved an early warning of equipment aging and time-series failures 30 days in advance with an accuracy of 92%.

[0015] Furthermore, the specific implementation steps of the early warning triggering mechanism of the time-series risk early warning and self-correction module are as follows: First, based on the fault probability output by the time-series health intelligent analysis module, three levels of early warning thresholds are set, where the first-level early warning threshold is a fault probability ≥ 80%, the second-level early warning threshold is 60% ≤ fault probability < 80%, and the third-level early warning threshold is 40% ≤ fault probability < 60%; second, when the fault probability reaches the first-level early warning threshold, a 30-day advance warning is triggered, notifying maintenance personnel through multiple channels such as audible and visual alarms, SMS push notifications, and platform pop-ups; when the fault probability reaches the second-level early warning threshold, a 15-day advance warning is triggered, simultaneously... A mild correction mechanism is activated; when the failure probability reaches the level 3 warning threshold, a 7-day advance warning is triggered, and a parameter monitoring enhancement mechanism is activated to increase the sampling frequency of core parameters; then the warning information includes detailed information such as fault node location, fault root cause analysis, and expected failure time, which facilitates maintenance personnel to formulate maintenance plans in advance; finally, after the warning is triggered, the system automatically records the time, level, and processing result information of the warning event to form a warning log, providing data support for subsequent model optimization. This warning mechanism achieves layered control of time-series risks through multi-level threshold settings, avoiding the problem of warning lag or false alarms caused by a single threshold.

[0016] Furthermore, the specific implementation steps of the fault self-diagnosis of the timing risk warning and self-correction module are as follows: First, when a warning is triggered, the system automatically extracts the historical operating parameters of the node, including clock skew, edge response consistency, and transmission delay, and compares them with the parameter baseline under normal operating conditions; second, an improved weighted frequent itemset mining algorithm is used to mine the association rules between parameter anomalies and fault root causes, wherein the weight of the frequent itemset is determined by the mutual information value of the parameters, and the higher the mutual information value, the greater the weight of the parameter in the frequent itemset; then, the fault root cause is located through association rules. When a continuous increase in clock skew and a decrease in edge response consistency are detected, it is determined that the increase in transmission delay is caused by PCB trace aging; when a jitter amplitude is detected... When an anomaly occurs and the power supply voltage fluctuates, it is determined that the clock signal distortion is caused by a power management unit (PMU) fault. Then, a personalized correction plan is generated based on the root cause of the fault. For example, for PCB trace aging, a dynamic delay compensation algorithm is used to adjust the clock signal transmission timing. For PMU faults, redundant power module switching is triggered. Finally, the correction plan is sent to the hardware acceleration and execution module, where the FPGA executes the correction action in real time. After the correction is completed, it is verified whether the timing synchronization accuracy has been restored to the normal range. If it has not been restored, the correction plan is readjusted until the requirements are met. This fault self-diagnosis mechanism improves the accuracy and efficiency of fault location through weighted frequent itemset mining, reducing the fault troubleshooting time from several hours to minutes.

[0017] Furthermore, the specific implementation steps of the FPGA side of the hardware acceleration and execution module are as follows: First, the FPGA side integrates a 512-channel parallel acquisition interface, with each interface configured with a high-speed comparator and a timestamp generation unit, supporting nanosecond-level timestamp marking to ensure the time accuracy of the acquired parameters; second, on-chip memory is deployed to cache the acquired raw parameter data, using a ping-pong caching mechanism to achieve continuous data acquisition and transmission, avoiding data loss; next, a timing compensation unit is integrated, supporting dynamic adjustment of the clock division coefficient and delay line parameters to achieve nanosecond-level timing compensation; then, a PCIe high-speed interface is deployed to transmit the preprocessed parameter data to the ARM side, while receiving correction instructions issued by the ARM side; finally, the FPGA side adopts a modular design, including an acquisition module, a cache module, a compensation module, and an interface module. Each module communicates through an AXI bus to ensure high bandwidth and low latency data transmission. The hardware design of this FPGA side uses TSMC 28nm process, achieving a balance between low power consumption and high performance. While ensuring the maximum operating frequency of the system reaches 218MHz, the power consumption is reduced by 42% compared to traditional designs, meeting the reliability requirements of industrial-grade scenarios.

[0018] Furthermore, the specific implementation steps of the ARM side of the hardware acceleration and execution module are as follows: First, the ARM side is equipped with a Linux operating system and deploys the algorithm model of the time-series health intelligent analysis module, including an improved entropy weight-mutual information fusion weight algorithm and an attention-enhanced LSTM model. Second, it supports edge computing and cloud collaboration. When the computing resources at the edge are insufficient, some health analysis tasks are uploaded to the cloud server to utilize the computing power of the cloud to improve the training speed and prediction accuracy of the model. Next, the MQTT communication protocol is deployed to realize data interaction with the visual operation and maintenance management module, transmitting health scores, early warning information, and correction scheme data to the operation and maintenance platform in real time. Then, it supports online updates and optimization of the model. By collecting the processing results of early warning events, the parameters and weights of the model are updated regularly to improve the adaptability and accuracy of the model. Finally, the ARM side adopts a redundant design, configuring a dual-core processor and backup memory to ensure that the backup processor can be quickly switched when the core processor fails, ensuring the continuous operation of the system. This ARM side design realizes flexible deployment and efficient operation of the algorithm, supports low-latency computing and cloud collaboration in edge scenarios, and meets the adaptation needs of systems of different scales.

[0019] Furthermore, the specific implementation steps of the visualized operation and maintenance management module are as follows: First, a time-series health heatmap of all network nodes is constructed, and the health score of each node is displayed through color coding, where red represents high-risk nodes, green represents normal nodes, and yellow represents warning nodes; second, a warning event timeline is generated, displaying the time, level, and processing result information of historical warning events, supporting filtering and querying by time range, warning level, and other dimensions; next, a query function for correction scheme execution logs is provided, allowing operation and maintenance personnel to view the execution time, execution content, and execution effect details of each correction scheme, facilitating traceability and analysis; then, remote operation and maintenance management is supported, allowing operation and maintenance personnel to issue correction instructions, adjust warning thresholds, and update model parameters through the platform without on-site operation; finally, data export and report generation functions are provided, supporting the export of health data, warning logs, correction schemes, etc., into reports in Excel, PDF, and other formats, facilitating subsequent data analysis and auditing. This visualized operation and maintenance management module significantly improves operation and maintenance efficiency through intuitive visualization and convenient remote management functions, reducing unplanned equipment downtime by more than 85%.

[0020] Compared with existing technologies, this intelligent control system for timing synchronization of integrated circuit boards has the following advantages:

[0021] I. This system utilizes an intelligent time-series health analysis module, employing an improved entropy-weighted mutual information fusion algorithm and an attention-enhanced long short-term memory network, to quantitatively evaluate and predict trends of collected multi-dimensional time-series parameters. This algorithm integrates the entropy value of the parameters and the mutual information value with time-series violation events, enabling more accurate calculation of the weights of each parameter. Simultaneously, an attention mechanism is introduced to automatically focus the model on parameters with higher correlation to time-series violations, thereby significantly improving the accuracy of time-series violation assessment and fault prediction. In practice, through training on a large amount of historical operating data, the model achieves early warning of equipment aging and time-series faults up to 30 days in advance, with an accuracy rate as high as 92%.

[0022] Second, this system integrates a visual operation and maintenance management module, which intuitively displays operation and maintenance data through visualization methods such as time-series health heatmaps and early warning timelines. It supports remote command issuance, fault log tracing, and multi-format report generation. This design enables operation and maintenance personnel to quickly locate problem nodes, formulate maintenance plans in advance, and respond to faults quickly through remote management functions without on-site operation. In specific implementation, this module reduces unplanned equipment downtime by more than 85% through intuitive visualization and convenient remote management functions, significantly improving operation and maintenance efficiency and reducing operation and maintenance costs.

[0023] Other advantages, objectives and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination or study, or may be learned from the practice of the invention. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0025] Figure 1 A flowchart of an intelligent control system for timing synchronization of an integrated circuit board;

[0026] Figure 2 A flowchart illustrating the specific implementation of a multi-dimensional timing parameter acquisition module for an intelligent timing synchronization control system for an integrated circuit board.

[0027] Figure 3 This is a flowchart of the early warning triggering mechanism of the timing risk warning and self-correction module in an intelligent timing synchronization control system for integrated circuit boards. Detailed Implementation

[0028] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided below.

[0029] Example 1

[0030] This embodiment applies to the PLC core control board of a precision machining production line for automotive parts. This control board needs to drive multiple servo motors and sensors to work together. The timing synchronization accuracy directly affects the dimensional tolerance of the machined parts. This system is needed to realize real-time monitoring of timing parameters, risk warning and self-correction to ensure the continuous operation of the production line.

[0031] During the system deployment phase, 512 parallel acquisition channels of a multi-dimensional timing parameter acquisition module are first deployed at key locations on the PLC core control board, such as the clock tree node, high-speed serial interface, and power management unit. Each channel is equipped with an independent high-speed comparator and timestamp generation unit to ensure that no parameters are missed in the acquisition of each node. The specific acquisition process is as follows: Figure 2 As shown. During the acquisition process, DMA (Direct Memory Access) technology is used to cache core operating parameters such as clock skew, edge response consistency, jitter amplitude, and transmission delay in the FPGA's on-chip memory at a sampling frequency of no less than 1kHz, avoiding data delays caused by CPU intervention. The cached raw data is then preprocessed, using an adaptive wavelet threshold denoising algorithm to detect noise variance in real time and dynamically adjust the threshold to complete the denoising operation. After normalization and timestamp alignment, the preprocessed parameter data is finally transmitted to the timing health intelligent analysis module on the ARM side via the PCIe high-speed interface.

[0032] This system works collaboratively through five modules: multi-dimensional time series parameter acquisition, intelligent time series health analysis, time series risk warning and self-correction, hardware acceleration and execution, and visualized operation and maintenance management. The overall process is as follows: Figure 1 As shown, precise timing control of the PLC core control board is achieved. After receiving the data, the timing health intelligent analysis module first uses an improved entropy weight-mutual information fusion weight algorithm to calculate the weights of various parameters such as clock skew and transmission delay. The formula is: ,in For the first The weight of the item parameter, For the first The entropy value of the term parameter, For the first The mutual information value between the parameter and the timing violation event. The weights of all parameters are normalized. , The first The information entropy and mutual information values ​​of the parameters are used to accurately identify the key parameters that have the greatest impact on time synchronization. Then, an attention-enhanced long short-term memory network is used to predict the health of the parameter change trends, outputting the time health score and failure probability of each node. The prediction formula of the output layer is as follows: ,in Output the current state. For output gate, In cellular state, As an attention-weighted event, when the failure probability of the control node corresponding to a certain servo motor reaches 72%, the system immediately triggers a 15-day advance warning. The warning triggering mechanism is as follows: Figure 3 As shown, the system simultaneously notifies the system through three channels: audible and visual alarms from the production line control center, SMS notifications to maintenance personnel's mobile phones, and pop-up windows on the industrial internet platform. The warning information clearly identifies the faulty node as the clock drive node of the servo motor M3, the root cause of the fault is preliminarily determined to be an abnormal increase in transmission delay, and the expected fault time is 15 days later.

[0033] Upon triggering the warning, the timing risk warning and self-correction module initiates a fault self-diagnosis process: it automatically extracts the node's historical operating parameters for the past three months, compares them with the baseline parameters under normal operating conditions, and uses an improved weighted frequent itemset mining algorithm to uncover the association rules between parameter anomalies and the root cause of the fault, ultimately confirming that the root cause is clock division coefficient drift. Based on this root cause, a personalized correction plan is generated—adjusting the node's clock division coefficient to the standard range, and then the correction plan is sent to the hardware acceleration and execution module. After receiving the instruction, the FPGA dynamically adjusts the clock division coefficient through the timing compensation unit, relying on a ping-pong caching mechanism to ensure that data acquisition and compensation actions are executed in parallel, achieving nanosecond-level timing compensation. After correction is completed, the system automatically verifies the timing synchronization accuracy of the node, confirms that it has returned to the normal range, and records information such as the warning level, processing time, and correction parameters to form a warning log.

[0034] Hardware acceleration and execution modules ensure stable system operation throughout: The FPGA side adopts a modular design, with the acquisition module, cache module, compensation module, and interface module communicating efficiently via the AXI bus. The 512-channel parallel acquisition interface ensures synchronous acquisition of parameters from multiple nodes. The ARM side is equipped with a Linux operating system, running an improved entropy weight-mutual information fusion weight algorithm and an attention-enhanced LSTM model. Due to limited edge computing resources on the production line, some historical data health trend backtracking analysis tasks are uploaded to the cloud server. Edge-cloud collaboration improves model processing speed, and the health score and correction results are pushed to the visualized operation and maintenance management module in real time using the MQTT communication protocol.

[0035] Operations and maintenance personnel can intuitively see the status of each node through the time-series health heatmap of the visualization operation and maintenance management module. They can filter the warning events of the past 30 days by warning timeline and view detailed information such as the execution time of the current correction plan, the adjusted clock parameters, and the execution effect. At the same time, they can export monthly reports in Excel format, which include data such as the health score statistics of each node, the number of warnings, and the correction success rate. Remote management can be completed without on-site operation.

[0036] Example 2

[0037] This embodiment is applied to a large data center that carries e-commerce transaction data. The server cluster contains 500 high-performance servers. The core integrated circuit board of each server needs to achieve timing synchronization between the CPU, memory, hard disk and network card to avoid data transmission packet loss, transaction delay and other problems. This system is used to centrally manage the timing status of the integrated circuit boards of the entire cluster.

[0038] During system deployment, 512 parallel acquisition channels of a multi-dimensional timing parameter acquisition module are deployed at key locations such as the clock tree node, high-speed serial interface, and power management unit on the core integrated circuit board of each server. Each channel is equipped with an independent high-speed comparator and timestamp generation unit. A total of 256,000 acquisition channels are deployed across the entire cluster to achieve full coverage acquisition of timing parameters. The specific acquisition process is as follows: Figure 2 As shown. During the acquisition process, parameters such as clock skew, edge response consistency, jitter amplitude, and transmission delay of each node are cached in the on-chip memory of the corresponding server's FPGA at a sampling frequency of 1kHz using DMA direct memory access technology. Then, an adaptive wavelet threshold denoising algorithm is used to denoise the raw data to eliminate the noise impact caused by electromagnetic interference in the data center. After normalization and timestamp alignment, the preprocessed data is aggregated to the ARM end of the cluster edge node through the PCIe high-speed interface.

[0039] This system achieves centralized timing control of integrated circuit boards in data center server clusters through the collaborative operation of five major modules. The overall workflow is as follows: Figure 1 As shown. The time-series health intelligent analysis module centrally processes the data from the entire cluster: it uses an improved entropy weight-mutual information fusion weight algorithm to calculate the weights of various parameters, identifying transmission latency and jitter as the core parameters affecting the time sequence of transaction data transmission; it predicts the time-series health of each server through an attention-enhanced long short-term memory network. When the failure probability of 12 servers reaches 85%, the system immediately triggers a 30-day advance warning. The warning triggering mechanism is as follows. Figure 3As shown, alarms were simultaneously issued through three channels: pop-up windows on the data center operation and maintenance platform, SMS messages from the operation and maintenance manager, and telephone voice notifications. The warning information clearly indicated that the faulty node was the timing node of the communication between the network card and the CPU, the root cause of the fault was excessive jitter, and the estimated fault time was 30 days later. It also included details such as the location number of the 12 servers and the current jitter value.

[0040] Upon triggering the warning, the timing risk warning and self-correction module initiates batch fault self-diagnosis: it automatically extracts the historical operating parameters of the corresponding nodes of the 12 servers, compares them with the baseline parameters of servers operating normally in the cluster, and uses an improved weighted frequent itemset mining algorithm to uncover the correlation rules between excessive jitter and hardware parameters, discovering that the root cause of the fault is unstable clock signal drive voltage. A personalized batch correction solution is generated for this common problem—adjusting the clock signal drive voltage of the 12 servers from 1.0V to 1.2V, while simultaneously switching the redundant clock modules of some nodes. The calibration scheme is distributed to the hardware acceleration and execution modules of each server through the cluster management network. After receiving the instruction, the FPGA dynamically adjusts the driving voltage through the timing compensation unit. Relying on the ping-pong caching mechanism, the data acquisition and calibration actions are guaranteed to be in conflict, achieving nanosecond-level timing compensation. After calibration, the system verifies the timing synchronization accuracy of each server one by one, confirming that the transaction response latency has been restored to the normal range of ≤10ms. For the two servers that did not meet the initial calibration standard, the driving voltage is readjusted to 1.25V. Finally, all servers meet the requirements, and the warning processing process of each server is recorded to form a log.

[0041] Hardware acceleration and execution modules ensure efficient operation of the entire cluster: The 512-channel parallel acquisition interface on the FPGA side supports nanosecond-level timestamp marking, and the ping-pong caching mechanism enables continuous data acquisition and transmission. The modular design ensures that each functional module operates independently and that failures do not affect each other. The ARM side is equipped with a Linux operating system and runs the core algorithm model. Due to the huge amount of data in the entire cluster, the model training task for health trend prediction is uploaded to the cloud big data platform. The training accuracy and speed are improved through edge-cloud collaboration. Real-time data interaction with the visual operation and maintenance management module is achieved through the MQTT communication protocol. At the same time, the ARM side is equipped with a dual-core processor and backup storage. When the core processor of a server fails, it quickly switches to the backup processor to ensure that the timing management is not interrupted.

[0042] The visualized operation and maintenance management module provides operation and maintenance personnel with a centralized management interface: it displays the status of all 500 servers in the cluster through a time-series health heatmap, and supports filtering nodes by server rack location and warning level; it allows viewing historical warning events of the entire cluster through the warning timeline, tracing the processing flow of each warning; it provides a remote command issuance function, allowing operation and maintenance personnel to batch adjust the warning thresholds of cluster servers and update model parameters; it supports exporting the health data, warning logs, and correction schemes of the entire cluster into quarterly operation and maintenance reports in PDF format, providing a basis for decision-making for data center hardware upgrades and operation and maintenance optimization.

[0043] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A timing synchronization intelligent control system for integrated circuit boards, characterized in that, The system comprises the following components: a multi-dimensional time series parameter acquisition module, a time series health intelligent analysis module, a time series risk early warning and self-correction module, a hardware acceleration and execution module, and a visual operation and maintenance management module; The multi-dimensional timing parameter acquisition module: collects core operating parameters of each node of the integrated circuit board in real time, such as clock skew, edge response consistency, jitter amplitude, and transmission delay. It deploys a multi-channel parallel acquisition unit and adopts DMA direct memory access technology and adaptive wavelet threshold denoising preprocessing technology to ensure data timeliness and accuracy. The time-series health intelligent analysis module: performs quantitative evaluation and trend prediction on the collected parameters, and adopts an improved entropy weight-mutual information fusion weight algorithm and attention-enhanced long short-term memory network to realize parameter weight calculation and health trend prediction, thereby improving the accuracy of time-series violation evaluation and fault prediction. The timing risk warning and self-correction module is used to trigger early warning of timing violations and generate personalized correction schemes. Based on a multi-level warning threshold triggering mechanism, combined with a weighted frequent itemset mining algorithm, it realizes fault self-diagnosis and dynamically adjusts clock parameters or switches redundant modules to complete correction. The hardware acceleration and execution module is based on an FPGA+ARM dual-core architecture to achieve high-speed data processing and instruction execution. The FPGA side adopts a ping-pong caching mechanism to achieve continuous data acquisition and nanosecond-level timing compensation. The ARM side supports edge-cloud collaboration and online model updates. Redundant design is configured to ensure operational stability. The visualized operation and maintenance management module displays operation and maintenance data and supports remote management. It visualizes data through time-series health heatmaps and early warning timelines, and supports remote command issuance, fault log tracing, and multi-format report generation.

2. The intelligent control system for timing synchronization of an integrated circuit board according to claim 1, characterized in that, The specific implementation steps of the multi-dimensional timing parameter acquisition module are as follows: First, 512 parallel acquisition channels are deployed in key locations such as the clock tree node, high-speed serial interface, and power management unit of the integrated circuit board. Each channel is configured with an independent high-speed comparator and timestamp generation unit. Second, the acquired raw parameter data is cached in the FPGA on-chip memory at a sampling frequency of not less than 1kHz using DMA direct memory access technology. Then, the cached data is preprocessed, including denoising, normalization, and timestamp alignment. The denoising adopts an adaptive wavelet threshold algorithm, and the threshold parameter is dynamically adjusted by detecting the noise variance in real time. Finally, the preprocessed parameter data is transmitted to the health analysis module on the ARM side via the PCIe high-speed interface.

3. The intelligent control system for timing synchronization of an integrated circuit board according to claim 1, characterized in that, In the aforementioned time-series health intelligent analysis module, an improved entropy weight-mutual information fusion algorithm is used to calculate the weights of each parameter, as shown in the formula: ,in For the first The weight of the item parameter, For the first The entropy value of the term parameter, For the first The mutual information value between the parameter and the timing violation event. The weights of all parameters are normalized. , The first Information entropy and mutual information value of the item parameter.

4. The intelligent control system for timing synchronization of an integrated circuit board according to claim 1, characterized in that, In the aforementioned time-series health intelligent analysis module, an improved attention-enhanced long short-term memory network is used for health prediction. The prediction formula for its output layer is as follows: ,in Output the current state. For output gate, In cellular state, This represents the attention weight.

5. The intelligent control system for timing synchronization of an integrated circuit board according to claim 1, characterized in that, The specific implementation steps of the early warning triggering mechanism of the time-series risk early warning and self-correction module are as follows: First, based on the fault probability output by the time-series health intelligent analysis module, three levels of early warning thresholds are set, where the first-level early warning threshold is a fault probability ≥ 80%, the second-level early warning threshold is 60% ≤ fault probability < 80%, and the third-level early warning threshold is 40% ≤ fault probability < 60%. Second, when the fault probability reaches the first-level early warning threshold, a 30-day advance warning is triggered, and maintenance personnel are notified through multiple channels such as audible and visual alarms, SMS push notifications, and platform pop-ups. When the fault probability reaches the second-level early warning threshold, a 15-day advance warning is triggered, and a mild correction mechanism is activated. When the fault probability reaches the third-level early warning threshold, a 7-day advance warning is triggered, and a parameter monitoring enhancement mechanism is activated, increasing the sampling frequency of core parameters. Next, the early warning information includes detailed information such as fault node location, fault root cause analysis, and expected fault time. Finally, after the early warning is triggered, the system automatically records the time, level, and processing result information of the early warning event, forming an early warning log.

6. The intelligent control system for timing synchronization of an integrated circuit board according to claim 1 or 5, characterized in that, The specific implementation steps of the fault self-diagnosis of the timing risk warning and self-correction module are as follows: First, when the warning is triggered, the system automatically extracts the historical operating parameters of the node, including clock skew, edge response consistency, and transmission delay, and compares them with the parameter baseline under normal operating conditions. Secondly, an improved weighted frequent itemset mining algorithm is used to mine the association rules between parameter anomalies and fault root causes. Then, the fault root causes are located through the association rules. Next, a personalized correction scheme is generated based on the fault root causes. Finally, the correction scheme is sent to the hardware acceleration and execution module, and the FPGA performs the correction action in real time. After the correction is completed, it is verified whether the timing synchronization accuracy has been restored to the normal range. If it has not been restored, the correction scheme is readjusted until the requirements are met.

7. The intelligent control system for timing synchronization of an integrated circuit board according to claim 1, characterized in that, The specific implementation steps of the hardware acceleration and execution module on the FPGA side are as follows: First, the FPGA side integrates a 512-channel parallel acquisition interface, with each interface configured with a high-speed comparator and a timestamp generation unit, supporting nanosecond-level timestamp marking; second, on-chip memory is deployed to cache the acquired raw parameter data, and a ping-pong caching mechanism is used to realize continuous data acquisition and transmission; next, a timing compensation unit is integrated to support dynamic adjustment of the clock division coefficient and delay line parameters; then, a PCIe high-speed interface is deployed to transmit the preprocessed parameter data to the ARM side, while receiving correction instructions issued by the ARM side; finally, the FPGA side adopts a modular design, including an acquisition module, a caching module, a compensation module, and an interface module, and each module communicates through an AXI bus.

8. The intelligent control system for timing synchronization of an integrated circuit board according to claim 1, characterized in that, The specific implementation steps of the hardware acceleration and execution module on the ARM side are as follows: First, the ARM side is equipped with a Linux operating system, and the algorithm model of the time-series health intelligent analysis module is deployed, including an improved entropy weight-mutual information fusion weight algorithm and an attention-enhanced LSTM model; second, it supports edge computing and cloud collaboration. When the computing resources at the edge are insufficient, some health analysis tasks are uploaded to the cloud server to utilize the computing power of the cloud to improve the training speed and prediction accuracy of the model; then, the MQTT communication protocol is deployed to realize data interaction with the visual operation and maintenance management module, and transmit health scores, early warning information, and correction scheme data to the operation and maintenance platform in real time; Then, it supports online updates and optimization of the model. By collecting the processing results of early warning events, the parameters and weights of the model are updated regularly. Finally, the ARM side adopts a redundant design, with a dual-core processor and backup memory configured to ensure that the backup processor can be quickly switched when the core processor fails, thus ensuring the continuous operation of the system.

9. The intelligent control system for timing synchronization of an integrated circuit board according to claim 1, characterized in that, The specific implementation steps of the visualized operation and maintenance management module are as follows: First, a time-series health heatmap of all network nodes is constructed, and the health score of each node is displayed through color coding, where red represents high-risk nodes, green represents normal nodes, and yellow represents warning nodes; second, a warning event timeline is generated, displaying the time, level, and processing result information of historical warning events, supporting filtering and querying by time range, warning level, and other dimensions; next, a function to query the execution log of correction schemes is provided, allowing operation and maintenance personnel to view the execution time, execution content, and execution effect details of each correction scheme; then, remote operation and maintenance management is supported, allowing operation and maintenance personnel to issue correction instructions, adjust warning thresholds, and update model parameters through the platform without on-site operation; finally, data export and report generation functions are provided, supporting the export of health data, warning logs, correction schemes, etc., into reports in Excel, PDF, and other formats.

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