Inter-core communication method of multi-core processor and electronic device

Abstract

The application discloses a core-to-core communication method of a multi-core processor and electronic equipment. The communication method is configured in each core and comprises the following steps: a sending side sends buffer application information to apply for a buffer from a buffer free list; it is judged whether the buffer free list is empty; if yes, available indexes in a recycling ring queue are used as first index values; if not, a head index of the buffer free list is obtained as the first index value; the first index value is written into a sending ring queue and the write index thereof is updated, and a core-to-core interrupt or a mailbox is triggered to inform a receiving side; so that the receiving side reads the first index value through the sending ring queue, writes the first index value into a recycling ring queue and updates the write index of the recycling ring queue after corresponding data processing. Through independent operation of the two ring queues by the sending side and the receiving side, communication data is transmitted based on the index value, zero-copy transmission is realized, and the data transmission efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of embedded systems technology, and in particular to an inter-core communication method and electronic device for a multi-core processor. Background Technology

[0002] As automotive electronic and electrical architectures evolve towards domain controller-centric architectures, high-performance automotive-grade multi-core MCUs are widely used. The operating system software architecture of multi-core MCUs typically adopts an SMP (Symmetric multi-processing) design, where tasks on all cores are uniformly scheduled by a single operating system. This poses a significant challenge for embedded RTOS (Real-time operating system), making it difficult to achieve a high level of functional safety.

[0003] To address this issue, the AMP (Asymmetric multi-processing) design was proposed to build a vehicle domain controller software system with a multi-core MCU. The inter-core communication scheme is a key component. Existing AMP inter-core communication involves a large amount of communication data such as CAN, LIN, Ethernet, analog I / O, digital I / O, and PWM I / O. Controlling the transmission of communication data between multiple cores through flag polling or communication channel interlocking mechanisms will result in a waste of CPU resources and potentially large communication delays. At the same time, the interlocking mechanism also brings additional system overhead and potential deadlock risks, making it difficult to efficiently handle the frequent peer-to-peer communication needs between computing cores. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a method, system, medium, and electronic device for inter-core communication in multi-core processors.

[0005] To achieve the above objectives, the present invention employs the following technical solution: an inter-core communication method for a multi-core processor, wherein the communication method is configured in each core, and on the sending side, includes: Send a cache request message to request a cache from the buffer free list; Check if the buffer free list is empty; If so, then use the available index in the circular queue as the first index value; If not, then obtain the head index of the buffer free list as the first index value; The first index value is written to the sending ring queue and its write index is updated. At the same time, an inter-core interrupt or mailbox is triggered to notify the receiving side. This allows the receiving side to read the first index value through the sending ring queue, and after performing the corresponding data processing, write the first index value to the recycling ring queue and update the write index of the recycling ring queue.

[0006] Preferred configuration: In a multi-core architecture, each core has a private memory area, and each core in the private memory area is allocated a shared memory area corresponding to the core. An independent communication channel is established between any two cores through the shared memory area.

[0007] Preferred: Each core can only access its own private memory area.

[0008] Preferably, the correspondence between the cores and the communication channels is as follows: the number of cores is N, the number of independent communication channels is M, and M = N*(N-1) / 2, where N ≥ 2.

[0009] Preferably, each of the independent communication channels includes two sub-channels, namely, a transmission channel in which the transmitting side transmits and the receiving side receives, and a corresponding transmission channel in which the receiving side acts as the transmitting side and the transmitting side acts as the receiving side, with the transmitting side acting as the master operator on each transmission channel.

[0010] Preferably, each of the sub-channels has two circular queues and a message buffer array. The two circular queues include a sending ring and a recycling ring. The sending ring stores the first index value of the message buffer array that is in the sending state, and the recycling ring stores the second index value of the message buffer array that has been processed by the receiver.

[0011] Preferably, the multi-core configuration includes one management core and multiple computing cores, wherein the management core is responsible for managing the operating status of the computing cores.

[0012] Preferably, the step of reclaiming available indices from the circular queue as the first index value includes: Retrieve the indices of all currently reclaimed buffer blocks from the recycling ring and add them to the free list. After reading, update the read index of the recycling ring stored on the sending side to match the write index inside the recycling ring.

[0013] Preferably, the receiving side determines how many messages need to be processed by checking the difference between the header index in the sending ring of the sending side and its own sending ring read index.

[0014] This disclosure also includes an electronic device, wherein: One or more processors; the processor is an asymmetric processor, including at least one I / O core and a computing core, with the I / O cores and computing cores connected in a fully connected or star hybrid topology; Memory; and One or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs being used to perform the communication method described above.

[0015] The above technical solution has the following advantages or beneficial effects: This application implements a lock-free communication mechanism by setting up a recycling ring queue and a sending ring queue. The recycling ring queue and the sending ring queue are used for communication data transmission. The ring queue only stores the index value of the data block. The sending side and the receiving side transmit communication data based on the index value by independently operating the two ring queues, realizing zero copy during transmission and improving data transmission efficiency. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 The flow chart of the communication method proposed in this invention Figure One ; Figure 2 This is a schematic diagram of the inter-core communication principle in this invention; Figure 3 This is a schematic diagram illustrating the core memory partitioning in this invention; Figure 4 This is a schematic diagram of the communication system proposed in this invention. Figure 5 The flow chart of the communication method proposed in this invention Figure Two . Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Reference Figure 1 The present invention provides an embodiment of an inter-core communication method for a multi-core processor, wherein the communication method is configured in each core, and on the sending side, includes: S1. Send a cache request message to request cache from the buffer free list; determine whether the buffer free list is empty. If yes, proceed to step S2; otherwise, proceed to step S3. S2, then the available index in the circular queue is used as the first index value; S3, then obtain the head index of the buffer free list as the first index value; S4. Write the first index value to the sending ring queue and update its write index, while triggering an inter-core interrupt or mailbox to notify the receiving side; so that the receiving side reads the first index value through the sending ring queue, and after performing the corresponding data processing, writes the first index value to the recycling ring queue and updates the write index of the recycling ring queue.

[0020] In this embodiment, a lock-free communication mechanism is implemented by reclaiming and sending circular queues. These queues are used for communication data transmission. The circular queues only store the index values ​​of data blocks. The sending and receiving sides independently operate the two circular queues to transmit communication data based on the index values, achieving zero-copy transmission and improving data transmission efficiency. In some of the disclosed embodiments: such as Figures 2-3 As shown, in a multi-core system, each core has a private memory area, and each core has a corresponding shared memory area within its private memory area. Independent communication channels are built between any two cores through the shared memory area.

[0021] In some publicly available embodiments, each core can only access its own private memory area.

[0022] In some publicly disclosed embodiments: the correspondence between the cores and the communication channels is as follows: the number of cores is N, the number of independent communication channels is M, M=N*(N-1) / 2, where N≥2.

[0023] In some disclosed embodiments: each of the independent communication channels includes two sub-channels, the two sub-channels including a transmission channel in which the transmitting side transmits and the receiving side receives, and a corresponding transmission channel in which the receiving side acts as the transmitting side and the transmitting side acts as the receiving side, with the transmitting side acting as the master operator on each transmission channel.

[0024] In one specific embodiment, refer to Figures 2-3 Taking a quad-core asymmetric processor as an example: All four cores were assigned to two types of functions: Management Functions: Core 0 is configured as the sole I / O interface and management core in the system, serving as the I / O core. All low-level drivers that interact with external physical devices, such as CAN, LIN, Ethernet, AIO, DIO, PWMIO, and other communication data, run only on core 0. It is also responsible for managing the startup, shutdown, sleep, and wake-up of cores 1 through 3.

[0025] Computing Functions: Cores 1, 2, and 3 are configured as computing cores. They do not directly access any external physical devices and are only used to perform computationally intensive tasks, such as sensor data fusion and various control algorithms. When a computing core needs to perform I / O operations, it exchanges communication data of the corresponding I / O type with core 0 through an inter-core communication mechanism.

[0026] Each core is allocated an independent, private memory region. This region is used to store the corresponding core's local data. By configuring a Memory Protection Unit (MPU), each core can be strictly restricted to accessing only its own private memory, thus ensuring basic isolation between cores.

[0027] To implement a fully connected or star hybrid topology communication network, multiple shared memory regions are set up within the address space accessible to all cores. In a quad-core system, implementing a fully connected network requires 4×(4... 1) / 2 = 6 independent communication channels. The allocation and access permission matrix is ​​shown in Table 1 below:

[0028] Table 1 A secure and interference-free communication foundation is built by combining the access control functions of the hardware MPU. For example, core 2 cannot access the communication channel between core 0 and core 3, thus eliminating the potential risk of data tampering. This deterministic and protected resource allocation is key to achieving a highly reliable real-time system. The size of the shared memory block between each core is set to 64KB, occupying a total of 384KB of memory.

[0029] Reference Figure 5 The System Management Module (SYS MGNT) belongs to the system service layer and is responsible for vehicle-level system initialization and mode management, such as hibernation / wake-up and fault monitoring, and other global system behaviors.

[0030] A software component (SWC) is an application-layer functional module. It is a modular software unit that implements specific functions, such as headlight control or wiper control, and interacts with other components or basic software through ports.

[0031] The Inter-Processor Communication (IPC) module is responsible for communication between multiple cores (core 0 to core 3), enabling cross-core data transmission and synchronization.

[0032] The communication and I / O driver modules (CAN / LIN / ETH / AIO / DIO / PWM) are as follows: CAN / LIN / ETH are the communication drivers for the vehicle bus (Controller Area Network / Local Interconnect Network / Ethernet); AIO (Analog Input / Output), DIO (Digital Input / Output), and PWM (Pulse Width Modulation) are the hardware I / O driver modules, responsible for hardware interaction with sensors and actuators.

[0033] Basic Software (BSW) is a collection of underlying support software excluding communication / IO drivers. It typically includes functions such as operating system adaptation, memory management, and diagnostics, providing a basic environment for the application layer and system service layer.

[0034] A real-time operating system (RTOS) provides functions such as task scheduling, inter-process communication, clock, and peripheral management, and ensures that the real-time requirements of automotive software systems are met, achieving millisecond-level response.

[0035] In some of the disclosed embodiments: each of the sub-channels has two circular queues and a message buffer array. The two circular queues include a sending ring and a recycling ring. The sending ring stores the first index value of the message buffer array in the sending state, and the recycling ring stores the second index value of the message buffer array that has been processed by the receiver.

[0036] In some publicly disclosed embodiments: the multi-core includes a management core and multiple computing cores, wherein the management core is responsible for managing the operating status of the computing cores.

[0037] In some disclosed embodiments: the step of reclaiming available indices from the circular queue as the first index value includes: Retrieve the indices of all currently reclaimed buffer blocks from the recycling ring and add them to the free list. After reading, update the read index of the recycling ring stored on the sending side to match the write index inside the recycling ring.

[0038] In some publicly available embodiments: the receiving side determines how many messages still need to be processed by checking the difference between the header index in the sending side's sending ring and its own sending ring read index.

[0039] Reference Figure 4 In one specific implementation, communication between the sending side (sending core) and the receiving side (receiving core) includes the following steps: S321. Based on the cache request information, the sending core first checks whether the available buffer list is empty. If the available buffer list is empty, it retrieves the indices of all currently reclaimed buffer blocks from the recycling ring and adds them to the free list. After reading, it updates the read index of the recycling ring stored by itself (the sending side) to be consistent with the write index inside the recycling ring (the receiving side).

[0040] If there is an available buffer list, select the index value at the head of the list and write it to the position pointed to by the index in the sending ring.

[0041] S322. Update the write index of the transmitting ring, triggering an inter-core interrupt or mailbox notification to the receiving core. If a new data block is available, execution resumes from S321. S323. Upon receiving the interrupt or mailbox notification, the receiver notifies the receiving task to perform message reception. S324. The receiving task retrieves the index value of the buffer array from the index stored in its own transmitting ring (receiving side), calculates the address of the data block to be processed using this index, and then reads the data packet at that address and sends it to the higher-level protocol stack for processing.

[0042] S325. After the data block is processed, update the receiving side's sending loop read index. The receiving side then writes the index value of the data block that was just processed into the position pointed to by the write index in the recycling ring, and then updates the recycling ring write index.

[0043] S326. Check the difference between the header index and the read index in the sending ring to determine how many messages need to be processed. If there are any follow-ups, re-execute from S324.

[0044] This disclosure also includes an embodiment of an electronic device, comprising: One or more processors; the processor is an asymmetric processor, including at least one I / O core and a computing core, with the I / O cores and computing cores connected in a fully connected or star hybrid topology; Memory; and One or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs being used to perform the following communication methods.

[0045] S1. Send a cache request message to request cache from the buffer free list; determine whether the buffer free list is empty. If yes, proceed to step S2; otherwise, proceed to step S3. S2, then the available index in the circular queue is used as the first index value; S3, then obtain the head index of the buffer free list as the first index value; S4. Write the first index value to the sending ring queue and update its write index, while triggering an inter-core interrupt or mailbox to notify the receiving side; so that the receiving side reads the first index value through the sending ring queue, and after performing the corresponding data processing, writes the first index value to the recycling ring queue and updates the write index of the recycling ring queue.

[0046] The memory, in particular, is used to store computer programs. This memory may include high-speed random access memory (RAM) and may also include non-volatile memory (Non-volatile memory). Volatile Memory (NVM), such as at least one disk storage device, can also be a USB flash drive, external hard drive, read-only memory, disk or optical disc, etc.

[0047] A processor is used to execute computer programs stored in memory. The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly manifested as execution by a hardware processor, or execution by a combination of hardware and software modules within the processor.

[0048] Alternatively, the memory can be either standalone or integrated with the processor.

[0049] When memory is a device independent of the processor, electronic devices may also include a bus. This bus is used to connect the memory and the processor. This bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc.

[0050] It should be noted that, through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the prior art, can be embodied in the form of software products. These computer software products can be stored in computer-readable storage media, such as ROM / RAM, magnetic disks, optical disks, etc., and include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or certain portions of the embodiments. In this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. In the absence of further restrictions, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0051] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for inter-core communication in a multi-core processor, characterized in that, The communication method is configured in each core, and on the sending side, includes: Send a cache request message to request a cache from the buffer free list; Check if the buffer free list is empty; If so, then use the available index in the circular queue as the first index value; If not, then obtain the head index of the buffer free list as the first index value; The first index value is written to the sending ring queue and its write index is updated. At the same time, an inter-core interrupt or mailbox is triggered to notify the receiving side. This allows the receiving side to read the first index value through the sending ring queue, and after performing the corresponding data processing, write the first index value to the recycling ring queue and update the write index of the recycling ring queue.

2. The communication method according to claim 1, characterized in that: In a multi-core system, each core has a private memory area, and each core has a corresponding shared memory area within its private memory area. Independent communication channels can be established between any two cores through the shared memory area.

3. The communication method according to claim 2, characterized in that: Each core can only access its own private memory area.

4. The communication method according to claim 1, characterized in that: The correspondence between the cores and the communication channels is as follows: the number of cores is N, and the number of independent communication channels is M, where M = N*(N-1) / 2, and N ≥ 2.

5. The communication method according to claim 1, characterized in that: Each of the independent communication channels includes two sub-channels, namely a transmission channel in which the transmitting side transmits and the receiving side receives, and a corresponding transmission channel in which the receiving side acts as the transmitting side and the transmitting side acts as the receiving side. In each transmission channel, the transmitting side acts as the master operator.

6. The communication method according to claim 1, characterized in that: Each of the sub-channels contains two circular queues and a message buffer array. The two circular queues include a sending ring and a recycling ring. The sending ring stores the first index value of the message buffer array that is in the sending state, and the recycling ring stores the second index value of the message buffer array that has been processed by the receiver.

7. The communication method according to claim 1, characterized in that: The multi-core system includes one management core and multiple computing cores, with the management core responsible for managing the operating status of the computing cores.

8. The communication method according to claim 1, characterized in that: The step of reclaiming available indices from the circular queue as the first index value includes: Retrieve the indices of all currently reclaimed buffer blocks from the recycling ring and add them to the free list. After reading, update the read index of the recycling ring stored on the sending side to match the write index inside the recycling ring.

9. The communication method according to claim 1, characterized in that: The receiving side determines how many messages need to be processed by checking the difference between the header index in the sending ring of the sending side and its own sending ring read index.

10. An electronic device, characterized in that, include: One or more processors; The processor is an asymmetric processor, including at least one I / O core and a computing core, with several I / O cores and computing cores connected in a fully interconnected or star hybrid topology. Memory; as well as One or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs being used to perform the communication method as described in any one of claims 1-9.

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