A method and apparatus for verifying a yield analysis tool

Abstract

The application discloses a yield analysis tool verification method and device, the method comprises the following steps: obtaining design data, process parameter variables and simulation configuration data corresponding to a first test case; inputting the design data, process parameter variables and simulation configuration data corresponding to the first test case into a to-be-verified yield analysis tool and a verified yield analysis tool respectively to obtain first and second simulation results; obtaining design data corresponding to a second test case; inputting the design data, process parameter variables and simulation configuration data corresponding to the second test case into the to-be-verified yield analysis tool and the verified yield analysis tool respectively to obtain third and fourth simulation results; and verifying the to-be-verified yield analysis tool based on the four simulation results. In the application, the verification of the yield analysis tool is realized by combining the two simulation results, the accuracy and reliability of the verification of the yield analysis tool are improved, and thus the accuracy and effectiveness of the yield analysis tool are ensured.

Description

Technical Field

[0001] This application relates to the field of EDA technology, and in particular to a verification method and apparatus for a yield analysis tool. Background Technology

[0002] In integrated circuit design and manufacturing, yield is a crucial metric, referring to the proportion of qualified products in a batch. A high yield directly impacts production costs, product quality, and market competitiveness. With the continued advancement of Moore's Law, chip feature sizes have entered the nanometer scale or even smaller. Even minute fluctuations in process parameters, such as slight changes in temperature, pressure, and material purity, can become significant factors affecting yield.

[0003] Especially in integrated circuits, some circuit modules that are repeated a lot, such as standard cell libraries and memory arrays, have extremely high yield requirements and are more significantly affected by fluctuations in process parameters. Furthermore, the performance and reliability of these modules directly affect the yield of the entire chip.

[0004] Therefore, using yield analysis tools during the design phase enables rapid and comprehensive assessment of the impact of process parameter variations on yield. These tools can also perform sensitivity analysis to identify factors (process parameters, process conditions, etc.) that significantly affect yield, which is of great importance for improving integrated circuit yield and optimizing design.

[0005] In conclusion, a more accurate validation method is needed for yield analysis tools to ensure their accuracy and effectiveness. Summary of the Invention

[0006] To address the aforementioned issues, this application provides a verification method and apparatus for yield analysis tools, which verifies the yield analysis tools by combining the results of two simulations, thereby improving the accuracy and reliability of the verification and ensuring the accuracy and effectiveness of the yield analysis tools.

[0007] The embodiments of this application disclose the following technical solutions:

[0008] Firstly, this application provides a verification method for a yield analysis tool, characterized by comprising:

[0009] Obtain the design data, process parameter variables, and simulation configuration data corresponding to the first test case; wherein, the simulation configuration data includes: simulator configuration data and model configuration data;

[0010] The design data corresponding to the first test case, the process parameter variables, and the simulation configuration data are respectively input to the yield analysis tool to be verified and the yield analysis tool to be verified, so as to obtain the first simulation result output by the yield analysis tool to be verified and the second simulation result output by the yield analysis tool to be verified;

[0011] Obtain the design data corresponding to the second test case; wherein, the second test case is a test case obtained by optimizing the first test case;

[0012] The design data corresponding to the second test case, the process parameter variables, and the simulation configuration data are respectively input to the yield analysis tool to be verified and the yield analysis tool to be verified, so as to obtain the third simulation result output by the yield analysis tool to be verified and the fourth simulation result output by the yield analysis tool to be verified.

[0013] The yield analysis tool to be verified is validated based on the first simulation result, the second simulation result, the third simulation result, and the fourth simulation result.

[0014] Optionally, the verification of the yield analysis tool to be verified based on the first simulation result, the second simulation result, the third simulation result, and the fourth simulation result includes:

[0015] The first simulation result and the second simulation result are compared to obtain a first comparison result; wherein, the first comparison result includes: comparison is consistent and comparison is inconsistent;

[0016] When the first comparison result is consistent, the third simulation result and the fourth simulation result are compared to obtain the second comparison result; wherein, the second comparison result includes: consistent comparison and inconsistent comparison.

[0017] When the second comparison result is consistent, the verification of the yield analysis tool to be verified is determined to be successful.

[0018] Optionally, the method further includes:

[0019] When the first comparison result is inconsistent, it is determined that the verification of the yield analysis tool to be verified has failed.

[0020] Optionally, the method further includes:

[0021] When the second comparison result is inconsistent, it is determined that the verification of the yield analysis tool to be verified has failed.

[0022] Optionally, comparing the first simulation result and the second simulation result to obtain a first comparison result includes:

[0023] Calculate the relative error between the first simulation result and the second simulation result, and determine whether the relative error is greater than a first preset error;

[0024] If the relative error is not greater than the first preset error, then the first comparison result is determined to be consistent.

[0025] If the relative error is greater than the first preset error, then the first comparison result is determined to be inconsistent.

[0026] Optionally, comparing the third simulation result and the fourth simulation result to obtain a second comparison result includes:

[0027] Calculate the relative error between the third simulation result and the fourth simulation result, and determine whether the relative error is greater than the second preset error;

[0028] If the relative error is not greater than the second preset error, then the second comparison result is determined to be consistent.

[0029] If the relative error is greater than the second preset error, then the second comparison result is determined to be inconsistent.

[0030] Optionally, the second test case is a test case obtained by optimizing the first test case based on the first simulation results.

[0031] Secondly, this application provides a verification device for a yield analysis tool, characterized in that it includes:

[0032] The first acquisition module is used to acquire the design data, process parameter variables, and simulation configuration data corresponding to the first test case; wherein, the simulation configuration data includes: simulator configuration data and model configuration data;

[0033] The first input module is used to input the design data corresponding to the first test case, the process parameter variables and the simulation configuration data to the yield analysis tool to be verified and the yield analysis tool to be verified, respectively, so as to obtain the first simulation result output by the yield analysis tool to be verified and the second simulation result output by the yield analysis tool to be verified;

[0034] The second acquisition module is used to acquire the design data corresponding to the second test case; wherein, the second test case is a test case obtained by optimizing the first test case;

[0035] The second input module is used to input the design data corresponding to the second test case, the process parameter variables, and the simulation configuration data to the yield analysis tool to be verified and the yield analysis tool to be verified, respectively, so as to obtain the third simulation result output by the yield analysis tool to be verified and the fourth simulation result output by the yield analysis tool to be verified.

[0036] The tool verification module is used to verify the yield analysis tool to be verified based on the first simulation result, the second simulation result, the third simulation result, and the fourth simulation result.

[0037] Optionally, the tool verification module is specifically used for:

[0038] The first simulation result and the second simulation result are compared to obtain a first comparison result; wherein, the first comparison result includes: comparison is consistent and comparison is inconsistent;

[0039] When the first comparison result is consistent, the third simulation result and the fourth simulation result are compared to obtain the second comparison result; wherein, the second comparison result includes: consistent comparison and inconsistent comparison.

[0040] When the second comparison result is consistent, the verification of the yield analysis tool to be verified is determined to be successful.

[0041] Optionally, the tool verification module is further configured to determine that the verification of the yield analysis tool to be verified has failed when the first comparison result is inconsistent.

[0042] Compared with the prior art, this application has the following beneficial effects: based on the first simulation results, the second simulation results, the third simulation results and the fourth simulation results, a comprehensive analysis is performed on the yield analysis tool to be verified, thereby completing the verification of the yield analysis tool to be verified, improving the accuracy and reliability of the verification of the yield analysis tool to be verified, and thus ensuring the accuracy and effectiveness of the yield analysis tool. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 A flowchart illustrating a verification method for a yield analysis tool provided in an embodiment of this application;

[0045] Figure 2An example diagram illustrating the input and output of a yield analysis tool provided in this application embodiment;

[0046] Figure 3 A schematic diagram of the verification process for a yield analysis tool to be verified, provided as an embodiment of this application;

[0047] Figure 4 This is a schematic diagram of the structure of a verification device for a yield analysis tool provided in an embodiment of this application. Detailed Implementation

[0048] As described earlier, analysis using yield analysis tools (such as yield analysis and sensitivity analysis) during the design phase is crucial for improving integrated circuit yield and optimizing design. Therefore, ensuring the accuracy and effectiveness of yield analysis tools is paramount. If the accuracy and effectiveness of yield analysis tools are poor, the analysis results output by these tools may be biased, thus affecting the optimization of integrated circuit design.

[0049] This application provides a verification method for a yield analysis tool, comprising: acquiring design data, process parameter variables, and simulation configuration data corresponding to a first test case; inputting the design data, process parameter variables, and simulation configuration data corresponding to the first test case into a yield analysis tool to be verified and a verified yield analysis tool, respectively, to obtain a first simulation result output by the yield analysis tool to be verified and a second simulation result output by the verified yield analysis tool; acquiring design data corresponding to a second test case; inputting the design data, process parameter variables, and simulation configuration data corresponding to the second test case into a yield analysis tool to be verified and a verified yield analysis tool, respectively, to obtain a third simulation result output by the yield analysis tool to be verified and a fourth simulation result output by the verified yield analysis tool; and verifying the yield analysis tool to be verified based on the first simulation result, the second simulation result, the third simulation result, and the fourth simulation result. In this embodiment, based on the first simulation result, the second simulation result, the third simulation result, and the fourth simulation result, a comprehensive analysis is performed on the yield analysis tool to be verified, thereby completing the verification of the yield analysis tool to be verified. This improves the accuracy and reliability of the verification of the yield analysis tool, thereby ensuring the accuracy and effectiveness of the yield analysis tool. It avoids the situation where the analysis results output by the yield analysis tool may be biased due to poor accuracy and effectiveness, which may affect the design optimization of integrated circuits.

[0050] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0051] Example 1:

[0052] The following is combined with Figures 1-3 This paper details a verification method for a yield analysis tool provided in an embodiment of this application.

[0053] like Figure 1 As shown in the embodiments of this application, a verification method for a yield analysis tool includes the following steps:

[0054] S101. Obtain the design data, process parameter variables, and simulation configuration data corresponding to the first test case.

[0055] The first test case is a pre-prepared integrated circuit design with yield requirements. For example, the first test case may be an integrated circuit design that includes modules that are repeated many times (e.g., standard cell libraries, memory arrays, etc.); or an integrated circuit design that is significantly / agilely affected by fluctuations in process parameters.

[0056] The design data corresponding to the first test case is one of the basic inputs of the yield analysis tool. It refers to the various data and files generated and used in the integrated circuit design process, which describe the logic function, physical results and manufacturing requirements of the circuit.

[0057] Specifically, the design data corresponding to the first test case can be: netlist file, schematic file, layout file, design rule file, etc.

[0058] A netlist file contains all the connection information and component parameters for a test case (integrated circuit). Netlist files are typically generated by circuit design tools and, after pre-simulation verification, are used for yield analysis. For example, a netlist file includes: a component list, connection information, and parameter values. The component list lists all components in the integrated circuit (such as resistors, capacitors, transistors, etc.), the connection information describes the connections between each component, and the parameter values ​​are the specific parameter values ​​for each component.

[0059] A schematic file is a graphical representation of a test case (integrated circuit), containing graphical information about components and connections.

[0060] Layout files, such as GDSII files, contain physical layout information for test cases (integrated circuits) and are used to account for layout parasitic effects. Layout parasitic effects refer to the unexpected parasitic components (such as parasitic resistance, parasitic capacitance, and parasitic inductance) that appear in the circuit due to the details of the physical layout and the limitations of the manufacturing process in integrated circuit design. These parasitic components may affect the performance of the integrated circuit or even cause it to malfunction.

[0061] The design rule document contains the layout and principles of Design Rule Detection (DRC). Figure 1 Information from compliance checks (LVS) ensures that integrated circuit designs meet manufacturing requirements.

[0062] Process variation parameters refer to process parameters that may change during the integrated circuit manufacturing process. Changes in these parameters can affect the performance of integrated circuits and thus the yield.

[0063] Specifically, process variables include, but are not limited to: threshold voltage (Vth), bias voltage (Vbias), electron mobility (μ), and gate oxide thickness (Tox).

[0064] Threshold voltage (Vth) refers to the voltage required for a gate-controlled transistor to turn on. Fluctuations in the threshold voltage affect the transistor's turn-on and turn-off characteristics, thus impacting circuit performance and power consumption. Bias voltage (Vbias) refers to the voltage between the base and emitter and between the collector and base when the transistor is in amplification mode. Changes in bias voltage affect the transistor's gain and linearity, thus affecting amplifier performance. A correct bias voltage ensures that an amplifier composed of transistors will not distort signals during signal amplification. Electron mobility (μ) refers to the conductivity of charge carriers, determining the conductivity of a semiconductor. Changes in electron mobility affect the transistor's switching speed and current drive capability. Gate oxide thickness (Tox) refers to the thickness of the insulating layer between the transistor gate and the semiconductor substrate. Changes in gate oxide thickness affect the transistor's threshold voltage and leakage current.

[0065] The simulation configuration data includes: simulator configuration data and model configuration data.

[0066] The simulator configuration data includes: the compatible simulator type data, the simulator's simulation type data, and the simulation process corner data, etc.

[0067] The compatible emulator type data is used to indicate the compatible emulator type. Specifically, the compatible emulator type (e.g., HSPICE, Spectre, etc.) needs to be determined based on the type of test cases (integrated circuits) to be simulated and the simulation purpose.

[0068] The simulator's simulation type data indicates the type of simulation used by the simulator. Specifically, different simulation types are suitable for different simulation needs. Common simulation types include: DC simulation, AC simulation, transient simulation, and noise simulation. DC simulation is used to analyze the behavior of test cases (integrated circuits) under steady-state conditions; AC simulation is used to analyze the behavior of test cases (integrated circuits) in the frequency domain, such as frequency response; transient simulation is used to analyze the behavior of test cases (integrated circuits) in the time domain, such as signal propagation and dynamic response; and noise simulation is used to analyze the noise characteristics of test cases (integrated circuits).

[0069] Simulation process corner data is used to indicate the simulation process corner during the simulation process. A simulation process corner (ProcessCorner) refers to different conditions during manufacturing, caused by variations in process parameters, leading to fluctuations in integrated circuit performance within a certain range. These conditions are typically categorized into several typical simulation process corners, each representing a specific set of process parameter values. Specifically, common simulation process corners include: Typical-Typical (TT), Fast-Fast (FF), Slow-Slow (SS), Fast-Slow (FS), and Slow-Fast (SF), etc.

[0070] The model configuration data includes: simulation model data, sampling method data, and simulation parameter data.

[0071] Simulation model data is used to indicate the appropriate simulation model. Specifically, the appropriate simulation model is determined based on the simulation objective and resource constraints. For example, a traditional Monte Carlo simulation model can be selected if high-precision simulation results are required; a device simulation model can be selected if rapid simulation is required.

[0072] Sampling method data indicates the sampling method used. Common sampling methods include: random sampling, stratified sampling, and importance sampling.

[0073] Simulation parameter data is used to indicate the corresponding simulation parameters. Simulation parameters include: sample size, seed value, convergence criterion, simulation time step, etc.

[0074] S102. Input the design data, process parameter variables and simulation configuration data corresponding to the first test case into the yield analysis tool to be verified and the yield analysis tool to be verified, respectively, so as to obtain the first simulation result output by the yield analysis tool to be verified and the second simulation result output by the yield analysis tool to be verified.

[0075] Among them, the validated yield analysis tool is a yield analysis tool that has been pre-validated.

[0076] Specifically, the design data, process parameter variables, and simulation configuration data corresponding to the first test case are input into the yield analysis tool to be verified. Based on the design data, process parameter variables, and simulation configuration data corresponding to the first test case, the yield analysis tool performs a simulation task and outputs the first simulation result. It should be noted that the process of the verified yield analysis tool is similar to that of the yield analysis tool to be verified, and will not be described in detail here.

[0077] To make it easier to understand, the following will be combined with... Figure 2 This section will provide a detailed explanation of the inputs and outputs of the yield analysis tool.

[0078] like Figure 2 As shown, the inputs to the yield analysis tool include three aspects of data: design data, process parameter variables, and simulation configuration data. The simulation results output by the yield analysis tool include: yield, statistical analysis results of key performance indicators (KPIs), worst-case analysis results, and sensitivity analysis results.

[0079] Key performance indicators include, but are not limited to: gain, which measures the ability to amplify signals; bandwidth, which refers to the range within which an integrated circuit maintains its performance in a specific frequency range; power consumption, an important indicator for measuring its energy efficiency; noise, which measures the integrated circuit's ability to resist interference; and phase margin, an indicator for measuring circuit stability.

[0080] The worst-case analysis results include worst-case performance and worst-case parameters. Worst-case performance is the performance metric of the worst-performing sample among all simulation samples; worst-case parameters are the combination of parameters that lead to the worst-case performance.

[0081] The sensitivity analysis results include: parameter sensitivity, which measures the degree of influence of each process parameter on the performance of integrated circuits; and sensitivity coefficient, which is a quantitative result of the degree of influence of each parameter on the performance index, generally expressed as a percentage or standardized value.

[0082] like Figure 2 As shown, the simulation results are: yield rate 95%; mean bandwidth 10MHz; bandwidth variance 2MHz. 2The average power consumption is 1.2mW, and the power consumption variance is 0.1mW. 2 The noise mean is 1 nV / √Hz, and the noise variance is 0.1 nV / √Hz. 2 The worst-case analysis results are: gain of 98dB, bandwidth of 8MHz, power consumption of 1.3mW, and noise of 1.2nV / √Hz. The sensitivity analysis results are: threshold voltage has the greatest impact on gain, with a sensitivity coefficient of 0.8, and mobility has the greatest impact on bandwidth, with a sensitivity coefficient of 0.7.

[0083] Furthermore, in addition to Figure 2 The simulation results shown include data such as the number of simulations and simulation time.

[0084] The first and second simulation results contain the same data types. For example, if the first simulation result includes yield, mean gain, and variance of gain, then the second simulation result also includes yield, mean gain, and variance of gain.

[0085] In one possible implementation, the data types included in the simulation results output by the yield analysis tool to be verified and the yield analysis tool to be verified are pre-defined.

[0086] S103. Obtain the design data corresponding to the second test case.

[0087] The second test case is an optimized version of the first test case.

[0088] In one possible implementation, the second test case is a pre-optimized version of the first test case. That is, a set of corresponding test cases (the first test case and the second test case) is predetermined.

[0089] S104. Input the design data, process parameter variables and simulation configuration data corresponding to the second test case into the yield analysis tool to be verified and the yield analysis tool to be verified, respectively, so as to obtain the third simulation result output by the yield analysis tool to be verified and the fourth simulation result output by the yield analysis tool to be verified.

[0090] The process parameter variables and simulation configuration data are the same as those input in S102, i.e., they remain unchanged.

[0091] It should be noted that the third and fourth simulation results contain the same data types, and the third simulation result contains the same data types as the first simulation result. In other words, the first, second, third, and fourth simulation results contain the same data types.

[0092] S105. Based on the first simulation results, the second simulation results, the third simulation results, and the fourth simulation results, the yield analysis tool to be verified is validated.

[0093] In this embodiment, based on the first simulation result, the second simulation result, the third simulation result, and the fourth simulation result, a comprehensive analysis is performed on the yield analysis tool to be verified, thereby completing the verification of the yield analysis tool to be verified and improving the accuracy of the verification of the yield analysis tool, which helps to ensure the accuracy and effectiveness of the yield analysis tool.

[0094] In one possible implementation, the first simulation result and the second simulation result are compared, and the third simulation result and the fourth simulation result are compared, thereby realizing the verification of the yield analysis tool to be verified.

[0095] To make it easier to understand, the following will be combined with... Figure 3 This section provides a detailed explanation of how to validate yield analysis tools.

[0096] S301. Compare the first simulation result and the second simulation result to obtain the first comparison result.

[0097] The first comparison results include: consistent comparisons and inconsistent comparisons.

[0098] In one possible implementation, the relative error between the first simulation result and the second simulation result is calculated, and it is determined whether the relative error is greater than a first preset error. If the relative error is not greater than the first preset error, the first comparison result is determined to be consistent. If the relative error is greater than the first preset error, the first comparison result is determined to be inconsistent.

[0099] Specifically, the first preset error includes first preset errors corresponding to multiple data types respectively. The relative error between the first simulation result and the second simulation result is calculated by comparing the relative error between each data type in the first simulation result and the same data type in the second simulation result, and then comparing the relative error corresponding to each data type with the first preset error corresponding to that data type to obtain a first sub-comparison result. If all first sub-comparison results for each data type are consistent, the first comparison result is determined to be consistent; if one or more first sub-comparison results for each data type are inconsistent, the first comparison result is determined to be inconsistent.

[0100] If the first comparison result is consistent, then proceed to S302.

[0101] If the first comparison result is inconsistent, then proceed to S304.

[0102] S302. Compare the third simulation results and the fourth simulation results to obtain the second comparison results. The second comparison results include: consistent comparison and inconsistent comparison.

[0103] In one possible implementation, the relative error between the third simulation result and the fourth simulation result is calculated, and it is determined whether the relative error is greater than a second preset error. If the relative error is not greater than the second preset error, the second comparison result is determined to be consistent. If the relative error is greater than the second preset error, the second comparison result is determined to be inconsistent.

[0104] Specifically, the second preset error includes second preset errors corresponding to multiple data types respectively. The relative error between the third and fourth simulation results is calculated by comparing the relative error between each data type in the third simulation result and the same data type in the fourth simulation result, and then comparing the relative error corresponding to each data type with the second preset error corresponding to that data type to obtain a second sub-comparison result. If all second sub-comparison results for each data type are consistent, the second comparison result is determined to be consistent; if one or more second sub-comparison results for each data type are inconsistent, the second comparison result is determined to be inconsistent.

[0105] It should be noted that the second preset error can be the same as or different from the first preset error. The specific setting depends on the actual situation, and this application does not impose any specific limitations.

[0106] If the second comparison result is consistent, then proceed to S303.

[0107] If the second comparison result is inconsistent, then proceed to S304.

[0108] S303. Confirm that the validation of the yield analysis tool to be validated has passed.

[0109] When the first comparison result is consistent and the second comparison result is consistent, the verification of the yield analysis tool to be verified is successful. That is, the two simulation results output by the yield analysis tool to be verified are consistent with the two simulation results output by the verified yield analysis tool, indicating that the verification of the yield analysis tool to be verified is successful.

[0110] By performing two comparisons to validate the yield analysis tool, the accuracy of the validation is improved, and errors in the overall validation of the yield analysis tool are avoided due to errors in the simulation results output by a validated yield analysis tool in one instance.

[0111] S304. The validation of the yield analysis tool to be validated has failed.

[0112] Specifically, if the first comparison result is inconsistent, it is directly determined that the validation of the yield analysis tool has failed. If the first comparison result is consistent, but the second comparison result is inconsistent, it is also determined that the validation of the yield analysis tool has failed.

[0113] Furthermore, when the verification of the yield analysis tool to be verified fails, the design defects, algorithm problems or operational problems of the yield analysis tool to be verified are analyzed based on the simulation results of the verified yield analysis tool, so as to optimize and update the yield analysis tool to be verified, thereby obtaining the updated yield analysis tool to be verified, and then verifying the updated yield analysis tool.

[0114] In one possible implementation, the second test case is an optimized test case based on the first simulation results of the yield analysis tool to be verified.

[0115] Specifically, based on the first simulation results, analyze the potential problems or performance bottlenecks of the first test case, which may include signal distortion, excessive power consumption, and excessively long response time. Based on the potential problems or performance bottlenecks, analyze the key factors affecting performance and potential optimization points. Based on the analysis results, optimize the first test case and conduct comprehensive testing and verification on the optimized first test case to ensure that it can correctly perform the predetermined function under various working conditions, thereby obtaining the second test case.

[0116] Specifically, based on the analysis results, the optimization of the first test case includes: evaluating and replacing key components of the circuit and adjusting the corresponding parameters, adding peripheral compensation circuits, and optimizing power consumption.

[0117] Evaluate the replacement of key components in the circuit and adjust the corresponding parameters. For linear components, evaluate the feasibility of replacing key linear components (such as resistors, capacitors, and inductors) in the circuit and adjust the parameters of these linear components to improve circuit performance. For nonlinear components (such as transistors), adjust the operating points such as bias voltage and bias current to optimize their performance.

[0118] Adding external compensation circuitry can improve circuit stability and response characteristics; for example, adding a feedback network can enhance amplifier stability.

[0119] Functional optimization refers to reducing circuit power consumption by optimizing circuit structure and component selection. For example, using low-power transistors or optimizing power management circuitry.

[0120] Specifically, the optimized first test case undergoes comprehensive testing and verification, including: functional verification, efficiency testing, stability testing, and load capacity testing.

[0121] Furthermore, after obtaining the second test case, it can be determined through a verified yield analysis tool that the performance of the second test case is superior to that of the first test case.

[0122] This application provides a method for verifying a yield analysis tool, comprising: acquiring design data, process parameter variables, and simulation configuration data corresponding to a first test case; inputting the design data, process parameter variables, and simulation configuration data corresponding to the first test case into a yield analysis tool to be verified and a verified yield analysis tool, respectively, to obtain a first simulation result output by the yield analysis tool to be verified and a second simulation result output by the verified yield analysis tool; acquiring design data corresponding to a second test case; inputting the design data, process parameter variables, and simulation configuration data corresponding to the second test case into a yield analysis tool to be verified and a verified yield analysis tool, respectively, to obtain a third simulation result output by the yield analysis tool to be verified and a fourth simulation result output by the verified yield analysis tool; and verifying the yield analysis tool to be verified based on the first simulation result, the second simulation result, the third simulation result, and the fourth simulation result. In this embodiment of the application, a comprehensive analysis is performed on the yield analysis tool to be verified based on the first simulation result, the second simulation result, the third simulation result and the fourth simulation result, thereby completing the verification of the yield analysis tool to be verified, improving the accuracy and reliability of the verification of the yield analysis tool to be verified, and thus ensuring the accuracy and effectiveness of the yield analysis tool.

[0123] Furthermore, by comparing the first simulation result with the second simulation result, and the second simulation result with the third simulation result and the fourth simulation result, the yield analysis tool to be verified is verified twice, which further improves the accuracy and reliability of the verification of the yield analysis tool to be verified, and avoids the situation where the overall verification of the yield analysis tool is wrong due to the error in the simulation results output by the verified yield analysis tool.

[0124] Example 2:

[0125] The following is combined with Figure 4 This application provides a detailed description of a verification device for a yield analysis tool.

[0126] like Figure 4 As shown in the embodiment of this application, a verification device for a yield analysis tool includes the following modules:

[0127] The first acquisition module 401 is used to acquire the design data, process parameter variables and simulation configuration data corresponding to the first test case; wherein, the simulation configuration data includes: simulator configuration data and model configuration data;

[0128] The first input module 402 is used to input the design data, process parameter variables and simulation configuration data corresponding to the first test case to the yield analysis tool to be verified and the yield analysis tool to be verified, respectively, so as to obtain the first simulation result output by the yield analysis tool to be verified and the second simulation result output by the yield analysis tool to be verified.

[0129] The second acquisition module 403 is used to acquire the design data corresponding to the second test case; wherein, the second test case is a test case obtained by optimizing the first test case;

[0130] The second input module 404 is used to input the design data, process parameter variables and simulation configuration data corresponding to the second test case to the yield analysis tool to be verified and the yield analysis tool to be verified, respectively, so as to obtain the third simulation result output by the yield analysis tool to be verified and the fourth simulation result output by the yield analysis tool to be verified.

[0131] The tool verification module 405 is used to verify the yield analysis tool to be verified based on the first simulation result, the second simulation result, the third simulation result, and the fourth simulation result.

[0132] In one possible implementation, the tool verification module 405 is specifically used to compare the first simulation result and the second simulation result to obtain a first comparison result; wherein the first comparison result includes: comparison consistent and comparison inconsistent; when the first comparison result is comparison consistent, the third simulation result and the fourth simulation result are compared to obtain a second comparison result; wherein the second comparison result includes: comparison consistent and comparison inconsistent; when the second comparison result is comparison consistent, it is determined that the verification of the yield analysis tool to be verified has passed.

[0133] In one possible implementation, the tool verification module 405 is further configured to determine that the verification of the yield analysis tool to be verified has failed when the first comparison result is inconsistent; and to determine that the verification of the yield analysis tool to be verified has failed when the second comparison result is inconsistent.

[0134] In one possible implementation, the tool verification module 405 is specifically used to calculate the relative error between the first simulation result and the second simulation result, and to determine whether the relative error is greater than a first preset error; if the relative error is not greater than the first preset error, the first comparison result is determined to be consistent; if the relative error is greater than the first preset error, the first comparison result is determined to be inconsistent.

[0135] In one possible implementation, the tool verification module 405 is specifically used to calculate the relative error between the third simulation result and the fourth simulation result, and to determine whether the relative error is greater than the second preset error; if the relative error is not greater than the second preset error, the second comparison result is determined to be consistent; if the relative error is greater than the second preset error, the second comparison result is determined to be inconsistent.

[0136] This application provides a verification device for a yield analysis tool, comprising: a first acquisition module 401, used to acquire design data, process parameter variables, and simulation configuration data corresponding to a first test case; a first input module 402, used to input the design data, process parameter variables, and simulation configuration data corresponding to the first test case to a yield analysis tool to be verified and a verified yield analysis tool, respectively, to obtain a first simulation result output by the yield analysis tool to be verified and a second simulation result output by the verified yield analysis tool; a second acquisition module 403, used to acquire design data corresponding to a second test case; a second input module 404, used to input the design data, process parameter variables, and simulation configuration data corresponding to the second test case to a yield analysis tool to be verified and a verified yield analysis tool, respectively, to obtain a third simulation result output by the yield analysis tool to be verified and a fourth simulation result output by the verified yield analysis tool; and a tool verification module 405, used to verify the yield analysis tool to be verified based on the first simulation result, the second simulation result, the third simulation result, and the fourth simulation result. In this embodiment of the application, a comprehensive analysis is performed on the yield analysis tool to be verified based on the first simulation result, the second simulation result, the third simulation result and the fourth simulation result, thereby completing the verification of the yield analysis tool to be verified, improving the accuracy and reliability of the verification of the yield analysis tool to be verified, and thus ensuring the accuracy and effectiveness of the yield analysis tool.

[0137] Furthermore, by comparing the first simulation result with the second simulation result, and the second simulation result with the third simulation result and the fourth simulation result, the yield analysis tool to be verified is verified twice, which further improves the accuracy and reliability of the verification of the yield analysis tool to be verified, and avoids the situation where the overall verification of the yield analysis tool is wrong due to the error in the simulation results output by the verified yield analysis tool.

[0138] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method and apparatus embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiments. The method and apparatus embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components indicated as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of the solution in this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0139] The above description is merely one specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A verification method for a yield analysis tool, characterized in that, include: Obtain the design data, process parameter variables, and simulation configuration data corresponding to the first test case; wherein, the simulation configuration data includes: simulator configuration data and model configuration data; The design data corresponding to the first test case, the process parameter variables, and the simulation configuration data are respectively input to the yield analysis tool to be verified and the yield analysis tool to be verified, so as to obtain the first simulation result output by the yield analysis tool to be verified and the second simulation result output by the yield analysis tool to be verified; Obtain the design data corresponding to the second test case; wherein, the second test case is a test case obtained by optimizing the first test case; The design data corresponding to the second test case, the process parameter variables, and the simulation configuration data are respectively input to the yield analysis tool to be verified and the yield analysis tool to be verified, so as to obtain the third simulation result output by the yield analysis tool to be verified and the fourth simulation result output by the yield analysis tool to be verified. The yield analysis tool to be verified is validated based on the first simulation result, the second simulation result, the third simulation result, and the fourth simulation result.

2. The method according to claim 1, characterized in that, The verification of the yield analysis tool to be verified based on the first simulation result, the second simulation result, the third simulation result, and the fourth simulation result includes: The first simulation result and the second simulation result are compared to obtain a first comparison result; wherein, the first comparison result includes: comparison is consistent and comparison is inconsistent; When the first comparison result is consistent, the third simulation result and the fourth simulation result are compared to obtain the second comparison result; wherein, the second comparison result includes: consistent comparison and inconsistent comparison. When the second comparison result is consistent, the verification of the yield analysis tool to be verified is determined to be successful.

3. The method according to claim 2, characterized in that, The method further includes: When the first comparison result is inconsistent, it is determined that the verification of the yield analysis tool to be verified has failed.

4. The method according to claim 2, characterized in that, The method further includes: When the second comparison result is inconsistent, it is determined that the verification of the yield analysis tool to be verified has failed.

5. The method according to claim 2, characterized in that, The step of comparing the first simulation result and the second simulation result to obtain the first comparison result includes: Calculate the relative error between the first simulation result and the second simulation result, and determine whether the relative error is greater than a first preset error; If the relative error is not greater than the first preset error, then the first comparison result is determined to be consistent. If the relative error is greater than the first preset error, then the first comparison result is determined to be inconsistent.

6. The method according to claim 2, characterized in that, The comparison of the third and fourth simulation results to obtain the second comparison result includes: Calculate the relative error between the third simulation result and the fourth simulation result, and determine whether the relative error is greater than the second preset error; If the relative error is not greater than the second preset error, then the second comparison result is determined to be consistent. If the relative error is greater than the second preset error, then the second comparison result is determined to be inconsistent.

7. The method according to claim 1, characterized in that, The second test case is a test case obtained by optimizing the first test case based on the first simulation results.

8. A verification device for a yield analysis tool, characterized in that, include: The first acquisition module is used to acquire the design data, process parameter variables, and simulation configuration data corresponding to the first test case; wherein, the simulation configuration data includes: simulator configuration data and model configuration data; The first input module is used to input the design data corresponding to the first test case, the process parameter variables and the simulation configuration data to the yield analysis tool to be verified and the yield analysis tool to be verified, respectively, so as to obtain the first simulation result output by the yield analysis tool to be verified and the second simulation result output by the yield analysis tool to be verified; The second acquisition module is used to acquire the design data corresponding to the second test case; wherein, the second test case is a test case obtained by optimizing the first test case; The second input module is used to input the design data corresponding to the second test case, the process parameter variables, and the simulation configuration data to the yield analysis tool to be verified and the yield analysis tool to be verified, respectively, so as to obtain the third simulation result output by the yield analysis tool to be verified and the fourth simulation result output by the yield analysis tool to be verified. The tool verification module is used to verify the yield analysis tool to be verified based on the first simulation result, the second simulation result, the third simulation result, and the fourth simulation result.

9. The apparatus according to claim 8, characterized in that, The tool verification module is specifically used for: The first simulation result and the second simulation result are compared to obtain a first comparison result; wherein, the first comparison result includes: comparison is consistent and comparison is inconsistent; When the first comparison result is consistent, the third simulation result and the fourth simulation result are compared to obtain the second comparison result; wherein, the second comparison result includes: consistent comparison and inconsistent comparison. When the second comparison result is consistent, the verification of the yield analysis tool to be verified is determined to be successful.

10. The apparatus according to claim 9, characterized in that, The tool verification module is further configured to determine that the verification of the yield analysis tool to be verified has failed when the first comparison result is inconsistent.

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