Chip packaging method and chip packaging structure

Abstract

This invention discloses a chip packaging method and chip packaging structure. The method includes: disposing spacers on at least one of a first surface of a packaging substrate and a second surface of a chip; disposing a first colloid on at least one of the first surface, the second surface, and the spacers; bonding the packaging substrate and the chip together such that the spacers are sandwiched between the first and second surfaces and bonded by the first colloid; and curing the first colloid. The chip packaging structure generated by the above method can increase the shear displacement of the first colloid under a given load, reduce the chip's adhesion area, and ensure the height of the first colloid. The chip can more easily release expansion and internal stress through lateral displacement, reducing the degree of chip deformation and warping, and reducing stress on the chip. Therefore, when the chip packaging structure constructs an optical surface through the chip, the chip packaging method of this application can prevent the optical surface from deforming.

Description

Technical Field

[0001] This invention relates to a packaging method, and more particularly to a chip packaging method and chip packaging structure. Background Technology

[0002] Traditional chip packaging methods typically use adhesive materials to directly cover all or part of the chip area. If environmental factors change, such as excessively high chip temperatures, a thermal expansion mismatch can occur between the chip and the package, causing the chip to shift laterally relative to the package. The lateral load resulting from this thermal expansion mismatch is not easily released by the lateral displacement of the adhesive material, and much of the load causes the chip to bend, thus deforming the optical surface. This surface deformation leads to poor optical quality.

[0003] For example, MEMS optical scanners are chosen for vehicles as lidar to create real-time 3D maps. Minimizing the impact of light source divergence on the MEMS optical scanner is crucial, requiring the scanner surface to be as flat as possible. MEMS optical scanners obtained using traditional chip-mount methods, if poorly designed, can experience thermal expansion of both the chip and the package due to temperature changes. However, the degree of expansion cannot be synchronized, leading to stress and deformation on the chip. Therefore, traditional chip-mount methods can severely affect beam quality due to chip stress and deformation. Besides optical MEMS, many other MEMS devices, as well as some semiconductor and integrated circuit devices, use traditional chip-mount packaging methods, which can cause environmental stress and chip deformation problems during use.

[0004] Therefore, there is room for improvement in the packaging method of surface-mount packaged chips. Summary of the Invention

[0005] The present invention aims to at least solve one of the technical problems existing in the prior art. Therefore, the object of the present invention is to provide a chip packaging method, wherein the surface of the chip packaged by the chip packaging method easily releases stress caused by the environment, reducing the degree of chip deformation after heating.

[0006] Another objective of this invention is to propose a chip packaging structure obtained by applying the above-described chip packaging method.

[0007] A chip packaging method according to a first aspect of the present invention includes:

[0008] S1. A spacer is provided on at least one of the first surface of the packaging substrate and the second surface of the chip;

[0009] S2. A first colloid is disposed on at least one of the first surface, the second surface, and the spacer;

[0010] S3. The first surface of the packaging substrate and the second surface of the chip are joined together, with a spacer sandwiched between the first and second surfaces, and the first and second surfaces are bonded together by the first adhesive, or the first and second surfaces are bonded together by the spacer and the first adhesive, wherein the distribution area of ​​the first adhesive on the second surface is smaller than the area of ​​the second surface.

[0011] S4. Cure the first colloid.

[0012] According to the chip packaging method of the present invention, spacers and a first colloid are provided in a gap layer between a first surface of a packaging substrate and a second surface of a chip. After the gap layer is supported by the spacers, the first colloid is used to bond the first surface and the second surface, thereby maintaining the flatness of the chip.

[0013] Because spacers are used to support the void layer, the void layer does not need to be completely filled with the first colloid. Therefore, in this application, when setting the first colloid, the distribution area of ​​the first colloid on the second surface can be smaller than the area of ​​the second surface. After being supported by spacers, the surface tension of the first colloid and the weight of the chip (or packaging substrate) are less likely to cause the first colloid to become too thin, thus ensuring the height of the first colloid after curing.

[0014] The chip packaging structure obtained by this method achieves low-stress chip attachment. When affected by external environmental factors or its own operating heat, if there is a mismatch in thermal expansion between the chip and the packaging substrate, the chip can undergo lateral displacement relative to the packaging substrate. Due to the reduced attachment area on the chip, the lateral constraint of the first colloid on the chip is reduced, and with the height of the first colloid ensured, its ability to absorb shear displacement through deformation increases. Therefore, the chip can more easily release expansion and internal stress through lateral displacement, reducing the degree of chip deformation and warping, and decreasing stress on the chip. Thus, when the chip packaging structure constructs an optical surface through the chip, the chip packaging method of this application makes the optical surface less prone to deformation.

[0015] In particular, some solutions utilize materials for the first colloid that allow it to retain a certain degree of elasticity after curing, and the first colloid remains sufficiently flexible even when it is tall enough. The resulting chip packaging structure, under a given load, allows this packaging method to increase the shear displacement of the first colloid, reduce the chip's adhesion area, and ensure the height of the first colloid.

[0016] According to some embodiments of the chip packaging method of the present invention, step S1 includes:

[0017] S11. A second colloid is disposed on at least one of the first surface of the packaging substrate and the second surface of the chip;

[0018] S12. The second colloid is cured, and the cured second colloid forms the spacer.

[0019] In some embodiments, the second colloid is made of the same material as the first colloid.

[0020] According to some embodiments of the chip packaging method, when setting the second colloid in step S11, equal amounts of the second colloid are set at multiple spaced locations on at least one of the first surface and the second surface.

[0021] Optionally, during the curing of the second colloid in step S12, the first or second surface on which the second colloid is dripped is kept horizontally stationary so that after the second colloid is cured at multiple locations, the multiple spacers formed are of equal height and have a smooth arc surface on the top.

[0022] In some embodiments, when setting the first colloid in step S2, equal amounts of the first colloid are set at multiple spaced locations on at least one of the first surface and the second surface, and the first colloid is spaced apart from the spacer when the first surface and the second surface are joined; the amount of the first colloid at each location is greater than or equal to the amount of the second colloid at each location in step S12.

[0023] In some embodiments, when the first colloid is set in step S2, at least a portion of the first colloid is disposed on the spacer.

[0024] In some embodiments, step S12 includes:

[0025] The second colloid is cured for the first time;

[0026] Check whether the second colloid has reached the set height after curing. If not, add more of the second colloid and cure it again, then check again, until the second colloid reaches the set height after curing.

[0027] In some embodiments, during the curing of the first colloid in step S4, the encapsulation substrate and the chip are pressed together, and the first surface and the second surface are kept parallel during the pressing process, and the spacer is eventually in contact with both the first surface and the second surface.

[0028] According to a chip packaging structure of a second aspect of the present invention, the chip packaging method described above includes: a packaging substrate having a first surface; a chip having a second surface, with a gap layer formed between the first surface and the second surface; a spacer sandwiched between the first surface and the second surface; and a first colloid located within the gap layer, wherein the first surface and the second surface are bonded together by the first colloid, or the first surface and the second surface are bonded together by the spacer and the first colloid, wherein the distribution area of ​​the first colloid on the second surface is smaller than the area of ​​the second surface.

[0029] The chip packaging structure obtained by applying the above-described chip packaging method according to embodiments of the present invention achieves low-stress chip attachment. When affected by external environmental factors or its own operational heat generation, if there is a mismatch in thermal expansion between the chip and the packaging substrate, the chip can undergo lateral displacement relative to the packaging substrate. Because the attachment area on the chip is reduced, the lateral constraint on the chip by the first colloid is reduced, and with the height of the first colloid ensured, the ability of the first colloid to absorb shear displacement through its own deformation increases. Therefore, the chip can more easily release expansion and internal stress through lateral displacement, reducing the degree of chip deformation and warping, and reducing stress on the chip. Consequently, when the chip packaging structure constructs an optical surface through the chip, the optical surface is less prone to deformation.

[0030] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0031] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0032] Figure 1 This is a schematic diagram of the adhesive bonding method between the chip and the packaging substrate in the existing technology;

[0033] Figure 2 This is a flowchart of the chip packaging method in the embodiments of this application;

[0034] Figure 3 This is a schematic diagram showing spacers disposed on the first surface of the encapsulation substrate in some embodiments of this application;

[0035] Figure 4 yes Figure 3 A schematic diagram showing that a spacer is provided on the first surface of the encapsulation substrate and then a first colloid is provided thereon in the embodiment shown.

[0036] Figure 5 yes Figure 4The schematic diagram shown in the embodiment illustrates the chip being mounted on the packaging substrate;

[0037] Figure 6 This is a schematic diagram showing that, in some other embodiments of this application, a spacer is disposed on the first surface of the encapsulation substrate and then a first colloid is disposed thereon;

[0038] Figure 7 This is a schematic diagram showing that, in some embodiments of this application, a spacer is disposed on the first surface of the encapsulation substrate and then a first colloid is disposed thereon;

[0039] Figure 8 This is a flowchart of a chip packaging method in some embodiments of this application;

[0040] Figure 9 This is a schematic diagram showing the distribution of spacers on the packaging substrate in some embodiments of this application;

[0041] Figure 10 Based on Figure 9 A schematic diagram showing the distribution of spacers and the first colloid on the packaging substrate in the embodiment shown;

[0042] Figure 11 Based on Figure 9 Another schematic diagram showing the distribution of spacers and the first colloid on the packaging substrate of the embodiment shown;

[0043] Figure 12 This is a schematic diagram showing the distribution of spacers on the packaging substrate in some other embodiments of this application;

[0044] Figure 13 Based on Figure 12 A schematic diagram showing the distribution of spacers and the first colloid on the packaging substrate in the embodiment shown;

[0045] Figure 14 Based on Figure 12 Another schematic diagram showing the distribution of spacers and the first colloid on the packaging substrate of the embodiment shown.

[0046] Figure label:

[0047] Figure 1 In the middle: packaging substrate 1', chip 2', void layer 5';

[0048] The remaining figures are: chip packaging structure 100, packaging substrate 1, first surface 10, chip 2, second surface 20, first colloid 3, second colloid 4, spacer 40, and void layer 5. Detailed Implementation

[0049] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0050] In the description of this invention, it should be understood that the terms "upper," "lower," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, features defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0051] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0052] In existing chip packaging technologies, one approach involves coating an adhesive material between the chip and the packaging substrate, and then curing the adhesive material to fix the position between the chip and the packaging substrate, thus enabling the chip to be packaged and remain parallel.

[0053] Taking a MEMS optical scanner as an example, when the chip in a MEMS optical scanner is initially attached with an adhesive material, the material is compatible with the chip before use, and the initial stress distribution and bonding state of the chip are matched. However, after the MEMS optical scanner is put into use, temperature changes during normal operation will cause changes in the stress distribution on the chip, resulting in a mismatch between the stress distribution and the bonding state. If this stress mismatch is significant, it will affect the divergence of the MEMS optical scanner. MEMS (Micro-Electro-Mechanical System) is also called a microelectromechanical system, microsystem, or micromechanical system.

[0054] In some typical packaging schemes, such as Figure 1As shown, when attaching chip 2' with the attachment material, the attachment material should cover the entire chip area, that is, the gap layer 5' between chip 2' and packaging substrate 1' should be filled with the attachment material.

[0055] When there is a thermal expansion mismatch between chip 2' and packaging substrate 1', chip 2' will undergo lateral displacement relative to packaging substrate 1'. The lateral load caused by the thermal expansion mismatch is not easily released by the lateral displacement of the adhesive material, and most of the load will cause chip 2' to bend, thereby deforming the optical surface. If the adhesive material allows for a large shear displacement under relatively low load, the stress caused by the thermal expansion mismatch will not be large, and the deformation of the optical surface can be reduced.

[0056] To address the aforementioned problems, this application proposes a chip packaging method. The following references... Figures 2-14 A chip packaging method according to an embodiment of the first aspect of the present invention is described.

[0057] According to the chip packaging method of the present invention, referring to Figure 2 As shown, it includes:

[0058] S1. Spacers 40 are provided on at least one of the first surface 10 of the packaging substrate 1 and the second surface 20 of the chip 2;

[0059] S2. A first colloid 3 is disposed on at least one of the first surface 10, the second surface 20, and the spacer 40;

[0060] S3. The first surface 10 of the packaging substrate 1 and the second surface 20 of the chip 2 are joined together, so that the spacer 40 is sandwiched between the first surface 10 and the second surface 20, and the first surface 10 and the second surface 20 are bonded together by the first adhesive 3, or the first surface 10 and the second surface 20 are bonded together by the spacer 40 and the first adhesive 3, wherein the distribution area of ​​the first adhesive 3 on the second surface 20 is smaller than the area of ​​the second surface 20.

[0061] S4, Curing the first colloid 3.

[0062] When implementing step S1, the spacer 40 can be disposed only on the first surface 10 of the packaging substrate 1, or it can be disposed only on the second surface 20 of the chip 2. Alternatively, in some solutions, spacers 40 are disposed on both the first surface 10 of the packaging substrate 1 and the second surface 20 of the chip 2. In this case, it is important to note that when the first surface 10 of the packaging substrate 1 and the second surface 20 of the chip 2 are joined together in step S3, the spacers 40 on the two surfaces must be staggered so that the two spacers 40 cannot be stacked along the thickness direction of the chip 2.

[0063] When implementing step S2, the first colloid 3 can be disposed only on the first surface 10 of the packaging substrate 1, or it can be disposed only on the second surface 20 of the chip 2. Alternatively, in some solutions, the first colloid 3 is disposed on both the first surface 10 of the packaging substrate 1 and the second surface 20 of the chip 2.

[0064] Alternatively, in step S2 of some embodiments, at least a portion of the first adhesive 3 is disposed on the spacer 40. Taking the first adhesive 3 as disposed by dripping as an example, it can be dripped only onto the spacer 40, with a small amount of the first adhesive 3 remaining on the spacer 40 without flowing and thus not adhering to the first surface 10 or the second surface 20 of the spacer 40. Or, a larger amount of the first adhesive 3 is dripped, with some remaining on the spacer 40 and some flowing and adhering to the first surface 10 or the second surface 20 of the spacer 40. Alternatively, during dripping, a portion of the first adhesive 3 is dripped directly onto the spacer 40, and another portion is dripped directly onto at least one side of the first surface 10 and the second surface 20.

[0065] It should be noted that in some schemes, the spacer 40 and the first colloid 3 are set without interference. Step S1 can be performed first and then step S2, or step S2 can be performed first and then step S1, or both steps can be performed simultaneously, as long as it does not affect step S3.

[0066] In implementing step S3, the method of engaging the first surface 10 of the packaging substrate 1 and the second surface 20 of the chip 2 is not limited. The packaging substrate 1 can be held fixed, with the first surface 10 facing upwards and horizontal. Then, the chip 2 can be picked up using grippers or a suction cup, and the second surface 20 of the chip 2 can be placed face down on the packaging substrate 1. Alternatively, the chip 2 can be held fixed, with the second surface 20 facing upwards and horizontal. Then, the packaging substrate 1 can be picked up using grippers or a suction cup, and the first surface 10 of the packaging substrate 1 can be placed face down on the chip 2. In some solutions, the packaging substrate 1 and the chip 2 can be picked up separately using grippers or a suction cup, and then engaged in a vertical position.

[0067] In step S3, after the first surface 10 of the packaging substrate 1 and the second surface 20 of the chip 2 are joined together, the spacer 40 provides support, forming a gap layer 5 between the packaging substrate 1 and the chip 2. The presence of the spacer 40 maintains the chip 2 at a predetermined distance from the packaging substrate 1. This predetermined distance is the height of the spacer 40, also known as the thickness of the gap layer 5. The height of the spacer 40 refers to its dimension along the thickness direction of the chip 2.

[0068] The spacer 40 provides support during the curing process of the first colloid 3, helping to prevent the chip 2 from bending and deforming due to the tension of the first colloid 3, thus improving the flatness of the chip 2 surface. Furthermore, the height of the first colloid 3 after curing is thus fixed and maintained, and the resulting stress is gradually released under the support of the spacer 40. After curing, the first colloid 3 adapts to the chip environment, and its height matches the height of the spacer 40. The height of the spacer 40 can be adjusted according to actual needs to ensure sufficient gap between the chip 2 and the packaging substrate 1.

[0069] Furthermore, the spacer 40 can provide sufficient friction to the chip 2 or the packaging substrate 1 in step S3 so that the alignment of the chip 2 will not be easily affected during the curing process of the first colloid 3.

[0070] In step S3, after the first surface 10 of the packaging substrate 1 and the second surface 20 of the chip 2 are joined together, in some solutions the first adhesive 3 can be directly bonded to the first surface 10 and the second surface 20, while in other solutions the first adhesive 3 can be bonded to one side of the first surface 10 and the second surface 20, and the other side is indirectly bonded by the spacer 40. After the first adhesive 3 cures in step S4, the packaging substrate 1 and the chip 2 are fixed together, maintaining a stable relative position between the chip 2 and the packaging substrate 1.

[0071] After the first surface 10 of the encapsulation substrate 1 and the second surface 20 of the chip 2 are joined, they can be left to stand or pressed together by an external object. During the curing of the first colloid 3, they can be left to stand or placed in an environment that accelerates curing. Specifically, in some embodiments, in step S4, the encapsulation substrate 1 and the chip 2 can be pressed together, and during the pressing process, the first surface 10 and the second surface 20 are kept parallel, and the spacer 40 is ultimately in contact with both the first surface 10 and the second surface 20. This configuration ensures that the thickness of the void layer 5 is equal to the height of the spacer 40, reducing the skewness of the two surfaces caused by local tension and stress. The method of pressing and keeping the encapsulation substrate 1 and the chip 2 parallel can be achieved using methods known in the prior art.

[0072] Optionally, the first colloid 3 is a UV adhesive, and UV light is used to irradiate the UV adhesive in step S4. Some solutions involve baking the first colloid 3 in step S4. The baking process of the first colloid 3 can be adjusted as needed to create the desired adhesion stress for the initial chip 2, thereby expanding or changing the optimal operating range.

[0073] According to the chip packaging method of the present invention, spacers 40 and a first colloid 3 are provided in the gap layer 5 between the first surface 10 of the packaging substrate 1 and the second surface 20 of the chip 2. After the gap layer 5 is supported by the spacers 40, the first surface 10 and the second surface 20 are bonded by the first colloid 3, thereby maintaining the flatness of the chip 2.

[0074] Because spacers 40 are provided to support the void layer 5, the void layer 5 does not need to completely fill the first colloid 3. Therefore, in this application, when setting the first colloid 3, the distribution area of ​​the first colloid 3 on the second surface 20 can be smaller than the area of ​​the second surface 20. After being supported by spacers 40, the surface tension of the first colloid 3 and the weight of the chip 2 (or packaging substrate 1) are less likely to cause the first colloid 3 to become too thin, thus ensuring the height of the first colloid 3 after curing. Of course, the spacers 40 should be high enough to meet the bonding thickness requirements of the chip 2, but it should also allow the first colloid 3 to contact the chip 2 and the packaging substrate 1 at the bonding position.

[0075] The chip packaging structure 100 obtained by this method achieves low-stress attachment of the chip 2. When affected by external environment or its own operating heat, if there is a mismatch in thermal expansion between the chip 2 and the packaging substrate 1, the chip 2 can undergo lateral displacement relative to the packaging substrate 1. Due to the reduced attachment area on the chip 2, the lateral constraint of the first colloid 3 on the chip 2 is reduced, and after the height of the first colloid 3 is guaranteed, the ability of the first colloid 3 to absorb shear displacement through its own deformation increases. Therefore, the chip 2 can more easily release expansion and internal stress through lateral displacement, reducing the degree of chip 2 deformation and warping, and reducing the stress on the chip 2. Thus, when the chip packaging structure 100 constructs an optical surface through the chip 2, the chip packaging method of this application can make the optical surface less prone to deformation.

[0076] In particular, the materials used in some solutions for the first colloid 3 allow it to retain a certain degree of elasticity after curing, and it remains sufficiently flexible, especially when the first colloid 3 is tall enough. The resulting chip package structure 100, under a given load, can increase the shear displacement of the first colloid 3, reduce the adhesion area of ​​the chip 2, and ensure the height of the first colloid 3. Furthermore, under a given load, the shear displacement of the first colloid 3 in the chip package structure 100 can be maximized, allowing the first colloid 3 to absorb all thermal expansion mismatches between the chip 2 and the package substrate 1.

[0077] When the chip packaging method of this application is applied to the chip 2 attachment scenario of a MEMS optical scanner, the change in optical divergence can be measured to be very small during operation with temperature variations from -40℃ to 105℃. The MEMS optical scanner can pass shock tests up to 2000G, and the shock absorption performance of the packaged chip 2 is strong.

[0078] In this application, by limiting the distribution range of the first colloid 3, the amount of colloid used can be better controlled, ensuring that the first colloid 3 is concentrated in key areas, while ensuring that sufficient colloid is used to fill critical locations in the interlayer gaps and enhance adhesion, avoiding unnecessary waste or overfilling. By precisely controlling the distribution of the first colloid 3, the interaction between the colloid and the connected surfaces can be optimized, improving the bonding effect and the stability of the encapsulation structure.

[0079] Furthermore, this distribution helps reduce the impact of the first colloid 3 on surrounding components. Because the distribution area of ​​the first colloid 3 is reduced, its potential for spillage into the surrounding area is also decreased. This helps improve the reliability and consistency of the chip package structure 100, reducing potential side effects or adverse effects.

[0080] Figures 3-5 The chip packaging process is shown in some specific embodiments.

[0081] like Figure 3 As shown, during step S1, spacers 40 are provided on the first surface 10 of the packaging substrate 1. Figure 3 In the middle, spacers 40 are provided at at least two locations on the first surface 10.

[0082] like Figure 4 As shown, in step S2, a first colloid 3 is disposed on the first surface 10 of the encapsulation substrate 1. Figure 4 In the middle, the first colloid 3 is disposed at at least three locations on the first surface 10.

[0083] like Figure 5 As shown, in step S5, the first surface 10 of the packaging substrate 1 and the second surface 20 of the chip 2 are joined together. At this time, the spacer 40 holds the chip 2 in place, allowing the first adhesive 3 to adhere to the first surface 10 of the packaging substrate 1 and the second surface 20 of the chip 2. Then, wait for the first adhesive 3 to cure.

[0084] Figure 6 The embodiments of step S2 are shown in some other specific embodiments. That is, after the spacer 40 is provided on the first surface 10 of the encapsulation substrate 1, when the first colloid 3 is provided on the first surface 10 of the encapsulation substrate 1, the first colloid 3 is entirely provided on the spacer 40.

[0085] Figure 7 The following are some specific embodiments of step S2. That is, after the spacer 40 is provided on the first surface 10 of the encapsulation substrate 1, when the first colloid 3 is provided on the first surface 10 of the encapsulation substrate 1, a portion of the first colloid 3 is provided on the spacer 40, and a portion of the first colloid 3 is separated from the spacer 40 and directly provided on the first surface 10.

[0086] The first surface 10 and the second surface 20 are separated by a spacer 40 and held together by a first colloid 3, ensuring a stable bond between them and maintaining a balanced interlayer gap between the first surface 10 and the second surface 20. The adhesive force and elasticity of the first colloid 3 allow it to maintain a relatively stable state even when subjected to external impacts or vibrations. This greatly enhances the damage resistance of the chip 2 and improves the reliability of the entire chip packaging structure 100.

[0087] Depending on the placement of the first colloid 3 and the spacer 40, more specific embodiments can be combined, which will not be described in detail here.

[0088] Reference Figure 8 According to some embodiments of the present invention, the process of setting the spacer 40 in step S1 can be further refined, including:

[0089] S11. A second colloid 4 is disposed on at least one of the first surface 10 of the packaging substrate 1 and the second surface 20 of the chip 2.

[0090] S12. The second colloid 4 is cured, and the second colloid 4 forms a spacer 40 after curing.

[0091] In step S11, the second colloid 4 can be disposed only on the first surface 10 of the encapsulation substrate 1, or only on the second surface 20 of the chip 2. Alternatively, in some designs, the first surface 10 of the encapsulation substrate 1 and the second surface 20 of the chip 2 are each provided with the second colloid 4. In this case, it is important to note that when the first surface 10 of the encapsulation substrate 1 and the second surface 20 of the chip 2 are joined together in step S3, the second colloid 4 on the two surfaces must be staggered so that the two spacers 40 cannot be stacked along the thickness direction of the chip 2 after curing.

[0092] In this way, the second colloid 4 is transformed into a spacer 40 with a certain hardness. The spacer 40 has a specific shape and can provide sufficient support strength. The tip of the spacer 40 also has a sufficient coefficient of friction. This support strength ensures that the chip 2 can be stably held in the set position and will not be displaced by external forces or its own weight.

[0093] Spacers 40 are set using a second colloid 4, and the position of the spacers 40 is pre-fixed. Taking the setting of the second colloid 4 on the first surface 10 of the packaging substrate 1 in step S11 as an example, the second colloid 4 is bonded to the first surface 10 after curing. In this way, when the chip 2 and the packaging substrate 1 are subsequently joined, the second colloid 4 can firmly adhere to the packaging substrate 1, and can stably support the chip 2 after the chip 2 is aligned. The friction between the spacers 40 and the chip 2 can prevent the chip 2 from moving easily.

[0094] In some specific embodiments, the second colloid 4 is made of the same material as the first colloid 3. Using the same material means that the procurement of multiple materials can be reduced during the production process, simplifying supply chain management. The same material helps maintain process consistency and improves production efficiency. The same material ensures that the supporting forces on the chip 2 from the spacer 40 and the cured first colloid 3 are substantially the same, which helps improve the stress balance of the chip 2 and reduce localized stress concentration on the chip 2.

[0095] When implementing the chip packaging method of this application, the first colloid 3 and the second colloid 4 use the same material, which can also ensure that the first colloid 3 and the second colloid 4 have consistent physical and chemical properties, which helps to achieve a more accurate and reliable packaging effect.

[0096] Of course, this application does not exclude the possibility that the first colloid 3 and the second colloid 4 may use different materials.

[0097] In some alternative embodiments, the first colloid 3 is silicone. Because silicone can be formulated to have a very low tensile modulus, the first colloid 3 is relatively soft and can more easily absorb shear displacement through its own deformation. Another advantage of using silicone is that its mechanical properties do not change significantly over the temperature range exposed to the application of chip 2, and the first colloid 3 does not become brittle at low temperatures.

[0098] Optionally, the first colloid 3 can be made of polysilicon, which has the characteristics of both organic and inorganic materials, and can exhibit features such as heat resistance, weather resistance, mechanical strength, flame retardancy, and electrical insulation.

[0099] Among them, the temperature resistance of the polysilicon component gives the first colloid 3 high thermal stability and heat resistance, enabling it to maintain good performance at high temperatures.

[0100] The chemical stability of polysilicone components makes the first colloid 3 less prone to chemical reactions with other substances, exhibiting good chemical stability. This means that silicone is not easily degraded during use and can maintain its performance over a long period.

[0101] Of course, this application does not preclude the possibility that the first colloid 3 can be made of other colloidal materials, such as epoxy resin, since neither epoxy resin nor silicone is conductive. Depending on the needs of some application scenarios, the first colloid 3 may also be made of conductive colloidal materials disclosed in the prior art.

[0102] In some alternative embodiments, the second colloid 4 is silicone. The spacer 40 formed after the second colloid 4 is cured also has good adsorption properties, temperature resistance and chemical stability, ensuring that the packaged chip 2 has advantages such as stability and good heat resistance.

[0103] Of course, this application does not preclude the possibility that the second colloid 4 can be made of other colloidal materials, such as epoxy resin, since neither epoxy resin nor silicone is conductive. Depending on the needs of some application scenarios, the second colloid 4 can also be made of conductive colloidal materials disclosed in the prior art.

[0104] Alternatively, glass material can be used as the second colloid 4, allowing the glass material to be operated in different temperature environments at different steps. After the glass material solidifies into spacer 40, the spacer 40, being a glass body, can support the interlayer gaps between the chip 2 and the packaging substrate 1.

[0105] The use of glass material to obtain spacer 40 ensures that it can provide the required adhesion under high temperature conditions, provide reliable support after low temperature curing, and maintain the stability of spacer 40 during long-term use.

[0106] According to some embodiments of the chip packaging method, when setting the second colloid 4 in step S11, equal amounts of the second colloid 4 are set at multiple spaced locations on at least one of the first surface 10 and the second surface 20. Spacing the second colloid 4 apart prevents adjacent pieces from sticking together and avoids fusion due to viscosity and surface tension, thus helping to accurately control the height of the spacer 40 after curing. By setting equal amounts of the second colloid 4 at each location, the shape and height of the second colloid 4 after curing tend to be consistent based on its material properties, thereby further accurately controlling the height of the spacer 40 after curing.

[0107] Specifically, when setting the second colloid 4, ensure that the formation method of the second colloid 4 is consistent at each location and that the distribution is relatively uniform. This helps to ensure the shape consistency of the multiple spacers 40 formed.

[0108] Setting equal amounts also helps to control the overall amount of second colloid 4 used, avoiding waste or insufficient use.

[0109] Furthermore, during the curing of the second colloid 4 in step S12, the first surface 10 or the second surface 20 on which the second colloid 4 is dropped is kept horizontally and calmly so that after the second colloid 4 is cured at multiple locations, the resulting spacers 40 are of equal height and have smooth arc surfaces on their top surfaces. Smooth surfaces can reduce stress concentration and increase the stress-bearing area of ​​the chip 2.

[0110] The consistent height of the second colloid 4 at multiple locations ensures a uniform spacing between the chip 2 and the packaging substrate 1. This helps maintain the flatness of the chip 2 after the first colloid 3 has cured, improving the flatness of the chip 2 and reducing stress or distortion caused by height differences.

[0111] In some optional embodiments, the process in step S12 can be further refined, specifically including:

[0112] First curing of the second colloid 4;

[0113] Check whether the second colloid 4 has reached the set height after curing. If not, add more second colloid 4 and cure it again, then check again, until the second colloid 4 reaches the set height after curing.

[0114] By utilizing detection feedback, the high consistency of multiple spacers 40 can be further ensured, thereby improving support stability.

[0115] In some specific embodiments, when setting the first adhesive 3 in step S2, equal amounts of the first adhesive 3 are applied at multiple spaced locations on at least one of the first surface 10 and the second surface 20. The amount of the first adhesive 3 at each location is greater than or equal to the amount of the second adhesive 4 at each location in step S12. Furthermore, the first adhesive 3 is positioned such that when the first surface 10 and the second surface 20 are joined, the first adhesive 3 is separated from the spacer 40. This arrangement ensures that after the second adhesive 4 cures to form the spacer 40, the first adhesive 3 can fully contact the first surface 10 and the second surface 20, minimizing the chance of missed adhesion.

[0116] Because the first colloid 3 has a larger extrusion volume, it can better fill the interlayer gap between the first surface 10 and the second surface 20, and form a continuous contact layer after curing. This contact layer can enhance the adhesion between the first surface 10 and the second surface 20, and ensure that they can be firmly bonded together in the subsequent encapsulation process, thereby improving the reliability and durability of the chip 2 package.

[0117] In some other specific embodiments, when setting the first colloid 3 in step S2, equal amounts of the first colloid 3 are set on multiple spacers 40. When the spacers 40 are cured from the second colloid 4, the amount of the first colloid 3 and the second colloid 4 at each location is not limited.

[0118] In some embodiments, such as Figures 9-14 As shown, the first colloid 3 and the spacer 40 are spaced apart. This prevents the spacer 40 from sticking to the first colloid 3 and becoming too high, while the first colloid 3 sticking to the spacer 40 allows for better adhesion to the first surface 10 and the second surface 20, ensuring adhesion strength and reliability.

[0119] In this application, the spacers 40 are distributed in a dotted or linear pattern, and the first colloid 3 is distributed in a dotted, linear, or planar pattern.

[0120] For example, in the chip package structure 100, the spacer 40 is linear and a single line. The spacer 40 can be distributed along the edge of the chip 2, or distributed in a spiral pattern. Alternatively, there can be multiple spacers 40, which are multiple lines. Or, there can be multiple spacers 40, which are distributed in a dotted pattern. Or, some of the spacers 40 are dotted, and some are linear.

[0121] For example, in the chip packaging structure 100, the first colloid 3 is linear and a single line. The first colloid 3 can be distributed along the edge of the chip 2, or distributed in a spiral pattern. Alternatively, there can be multiple first colloids 3, which are multiple lines. Or, there can be multiple first colloids 3, which are distributed in a dotted pattern. Or, some of the first colloids 3 are distributed in a dotted pattern, and some are linear.

[0122] The spacer's more than 40 shapes and the first colloid 3's various shapes can be combined to obtain a variety of configurations. For example, in... Figure 9 In the process, the spacers 40 on the encapsulation substrate 1 are distributed at four points, at which time the first colloid 3 can be as follows: Figure 10 As shown in the multi-point distribution, the first colloid 3 can also be as follows: Figure 11 The patterns formed by the combination of multiple lines and dots shown vary. Figure 10 and Figure 11 In the example shown, the first colloid 3 is applied at positions spaced apart from the spacers 40. In other examples, the first colloid 3 is applied partially at positions spaced apart from the spacers 40 and partially at... Figure 10 and Figure 11 The spacer 40 shown can even be covered by the first colloid 3.

[0123] For example, in Figure 12 In the process, the spacers 40 on the encapsulation substrate 1 are distributed at multiple points, at which time the first colloid 3 can be distributed as follows: Figure 13 The multi-point distribution shown can also be as follows: Figure 14 The multi-line distribution shown optimizes shock and vibration resistance. Figure 13 and Figure 14 In the example shown, the first colloid 3 is applied at positions spaced apart from the spacers 40. In other examples, the first colloid 3 is applied partially at positions spaced apart from the spacers 40 and partially at... Figure 13 and Figure 14 The spacer 40 shown can even be covered by the first colloid 3.

[0124] The chip packaging structure 100 according to a second aspect embodiment of the present invention applies the above-described chip packaging method. For example... Figure 5As shown, the chip packaging structure 100 includes: a packaging substrate 1, a chip 2, spacers 40, and a first colloid 3. The packaging substrate 1 has a first surface 10, and the chip 2 has a second surface 20. A void layer 5 is formed between the first surface 10 and the second surface 20. The spacers 40 and the first colloid 3 are located within the void layer 5. The spacers 40 are sandwiched between the first surface 10 and the second surface 20. The first surface 10 and the second surface 20 are adhered to the first colloid 3, or the first surface 10 and the second surface 20 are adhered to each other through the spacers 40 and the first colloid 3. The distribution area of ​​the first colloid 3 on the second surface 20 is smaller than the area of ​​the second surface 20.

[0125] The chip packaging structure 100 obtained by this method achieves low-stress attachment of the chip 2. When affected by external environment or its own operating heat, if there is a mismatch in thermal expansion between the chip 2 and the packaging substrate 1, the chip 2 can undergo lateral displacement relative to the packaging substrate 1. Due to the reduced attachment area on the chip 2, the lateral constraint of the first colloid 3 on the chip 2 is reduced, and after the height of the first colloid 3 is guaranteed, the ability of the first colloid 3 to absorb shear displacement through its own deformation increases. Therefore, the chip 2 can more easily release expansion and internal stress through lateral displacement, reducing the degree of chip 2 deformation and warping, and reducing the stress on the chip 2. Thus, when the chip packaging structure 100 constructs an optical surface through the chip 2, the optical surface is less prone to deformation.

[0126] The detailed structure of the chip package structure 100 has been described in the above method embodiments and will not be repeated here. In the description of this specification, the reference to terms such as "embodiment," "example," etc., means that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0127] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A chip packaging method, characterized in that, include: S1. A spacer (40) is provided on at least one of the first surface (10) of the packaging substrate (1) and the second surface (20) of the chip (2); S2. A first colloid (3) is disposed on at least one of the first surface (10), the second surface (20), and the spacer (40); S3. The first surface (10) of the packaging substrate (1) and the second surface (20) of the chip (2) are joined together, so that the spacer (40) is sandwiched between the first surface (10) and the second surface (20), and the first surface (10) and the second surface (20) are bonded together by the first adhesive (3), or the first surface (10) and the second surface (20) are bonded together by the spacer (40) and the first adhesive (3), wherein the distribution area of ​​the first adhesive (3) on the second surface (20) is smaller than the area of ​​the second surface (20); S4. Curing the first colloid (3).

2. The chip packaging method according to claim 1, characterized in that, Step S1 includes: S11. A second colloid (4) is disposed on at least one of the first surface (10) of the packaging substrate (1) and the second surface (20) of the chip (2); S12. The second colloid (4) is cured, and the second colloid (4) forms the spacer (40) after curing.

3. The chip packaging method according to claim 2, characterized in that, The second colloid (4) is made of the same material as the first colloid (3).

4. The chip packaging method according to claim 2, characterized in that, When setting the second colloid (4) in step S11, equal amounts of the second colloid (4) are set at multiple spaced locations on at least one of the first surface (10) and the second surface (20).

5. The chip packaging method according to claim 4, characterized in that, When curing the second colloid (4) in step S12, the first surface (10) or the second surface (20) on which the second colloid (4) is dripped is kept horizontally still so that after the second colloid (4) at multiple locations is cured, the multiple spacers (40) formed are of equal height and have a smooth arc surface on the top.

6. The chip packaging method according to claim 4, characterized in that, When setting the first colloid (3) in step S2, at least one of the first surface (10) and the second surface (20), multiple spaced locations are selected to set equal amounts of the first colloid (3), and the first colloid (3) is spaced apart from the spacer (40) when the first surface (10) and the second surface (20) are joined; the amount of the first colloid (3) at each location is greater than or equal to the amount of the second colloid (4) at each location in step S12.

7. The chip packaging method according to claim 1, characterized in that, When setting the first colloid (3) in step S2, at least a portion of the first colloid (3) is disposed on the spacer (40).

8. The chip packaging method according to claim 2, characterized in that, Step S12 includes: The second colloid (4) is cured for the first time; Check whether the second colloid (4) has reached the set height after curing. If not, add the second colloid (4) and cure it again, and check again until the second colloid (4) reaches the set height after curing.

9. The chip packaging method according to any one of claims 1-8, characterized in that, In the curing of the first colloid (3) in step S4, the encapsulation substrate (1) and the chip (2) are pressed together, and the first surface (10) and the second surface (20) are kept parallel during the pressing process, and finally the spacer (40) contacts both the first surface (10) and the second surface (20).

10. A chip packaging structure (100) obtained by the chip packaging method according to any one of claims 1-9, characterized in that, include: A packaging substrate (1) having a first surface (10); Chip (2), the chip (2) having a second surface (20), a void layer (5) being formed between the first surface (10) and the second surface (20); A spacer (40) is sandwiched between the first surface (10) and the second surface (20); A first colloid (3) is located within the void layer (5), and the first surface (10) and the second surface (20) are bonded together by the first colloid (3), or the first surface (10) and the second surface (20) are bonded together by the spacer (40) and the first colloid (3), wherein the distribution area of ​​the first colloid (3) on the second surface (20) is smaller than the area of ​​the second surface (20).

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